ARM: dts: kirkwood: gpio-leds fixes for linkstation ls-wvl/vl
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-intel.c
blobc0f5586218c457c23a427387e635e8e3ca9e29d4
1 /*
2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/acpi.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-intel.h"
28 /* Offset from regs */
29 #define PADBAR 0x00c
30 #define GPI_IS 0x100
31 #define GPI_GPE_STS 0x140
32 #define GPI_GPE_EN 0x160
34 #define PADOWN_BITS 4
35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p) ((p) / 8)
39 /* Offset from pad_regs */
40 #define PADCFG0 0x000
41 #define PADCFG0_RXEVCFG_SHIFT 25
42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
43 #define PADCFG0_RXEVCFG_LEVEL 0
44 #define PADCFG0_RXEVCFG_EDGE 1
45 #define PADCFG0_RXEVCFG_DISABLED 2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
47 #define PADCFG0_RXINV BIT(23)
48 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
49 #define PADCFG0_GPIROUTSCI BIT(19)
50 #define PADCFG0_GPIROUTSMI BIT(18)
51 #define PADCFG0_GPIROUTNMI BIT(17)
52 #define PADCFG0_PMODE_SHIFT 10
53 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
54 #define PADCFG0_GPIORXDIS BIT(9)
55 #define PADCFG0_GPIOTXDIS BIT(8)
56 #define PADCFG0_GPIORXSTATE BIT(1)
57 #define PADCFG0_GPIOTXSTATE BIT(0)
59 #define PADCFG1 0x004
60 #define PADCFG1_TERM_UP BIT(13)
61 #define PADCFG1_TERM_SHIFT 10
62 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
63 #define PADCFG1_TERM_20K 4
64 #define PADCFG1_TERM_2K 3
65 #define PADCFG1_TERM_5K 2
66 #define PADCFG1_TERM_1K 1
68 struct intel_pad_context {
69 u32 padcfg0;
70 u32 padcfg1;
73 struct intel_community_context {
74 u32 *intmask;
77 struct intel_pinctrl_context {
78 struct intel_pad_context *pads;
79 struct intel_community_context *communities;
82 /**
83 * struct intel_pinctrl - Intel pinctrl private structure
84 * @dev: Pointer to the device structure
85 * @lock: Lock to serialize register access
86 * @pctldesc: Pin controller description
87 * @pctldev: Pointer to the pin controller device
88 * @chip: GPIO chip in this pin controller
89 * @soc: SoC/PCH specific pin configuration data
90 * @communities: All communities in this pin controller
91 * @ncommunities: Number of communities in this pin controller
92 * @context: Configuration saved over system sleep
94 struct intel_pinctrl {
95 struct device *dev;
96 spinlock_t lock;
97 struct pinctrl_desc pctldesc;
98 struct pinctrl_dev *pctldev;
99 struct gpio_chip chip;
100 const struct intel_pinctrl_soc_data *soc;
101 struct intel_community *communities;
102 size_t ncommunities;
103 struct intel_pinctrl_context context;
106 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
108 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
109 unsigned pin)
111 struct intel_community *community;
112 int i;
114 for (i = 0; i < pctrl->ncommunities; i++) {
115 community = &pctrl->communities[i];
116 if (pin >= community->pin_base &&
117 pin < community->pin_base + community->npins)
118 return community;
121 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
122 return NULL;
125 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
126 unsigned reg)
128 const struct intel_community *community;
129 unsigned padno;
131 community = intel_get_community(pctrl, pin);
132 if (!community)
133 return NULL;
135 padno = pin_to_padno(community, pin);
136 return community->pad_regs + reg + padno * 8;
139 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
141 const struct intel_community *community;
142 unsigned padno, gpp, offset, group;
143 void __iomem *padown;
145 community = intel_get_community(pctrl, pin);
146 if (!community)
147 return false;
148 if (!community->padown_offset)
149 return true;
151 padno = pin_to_padno(community, pin);
152 group = padno / community->gpp_size;
153 gpp = PADOWN_GPP(padno % community->gpp_size);
154 offset = community->padown_offset + 0x10 * group + gpp * 4;
155 padown = community->regs + offset;
157 return !(readl(padown) & PADOWN_MASK(padno));
160 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
162 const struct intel_community *community;
163 unsigned padno, gpp, offset;
164 void __iomem *hostown;
166 community = intel_get_community(pctrl, pin);
167 if (!community)
168 return true;
169 if (!community->hostown_offset)
170 return false;
172 padno = pin_to_padno(community, pin);
173 gpp = padno / community->gpp_size;
174 offset = community->hostown_offset + gpp * 4;
175 hostown = community->regs + offset;
177 return !(readl(hostown) & BIT(padno % community->gpp_size));
180 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
182 struct intel_community *community;
183 unsigned padno, gpp, offset;
184 u32 value;
186 community = intel_get_community(pctrl, pin);
187 if (!community)
188 return true;
189 if (!community->padcfglock_offset)
190 return false;
192 padno = pin_to_padno(community, pin);
193 gpp = padno / community->gpp_size;
196 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
197 * the pad is considered unlocked. Any other case means that it is
198 * either fully or partially locked and we don't touch it.
200 offset = community->padcfglock_offset + gpp * 8;
201 value = readl(community->regs + offset);
202 if (value & BIT(pin % community->gpp_size))
203 return true;
205 offset = community->padcfglock_offset + 4 + gpp * 8;
206 value = readl(community->regs + offset);
207 if (value & BIT(pin % community->gpp_size))
208 return true;
210 return false;
213 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
215 return intel_pad_owned_by_host(pctrl, pin) &&
216 !intel_pad_locked(pctrl, pin);
219 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
221 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
223 return pctrl->soc->ngroups;
226 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
227 unsigned group)
229 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
231 return pctrl->soc->groups[group].name;
234 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
235 const unsigned **pins, unsigned *npins)
237 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
239 *pins = pctrl->soc->groups[group].pins;
240 *npins = pctrl->soc->groups[group].npins;
241 return 0;
244 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
245 unsigned pin)
247 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
248 u32 cfg0, cfg1, mode;
249 bool locked, acpi;
251 if (!intel_pad_owned_by_host(pctrl, pin)) {
252 seq_puts(s, "not available");
253 return;
256 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
257 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
259 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
260 if (!mode)
261 seq_puts(s, "GPIO ");
262 else
263 seq_printf(s, "mode %d ", mode);
265 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
267 locked = intel_pad_locked(pctrl, pin);
268 acpi = intel_pad_acpi_mode(pctrl, pin);
270 if (locked || acpi) {
271 seq_puts(s, " [");
272 if (locked) {
273 seq_puts(s, "LOCKED");
274 if (acpi)
275 seq_puts(s, ", ");
277 if (acpi)
278 seq_puts(s, "ACPI");
279 seq_puts(s, "]");
283 static const struct pinctrl_ops intel_pinctrl_ops = {
284 .get_groups_count = intel_get_groups_count,
285 .get_group_name = intel_get_group_name,
286 .get_group_pins = intel_get_group_pins,
287 .pin_dbg_show = intel_pin_dbg_show,
290 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
292 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
294 return pctrl->soc->nfunctions;
297 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
298 unsigned function)
300 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
302 return pctrl->soc->functions[function].name;
305 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
306 unsigned function,
307 const char * const **groups,
308 unsigned * const ngroups)
310 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
312 *groups = pctrl->soc->functions[function].groups;
313 *ngroups = pctrl->soc->functions[function].ngroups;
314 return 0;
317 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
318 unsigned group)
320 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
321 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
322 unsigned long flags;
323 int i;
325 spin_lock_irqsave(&pctrl->lock, flags);
328 * All pins in the groups needs to be accessible and writable
329 * before we can enable the mux for this group.
331 for (i = 0; i < grp->npins; i++) {
332 if (!intel_pad_usable(pctrl, grp->pins[i])) {
333 spin_unlock_irqrestore(&pctrl->lock, flags);
334 return -EBUSY;
338 /* Now enable the mux setting for each pin in the group */
339 for (i = 0; i < grp->npins; i++) {
340 void __iomem *padcfg0;
341 u32 value;
343 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
344 value = readl(padcfg0);
346 value &= ~PADCFG0_PMODE_MASK;
347 value |= grp->mode << PADCFG0_PMODE_SHIFT;
349 writel(value, padcfg0);
352 spin_unlock_irqrestore(&pctrl->lock, flags);
354 return 0;
357 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
358 struct pinctrl_gpio_range *range,
359 unsigned pin)
361 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
362 void __iomem *padcfg0;
363 unsigned long flags;
364 u32 value;
366 spin_lock_irqsave(&pctrl->lock, flags);
368 if (!intel_pad_usable(pctrl, pin)) {
369 spin_unlock_irqrestore(&pctrl->lock, flags);
370 return -EBUSY;
373 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
374 /* Put the pad into GPIO mode */
375 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
376 /* Disable SCI/SMI/NMI generation */
377 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
378 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
379 /* Disable TX buffer and enable RX (this will be input) */
380 value &= ~PADCFG0_GPIORXDIS;
381 value |= PADCFG0_GPIOTXDIS;
382 writel(value, padcfg0);
384 spin_unlock_irqrestore(&pctrl->lock, flags);
386 return 0;
389 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
390 struct pinctrl_gpio_range *range,
391 unsigned pin, bool input)
393 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
394 void __iomem *padcfg0;
395 unsigned long flags;
396 u32 value;
398 spin_lock_irqsave(&pctrl->lock, flags);
400 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
402 value = readl(padcfg0);
403 if (input)
404 value |= PADCFG0_GPIOTXDIS;
405 else
406 value &= ~PADCFG0_GPIOTXDIS;
407 writel(value, padcfg0);
409 spin_unlock_irqrestore(&pctrl->lock, flags);
411 return 0;
414 static const struct pinmux_ops intel_pinmux_ops = {
415 .get_functions_count = intel_get_functions_count,
416 .get_function_name = intel_get_function_name,
417 .get_function_groups = intel_get_function_groups,
418 .set_mux = intel_pinmux_set_mux,
419 .gpio_request_enable = intel_gpio_request_enable,
420 .gpio_set_direction = intel_gpio_set_direction,
423 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
424 unsigned long *config)
426 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
427 enum pin_config_param param = pinconf_to_config_param(*config);
428 u32 value, term;
429 u16 arg = 0;
431 if (!intel_pad_owned_by_host(pctrl, pin))
432 return -ENOTSUPP;
434 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
435 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
437 switch (param) {
438 case PIN_CONFIG_BIAS_DISABLE:
439 if (term)
440 return -EINVAL;
441 break;
443 case PIN_CONFIG_BIAS_PULL_UP:
444 if (!term || !(value & PADCFG1_TERM_UP))
445 return -EINVAL;
447 switch (term) {
448 case PADCFG1_TERM_1K:
449 arg = 1000;
450 break;
451 case PADCFG1_TERM_2K:
452 arg = 2000;
453 break;
454 case PADCFG1_TERM_5K:
455 arg = 5000;
456 break;
457 case PADCFG1_TERM_20K:
458 arg = 20000;
459 break;
462 break;
464 case PIN_CONFIG_BIAS_PULL_DOWN:
465 if (!term || value & PADCFG1_TERM_UP)
466 return -EINVAL;
468 switch (term) {
469 case PADCFG1_TERM_5K:
470 arg = 5000;
471 break;
472 case PADCFG1_TERM_20K:
473 arg = 20000;
474 break;
477 break;
479 default:
480 return -ENOTSUPP;
483 *config = pinconf_to_config_packed(param, arg);
484 return 0;
487 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
488 unsigned long config)
490 unsigned param = pinconf_to_config_param(config);
491 unsigned arg = pinconf_to_config_argument(config);
492 void __iomem *padcfg1;
493 unsigned long flags;
494 int ret = 0;
495 u32 value;
497 spin_lock_irqsave(&pctrl->lock, flags);
499 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
500 value = readl(padcfg1);
502 switch (param) {
503 case PIN_CONFIG_BIAS_DISABLE:
504 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
505 break;
507 case PIN_CONFIG_BIAS_PULL_UP:
508 value &= ~PADCFG1_TERM_MASK;
510 value |= PADCFG1_TERM_UP;
512 switch (arg) {
513 case 20000:
514 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
515 break;
516 case 5000:
517 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
518 break;
519 case 2000:
520 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
521 break;
522 case 1000:
523 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
524 break;
525 default:
526 ret = -EINVAL;
529 break;
531 case PIN_CONFIG_BIAS_PULL_DOWN:
532 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
534 switch (arg) {
535 case 20000:
536 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
537 break;
538 case 5000:
539 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
540 break;
541 default:
542 ret = -EINVAL;
545 break;
548 if (!ret)
549 writel(value, padcfg1);
551 spin_unlock_irqrestore(&pctrl->lock, flags);
553 return ret;
556 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
557 unsigned long *configs, unsigned nconfigs)
559 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
560 int i, ret;
562 if (!intel_pad_usable(pctrl, pin))
563 return -ENOTSUPP;
565 for (i = 0; i < nconfigs; i++) {
566 switch (pinconf_to_config_param(configs[i])) {
567 case PIN_CONFIG_BIAS_DISABLE:
568 case PIN_CONFIG_BIAS_PULL_UP:
569 case PIN_CONFIG_BIAS_PULL_DOWN:
570 ret = intel_config_set_pull(pctrl, pin, configs[i]);
571 if (ret)
572 return ret;
573 break;
575 default:
576 return -ENOTSUPP;
580 return 0;
583 static const struct pinconf_ops intel_pinconf_ops = {
584 .is_generic = true,
585 .pin_config_get = intel_config_get,
586 .pin_config_set = intel_config_set,
589 static const struct pinctrl_desc intel_pinctrl_desc = {
590 .pctlops = &intel_pinctrl_ops,
591 .pmxops = &intel_pinmux_ops,
592 .confops = &intel_pinconf_ops,
593 .owner = THIS_MODULE,
596 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
598 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
599 void __iomem *reg;
601 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
602 if (!reg)
603 return -EINVAL;
605 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
608 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
610 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
611 void __iomem *reg;
613 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
614 if (reg) {
615 unsigned long flags;
616 u32 padcfg0;
618 spin_lock_irqsave(&pctrl->lock, flags);
619 padcfg0 = readl(reg);
620 if (value)
621 padcfg0 |= PADCFG0_GPIOTXSTATE;
622 else
623 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
624 writel(padcfg0, reg);
625 spin_unlock_irqrestore(&pctrl->lock, flags);
629 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
631 return pinctrl_gpio_direction_input(chip->base + offset);
634 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
635 int value)
637 intel_gpio_set(chip, offset, value);
638 return pinctrl_gpio_direction_output(chip->base + offset);
641 static const struct gpio_chip intel_gpio_chip = {
642 .owner = THIS_MODULE,
643 .request = gpiochip_generic_request,
644 .free = gpiochip_generic_free,
645 .direction_input = intel_gpio_direction_input,
646 .direction_output = intel_gpio_direction_output,
647 .get = intel_gpio_get,
648 .set = intel_gpio_set,
651 static void intel_gpio_irq_ack(struct irq_data *d)
653 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
654 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
655 const struct intel_community *community;
656 unsigned pin = irqd_to_hwirq(d);
658 spin_lock(&pctrl->lock);
660 community = intel_get_community(pctrl, pin);
661 if (community) {
662 unsigned padno = pin_to_padno(community, pin);
663 unsigned gpp_offset = padno % community->gpp_size;
664 unsigned gpp = padno / community->gpp_size;
666 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
669 spin_unlock(&pctrl->lock);
672 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
674 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
675 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
676 const struct intel_community *community;
677 unsigned pin = irqd_to_hwirq(d);
678 unsigned long flags;
680 spin_lock_irqsave(&pctrl->lock, flags);
682 community = intel_get_community(pctrl, pin);
683 if (community) {
684 unsigned padno = pin_to_padno(community, pin);
685 unsigned gpp_offset = padno % community->gpp_size;
686 unsigned gpp = padno / community->gpp_size;
687 void __iomem *reg;
688 u32 value;
690 reg = community->regs + community->ie_offset + gpp * 4;
691 value = readl(reg);
692 if (mask)
693 value &= ~BIT(gpp_offset);
694 else
695 value |= BIT(gpp_offset);
696 writel(value, reg);
699 spin_unlock_irqrestore(&pctrl->lock, flags);
702 static void intel_gpio_irq_mask(struct irq_data *d)
704 intel_gpio_irq_mask_unmask(d, true);
707 static void intel_gpio_irq_unmask(struct irq_data *d)
709 intel_gpio_irq_mask_unmask(d, false);
712 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
715 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
716 unsigned pin = irqd_to_hwirq(d);
717 unsigned long flags;
718 void __iomem *reg;
719 u32 value;
721 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
722 if (!reg)
723 return -EINVAL;
726 * If the pin is in ACPI mode it is still usable as a GPIO but it
727 * cannot be used as IRQ because GPI_IS status bit will not be
728 * updated by the host controller hardware.
730 if (intel_pad_acpi_mode(pctrl, pin)) {
731 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
732 return -EPERM;
735 spin_lock_irqsave(&pctrl->lock, flags);
737 value = readl(reg);
739 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
741 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
742 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
743 } else if (type & IRQ_TYPE_EDGE_FALLING) {
744 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
745 value |= PADCFG0_RXINV;
746 } else if (type & IRQ_TYPE_EDGE_RISING) {
747 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
748 } else if (type & IRQ_TYPE_LEVEL_LOW) {
749 value |= PADCFG0_RXINV;
750 } else {
751 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
754 writel(value, reg);
756 if (type & IRQ_TYPE_EDGE_BOTH)
757 irq_set_handler_locked(d, handle_edge_irq);
758 else if (type & IRQ_TYPE_LEVEL_MASK)
759 irq_set_handler_locked(d, handle_level_irq);
761 spin_unlock_irqrestore(&pctrl->lock, flags);
763 return 0;
766 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
768 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
769 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
770 const struct intel_community *community;
771 unsigned pin = irqd_to_hwirq(d);
772 unsigned padno, gpp, gpp_offset;
773 u32 gpe_en;
775 community = intel_get_community(pctrl, pin);
776 if (!community)
777 return -EINVAL;
779 padno = pin_to_padno(community, pin);
780 gpp = padno / community->gpp_size;
781 gpp_offset = padno % community->gpp_size;
783 /* Clear the existing wake status */
784 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
787 * The controller will generate wake when GPE of the corresponding
788 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
789 * set).
791 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
792 if (on)
793 gpe_en |= BIT(gpp_offset);
794 else
795 gpe_en &= ~BIT(gpp_offset);
796 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
798 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
799 return 0;
802 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
803 const struct intel_community *community)
805 struct gpio_chip *gc = &pctrl->chip;
806 irqreturn_t ret = IRQ_NONE;
807 int gpp;
809 for (gpp = 0; gpp < community->ngpps; gpp++) {
810 unsigned long pending, enabled, gpp_offset;
812 pending = readl(community->regs + GPI_IS + gpp * 4);
813 enabled = readl(community->regs + community->ie_offset +
814 gpp * 4);
816 /* Only interrupts that are enabled */
817 pending &= enabled;
819 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
820 unsigned padno, irq;
823 * The last group in community can have less pins
824 * than NPADS_IN_GPP.
826 padno = gpp_offset + gpp * community->gpp_size;
827 if (padno >= community->npins)
828 break;
830 irq = irq_find_mapping(gc->irqdomain,
831 community->pin_base + padno);
832 generic_handle_irq(irq);
834 ret |= IRQ_HANDLED;
838 return ret;
841 static irqreturn_t intel_gpio_irq(int irq, void *data)
843 const struct intel_community *community;
844 struct intel_pinctrl *pctrl = data;
845 irqreturn_t ret = IRQ_NONE;
846 int i;
848 /* Need to check all communities for pending interrupts */
849 for (i = 0; i < pctrl->ncommunities; i++) {
850 community = &pctrl->communities[i];
851 ret |= intel_gpio_community_irq_handler(pctrl, community);
854 return ret;
857 static struct irq_chip intel_gpio_irqchip = {
858 .name = "intel-gpio",
859 .irq_ack = intel_gpio_irq_ack,
860 .irq_mask = intel_gpio_irq_mask,
861 .irq_unmask = intel_gpio_irq_unmask,
862 .irq_set_type = intel_gpio_irq_type,
863 .irq_set_wake = intel_gpio_irq_wake,
866 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
868 int ret;
870 pctrl->chip = intel_gpio_chip;
872 pctrl->chip.ngpio = pctrl->soc->npins;
873 pctrl->chip.label = dev_name(pctrl->dev);
874 pctrl->chip.parent = pctrl->dev;
875 pctrl->chip.base = -1;
877 ret = gpiochip_add_data(&pctrl->chip, pctrl);
878 if (ret) {
879 dev_err(pctrl->dev, "failed to register gpiochip\n");
880 return ret;
883 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
884 0, 0, pctrl->soc->npins);
885 if (ret) {
886 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
887 goto fail;
891 * We need to request the interrupt here (instead of providing chip
892 * to the irq directly) because on some platforms several GPIO
893 * controllers share the same interrupt line.
895 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
896 dev_name(pctrl->dev), pctrl);
897 if (ret) {
898 dev_err(pctrl->dev, "failed to request interrupt\n");
899 goto fail;
902 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
903 handle_simple_irq, IRQ_TYPE_NONE);
904 if (ret) {
905 dev_err(pctrl->dev, "failed to add irqchip\n");
906 goto fail;
909 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
910 NULL);
911 return 0;
913 fail:
914 gpiochip_remove(&pctrl->chip);
916 return ret;
919 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
921 #ifdef CONFIG_PM_SLEEP
922 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
923 struct intel_community_context *communities;
924 struct intel_pad_context *pads;
925 int i;
927 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
928 if (!pads)
929 return -ENOMEM;
931 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
932 sizeof(*communities), GFP_KERNEL);
933 if (!communities)
934 return -ENOMEM;
937 for (i = 0; i < pctrl->ncommunities; i++) {
938 struct intel_community *community = &pctrl->communities[i];
939 u32 *intmask;
941 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
942 sizeof(*intmask), GFP_KERNEL);
943 if (!intmask)
944 return -ENOMEM;
946 communities[i].intmask = intmask;
949 pctrl->context.pads = pads;
950 pctrl->context.communities = communities;
951 #endif
953 return 0;
956 int intel_pinctrl_probe(struct platform_device *pdev,
957 const struct intel_pinctrl_soc_data *soc_data)
959 struct intel_pinctrl *pctrl;
960 int i, ret, irq;
962 if (!soc_data)
963 return -EINVAL;
965 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
966 if (!pctrl)
967 return -ENOMEM;
969 pctrl->dev = &pdev->dev;
970 pctrl->soc = soc_data;
971 spin_lock_init(&pctrl->lock);
974 * Make a copy of the communities which we can use to hold pointers
975 * to the registers.
977 pctrl->ncommunities = pctrl->soc->ncommunities;
978 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
979 sizeof(*pctrl->communities), GFP_KERNEL);
980 if (!pctrl->communities)
981 return -ENOMEM;
983 for (i = 0; i < pctrl->ncommunities; i++) {
984 struct intel_community *community = &pctrl->communities[i];
985 struct resource *res;
986 void __iomem *regs;
987 u32 padbar;
989 *community = pctrl->soc->communities[i];
991 res = platform_get_resource(pdev, IORESOURCE_MEM,
992 community->barno);
993 regs = devm_ioremap_resource(&pdev->dev, res);
994 if (IS_ERR(regs))
995 return PTR_ERR(regs);
997 /* Read offset of the pad configuration registers */
998 padbar = readl(regs + PADBAR);
1000 community->regs = regs;
1001 community->pad_regs = regs + padbar;
1002 community->ngpps = DIV_ROUND_UP(community->npins,
1003 community->gpp_size);
1006 irq = platform_get_irq(pdev, 0);
1007 if (irq < 0) {
1008 dev_err(&pdev->dev, "failed to get interrupt number\n");
1009 return irq;
1012 ret = intel_pinctrl_pm_init(pctrl);
1013 if (ret)
1014 return ret;
1016 pctrl->pctldesc = intel_pinctrl_desc;
1017 pctrl->pctldesc.name = dev_name(&pdev->dev);
1018 pctrl->pctldesc.pins = pctrl->soc->pins;
1019 pctrl->pctldesc.npins = pctrl->soc->npins;
1021 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1022 if (IS_ERR(pctrl->pctldev)) {
1023 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1024 return PTR_ERR(pctrl->pctldev);
1027 ret = intel_gpio_probe(pctrl, irq);
1028 if (ret) {
1029 pinctrl_unregister(pctrl->pctldev);
1030 return ret;
1033 platform_set_drvdata(pdev, pctrl);
1035 return 0;
1037 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1039 int intel_pinctrl_remove(struct platform_device *pdev)
1041 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1043 gpiochip_remove(&pctrl->chip);
1044 pinctrl_unregister(pctrl->pctldev);
1046 return 0;
1048 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1050 #ifdef CONFIG_PM_SLEEP
1051 int intel_pinctrl_suspend(struct device *dev)
1053 struct platform_device *pdev = to_platform_device(dev);
1054 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1055 struct intel_community_context *communities;
1056 struct intel_pad_context *pads;
1057 int i;
1059 pads = pctrl->context.pads;
1060 for (i = 0; i < pctrl->soc->npins; i++) {
1061 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1062 u32 val;
1064 if (!intel_pad_usable(pctrl, desc->number))
1065 continue;
1067 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1068 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1069 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1070 pads[i].padcfg1 = val;
1073 communities = pctrl->context.communities;
1074 for (i = 0; i < pctrl->ncommunities; i++) {
1075 struct intel_community *community = &pctrl->communities[i];
1076 void __iomem *base;
1077 unsigned gpp;
1079 base = community->regs + community->ie_offset;
1080 for (gpp = 0; gpp < community->ngpps; gpp++)
1081 communities[i].intmask[gpp] = readl(base + gpp * 4);
1084 return 0;
1086 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1088 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1090 size_t i;
1092 for (i = 0; i < pctrl->ncommunities; i++) {
1093 const struct intel_community *community;
1094 void __iomem *base;
1095 unsigned gpp;
1097 community = &pctrl->communities[i];
1098 base = community->regs;
1100 for (gpp = 0; gpp < community->ngpps; gpp++) {
1101 /* Mask and clear all interrupts */
1102 writel(0, base + community->ie_offset + gpp * 4);
1103 writel(0xffff, base + GPI_IS + gpp * 4);
1108 int intel_pinctrl_resume(struct device *dev)
1110 struct platform_device *pdev = to_platform_device(dev);
1111 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1112 const struct intel_community_context *communities;
1113 const struct intel_pad_context *pads;
1114 int i;
1116 /* Mask all interrupts */
1117 intel_gpio_irq_init(pctrl);
1119 pads = pctrl->context.pads;
1120 for (i = 0; i < pctrl->soc->npins; i++) {
1121 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1122 void __iomem *padcfg;
1123 u32 val;
1125 if (!intel_pad_usable(pctrl, desc->number))
1126 continue;
1128 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1129 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1130 if (val != pads[i].padcfg0) {
1131 writel(pads[i].padcfg0, padcfg);
1132 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1133 desc->number, readl(padcfg));
1136 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1137 val = readl(padcfg);
1138 if (val != pads[i].padcfg1) {
1139 writel(pads[i].padcfg1, padcfg);
1140 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1141 desc->number, readl(padcfg));
1145 communities = pctrl->context.communities;
1146 for (i = 0; i < pctrl->ncommunities; i++) {
1147 struct intel_community *community = &pctrl->communities[i];
1148 void __iomem *base;
1149 unsigned gpp;
1151 base = community->regs + community->ie_offset;
1152 for (gpp = 0; gpp < community->ngpps; gpp++) {
1153 writel(communities[i].intmask[gpp], base + gpp * 4);
1154 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1155 readl(base + gpp * 4));
1159 return 0;
1161 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1162 #endif
1164 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1165 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1166 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1167 MODULE_LICENSE("GPL v2");