drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c

   1 /*
   2  * Copyright (c) 2015, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21 #include <linux/slab.h>
  22 #include <linux/regmap.h>
  23 #include <linux/gpio.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27
  28 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  29
  30 #include "../core.h"
  31 #include "../pinctrl-utils.h"
  32
  33 /* mode */
  34 #define PM8XXX_GPIO_MODE_ENABLED        BIT(0)
  35 #define PM8XXX_GPIO_MODE_INPUT          0
  36 #define PM8XXX_GPIO_MODE_OUTPUT         2
  37
  38 /* output buffer */
  39 #define PM8XXX_GPIO_PUSH_PULL           0
  40 #define PM8XXX_GPIO_OPEN_DRAIN          1
  41
  42 /* bias */
  43 #define PM8XXX_GPIO_BIAS_PU_30          0
  44 #define PM8XXX_GPIO_BIAS_PU_1P5         1
  45 #define PM8XXX_GPIO_BIAS_PU_31P5        2
  46 #define PM8XXX_GPIO_BIAS_PU_1P5_30      3
  47 #define PM8XXX_GPIO_BIAS_PD             4
  48 #define PM8XXX_GPIO_BIAS_NP             5
  49
  50 /* GPIO registers */
  51 #define SSBI_REG_ADDR_GPIO_BASE         0x150
  52 #define SSBI_REG_ADDR_GPIO(n)           (SSBI_REG_ADDR_GPIO_BASE + n)
  53
  54 #define PM8XXX_BANK_WRITE               BIT(7)
  55
  56 #define PM8XXX_MAX_GPIOS               44
  57
  58 /* custom pinconf parameters */
  59 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
  60 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
  61
  62 /**
  63  * struct pm8xxx_pin_data - dynamic configuration for a pin
  64  * @reg:               address of the control register
  65  * @irq:               IRQ from the PMIC interrupt controller
  66  * @power_source:      logical selected voltage source, mapping in static data
  67  *                     is used translate to register values
  68  * @mode:              operating mode for the pin (input/output)
  69  * @open_drain:        output buffer configured as open-drain (vs push-pull)
  70  * @output_value:      configured output value
  71  * @bias:              register view of configured bias
  72  * @pull_up_strength:  placeholder for selected pull up strength
  73  *                     only used to configure bias when pull up is selected
  74  * @output_strength:   selector of output-strength
  75  * @disable:           pin disabled / configured as tristate
  76  * @function:          pinmux selector
  77  * @inverted:          pin logic is inverted
  78  */
  79 struct pm8xxx_pin_data {
  80         unsigned reg;
  81         int irq;
  82         u8 power_source;
  83         u8 mode;
  84         bool open_drain;
  85         bool output_value;
  86         u8 bias;
  87         u8 pull_up_strength;
  88         u8 output_strength;
  89         bool disable;
  90         u8 function;
  91         bool inverted;
  92 };
  93
  94 struct pm8xxx_gpio {
  95         struct device *dev;
  96         struct regmap *regmap;
  97         struct pinctrl_dev *pctrl;
  98         struct gpio_chip chip;
  99
 100         struct pinctrl_desc desc;
 101         unsigned npins;
 102 };
 103
 104 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
 105         {"qcom,drive-strength",         PM8XXX_QCOM_DRIVE_STRENGH,      0},
 106         {"qcom,pull-up-strength",       PM8XXX_QCOM_PULL_UP_STRENGTH,   0},
 107 };
 108
 109 #ifdef CONFIG_DEBUG_FS
 110 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
 111         PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
 112         PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
 113 };
 114 #endif
 115
 116 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
 117         "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 118         "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 119         "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 120         "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 121         "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 122         "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 123         "gpio44",
 124 };
 125
 126 static const char * const pm8xxx_gpio_functions[] = {
 127         PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
 128         PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
 129         PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
 130         PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
 131 };
 132
 133 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
 134                             struct pm8xxx_pin_data *pin, int bank)
 135 {
 136         unsigned int val = bank << 4;
 137         int ret;
 138
 139         ret = regmap_write(pctrl->regmap, pin->reg, val);
 140         if (ret) {
 141                 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
 142                 return ret;
 143         }
 144
 145         ret = regmap_read(pctrl->regmap, pin->reg, &val);
 146         if (ret) {
 147                 dev_err(pctrl->dev, "failed to read register %d\n", bank);
 148                 return ret;
 149         }
 150
 151         return val;
 152 }
 153
 154 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
 155                              struct pm8xxx_pin_data *pin,
 156                              int bank,
 157                              u8 val)
 158 {
 159         int ret;
 160
 161         val |= PM8XXX_BANK_WRITE;
 162         val |= bank << 4;
 163
 164         ret = regmap_write(pctrl->regmap, pin->reg, val);
 165         if (ret)
 166                 dev_err(pctrl->dev, "failed to write register\n");
 167
 168         return ret;
 169 }
 170
 171 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
 172 {
 173         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 174
 175         return pctrl->npins;
 176 }
 177
 178 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
 179                                          unsigned group)
 180 {
 181         return pm8xxx_groups[group];
 182 }
 183
 184
 185 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
 186                                  unsigned group,
 187                                  const unsigned **pins,
 188                                  unsigned *num_pins)
 189 {
 190         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 191
 192         *pins = &pctrl->desc.pins[group].number;
 193         *num_pins = 1;
 194
 195         return 0;
 196 }
 197
 198 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
 199         .get_groups_count       = pm8xxx_get_groups_count,
 200         .get_group_name         = pm8xxx_get_group_name,
 201         .get_group_pins         = pm8xxx_get_group_pins,
 202         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 203         .dt_free_map            = pinctrl_utils_dt_free_map,
 204 };
 205
 206 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
 207 {
 208         return ARRAY_SIZE(pm8xxx_gpio_functions);
 209 }
 210
 211 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
 212                                             unsigned function)
 213 {
 214         return pm8xxx_gpio_functions[function];
 215 }
 216
 217 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
 218                                       unsigned function,
 219                                       const char * const **groups,
 220                                       unsigned * const num_groups)
 221 {
 222         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 223
 224         *groups = pm8xxx_groups;
 225         *num_groups = pctrl->npins;
 226         return 0;
 227 }
 228
 229 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
 230                                  unsigned function,
 231                                  unsigned group)
 232 {
 233         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 234         struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
 235         u8 val;
 236
 237         pin->function = function;
 238         val = pin->function << 1;
 239
 240         pm8xxx_write_bank(pctrl, pin, 4, val);
 241
 242         return 0;
 243 }
 244
 245 static const struct pinmux_ops pm8xxx_pinmux_ops = {
 246         .get_functions_count    = pm8xxx_get_functions_count,
 247         .get_function_name      = pm8xxx_get_function_name,
 248         .get_function_groups    = pm8xxx_get_function_groups,
 249         .set_mux                = pm8xxx_pinmux_set_mux,
 250 };
 251
 252 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
 253                                  unsigned int offset,
 254                                  unsigned long *config)
 255 {
 256         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 257         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 258         unsigned param = pinconf_to_config_param(*config);
 259         unsigned arg;
 260
 261         switch (param) {
 262         case PIN_CONFIG_BIAS_DISABLE:
 263                 arg = pin->bias == PM8XXX_GPIO_BIAS_NP;
 264                 break;
 265         case PIN_CONFIG_BIAS_PULL_DOWN:
 266                 arg = pin->bias == PM8XXX_GPIO_BIAS_PD;
 267                 break;
 268         case PIN_CONFIG_BIAS_PULL_UP:
 269                 arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30;
 270                 break;
 271         case PM8XXX_QCOM_PULL_UP_STRENGTH:
 272                 arg = pin->pull_up_strength;
 273                 break;
 274         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 275                 arg = pin->disable;
 276                 break;
 277         case PIN_CONFIG_INPUT_ENABLE:
 278                 arg = pin->mode == PM8XXX_GPIO_MODE_INPUT;
 279                 break;
 280         case PIN_CONFIG_OUTPUT:
 281                 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
 282                         arg = pin->output_value;
 283                 else
 284                         arg = 0;
 285                 break;
 286         case PIN_CONFIG_POWER_SOURCE:
 287                 arg = pin->power_source;
 288                 break;
 289         case PM8XXX_QCOM_DRIVE_STRENGH:
 290                 arg = pin->output_strength;
 291                 break;
 292         case PIN_CONFIG_DRIVE_PUSH_PULL:
 293                 arg = !pin->open_drain;
 294                 break;
 295         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 296                 arg = pin->open_drain;
 297                 break;
 298         default:
 299                 return -EINVAL;
 300         }
 301
 302         *config = pinconf_to_config_packed(param, arg);
 303
 304         return 0;
 305 }
 306
 307 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
 308                                  unsigned int offset,
 309                                  unsigned long *configs,
 310                                  unsigned num_configs)
 311 {
 312         struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
 313         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 314         unsigned param;
 315         unsigned arg;
 316         unsigned i;
 317         u8 banks = 0;
 318         u8 val;
 319
 320         for (i = 0; i < num_configs; i++) {
 321                 param = pinconf_to_config_param(configs[i]);
 322                 arg = pinconf_to_config_argument(configs[i]);
 323
 324                 switch (param) {
 325                 case PIN_CONFIG_BIAS_DISABLE:
 326                         pin->bias = PM8XXX_GPIO_BIAS_NP;
 327                         banks |= BIT(2);
 328                         pin->disable = 0;
 329                         banks |= BIT(3);
 330                         break;
 331                 case PIN_CONFIG_BIAS_PULL_DOWN:
 332                         pin->bias = PM8XXX_GPIO_BIAS_PD;
 333                         banks |= BIT(2);
 334                         pin->disable = 0;
 335                         banks |= BIT(3);
 336                         break;
 337                 case PM8XXX_QCOM_PULL_UP_STRENGTH:
 338                         if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
 339                                 dev_err(pctrl->dev, "invalid pull-up strength\n");
 340                                 return -EINVAL;
 341                         }
 342                         pin->pull_up_strength = arg;
 343                         /* FALLTHROUGH */
 344                 case PIN_CONFIG_BIAS_PULL_UP:
 345                         pin->bias = pin->pull_up_strength;
 346                         banks |= BIT(2);
 347                         pin->disable = 0;
 348                         banks |= BIT(3);
 349                         break;
 350                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 351                         pin->disable = 1;
 352                         banks |= BIT(3);
 353                         break;
 354                 case PIN_CONFIG_INPUT_ENABLE:
 355                         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 356                         banks |= BIT(0) | BIT(1);
 357                         break;
 358                 case PIN_CONFIG_OUTPUT:
 359                         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 360                         pin->output_value = !!arg;
 361                         banks |= BIT(0) | BIT(1);
 362                         break;
 363                 case PIN_CONFIG_POWER_SOURCE:
 364                         pin->power_source = arg;
 365                         banks |= BIT(0);
 366                         break;
 367                 case PM8XXX_QCOM_DRIVE_STRENGH:
 368                         if (arg > PMIC_GPIO_STRENGTH_LOW) {
 369                                 dev_err(pctrl->dev, "invalid drive strength\n");
 370                                 return -EINVAL;
 371                         }
 372                         pin->output_strength = arg;
 373                         banks |= BIT(3);
 374                         break;
 375                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 376                         pin->open_drain = 0;
 377                         banks |= BIT(1);
 378                         break;
 379                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 380                         pin->open_drain = 1;
 381                         banks |= BIT(1);
 382                         break;
 383                 default:
 384                         dev_err(pctrl->dev,
 385                                 "unsupported config parameter: %x\n",
 386                                 param);
 387                         return -EINVAL;
 388                 }
 389         }
 390
 391         if (banks & BIT(0)) {
 392                 val = pin->power_source << 1;
 393                 val |= PM8XXX_GPIO_MODE_ENABLED;
 394                 pm8xxx_write_bank(pctrl, pin, 0, val);
 395         }
 396
 397         if (banks & BIT(1)) {
 398                 val = pin->mode << 2;
 399                 val |= pin->open_drain << 1;
 400                 val |= pin->output_value;
 401                 pm8xxx_write_bank(pctrl, pin, 1, val);
 402         }
 403
 404         if (banks & BIT(2)) {
 405                 val = pin->bias << 1;
 406                 pm8xxx_write_bank(pctrl, pin, 2, val);
 407         }
 408
 409         if (banks & BIT(3)) {
 410                 val = pin->output_strength << 2;
 411                 val |= pin->disable;
 412                 pm8xxx_write_bank(pctrl, pin, 3, val);
 413         }
 414
 415         if (banks & BIT(4)) {
 416                 val = pin->function << 1;
 417                 pm8xxx_write_bank(pctrl, pin, 4, val);
 418         }
 419
 420         if (banks & BIT(5)) {
 421                 val = 0;
 422                 if (!pin->inverted)
 423                         val |= BIT(3);
 424                 pm8xxx_write_bank(pctrl, pin, 5, val);
 425         }
 426
 427         return 0;
 428 }
 429
 430 static const struct pinconf_ops pm8xxx_pinconf_ops = {
 431         .is_generic = true,
 432         .pin_config_group_get = pm8xxx_pin_config_get,
 433         .pin_config_group_set = pm8xxx_pin_config_set,
 434 };
 435
 436 static struct pinctrl_desc pm8xxx_pinctrl_desc = {
 437         .name = "pm8xxx_gpio",
 438         .pctlops = &pm8xxx_pinctrl_ops,
 439         .pmxops = &pm8xxx_pinmux_ops,
 440         .confops = &pm8xxx_pinconf_ops,
 441         .owner = THIS_MODULE,
 442 };
 443
 444 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
 445                                        unsigned offset)
 446 {
 447         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 448         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 449         u8 val;
 450
 451         pin->mode = PM8XXX_GPIO_MODE_INPUT;
 452         val = pin->mode << 2;
 453
 454         pm8xxx_write_bank(pctrl, pin, 1, val);
 455
 456         return 0;
 457 }
 458
 459 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
 460                                         unsigned offset,
 461                                         int value)
 462 {
 463         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 464         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 465         u8 val;
 466
 467         pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
 468         pin->output_value = !!value;
 469
 470         val = pin->mode << 2;
 471         val |= pin->open_drain << 1;
 472         val |= pin->output_value;
 473
 474         pm8xxx_write_bank(pctrl, pin, 1, val);
 475
 476         return 0;
 477 }
 478
 479 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
 480 {
 481         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 482         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 483         bool state;
 484         int ret;
 485
 486         if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
 487                 ret = pin->output_value;
 488         } else {
 489                 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
 490                 if (!ret)
 491                         ret = !!state;
 492         }
 493
 494         return ret;
 495 }
 496
 497 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 498 {
 499         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 500         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 501         u8 val;
 502
 503         pin->output_value = !!value;
 504
 505         val = pin->mode << 2;
 506         val |= pin->open_drain << 1;
 507         val |= pin->output_value;
 508
 509         pm8xxx_write_bank(pctrl, pin, 1, val);
 510 }
 511
 512 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
 513                                 const struct of_phandle_args *gpio_desc,
 514                                 u32 *flags)
 515 {
 516         if (chip->of_gpio_n_cells < 2)
 517                 return -EINVAL;
 518
 519         if (flags)
 520                 *flags = gpio_desc->args[1];
 521
 522         return gpio_desc->args[0] - 1;
 523 }
 524
 525
 526 static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 527 {
 528         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 529         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 530
 531         return pin->irq;
 532 }
 533
 534 #ifdef CONFIG_DEBUG_FS
 535 #include <linux/seq_file.h>
 536
 537 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
 538                                   struct pinctrl_dev *pctldev,
 539                                   struct gpio_chip *chip,
 540                                   unsigned offset,
 541                                   unsigned gpio)
 542 {
 543         struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
 544         struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
 545
 546         static const char * const modes[] = {
 547                 "in", "both", "out", "off"
 548         };
 549         static const char * const biases[] = {
 550                 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 551                 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 552         };
 553         static const char * const buffer_types[] = {
 554                 "push-pull", "open-drain"
 555         };
 556         static const char * const strengths[] = {
 557                 "no", "high", "medium", "low"
 558         };
 559
 560         seq_printf(s, " gpio%-2d:", offset + 1);
 561         if (pin->disable) {
 562                 seq_puts(s, " ---");
 563         } else {
 564                 seq_printf(s, " %-4s", modes[pin->mode]);
 565                 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
 566                 seq_printf(s, " VIN%d", pin->power_source);
 567                 seq_printf(s, " %-27s", biases[pin->bias]);
 568                 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
 569                 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
 570                 seq_printf(s, " %-7s", strengths[pin->output_strength]);
 571                 if (pin->inverted)
 572                         seq_puts(s, " inverted");
 573         }
 574 }
 575
 576 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 577 {
 578         unsigned gpio = chip->base;
 579         unsigned i;
 580
 581         for (i = 0; i < chip->ngpio; i++, gpio++) {
 582                 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 583                 seq_puts(s, "\n");
 584         }
 585 }
 586
 587 #else
 588 #define pm8xxx_gpio_dbg_show NULL
 589 #endif
 590
 591 static struct gpio_chip pm8xxx_gpio_template = {
 592         .direction_input = pm8xxx_gpio_direction_input,
 593         .direction_output = pm8xxx_gpio_direction_output,
 594         .get = pm8xxx_gpio_get,
 595         .set = pm8xxx_gpio_set,
 596         .of_xlate = pm8xxx_gpio_of_xlate,
 597         .to_irq = pm8xxx_gpio_to_irq,
 598         .dbg_show = pm8xxx_gpio_dbg_show,
 599         .owner = THIS_MODULE,
 600 };
 601
 602 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
 603                                struct pm8xxx_pin_data *pin)
 604 {
 605         int val;
 606
 607         val = pm8xxx_read_bank(pctrl, pin, 0);
 608         if (val < 0)
 609                 return val;
 610
 611         pin->power_source = (val >> 1) & 0x7;
 612
 613         val = pm8xxx_read_bank(pctrl, pin, 1);
 614         if (val < 0)
 615                 return val;
 616
 617         pin->mode = (val >> 2) & 0x3;
 618         pin->open_drain = !!(val & BIT(1));
 619         pin->output_value = val & BIT(0);
 620
 621         val = pm8xxx_read_bank(pctrl, pin, 2);
 622         if (val < 0)
 623                 return val;
 624
 625         pin->bias = (val >> 1) & 0x7;
 626         if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
 627                 pin->pull_up_strength = pin->bias;
 628         else
 629                 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
 630
 631         val = pm8xxx_read_bank(pctrl, pin, 3);
 632         if (val < 0)
 633                 return val;
 634
 635         pin->output_strength = (val >> 2) & 0x3;
 636         pin->disable = val & BIT(0);
 637
 638         val = pm8xxx_read_bank(pctrl, pin, 4);
 639         if (val < 0)
 640                 return val;
 641
 642         pin->function = (val >> 1) & 0x7;
 643
 644         val = pm8xxx_read_bank(pctrl, pin, 5);
 645         if (val < 0)
 646                 return val;
 647
 648         pin->inverted = !(val & BIT(3));
 649
 650         return 0;
 651 }
 652
 653 static const struct of_device_id pm8xxx_gpio_of_match[] = {
 654         { .compatible = "qcom,pm8018-gpio" },
 655         { .compatible = "qcom,pm8038-gpio" },
 656         { .compatible = "qcom,pm8058-gpio" },
 657         { .compatible = "qcom,pm8917-gpio" },
 658         { .compatible = "qcom,pm8921-gpio" },
 659         { .compatible = "qcom,ssbi-gpio" },
 660         { },
 661 };
 662 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
 663
 664 static int pm8xxx_gpio_probe(struct platform_device *pdev)
 665 {
 666         struct pm8xxx_pin_data *pin_data;
 667         struct pinctrl_pin_desc *pins;
 668         struct pm8xxx_gpio *pctrl;
 669         int ret;
 670         int i, npins;
 671
 672         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 673         if (!pctrl)
 674                 return -ENOMEM;
 675
 676         pctrl->dev = &pdev->dev;
 677         npins = platform_irq_count(pdev);
 678         if (!npins)
 679                 return -EINVAL;
 680         if (npins < 0)
 681                 return npins;
 682         pctrl->npins = npins;
 683
 684         pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
 685         if (!pctrl->regmap) {
 686                 dev_err(&pdev->dev, "parent regmap unavailable\n");
 687                 return -ENXIO;
 688         }
 689
 690         pctrl->desc = pm8xxx_pinctrl_desc;
 691         pctrl->desc.npins = pctrl->npins;
 692
 693         pins = devm_kcalloc(&pdev->dev,
 694                             pctrl->desc.npins,
 695                             sizeof(struct pinctrl_pin_desc),
 696                             GFP_KERNEL);
 697         if (!pins)
 698                 return -ENOMEM;
 699
 700         pin_data = devm_kcalloc(&pdev->dev,
 701                                 pctrl->desc.npins,
 702                                 sizeof(struct pm8xxx_pin_data),
 703                                 GFP_KERNEL);
 704         if (!pin_data)
 705                 return -ENOMEM;
 706
 707         for (i = 0; i < pctrl->desc.npins; i++) {
 708                 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
 709                 pin_data[i].irq = platform_get_irq(pdev, i);
 710                 if (pin_data[i].irq < 0) {
 711                         dev_err(&pdev->dev,
 712                                 "missing interrupts for pin %d\n", i);
 713                         return pin_data[i].irq;
 714                 }
 715
 716                 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
 717                 if (ret)
 718                         return ret;
 719
 720                 pins[i].number = i;
 721                 pins[i].name = pm8xxx_groups[i];
 722                 pins[i].drv_data = &pin_data[i];
 723         }
 724         pctrl->desc.pins = pins;
 725
 726         pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
 727         pctrl->desc.custom_params = pm8xxx_gpio_bindings;
 728 #ifdef CONFIG_DEBUG_FS
 729         pctrl->desc.custom_conf_items = pm8xxx_conf_items;
 730 #endif
 731
 732         pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
 733         if (IS_ERR(pctrl->pctrl)) {
 734                 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
 735                 return PTR_ERR(pctrl->pctrl);
 736         }
 737
 738         pctrl->chip = pm8xxx_gpio_template;
 739         pctrl->chip.base = -1;
 740         pctrl->chip.parent = &pdev->dev;
 741         pctrl->chip.of_node = pdev->dev.of_node;
 742         pctrl->chip.of_gpio_n_cells = 2;
 743         pctrl->chip.label = dev_name(pctrl->dev);
 744         pctrl->chip.ngpio = pctrl->npins;
 745         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 746         if (ret) {
 747                 dev_err(&pdev->dev, "failed register gpiochip\n");
 748                 goto unregister_pinctrl;
 749         }
 750
 751         ret = gpiochip_add_pin_range(&pctrl->chip,
 752                                      dev_name(pctrl->dev),
 753                                      0, 0, pctrl->chip.ngpio);
 754         if (ret) {
 755                 dev_err(pctrl->dev, "failed to add pin range\n");
 756                 goto unregister_gpiochip;
 757         }
 758
 759         platform_set_drvdata(pdev, pctrl);
 760
 761         dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
 762
 763         return 0;
 764
 765 unregister_gpiochip:
 766         gpiochip_remove(&pctrl->chip);
 767
 768 unregister_pinctrl:
 769         pinctrl_unregister(pctrl->pctrl);
 770
 771         return ret;
 772 }
 773
 774 static int pm8xxx_gpio_remove(struct platform_device *pdev)
 775 {
 776         struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
 777
 778         gpiochip_remove(&pctrl->chip);
 779
 780         pinctrl_unregister(pctrl->pctrl);
 781
 782         return 0;
 783 }
 784
 785 static struct platform_driver pm8xxx_gpio_driver = {
 786         .driver = {
 787                 .name = "qcom-ssbi-gpio",
 788                 .of_match_table = pm8xxx_gpio_of_match,
 789         },
 790         .probe = pm8xxx_gpio_probe,
 791         .remove = pm8xxx_gpio_remove,
 792 };
 793
 794 module_platform_driver(pm8xxx_gpio_driver);
 795
 796 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
 797 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
 798 MODULE_LICENSE("GPL v2");