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[linux/fpc-iii.git] / drivers / dma / xilinx / xilinx_dma.c
blobcd271f78260516483aa792d4a7a621c3afbdc09f
1 /*
2 * DMA driver for Xilinx Video DMA Engine
3 *
4 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
5 *
6 * Based on the Freescale DMA driver.
7 *
8 * Description:
9 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
10 * core that provides high-bandwidth direct memory access between memory
11 * and AXI4-Stream type video target peripherals. The core provides efficient
12 * two dimensional DMA operations with independent asynchronous read (S2MM)
13 * and write (MM2S) channel operation. It can be configured to have either
14 * one channel or two channels. If configured as two channels, one is to
15 * transmit to the video device (MM2S) and another is to receive from the
16 * video device (S2MM). Initialization, status, interrupt and management
17 * registers are accessed through an AXI4-Lite slave interface.
18 *
19 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
20 * provides high-bandwidth one dimensional direct memory access between memory
21 * and AXI4-Stream target peripherals. It supports one receive and one
22 * transmit channel, both of them optional at synthesis time.
23 *
24 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
25 * Access (DMA) between a memory-mapped source address and a memory-mapped
26 * destination address.
27 *
28 * This program is free software: you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License as published by
30 * the Free Software Foundation, either version 2 of the License, or
31 * (at your option) any later version.
32 */
33
34 #include <linux/bitops.h>
35 #include <linux/dmapool.h>
36 #include <linux/dma/xilinx_dma.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/iopoll.h>
41 #include <linux/module.h>
42 #include <linux/of_address.h>
43 #include <linux/of_dma.h>
44 #include <linux/of_platform.h>
45 #include <linux/of_irq.h>
46 #include <linux/slab.h>
47 #include <linux/clk.h>
48 #include <linux/io-64-nonatomic-lo-hi.h>
49
50 #include "../dmaengine.h"
51
52 /* Register/Descriptor Offsets */
53 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
54 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
55 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
56 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
57
58 /* Control Registers */
59 #define XILINX_DMA_REG_DMACR 0x0000
60 #define XILINX_DMA_DMACR_DELAY_MAX 0xff
61 #define XILINX_DMA_DMACR_DELAY_SHIFT 24
62 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
63 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
64 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
65 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
66 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
67 #define XILINX_DMA_DMACR_MASTER_SHIFT 8
68 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
69 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
70 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
71 #define XILINX_DMA_DMACR_RESET BIT(2)
72 #define XILINX_DMA_DMACR_CIRC_EN BIT(1)
73 #define XILINX_DMA_DMACR_RUNSTOP BIT(0)
74 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
75 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
76 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
77 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
78
79 #define XILINX_DMA_REG_DMASR 0x0004
80 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
81 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
82 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
83 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
84 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
85 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
86 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
87 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
88 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
89 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
90 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
91 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
92 #define XILINX_DMA_DMASR_IDLE BIT(1)
93 #define XILINX_DMA_DMASR_HALTED BIT(0)
94 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
95 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
96
97 #define XILINX_DMA_REG_CURDESC 0x0008
98 #define XILINX_DMA_REG_TAILDESC 0x0010
99 #define XILINX_DMA_REG_REG_INDEX 0x0014
100 #define XILINX_DMA_REG_FRMSTORE 0x0018
101 #define XILINX_DMA_REG_THRESHOLD 0x001c
102 #define XILINX_DMA_REG_FRMPTR_STS 0x0024
103 #define XILINX_DMA_REG_PARK_PTR 0x0028
104 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
105 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
106 #define XILINX_DMA_REG_VDMA_VERSION 0x002c
107
108 /* Register Direct Mode Registers */
109 #define XILINX_DMA_REG_VSIZE 0x0000
110 #define XILINX_DMA_REG_HSIZE 0x0004
111
112 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
113 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
114 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
115
116 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
117 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
118
119 /* HW specific definitions */
120 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
121
122 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
123 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
124 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
125 XILINX_DMA_DMASR_ERR_IRQ)
126
127 #define XILINX_DMA_DMASR_ALL_ERR_MASK \
128 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
129 XILINX_DMA_DMASR_SOF_LATE_ERR | \
130 XILINX_DMA_DMASR_SG_DEC_ERR | \
131 XILINX_DMA_DMASR_SG_SLV_ERR | \
132 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
133 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
134 XILINX_DMA_DMASR_DMA_DEC_ERR | \
135 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
136 XILINX_DMA_DMASR_DMA_INT_ERR)
137
138 /*
139 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
140 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
141 * is enabled in the h/w system.
142 */
143 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
144 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
145 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
146 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
147 XILINX_DMA_DMASR_DMA_INT_ERR)
148
149 /* Axi VDMA Flush on Fsync bits */
150 #define XILINX_DMA_FLUSH_S2MM 3
151 #define XILINX_DMA_FLUSH_MM2S 2
152 #define XILINX_DMA_FLUSH_BOTH 1
153
154 /* Delay loop counter to prevent hardware failure */
155 #define XILINX_DMA_LOOP_COUNT 1000000
156
157 /* AXI DMA Specific Registers/Offsets */
158 #define XILINX_DMA_REG_SRCDSTADDR 0x18
159 #define XILINX_DMA_REG_BTT 0x28
160
161 /* AXI DMA Specific Masks/Bit fields */
162 #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0)
163 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
164 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
165 #define XILINX_DMA_CR_COALESCE_SHIFT 16
166 #define XILINX_DMA_BD_SOP BIT(27)
167 #define XILINX_DMA_BD_EOP BIT(26)
168 #define XILINX_DMA_COALESCE_MAX 255
169 #define XILINX_DMA_NUM_APP_WORDS 5
170
171 /* Multi-Channel DMA Descriptor offsets*/
172 #define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20)
173 #define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20)
174
175 /* Multi-Channel DMA Masks/Shifts */
176 #define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0)
177 #define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0)
178 #define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19)
179 #define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0)
180 #define XILINX_DMA_BD_STRIDE_SHIFT 0
181 #define XILINX_DMA_BD_VSIZE_SHIFT 19
182
183 /* AXI CDMA Specific Registers/Offsets */
184 #define XILINX_CDMA_REG_SRCADDR 0x18
185 #define XILINX_CDMA_REG_DSTADDR 0x20
186
187 /* AXI CDMA Specific Masks */
188 #define XILINX_CDMA_CR_SGMODE BIT(3)
189
190 /**
191 * struct xilinx_vdma_desc_hw - Hardware Descriptor
192 * @next_desc: Next Descriptor Pointer @0x00
193 * @pad1: Reserved @0x04
194 * @buf_addr: Buffer address @0x08
195 * @buf_addr_msb: MSB of Buffer address @0x0C
196 * @vsize: Vertical Size @0x10
197 * @hsize: Horizontal Size @0x14
198 * @stride: Number of bytes between the first
199 * pixels of each horizontal line @0x18
200 */
201 struct xilinx_vdma_desc_hw {
202 u32 next_desc;
203 u32 pad1;
204 u32 buf_addr;
205 u32 buf_addr_msb;
206 u32 vsize;
207 u32 hsize;
208 u32 stride;
209 } __aligned(64);
210
211 /**
212 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
213 * @next_desc: Next Descriptor Pointer @0x00
214 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
215 * @buf_addr: Buffer address @0x08
216 * @buf_addr_msb: MSB of Buffer address @0x0C
217 * @pad1: Reserved @0x10
218 * @pad2: Reserved @0x14
219 * @control: Control field @0x18
220 * @status: Status field @0x1C
221 * @app: APP Fields @0x20 - 0x30
222 */
223 struct xilinx_axidma_desc_hw {
224 u32 next_desc;
225 u32 next_desc_msb;
226 u32 buf_addr;
227 u32 buf_addr_msb;
228 u32 mcdma_control;
229 u32 vsize_stride;
230 u32 control;
231 u32 status;
232 u32 app[XILINX_DMA_NUM_APP_WORDS];
233 } __aligned(64);
234
235 /**
236 * struct xilinx_cdma_desc_hw - Hardware Descriptor
237 * @next_desc: Next Descriptor Pointer @0x00
238 * @next_descmsb: Next Descriptor Pointer MSB @0x04
239 * @src_addr: Source address @0x08
240 * @src_addrmsb: Source address MSB @0x0C
241 * @dest_addr: Destination address @0x10
242 * @dest_addrmsb: Destination address MSB @0x14
243 * @control: Control field @0x18
244 * @status: Status field @0x1C
245 */
246 struct xilinx_cdma_desc_hw {
247 u32 next_desc;
248 u32 next_desc_msb;
249 u32 src_addr;
250 u32 src_addr_msb;
251 u32 dest_addr;
252 u32 dest_addr_msb;
253 u32 control;
254 u32 status;
255 } __aligned(64);
256
257 /**
258 * struct xilinx_vdma_tx_segment - Descriptor segment
259 * @hw: Hardware descriptor
260 * @node: Node in the descriptor segments list
261 * @phys: Physical address of segment
262 */
263 struct xilinx_vdma_tx_segment {
264 struct xilinx_vdma_desc_hw hw;
265 struct list_head node;
266 dma_addr_t phys;
267 } __aligned(64);
268
269 /**
270 * struct xilinx_axidma_tx_segment - Descriptor segment
271 * @hw: Hardware descriptor
272 * @node: Node in the descriptor segments list
273 * @phys: Physical address of segment
274 */
275 struct xilinx_axidma_tx_segment {
276 struct xilinx_axidma_desc_hw hw;
277 struct list_head node;
278 dma_addr_t phys;
279 } __aligned(64);
280
281 /**
282 * struct xilinx_cdma_tx_segment - Descriptor segment
283 * @hw: Hardware descriptor
284 * @node: Node in the descriptor segments list
285 * @phys: Physical address of segment
286 */
287 struct xilinx_cdma_tx_segment {
288 struct xilinx_cdma_desc_hw hw;
289 struct list_head node;
290 dma_addr_t phys;
291 } __aligned(64);
292
293 /**
294 * struct xilinx_dma_tx_descriptor - Per Transaction structure
295 * @async_tx: Async transaction descriptor
296 * @segments: TX segments list
297 * @node: Node in the channel descriptors list
298 * @cyclic: Check for cyclic transfers.
299 */
300 struct xilinx_dma_tx_descriptor {
301 struct dma_async_tx_descriptor async_tx;
302 struct list_head segments;
303 struct list_head node;
304 bool cyclic;
305 };
306
307 /**
308 * struct xilinx_dma_chan - Driver specific DMA channel structure
309 * @xdev: Driver specific device structure
310 * @ctrl_offset: Control registers offset
311 * @desc_offset: TX descriptor registers offset
312 * @lock: Descriptor operation lock
313 * @pending_list: Descriptors waiting
314 * @active_list: Descriptors ready to submit
315 * @done_list: Complete descriptors
316 * @common: DMA common channel
317 * @desc_pool: Descriptors pool
318 * @dev: The dma device
319 * @irq: Channel IRQ
320 * @id: Channel ID
321 * @direction: Transfer direction
322 * @num_frms: Number of frames
323 * @has_sg: Support scatter transfers
324 * @cyclic: Check for cyclic transfers.
325 * @genlock: Support genlock mode
326 * @err: Channel has errors
327 * @tasklet: Cleanup work after irq
328 * @config: Device configuration info
329 * @flush_on_fsync: Flush on Frame sync
330 * @desc_pendingcount: Descriptor pending count
331 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
332 * @desc_submitcount: Descriptor h/w submitted count
333 * @residue: Residue for AXI DMA
334 * @seg_v: Statically allocated segments base
335 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
336 * @start_transfer: Differentiate b/w DMA IP's transfer
337 */
338 struct xilinx_dma_chan {
339 struct xilinx_dma_device *xdev;
340 u32 ctrl_offset;
341 u32 desc_offset;
342 spinlock_t lock;
343 struct list_head pending_list;
344 struct list_head active_list;
345 struct list_head done_list;
346 struct dma_chan common;
347 struct dma_pool *desc_pool;
348 struct device *dev;
349 int irq;
350 int id;
351 enum dma_transfer_direction direction;
352 int num_frms;
353 bool has_sg;
354 bool cyclic;
355 bool genlock;
356 bool err;
357 struct tasklet_struct tasklet;
358 struct xilinx_vdma_config config;
359 bool flush_on_fsync;
360 u32 desc_pendingcount;
361 bool ext_addr;
362 u32 desc_submitcount;
363 u32 residue;
364 struct xilinx_axidma_tx_segment *seg_v;
365 struct xilinx_axidma_tx_segment *cyclic_seg_v;
366 void (*start_transfer)(struct xilinx_dma_chan *chan);
367 u16 tdest;
368 };
369
370 struct xilinx_dma_config {
371 enum xdma_ip_type dmatype;
372 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
373 struct clk **tx_clk, struct clk **txs_clk,
374 struct clk **rx_clk, struct clk **rxs_clk);
375 };
376
377 /**
378 * struct xilinx_dma_device - DMA device structure
379 * @regs: I/O mapped base address
380 * @dev: Device Structure
381 * @common: DMA device structure
382 * @chan: Driver specific DMA channel
383 * @has_sg: Specifies whether Scatter-Gather is present or not
384 * @mcdma: Specifies whether Multi-Channel is present or not
385 * @flush_on_fsync: Flush on frame sync
386 * @ext_addr: Indicates 64 bit addressing is supported by dma device
387 * @pdev: Platform device structure pointer
388 * @dma_config: DMA config structure
389 * @axi_clk: DMA Axi4-lite interace clock
390 * @tx_clk: DMA mm2s clock
391 * @txs_clk: DMA mm2s stream clock
392 * @rx_clk: DMA s2mm clock
393 * @rxs_clk: DMA s2mm stream clock
394 * @nr_channels: Number of channels DMA device supports
395 * @chan_id: DMA channel identifier
396 */
397 struct xilinx_dma_device {
398 void __iomem *regs;
399 struct device *dev;
400 struct dma_device common;
401 struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
402 bool has_sg;
403 bool mcdma;
404 u32 flush_on_fsync;
405 bool ext_addr;
406 struct platform_device *pdev;
407 const struct xilinx_dma_config *dma_config;
408 struct clk *axi_clk;
409 struct clk *tx_clk;
410 struct clk *txs_clk;
411 struct clk *rx_clk;
412 struct clk *rxs_clk;
413 u32 nr_channels;
414 u32 chan_id;
415 };
416
417 /* Macros */
418 #define to_xilinx_chan(chan) \
419 container_of(chan, struct xilinx_dma_chan, common)
420 #define to_dma_tx_descriptor(tx) \
421 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
422 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
423 readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
424 cond, delay_us, timeout_us)
425
426 /* IO accessors */
427 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
428 {
429 return ioread32(chan->xdev->regs + reg);
430 }
431
432 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
433 {
434 iowrite32(value, chan->xdev->regs + reg);
435 }
436
437 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
438 u32 value)
439 {
440 dma_write(chan, chan->desc_offset + reg, value);
441 }
442
443 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
444 {
445 return dma_read(chan, chan->ctrl_offset + reg);
446 }
447
448 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
449 u32 value)
450 {
451 dma_write(chan, chan->ctrl_offset + reg, value);
452 }
453
454 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
455 u32 clr)
456 {
457 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
458 }
459
460 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
461 u32 set)
462 {
463 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
464 }
465
466 /**
467 * vdma_desc_write_64 - 64-bit descriptor write
468 * @chan: Driver specific VDMA channel
469 * @reg: Register to write
470 * @value_lsb: lower address of the descriptor.
471 * @value_msb: upper address of the descriptor.
472 *
473 * Since vdma driver is trying to write to a register offset which is not a
474 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
475 * instead of a single 64 bit register write.
476 */
477 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
478 u32 value_lsb, u32 value_msb)
479 {
480 /* Write the lsb 32 bits*/
481 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
482
483 /* Write the msb 32 bits */
484 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
485 }
486
487 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
488 {
489 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
490 }
491
492 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
493 dma_addr_t addr)
494 {
495 if (chan->ext_addr)
496 dma_writeq(chan, reg, addr);
497 else
498 dma_ctrl_write(chan, reg, addr);
499 }
500
501 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
502 struct xilinx_axidma_desc_hw *hw,
503 dma_addr_t buf_addr, size_t sg_used,
504 size_t period_len)
505 {
506 if (chan->ext_addr) {
507 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
508 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
509 period_len);
510 } else {
511 hw->buf_addr = buf_addr + sg_used + period_len;
512 }
513 }
514
515 /* -----------------------------------------------------------------------------
516 * Descriptors and segments alloc and free
517 */
518
519 /**
520 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
521 * @chan: Driver specific DMA channel
522 *
523 * Return: The allocated segment on success and NULL on failure.
524 */
525 static struct xilinx_vdma_tx_segment *
526 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
527 {
528 struct xilinx_vdma_tx_segment *segment;
529 dma_addr_t phys;
530
531 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
532 if (!segment)
533 return NULL;
534
535 segment->phys = phys;
536
537 return segment;
538 }
539
540 /**
541 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
542 * @chan: Driver specific DMA channel
543 *
544 * Return: The allocated segment on success and NULL on failure.
545 */
546 static struct xilinx_cdma_tx_segment *
547 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
548 {
549 struct xilinx_cdma_tx_segment *segment;
550 dma_addr_t phys;
551
552 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
553 if (!segment)
554 return NULL;
555
556 segment->phys = phys;
557
558 return segment;
559 }
560
561 /**
562 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
563 * @chan: Driver specific DMA channel
564 *
565 * Return: The allocated segment on success and NULL on failure.
566 */
567 static struct xilinx_axidma_tx_segment *
568 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
569 {
570 struct xilinx_axidma_tx_segment *segment;
571 dma_addr_t phys;
572
573 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
574 if (!segment)
575 return NULL;
576
577 segment->phys = phys;
578
579 return segment;
580 }
581
582 /**
583 * xilinx_dma_free_tx_segment - Free transaction segment
584 * @chan: Driver specific DMA channel
585 * @segment: DMA transaction segment
586 */
587 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
588 struct xilinx_axidma_tx_segment *segment)
589 {
590 dma_pool_free(chan->desc_pool, segment, segment->phys);
591 }
592
593 /**
594 * xilinx_cdma_free_tx_segment - Free transaction segment
595 * @chan: Driver specific DMA channel
596 * @segment: DMA transaction segment
597 */
598 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
599 struct xilinx_cdma_tx_segment *segment)
600 {
601 dma_pool_free(chan->desc_pool, segment, segment->phys);
602 }
603
604 /**
605 * xilinx_vdma_free_tx_segment - Free transaction segment
606 * @chan: Driver specific DMA channel
607 * @segment: DMA transaction segment
608 */
609 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
610 struct xilinx_vdma_tx_segment *segment)
611 {
612 dma_pool_free(chan->desc_pool, segment, segment->phys);
613 }
614
615 /**
616 * xilinx_dma_tx_descriptor - Allocate transaction descriptor
617 * @chan: Driver specific DMA channel
618 *
619 * Return: The allocated descriptor on success and NULL on failure.
620 */
621 static struct xilinx_dma_tx_descriptor *
622 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
623 {
624 struct xilinx_dma_tx_descriptor *desc;
625
626 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
627 if (!desc)
628 return NULL;
629
630 INIT_LIST_HEAD(&desc->segments);
631
632 return desc;
633 }
634
635 /**
636 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
637 * @chan: Driver specific DMA channel
638 * @desc: DMA transaction descriptor
639 */
640 static void
641 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
642 struct xilinx_dma_tx_descriptor *desc)
643 {
644 struct xilinx_vdma_tx_segment *segment, *next;
645 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
646 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
647
648 if (!desc)
649 return;
650
651 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
652 list_for_each_entry_safe(segment, next, &desc->segments, node) {
653 list_del(&segment->node);
654 xilinx_vdma_free_tx_segment(chan, segment);
655 }
656 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
657 list_for_each_entry_safe(cdma_segment, cdma_next,
658 &desc->segments, node) {
659 list_del(&cdma_segment->node);
660 xilinx_cdma_free_tx_segment(chan, cdma_segment);
661 }
662 } else {
663 list_for_each_entry_safe(axidma_segment, axidma_next,
664 &desc->segments, node) {
665 list_del(&axidma_segment->node);
666 xilinx_dma_free_tx_segment(chan, axidma_segment);
667 }
668 }
669
670 kfree(desc);
671 }
672
673 /* Required functions */
674
675 /**
676 * xilinx_dma_free_desc_list - Free descriptors list
677 * @chan: Driver specific DMA channel
678 * @list: List to parse and delete the descriptor
679 */
680 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
681 struct list_head *list)
682 {
683 struct xilinx_dma_tx_descriptor *desc, *next;
684
685 list_for_each_entry_safe(desc, next, list, node) {
686 list_del(&desc->node);
687 xilinx_dma_free_tx_descriptor(chan, desc);
688 }
689 }
690
691 /**
692 * xilinx_dma_free_descriptors - Free channel descriptors
693 * @chan: Driver specific DMA channel
694 */
695 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
696 {
697 unsigned long flags;
698
699 spin_lock_irqsave(&chan->lock, flags);
700
701 xilinx_dma_free_desc_list(chan, &chan->pending_list);
702 xilinx_dma_free_desc_list(chan, &chan->done_list);
703 xilinx_dma_free_desc_list(chan, &chan->active_list);
704
705 spin_unlock_irqrestore(&chan->lock, flags);
706 }
707
708 /**
709 * xilinx_dma_free_chan_resources - Free channel resources
710 * @dchan: DMA channel
711 */
712 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
713 {
714 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
715
716 dev_dbg(chan->dev, "Free all channel resources.\n");
717
718 xilinx_dma_free_descriptors(chan);
719 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
720 xilinx_dma_free_tx_segment(chan, chan->cyclic_seg_v);
721 xilinx_dma_free_tx_segment(chan, chan->seg_v);
722 }
723 dma_pool_destroy(chan->desc_pool);
724 chan->desc_pool = NULL;
725 }
726
727 /**
728 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
729 * @chan: Driver specific dma channel
730 * @desc: dma transaction descriptor
731 * @flags: flags for spin lock
732 */
733 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
734 struct xilinx_dma_tx_descriptor *desc,
735 unsigned long *flags)
736 {
737 dma_async_tx_callback callback;
738 void *callback_param;
739
740 callback = desc->async_tx.callback;
741 callback_param = desc->async_tx.callback_param;
742 if (callback) {
743 spin_unlock_irqrestore(&chan->lock, *flags);
744 callback(callback_param);
745 spin_lock_irqsave(&chan->lock, *flags);
746 }
747 }
748
749 /**
750 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
751 * @chan: Driver specific DMA channel
752 */
753 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
754 {
755 struct xilinx_dma_tx_descriptor *desc, *next;
756 unsigned long flags;
757
758 spin_lock_irqsave(&chan->lock, flags);
759
760 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
761 struct dmaengine_desc_callback cb;
762
763 if (desc->cyclic) {
764 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
765 break;
766 }
767
768 /* Remove from the list of running transactions */
769 list_del(&desc->node);
770
771 /* Run the link descriptor callback function */
772 dmaengine_desc_get_callback(&desc->async_tx, &cb);
773 if (dmaengine_desc_callback_valid(&cb)) {
774 spin_unlock_irqrestore(&chan->lock, flags);
775 dmaengine_desc_callback_invoke(&cb, NULL);
776 spin_lock_irqsave(&chan->lock, flags);
777 }
778
779 /* Run any dependencies, then free the descriptor */
780 dma_run_dependencies(&desc->async_tx);
781 xilinx_dma_free_tx_descriptor(chan, desc);
782 }
783
784 spin_unlock_irqrestore(&chan->lock, flags);
785 }
786
787 /**
788 * xilinx_dma_do_tasklet - Schedule completion tasklet
789 * @data: Pointer to the Xilinx DMA channel structure
790 */
791 static void xilinx_dma_do_tasklet(unsigned long data)
792 {
793 struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
794
795 xilinx_dma_chan_desc_cleanup(chan);
796 }
797
798 /**
799 * xilinx_dma_alloc_chan_resources - Allocate channel resources
800 * @dchan: DMA channel
801 *
802 * Return: '0' on success and failure value on error
803 */
804 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
805 {
806 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
807
808 /* Has this channel already been allocated? */
809 if (chan->desc_pool)
810 return 0;
811
812 /*
813 * We need the descriptor to be aligned to 64bytes
814 * for meeting Xilinx VDMA specification requirement.
815 */
816 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
817 chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool",
818 chan->dev,
819 sizeof(struct xilinx_axidma_tx_segment),
820 __alignof__(struct xilinx_axidma_tx_segment),
821 0);
822 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
823 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
824 chan->dev,
825 sizeof(struct xilinx_cdma_tx_segment),
826 __alignof__(struct xilinx_cdma_tx_segment),
827 0);
828 } else {
829 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
830 chan->dev,
831 sizeof(struct xilinx_vdma_tx_segment),
832 __alignof__(struct xilinx_vdma_tx_segment),
833 0);
834 }
835
836 if (!chan->desc_pool) {
837 dev_err(chan->dev,
838 "unable to allocate channel %d descriptor pool\n",
839 chan->id);
840 return -ENOMEM;
841 }
842
843 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
844 /*
845 * For AXI DMA case after submitting a pending_list, keep
846 * an extra segment allocated so that the "next descriptor"
847 * pointer on the tail descriptor always points to a
848 * valid descriptor, even when paused after reaching taildesc.
849 * This way, it is possible to issue additional
850 * transfers without halting and restarting the channel.
851 */
852 chan->seg_v = xilinx_axidma_alloc_tx_segment(chan);
853
854 /*
855 * For cyclic DMA mode we need to program the tail Descriptor
856 * register with a value which is not a part of the BD chain
857 * so allocating a desc segment during channel allocation for
858 * programming tail descriptor.
859 */
860 chan->cyclic_seg_v = xilinx_axidma_alloc_tx_segment(chan);
861 }
862
863 dma_cookie_init(dchan);
864
865 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
866 /* For AXI DMA resetting once channel will reset the
867 * other channel as well so enable the interrupts here.
868 */
869 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
870 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
871 }
872
873 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
874 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
875 XILINX_CDMA_CR_SGMODE);
876
877 return 0;
878 }
879
880 /**
881 * xilinx_dma_tx_status - Get DMA transaction status
882 * @dchan: DMA channel
883 * @cookie: Transaction identifier
884 * @txstate: Transaction state
885 *
886 * Return: DMA transaction status
887 */
888 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
889 dma_cookie_t cookie,
890 struct dma_tx_state *txstate)
891 {
892 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
893 struct xilinx_dma_tx_descriptor *desc;
894 struct xilinx_axidma_tx_segment *segment;
895 struct xilinx_axidma_desc_hw *hw;
896 enum dma_status ret;
897 unsigned long flags;
898 u32 residue = 0;
899
900 ret = dma_cookie_status(dchan, cookie, txstate);
901 if (ret == DMA_COMPLETE || !txstate)
902 return ret;
903
904 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
905 spin_lock_irqsave(&chan->lock, flags);
906
907 desc = list_last_entry(&chan->active_list,
908 struct xilinx_dma_tx_descriptor, node);
909 if (chan->has_sg) {
910 list_for_each_entry(segment, &desc->segments, node) {
911 hw = &segment->hw;
912 residue += (hw->control - hw->status) &
913 XILINX_DMA_MAX_TRANS_LEN;
914 }
915 }
916 spin_unlock_irqrestore(&chan->lock, flags);
917
918 chan->residue = residue;
919 dma_set_residue(txstate, chan->residue);
920 }
921
922 return ret;
923 }
924
925 /**
926 * xilinx_dma_is_running - Check if DMA channel is running
927 * @chan: Driver specific DMA channel
928 *
929 * Return: '1' if running, '0' if not.
930 */
931 static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan)
932 {
933 return !(dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
934 XILINX_DMA_DMASR_HALTED) &&
935 (dma_ctrl_read(chan, XILINX_DMA_REG_DMACR) &
936 XILINX_DMA_DMACR_RUNSTOP);
937 }
938
939 /**
940 * xilinx_dma_is_idle - Check if DMA channel is idle
941 * @chan: Driver specific DMA channel
942 *
943 * Return: '1' if idle, '0' if not.
944 */
945 static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan)
946 {
947 return dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
948 XILINX_DMA_DMASR_IDLE;
949 }
950
951 /**
952 * xilinx_dma_halt - Halt DMA channel
953 * @chan: Driver specific DMA channel
954 */
955 static void xilinx_dma_halt(struct xilinx_dma_chan *chan)
956 {
957 int err;
958 u32 val;
959
960 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
961
962 /* Wait for the hardware to halt */
963 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
964 (val & XILINX_DMA_DMASR_HALTED), 0,
965 XILINX_DMA_LOOP_COUNT);
966
967 if (err) {
968 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
969 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
970 chan->err = true;
971 }
972 }
973
974 /**
975 * xilinx_dma_start - Start DMA channel
976 * @chan: Driver specific DMA channel
977 */
978 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
979 {
980 int err;
981 u32 val;
982
983 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
984
985 /* Wait for the hardware to start */
986 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
987 !(val & XILINX_DMA_DMASR_HALTED), 0,
988 XILINX_DMA_LOOP_COUNT);
989
990 if (err) {
991 dev_err(chan->dev, "Cannot start channel %p: %x\n",
992 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
993
994 chan->err = true;
995 }
996 }
997
998 /**
999 * xilinx_vdma_start_transfer - Starts VDMA transfer
1000 * @chan: Driver specific channel struct pointer
1001 */
1002 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1003 {
1004 struct xilinx_vdma_config *config = &chan->config;
1005 struct xilinx_dma_tx_descriptor *desc, *tail_desc;
1006 u32 reg;
1007 struct xilinx_vdma_tx_segment *tail_segment;
1008
1009 /* This function was invoked with lock held */
1010 if (chan->err)
1011 return;
1012
1013 if (list_empty(&chan->pending_list))
1014 return;
1015
1016 desc = list_first_entry(&chan->pending_list,
1017 struct xilinx_dma_tx_descriptor, node);
1018 tail_desc = list_last_entry(&chan->pending_list,
1019 struct xilinx_dma_tx_descriptor, node);
1020
1021 tail_segment = list_last_entry(&tail_desc->segments,
1022 struct xilinx_vdma_tx_segment, node);
1023
1024 /* If it is SG mode and hardware is busy, cannot submit */
1025 if (chan->has_sg && xilinx_dma_is_running(chan) &&
1026 !xilinx_dma_is_idle(chan)) {
1027 dev_dbg(chan->dev, "DMA controller still busy\n");
1028 return;
1029 }
1030
1031 /*
1032 * If hardware is idle, then all descriptors on the running lists are
1033 * done, start new transfers
1034 */
1035 if (chan->has_sg)
1036 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1037 desc->async_tx.phys);
1038
1039 /* Configure the hardware using info in the config structure */
1040 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1041
1042 if (config->frm_cnt_en)
1043 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1044 else
1045 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1046
1047 /* Configure channel to allow number frame buffers */
1048 dma_ctrl_write(chan, XILINX_DMA_REG_FRMSTORE,
1049 chan->desc_pendingcount);
1050
1051 /*
1052 * With SG, start with circular mode, so that BDs can be fetched.
1053 * In direct register mode, if not parking, enable circular mode
1054 */
1055 if (chan->has_sg || !config->park)
1056 reg |= XILINX_DMA_DMACR_CIRC_EN;
1057
1058 if (config->park)
1059 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1060
1061 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1062
1063 if (config->park && (config->park_frm >= 0) &&
1064 (config->park_frm < chan->num_frms)) {
1065 if (chan->direction == DMA_MEM_TO_DEV)
1066 dma_write(chan, XILINX_DMA_REG_PARK_PTR,
1067 config->park_frm <<
1068 XILINX_DMA_PARK_PTR_RD_REF_SHIFT);
1069 else
1070 dma_write(chan, XILINX_DMA_REG_PARK_PTR,
1071 config->park_frm <<
1072 XILINX_DMA_PARK_PTR_WR_REF_SHIFT);
1073 }
1074
1075 /* Start the hardware */
1076 xilinx_dma_start(chan);
1077
1078 if (chan->err)
1079 return;
1080
1081 /* Start the transfer */
1082 if (chan->has_sg) {
1083 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1084 tail_segment->phys);
1085 } else {
1086 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1087 int i = 0;
1088
1089 if (chan->desc_submitcount < chan->num_frms)
1090 i = chan->desc_submitcount;
1091
1092 list_for_each_entry(segment, &desc->segments, node) {
1093 if (chan->ext_addr)
1094 vdma_desc_write_64(chan,
1095 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1096 segment->hw.buf_addr,
1097 segment->hw.buf_addr_msb);
1098 else
1099 vdma_desc_write(chan,
1100 XILINX_VDMA_REG_START_ADDRESS(i++),
1101 segment->hw.buf_addr);
1102
1103 last = segment;
1104 }
1105
1106 if (!last)
1107 return;
1108
1109 /* HW expects these parameters to be same for one transaction */
1110 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1111 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1112 last->hw.stride);
1113 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1114 }
1115
1116 if (!chan->has_sg) {
1117 list_del(&desc->node);
1118 list_add_tail(&desc->node, &chan->active_list);
1119 chan->desc_submitcount++;
1120 chan->desc_pendingcount--;
1121 if (chan->desc_submitcount == chan->num_frms)
1122 chan->desc_submitcount = 0;
1123 } else {
1124 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1125 chan->desc_pendingcount = 0;
1126 }
1127 }
1128
1129 /**
1130 * xilinx_cdma_start_transfer - Starts cdma transfer
1131 * @chan: Driver specific channel struct pointer
1132 */
1133 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1134 {
1135 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1136 struct xilinx_cdma_tx_segment *tail_segment;
1137 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1138
1139 if (chan->err)
1140 return;
1141
1142 if (list_empty(&chan->pending_list))
1143 return;
1144
1145 head_desc = list_first_entry(&chan->pending_list,
1146 struct xilinx_dma_tx_descriptor, node);
1147 tail_desc = list_last_entry(&chan->pending_list,
1148 struct xilinx_dma_tx_descriptor, node);
1149 tail_segment = list_last_entry(&tail_desc->segments,
1150 struct xilinx_cdma_tx_segment, node);
1151
1152 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1153 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1154 ctrl_reg |= chan->desc_pendingcount <<
1155 XILINX_DMA_CR_COALESCE_SHIFT;
1156 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1157 }
1158
1159 if (chan->has_sg) {
1160 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1161 head_desc->async_tx.phys);
1162
1163 /* Update tail ptr register which will start the transfer */
1164 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1165 tail_segment->phys);
1166 } else {
1167 /* In simple mode */
1168 struct xilinx_cdma_tx_segment *segment;
1169 struct xilinx_cdma_desc_hw *hw;
1170
1171 segment = list_first_entry(&head_desc->segments,
1172 struct xilinx_cdma_tx_segment,
1173 node);
1174
1175 hw = &segment->hw;
1176
1177 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
1178 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
1179
1180 /* Start the transfer */
1181 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1182 hw->control & XILINX_DMA_MAX_TRANS_LEN);
1183 }
1184
1185 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1186 chan->desc_pendingcount = 0;
1187 }
1188
1189 /**
1190 * xilinx_dma_start_transfer - Starts DMA transfer
1191 * @chan: Driver specific channel struct pointer
1192 */
1193 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1194 {
1195 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1196 struct xilinx_axidma_tx_segment *tail_segment, *old_head, *new_head;
1197 u32 reg;
1198
1199 if (chan->err)
1200 return;
1201
1202 if (list_empty(&chan->pending_list))
1203 return;
1204
1205 /* If it is SG mode and hardware is busy, cannot submit */
1206 if (chan->has_sg && xilinx_dma_is_running(chan) &&
1207 !xilinx_dma_is_idle(chan)) {
1208 dev_dbg(chan->dev, "DMA controller still busy\n");
1209 return;
1210 }
1211
1212 head_desc = list_first_entry(&chan->pending_list,
1213 struct xilinx_dma_tx_descriptor, node);
1214 tail_desc = list_last_entry(&chan->pending_list,
1215 struct xilinx_dma_tx_descriptor, node);
1216 tail_segment = list_last_entry(&tail_desc->segments,
1217 struct xilinx_axidma_tx_segment, node);
1218
1219 if (chan->has_sg && !chan->xdev->mcdma) {
1220 old_head = list_first_entry(&head_desc->segments,
1221 struct xilinx_axidma_tx_segment, node);
1222 new_head = chan->seg_v;
1223 /* Copy Buffer Descriptor fields. */
1224 new_head->hw = old_head->hw;
1225
1226 /* Swap and save new reserve */
1227 list_replace_init(&old_head->node, &new_head->node);
1228 chan->seg_v = old_head;
1229
1230 tail_segment->hw.next_desc = chan->seg_v->phys;
1231 head_desc->async_tx.phys = new_head->phys;
1232 }
1233
1234 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1235
1236 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1237 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1238 reg |= chan->desc_pendingcount <<
1239 XILINX_DMA_CR_COALESCE_SHIFT;
1240 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1241 }
1242
1243 if (chan->has_sg && !chan->xdev->mcdma)
1244 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1245 head_desc->async_tx.phys);
1246
1247 if (chan->has_sg && chan->xdev->mcdma) {
1248 if (chan->direction == DMA_MEM_TO_DEV) {
1249 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1250 head_desc->async_tx.phys);
1251 } else {
1252 if (!chan->tdest) {
1253 dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
1254 head_desc->async_tx.phys);
1255 } else {
1256 dma_ctrl_write(chan,
1257 XILINX_DMA_MCRX_CDESC(chan->tdest),
1258 head_desc->async_tx.phys);
1259 }
1260 }
1261 }
1262
1263 xilinx_dma_start(chan);
1264
1265 if (chan->err)
1266 return;
1267
1268 /* Start the transfer */
1269 if (chan->has_sg && !chan->xdev->mcdma) {
1270 if (chan->cyclic)
1271 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1272 chan->cyclic_seg_v->phys);
1273 else
1274 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1275 tail_segment->phys);
1276 } else if (chan->has_sg && chan->xdev->mcdma) {
1277 if (chan->direction == DMA_MEM_TO_DEV) {
1278 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1279 tail_segment->phys);
1280 } else {
1281 if (!chan->tdest) {
1282 dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
1283 tail_segment->phys);
1284 } else {
1285 dma_ctrl_write(chan,
1286 XILINX_DMA_MCRX_TDESC(chan->tdest),
1287 tail_segment->phys);
1288 }
1289 }
1290 } else {
1291 struct xilinx_axidma_tx_segment *segment;
1292 struct xilinx_axidma_desc_hw *hw;
1293
1294 segment = list_first_entry(&head_desc->segments,
1295 struct xilinx_axidma_tx_segment,
1296 node);
1297 hw = &segment->hw;
1298
1299 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
1300
1301 /* Start the transfer */
1302 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1303 hw->control & XILINX_DMA_MAX_TRANS_LEN);
1304 }
1305
1306 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1307 chan->desc_pendingcount = 0;
1308 }
1309
1310 /**
1311 * xilinx_dma_issue_pending - Issue pending transactions
1312 * @dchan: DMA channel
1313 */
1314 static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1315 {
1316 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1317 unsigned long flags;
1318
1319 spin_lock_irqsave(&chan->lock, flags);
1320 chan->start_transfer(chan);
1321 spin_unlock_irqrestore(&chan->lock, flags);
1322 }
1323
1324 /**
1325 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1326 * @chan : xilinx DMA channel
1327 *
1328 * CONTEXT: hardirq
1329 */
1330 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1331 {
1332 struct xilinx_dma_tx_descriptor *desc, *next;
1333
1334 /* This function was invoked with lock held */
1335 if (list_empty(&chan->active_list))
1336 return;
1337
1338 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1339 list_del(&desc->node);
1340 if (!desc->cyclic)
1341 dma_cookie_complete(&desc->async_tx);
1342 list_add_tail(&desc->node, &chan->done_list);
1343 }
1344 }
1345
1346 /**
1347 * xilinx_dma_reset - Reset DMA channel
1348 * @chan: Driver specific DMA channel
1349 *
1350 * Return: '0' on success and failure value on error
1351 */
1352 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1353 {
1354 int err;
1355 u32 tmp;
1356
1357 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1358
1359 /* Wait for the hardware to finish reset */
1360 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1361 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1362 XILINX_DMA_LOOP_COUNT);
1363
1364 if (err) {
1365 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1366 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1367 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1368 return -ETIMEDOUT;
1369 }
1370
1371 chan->err = false;
1372
1373 return err;
1374 }
1375
1376 /**
1377 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1378 * @chan: Driver specific DMA channel
1379 *
1380 * Return: '0' on success and failure value on error
1381 */
1382 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1383 {
1384 int err;
1385
1386 /* Reset VDMA */
1387 err = xilinx_dma_reset(chan);
1388 if (err)
1389 return err;
1390
1391 /* Enable interrupts */
1392 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1393 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1394
1395 return 0;
1396 }
1397
1398 /**
1399 * xilinx_dma_irq_handler - DMA Interrupt handler
1400 * @irq: IRQ number
1401 * @data: Pointer to the Xilinx DMA channel structure
1402 *
1403 * Return: IRQ_HANDLED/IRQ_NONE
1404 */
1405 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1406 {
1407 struct xilinx_dma_chan *chan = data;
1408 u32 status;
1409
1410 /* Read the status and ack the interrupts. */
1411 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1412 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1413 return IRQ_NONE;
1414
1415 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1416 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1417
1418 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1419 /*
1420 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1421 * error is recoverable, ignore it. Otherwise flag the error.
1422 *
1423 * Only recoverable errors can be cleared in the DMASR register,
1424 * make sure not to write to other error bits to 1.
1425 */
1426 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1427
1428 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1429 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1430
1431 if (!chan->flush_on_fsync ||
1432 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1433 dev_err(chan->dev,
1434 "Channel %p has errors %x, cdr %x tdr %x\n",
1435 chan, errors,
1436 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1437 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1438 chan->err = true;
1439 }
1440 }
1441
1442 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1443 /*
1444 * Device takes too long to do the transfer when user requires
1445 * responsiveness.
1446 */
1447 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1448 }
1449
1450 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1451 spin_lock(&chan->lock);
1452 xilinx_dma_complete_descriptor(chan);
1453 chan->start_transfer(chan);
1454 spin_unlock(&chan->lock);
1455 }
1456
1457 tasklet_schedule(&chan->tasklet);
1458 return IRQ_HANDLED;
1459 }
1460
1461 /**
1462 * append_desc_queue - Queuing descriptor
1463 * @chan: Driver specific dma channel
1464 * @desc: dma transaction descriptor
1465 */
1466 static void append_desc_queue(struct xilinx_dma_chan *chan,
1467 struct xilinx_dma_tx_descriptor *desc)
1468 {
1469 struct xilinx_vdma_tx_segment *tail_segment;
1470 struct xilinx_dma_tx_descriptor *tail_desc;
1471 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1472 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1473
1474 if (list_empty(&chan->pending_list))
1475 goto append;
1476
1477 /*
1478 * Add the hardware descriptor to the chain of hardware descriptors
1479 * that already exists in memory.
1480 */
1481 tail_desc = list_last_entry(&chan->pending_list,
1482 struct xilinx_dma_tx_descriptor, node);
1483 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1484 tail_segment = list_last_entry(&tail_desc->segments,
1485 struct xilinx_vdma_tx_segment,
1486 node);
1487 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1488 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1489 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1490 struct xilinx_cdma_tx_segment,
1491 node);
1492 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1493 } else {
1494 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1495 struct xilinx_axidma_tx_segment,
1496 node);
1497 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1498 }
1499
1500 /*
1501 * Add the software descriptor and all children to the list
1502 * of pending transactions
1503 */
1504 append:
1505 list_add_tail(&desc->node, &chan->pending_list);
1506 chan->desc_pendingcount++;
1507
1508 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1509 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1510 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1511 chan->desc_pendingcount = chan->num_frms;
1512 }
1513 }
1514
1515 /**
1516 * xilinx_dma_tx_submit - Submit DMA transaction
1517 * @tx: Async transaction descriptor
1518 *
1519 * Return: cookie value on success and failure value on error
1520 */
1521 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1522 {
1523 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1524 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1525 dma_cookie_t cookie;
1526 unsigned long flags;
1527 int err;
1528
1529 if (chan->cyclic) {
1530 xilinx_dma_free_tx_descriptor(chan, desc);
1531 return -EBUSY;
1532 }
1533
1534 if (chan->err) {
1535 /*
1536 * If reset fails, need to hard reset the system.
1537 * Channel is no longer functional
1538 */
1539 err = xilinx_dma_chan_reset(chan);
1540 if (err < 0)
1541 return err;
1542 }
1543
1544 spin_lock_irqsave(&chan->lock, flags);
1545
1546 cookie = dma_cookie_assign(tx);
1547
1548 /* Put this transaction onto the tail of the pending queue */
1549 append_desc_queue(chan, desc);
1550
1551 if (desc->cyclic)
1552 chan->cyclic = true;
1553
1554 spin_unlock_irqrestore(&chan->lock, flags);
1555
1556 return cookie;
1557 }
1558
1559 /**
1560 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1561 * DMA_SLAVE transaction
1562 * @dchan: DMA channel
1563 * @xt: Interleaved template pointer
1564 * @flags: transfer ack flags
1565 *
1566 * Return: Async transaction descriptor on success and NULL on failure
1567 */
1568 static struct dma_async_tx_descriptor *
1569 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
1570 struct dma_interleaved_template *xt,
1571 unsigned long flags)
1572 {
1573 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1574 struct xilinx_dma_tx_descriptor *desc;
1575 struct xilinx_vdma_tx_segment *segment, *prev = NULL;
1576 struct xilinx_vdma_desc_hw *hw;
1577
1578 if (!is_slave_direction(xt->dir))
1579 return NULL;
1580
1581 if (!xt->numf || !xt->sgl[0].size)
1582 return NULL;
1583
1584 if (xt->frame_size != 1)
1585 return NULL;
1586
1587 /* Allocate a transaction descriptor. */
1588 desc = xilinx_dma_alloc_tx_descriptor(chan);
1589 if (!desc)
1590 return NULL;
1591
1592 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1593 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1594 async_tx_ack(&desc->async_tx);
1595
1596 /* Allocate the link descriptor from DMA pool */
1597 segment = xilinx_vdma_alloc_tx_segment(chan);
1598 if (!segment)
1599 goto error;
1600
1601 /* Fill in the hardware descriptor */
1602 hw = &segment->hw;
1603 hw->vsize = xt->numf;
1604 hw->hsize = xt->sgl[0].size;
1605 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
1606 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
1607 hw->stride |= chan->config.frm_dly <<
1608 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
1609
1610 if (xt->dir != DMA_MEM_TO_DEV) {
1611 if (chan->ext_addr) {
1612 hw->buf_addr = lower_32_bits(xt->dst_start);
1613 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
1614 } else {
1615 hw->buf_addr = xt->dst_start;
1616 }
1617 } else {
1618 if (chan->ext_addr) {
1619 hw->buf_addr = lower_32_bits(xt->src_start);
1620 hw->buf_addr_msb = upper_32_bits(xt->src_start);
1621 } else {
1622 hw->buf_addr = xt->src_start;
1623 }
1624 }
1625
1626 /* Insert the segment into the descriptor segments list. */
1627 list_add_tail(&segment->node, &desc->segments);
1628
1629 prev = segment;
1630
1631 /* Link the last hardware descriptor with the first. */
1632 segment = list_first_entry(&desc->segments,
1633 struct xilinx_vdma_tx_segment, node);
1634 desc->async_tx.phys = segment->phys;
1635
1636 return &desc->async_tx;
1637
1638 error:
1639 xilinx_dma_free_tx_descriptor(chan, desc);
1640 return NULL;
1641 }
1642
1643 /**
1644 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
1645 * @dchan: DMA channel
1646 * @dma_dst: destination address
1647 * @dma_src: source address
1648 * @len: transfer length
1649 * @flags: transfer ack flags
1650 *
1651 * Return: Async transaction descriptor on success and NULL on failure
1652 */
1653 static struct dma_async_tx_descriptor *
1654 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
1655 dma_addr_t dma_src, size_t len, unsigned long flags)
1656 {
1657 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1658 struct xilinx_dma_tx_descriptor *desc;
1659 struct xilinx_cdma_tx_segment *segment, *prev;
1660 struct xilinx_cdma_desc_hw *hw;
1661
1662 if (!len || len > XILINX_DMA_MAX_TRANS_LEN)
1663 return NULL;
1664
1665 desc = xilinx_dma_alloc_tx_descriptor(chan);
1666 if (!desc)
1667 return NULL;
1668
1669 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1670 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1671
1672 /* Allocate the link descriptor from DMA pool */
1673 segment = xilinx_cdma_alloc_tx_segment(chan);
1674 if (!segment)
1675 goto error;
1676
1677 hw = &segment->hw;
1678 hw->control = len;
1679 hw->src_addr = dma_src;
1680 hw->dest_addr = dma_dst;
1681 if (chan->ext_addr) {
1682 hw->src_addr_msb = upper_32_bits(dma_src);
1683 hw->dest_addr_msb = upper_32_bits(dma_dst);
1684 }
1685
1686 /* Fill the previous next descriptor with current */
1687 prev = list_last_entry(&desc->segments,
1688 struct xilinx_cdma_tx_segment, node);
1689 prev->hw.next_desc = segment->phys;
1690
1691 /* Insert the segment into the descriptor segments list. */
1692 list_add_tail(&segment->node, &desc->segments);
1693
1694 prev = segment;
1695
1696 /* Link the last hardware descriptor with the first. */
1697 segment = list_first_entry(&desc->segments,
1698 struct xilinx_cdma_tx_segment, node);
1699 desc->async_tx.phys = segment->phys;
1700 prev->hw.next_desc = segment->phys;
1701
1702 return &desc->async_tx;
1703
1704 error:
1705 xilinx_dma_free_tx_descriptor(chan, desc);
1706 return NULL;
1707 }
1708
1709 /**
1710 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1711 * @dchan: DMA channel
1712 * @sgl: scatterlist to transfer to/from
1713 * @sg_len: number of entries in @scatterlist
1714 * @direction: DMA direction
1715 * @flags: transfer ack flags
1716 * @context: APP words of the descriptor
1717 *
1718 * Return: Async transaction descriptor on success and NULL on failure
1719 */
1720 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
1721 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
1722 enum dma_transfer_direction direction, unsigned long flags,
1723 void *context)
1724 {
1725 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1726 struct xilinx_dma_tx_descriptor *desc;
1727 struct xilinx_axidma_tx_segment *segment = NULL, *prev = NULL;
1728 u32 *app_w = (u32 *)context;
1729 struct scatterlist *sg;
1730 size_t copy;
1731 size_t sg_used;
1732 unsigned int i;
1733
1734 if (!is_slave_direction(direction))
1735 return NULL;
1736
1737 /* Allocate a transaction descriptor. */
1738 desc = xilinx_dma_alloc_tx_descriptor(chan);
1739 if (!desc)
1740 return NULL;
1741
1742 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1743 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1744
1745 /* Build transactions using information in the scatter gather list */
1746 for_each_sg(sgl, sg, sg_len, i) {
1747 sg_used = 0;
1748
1749 /* Loop until the entire scatterlist entry is used */
1750 while (sg_used < sg_dma_len(sg)) {
1751 struct xilinx_axidma_desc_hw *hw;
1752
1753 /* Get a free segment */
1754 segment = xilinx_axidma_alloc_tx_segment(chan);
1755 if (!segment)
1756 goto error;
1757
1758 /*
1759 * Calculate the maximum number of bytes to transfer,
1760 * making sure it is less than the hw limit
1761 */
1762 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
1763 XILINX_DMA_MAX_TRANS_LEN);
1764 hw = &segment->hw;
1765
1766 /* Fill in the descriptor */
1767 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
1768 sg_used, 0);
1769
1770 hw->control = copy;
1771
1772 if (chan->direction == DMA_MEM_TO_DEV) {
1773 if (app_w)
1774 memcpy(hw->app, app_w, sizeof(u32) *
1775 XILINX_DMA_NUM_APP_WORDS);
1776 }
1777
1778 if (prev)
1779 prev->hw.next_desc = segment->phys;
1780
1781 prev = segment;
1782 sg_used += copy;
1783
1784 /*
1785 * Insert the segment into the descriptor segments
1786 * list.
1787 */
1788 list_add_tail(&segment->node, &desc->segments);
1789 }
1790 }
1791
1792 segment = list_first_entry(&desc->segments,
1793 struct xilinx_axidma_tx_segment, node);
1794 desc->async_tx.phys = segment->phys;
1795 prev->hw.next_desc = segment->phys;
1796
1797 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1798 if (chan->direction == DMA_MEM_TO_DEV) {
1799 segment->hw.control |= XILINX_DMA_BD_SOP;
1800 segment = list_last_entry(&desc->segments,
1801 struct xilinx_axidma_tx_segment,
1802 node);
1803 segment->hw.control |= XILINX_DMA_BD_EOP;
1804 }
1805
1806 return &desc->async_tx;
1807
1808 error:
1809 xilinx_dma_free_tx_descriptor(chan, desc);
1810 return NULL;
1811 }
1812
1813 /**
1814 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
1815 * @chan: DMA channel
1816 * @sgl: scatterlist to transfer to/from
1817 * @sg_len: number of entries in @scatterlist
1818 * @direction: DMA direction
1819 * @flags: transfer ack flags
1820 */
1821 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
1822 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
1823 size_t period_len, enum dma_transfer_direction direction,
1824 unsigned long flags)
1825 {
1826 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1827 struct xilinx_dma_tx_descriptor *desc;
1828 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
1829 size_t copy, sg_used;
1830 unsigned int num_periods;
1831 int i;
1832 u32 reg;
1833
1834 if (!period_len)
1835 return NULL;
1836
1837 num_periods = buf_len / period_len;
1838
1839 if (!num_periods)
1840 return NULL;
1841
1842 if (!is_slave_direction(direction))
1843 return NULL;
1844
1845 /* Allocate a transaction descriptor. */
1846 desc = xilinx_dma_alloc_tx_descriptor(chan);
1847 if (!desc)
1848 return NULL;
1849
1850 chan->direction = direction;
1851 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1852 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1853
1854 for (i = 0; i < num_periods; ++i) {
1855 sg_used = 0;
1856
1857 while (sg_used < period_len) {
1858 struct xilinx_axidma_desc_hw *hw;
1859
1860 /* Get a free segment */
1861 segment = xilinx_axidma_alloc_tx_segment(chan);
1862 if (!segment)
1863 goto error;
1864
1865 /*
1866 * Calculate the maximum number of bytes to transfer,
1867 * making sure it is less than the hw limit
1868 */
1869 copy = min_t(size_t, period_len - sg_used,
1870 XILINX_DMA_MAX_TRANS_LEN);
1871 hw = &segment->hw;
1872 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
1873 period_len * i);
1874 hw->control = copy;
1875
1876 if (prev)
1877 prev->hw.next_desc = segment->phys;
1878
1879 prev = segment;
1880 sg_used += copy;
1881
1882 /*
1883 * Insert the segment into the descriptor segments
1884 * list.
1885 */
1886 list_add_tail(&segment->node, &desc->segments);
1887 }
1888 }
1889
1890 head_segment = list_first_entry(&desc->segments,
1891 struct xilinx_axidma_tx_segment, node);
1892 desc->async_tx.phys = head_segment->phys;
1893
1894 desc->cyclic = true;
1895 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1896 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
1897 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1898
1899 segment = list_last_entry(&desc->segments,
1900 struct xilinx_axidma_tx_segment,
1901 node);
1902 segment->hw.next_desc = (u32) head_segment->phys;
1903
1904 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1905 if (direction == DMA_MEM_TO_DEV) {
1906 head_segment->hw.control |= XILINX_DMA_BD_SOP;
1907 segment->hw.control |= XILINX_DMA_BD_EOP;
1908 }
1909
1910 return &desc->async_tx;
1911
1912 error:
1913 xilinx_dma_free_tx_descriptor(chan, desc);
1914 return NULL;
1915 }
1916
1917 /**
1918 * xilinx_dma_prep_interleaved - prepare a descriptor for a
1919 * DMA_SLAVE transaction
1920 * @dchan: DMA channel
1921 * @xt: Interleaved template pointer
1922 * @flags: transfer ack flags
1923 *
1924 * Return: Async transaction descriptor on success and NULL on failure
1925 */
1926 static struct dma_async_tx_descriptor *
1927 xilinx_dma_prep_interleaved(struct dma_chan *dchan,
1928 struct dma_interleaved_template *xt,
1929 unsigned long flags)
1930 {
1931 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1932 struct xilinx_dma_tx_descriptor *desc;
1933 struct xilinx_axidma_tx_segment *segment;
1934 struct xilinx_axidma_desc_hw *hw;
1935
1936 if (!is_slave_direction(xt->dir))
1937 return NULL;
1938
1939 if (!xt->numf || !xt->sgl[0].size)
1940 return NULL;
1941
1942 if (xt->frame_size != 1)
1943 return NULL;
1944
1945 /* Allocate a transaction descriptor. */
1946 desc = xilinx_dma_alloc_tx_descriptor(chan);
1947 if (!desc)
1948 return NULL;
1949
1950 chan->direction = xt->dir;
1951 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
1952 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
1953
1954 /* Get a free segment */
1955 segment = xilinx_axidma_alloc_tx_segment(chan);
1956 if (!segment)
1957 goto error;
1958
1959 hw = &segment->hw;
1960
1961 /* Fill in the descriptor */
1962 if (xt->dir != DMA_MEM_TO_DEV)
1963 hw->buf_addr = xt->dst_start;
1964 else
1965 hw->buf_addr = xt->src_start;
1966
1967 hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
1968 hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
1969 XILINX_DMA_BD_VSIZE_MASK;
1970 hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
1971 XILINX_DMA_BD_STRIDE_MASK;
1972 hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
1973
1974 /*
1975 * Insert the segment into the descriptor segments
1976 * list.
1977 */
1978 list_add_tail(&segment->node, &desc->segments);
1979
1980
1981 segment = list_first_entry(&desc->segments,
1982 struct xilinx_axidma_tx_segment, node);
1983 desc->async_tx.phys = segment->phys;
1984
1985 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
1986 if (xt->dir == DMA_MEM_TO_DEV) {
1987 segment->hw.control |= XILINX_DMA_BD_SOP;
1988 segment = list_last_entry(&desc->segments,
1989 struct xilinx_axidma_tx_segment,
1990 node);
1991 segment->hw.control |= XILINX_DMA_BD_EOP;
1992 }
1993
1994 return &desc->async_tx;
1995
1996 error:
1997 xilinx_dma_free_tx_descriptor(chan, desc);
1998 return NULL;
1999 }
2000
2001 /**
2002 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2003 * @chan: Driver specific DMA Channel pointer
2004 */
2005 static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2006 {
2007 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2008 u32 reg;
2009
2010 if (chan->cyclic)
2011 xilinx_dma_chan_reset(chan);
2012
2013 /* Halt the DMA engine */
2014 xilinx_dma_halt(chan);
2015
2016 /* Remove and free all of the descriptors in the lists */
2017 xilinx_dma_free_descriptors(chan);
2018
2019 if (chan->cyclic) {
2020 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2021 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2022 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2023 chan->cyclic = false;
2024 }
2025
2026 return 0;
2027 }
2028
2029 /**
2030 * xilinx_dma_channel_set_config - Configure VDMA channel
2031 * Run-time configuration for Axi VDMA, supports:
2032 * . halt the channel
2033 * . configure interrupt coalescing and inter-packet delay threshold
2034 * . start/stop parking
2035 * . enable genlock
2036 *
2037 * @dchan: DMA channel
2038 * @cfg: VDMA device configuration pointer
2039 *
2040 * Return: '0' on success and failure value on error
2041 */
2042 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2043 struct xilinx_vdma_config *cfg)
2044 {
2045 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2046 u32 dmacr;
2047
2048 if (cfg->reset)
2049 return xilinx_dma_chan_reset(chan);
2050
2051 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2052
2053 chan->config.frm_dly = cfg->frm_dly;
2054 chan->config.park = cfg->park;
2055
2056 /* genlock settings */
2057 chan->config.gen_lock = cfg->gen_lock;
2058 chan->config.master = cfg->master;
2059
2060 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2061 if (cfg->gen_lock && chan->genlock) {
2062 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2063 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2064 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2065 }
2066
2067 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2068 if (cfg->park)
2069 chan->config.park_frm = cfg->park_frm;
2070 else
2071 chan->config.park_frm = -1;
2072
2073 chan->config.coalesc = cfg->coalesc;
2074 chan->config.delay = cfg->delay;
2075
2076 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2077 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2078 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2079 chan->config.coalesc = cfg->coalesc;
2080 }
2081
2082 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2083 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2084 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2085 chan->config.delay = cfg->delay;
2086 }
2087
2088 /* FSync Source selection */
2089 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2090 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2091
2092 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2093
2094 return 0;
2095 }
2096 EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2097
2098 /* -----------------------------------------------------------------------------
2099 * Probe and remove
2100 */
2101
2102 /**
2103 * xilinx_dma_chan_remove - Per Channel remove function
2104 * @chan: Driver specific DMA channel
2105 */
2106 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2107 {
2108 /* Disable all interrupts */
2109 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2110 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2111
2112 if (chan->irq > 0)
2113 free_irq(chan->irq, chan);
2114
2115 tasklet_kill(&chan->tasklet);
2116
2117 list_del(&chan->common.device_node);
2118 }
2119
2120 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2121 struct clk **tx_clk, struct clk **rx_clk,
2122 struct clk **sg_clk, struct clk **tmp_clk)
2123 {
2124 int err;
2125
2126 *tmp_clk = NULL;
2127
2128 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2129 if (IS_ERR(*axi_clk)) {
2130 err = PTR_ERR(*axi_clk);
2131 dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err);
2132 return err;
2133 }
2134
2135 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2136 if (IS_ERR(*tx_clk))
2137 *tx_clk = NULL;
2138
2139 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2140 if (IS_ERR(*rx_clk))
2141 *rx_clk = NULL;
2142
2143 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2144 if (IS_ERR(*sg_clk))
2145 *sg_clk = NULL;
2146
2147 err = clk_prepare_enable(*axi_clk);
2148 if (err) {
2149 dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err);
2150 return err;
2151 }
2152
2153 err = clk_prepare_enable(*tx_clk);
2154 if (err) {
2155 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2156 goto err_disable_axiclk;
2157 }
2158
2159 err = clk_prepare_enable(*rx_clk);
2160 if (err) {
2161 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2162 goto err_disable_txclk;
2163 }
2164
2165 err = clk_prepare_enable(*sg_clk);
2166 if (err) {
2167 dev_err(&pdev->dev, "failed to enable sg_clk (%u)\n", err);
2168 goto err_disable_rxclk;
2169 }
2170
2171 return 0;
2172
2173 err_disable_rxclk:
2174 clk_disable_unprepare(*rx_clk);
2175 err_disable_txclk:
2176 clk_disable_unprepare(*tx_clk);
2177 err_disable_axiclk:
2178 clk_disable_unprepare(*axi_clk);
2179
2180 return err;
2181 }
2182
2183 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2184 struct clk **dev_clk, struct clk **tmp_clk,
2185 struct clk **tmp1_clk, struct clk **tmp2_clk)
2186 {
2187 int err;
2188
2189 *tmp_clk = NULL;
2190 *tmp1_clk = NULL;
2191 *tmp2_clk = NULL;
2192
2193 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2194 if (IS_ERR(*axi_clk)) {
2195 err = PTR_ERR(*axi_clk);
2196 dev_err(&pdev->dev, "failed to get axi_clk (%u)\n", err);
2197 return err;
2198 }
2199
2200 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2201 if (IS_ERR(*dev_clk)) {
2202 err = PTR_ERR(*dev_clk);
2203 dev_err(&pdev->dev, "failed to get dev_clk (%u)\n", err);
2204 return err;
2205 }
2206
2207 err = clk_prepare_enable(*axi_clk);
2208 if (err) {
2209 dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err);
2210 return err;
2211 }
2212
2213 err = clk_prepare_enable(*dev_clk);
2214 if (err) {
2215 dev_err(&pdev->dev, "failed to enable dev_clk (%u)\n", err);
2216 goto err_disable_axiclk;
2217 }
2218
2219 return 0;
2220
2221 err_disable_axiclk:
2222 clk_disable_unprepare(*axi_clk);
2223
2224 return err;
2225 }
2226
2227 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2228 struct clk **tx_clk, struct clk **txs_clk,
2229 struct clk **rx_clk, struct clk **rxs_clk)
2230 {
2231 int err;
2232
2233 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2234 if (IS_ERR(*axi_clk)) {
2235 err = PTR_ERR(*axi_clk);
2236 dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err);
2237 return err;
2238 }
2239
2240 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2241 if (IS_ERR(*tx_clk))
2242 *tx_clk = NULL;
2243
2244 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2245 if (IS_ERR(*txs_clk))
2246 *txs_clk = NULL;
2247
2248 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2249 if (IS_ERR(*rx_clk))
2250 *rx_clk = NULL;
2251
2252 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2253 if (IS_ERR(*rxs_clk))
2254 *rxs_clk = NULL;
2255
2256 err = clk_prepare_enable(*axi_clk);
2257 if (err) {
2258 dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err);
2259 return err;
2260 }
2261
2262 err = clk_prepare_enable(*tx_clk);
2263 if (err) {
2264 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2265 goto err_disable_axiclk;
2266 }
2267
2268 err = clk_prepare_enable(*txs_clk);
2269 if (err) {
2270 dev_err(&pdev->dev, "failed to enable txs_clk (%u)\n", err);
2271 goto err_disable_txclk;
2272 }
2273
2274 err = clk_prepare_enable(*rx_clk);
2275 if (err) {
2276 dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2277 goto err_disable_txsclk;
2278 }
2279
2280 err = clk_prepare_enable(*rxs_clk);
2281 if (err) {
2282 dev_err(&pdev->dev, "failed to enable rxs_clk (%u)\n", err);
2283 goto err_disable_rxclk;
2284 }
2285
2286 return 0;
2287
2288 err_disable_rxclk:
2289 clk_disable_unprepare(*rx_clk);
2290 err_disable_txsclk:
2291 clk_disable_unprepare(*txs_clk);
2292 err_disable_txclk:
2293 clk_disable_unprepare(*tx_clk);
2294 err_disable_axiclk:
2295 clk_disable_unprepare(*axi_clk);
2296
2297 return err;
2298 }
2299
2300 static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2301 {
2302 clk_disable_unprepare(xdev->rxs_clk);
2303 clk_disable_unprepare(xdev->rx_clk);
2304 clk_disable_unprepare(xdev->txs_clk);
2305 clk_disable_unprepare(xdev->tx_clk);
2306 clk_disable_unprepare(xdev->axi_clk);
2307 }
2308
2309 /**
2310 * xilinx_dma_chan_probe - Per Channel Probing
2311 * It get channel features from the device tree entry and
2312 * initialize special channel handling routines
2313 *
2314 * @xdev: Driver specific device structure
2315 * @node: Device node
2316 *
2317 * Return: '0' on success and failure value on error
2318 */
2319 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2320 struct device_node *node, int chan_id)
2321 {
2322 struct xilinx_dma_chan *chan;
2323 bool has_dre = false;
2324 u32 value, width;
2325 int err;
2326
2327 /* Allocate and initialize the channel structure */
2328 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2329 if (!chan)
2330 return -ENOMEM;
2331
2332 chan->dev = xdev->dev;
2333 chan->xdev = xdev;
2334 chan->has_sg = xdev->has_sg;
2335 chan->desc_pendingcount = 0x0;
2336 chan->ext_addr = xdev->ext_addr;
2337
2338 spin_lock_init(&chan->lock);
2339 INIT_LIST_HEAD(&chan->pending_list);
2340 INIT_LIST_HEAD(&chan->done_list);
2341 INIT_LIST_HEAD(&chan->active_list);
2342
2343 /* Retrieve the channel properties from the device tree */
2344 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2345
2346 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2347
2348 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2349 if (err) {
2350 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2351 return err;
2352 }
2353 width = value >> 3; /* Convert bits to bytes */
2354
2355 /* If data width is greater than 8 bytes, DRE is not in hw */
2356 if (width > 8)
2357 has_dre = false;
2358
2359 if (!has_dre)
2360 xdev->common.copy_align = fls(width - 1);
2361
2362 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2363 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2364 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2365 chan->direction = DMA_MEM_TO_DEV;
2366 chan->id = chan_id;
2367 chan->tdest = chan_id;
2368
2369 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2370 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2371 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2372
2373 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2374 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2375 chan->flush_on_fsync = true;
2376 }
2377 } else if (of_device_is_compatible(node,
2378 "xlnx,axi-vdma-s2mm-channel") ||
2379 of_device_is_compatible(node,
2380 "xlnx,axi-dma-s2mm-channel")) {
2381 chan->direction = DMA_DEV_TO_MEM;
2382 chan->id = chan_id;
2383 chan->tdest = chan_id - xdev->nr_channels;
2384
2385 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2386 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2387 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2388
2389 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2390 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2391 chan->flush_on_fsync = true;
2392 }
2393 } else {
2394 dev_err(xdev->dev, "Invalid channel compatible node\n");
2395 return -EINVAL;
2396 }
2397
2398 /* Request the interrupt */
2399 chan->irq = irq_of_parse_and_map(node, 0);
2400 err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
2401 "xilinx-dma-controller", chan);
2402 if (err) {
2403 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2404 return err;
2405 }
2406
2407 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
2408 chan->start_transfer = xilinx_dma_start_transfer;
2409 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
2410 chan->start_transfer = xilinx_cdma_start_transfer;
2411 else
2412 chan->start_transfer = xilinx_vdma_start_transfer;
2413
2414 /* Initialize the tasklet */
2415 tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
2416 (unsigned long)chan);
2417
2418 /*
2419 * Initialize the DMA channel and add it to the DMA engine channels
2420 * list.
2421 */
2422 chan->common.device = &xdev->common;
2423
2424 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2425 xdev->chan[chan->id] = chan;
2426
2427 /* Reset the channel */
2428 err = xilinx_dma_chan_reset(chan);
2429 if (err < 0) {
2430 dev_err(xdev->dev, "Reset channel failed\n");
2431 return err;
2432 }
2433
2434 return 0;
2435 }
2436
2437 /**
2438 * xilinx_dma_child_probe - Per child node probe
2439 * It get number of dma-channels per child node from
2440 * device-tree and initializes all the channels.
2441 *
2442 * @xdev: Driver specific device structure
2443 * @node: Device node
2444 *
2445 * Return: 0 always.
2446 */
2447 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2448 struct device_node *node) {
2449 int ret, i, nr_channels = 1;
2450
2451 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2452 if ((ret < 0) && xdev->mcdma)
2453 dev_warn(xdev->dev, "missing dma-channels property\n");
2454
2455 for (i = 0; i < nr_channels; i++)
2456 xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
2457
2458 xdev->nr_channels += nr_channels;
2459
2460 return 0;
2461 }
2462
2463 /**
2464 * of_dma_xilinx_xlate - Translation function
2465 * @dma_spec: Pointer to DMA specifier as found in the device tree
2466 * @ofdma: Pointer to DMA controller data
2467 *
2468 * Return: DMA channel pointer on success and NULL on error
2469 */
2470 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2471 struct of_dma *ofdma)
2472 {
2473 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2474 int chan_id = dma_spec->args[0];
2475
2476 if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
2477 return NULL;
2478
2479 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2480 }
2481
2482 static const struct xilinx_dma_config axidma_config = {
2483 .dmatype = XDMA_TYPE_AXIDMA,
2484 .clk_init = axidma_clk_init,
2485 };
2486
2487 static const struct xilinx_dma_config axicdma_config = {
2488 .dmatype = XDMA_TYPE_CDMA,
2489 .clk_init = axicdma_clk_init,
2490 };
2491
2492 static const struct xilinx_dma_config axivdma_config = {
2493 .dmatype = XDMA_TYPE_VDMA,
2494 .clk_init = axivdma_clk_init,
2495 };
2496
2497 static const struct of_device_id xilinx_dma_of_ids[] = {
2498 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2499 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2500 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2501 {}
2502 };
2503 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
2504
2505 /**
2506 * xilinx_dma_probe - Driver probe function
2507 * @pdev: Pointer to the platform_device structure
2508 *
2509 * Return: '0' on success and failure value on error
2510 */
2511 static int xilinx_dma_probe(struct platform_device *pdev)
2512 {
2513 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
2514 struct clk **, struct clk **, struct clk **)
2515 = axivdma_clk_init;
2516 struct device_node *node = pdev->dev.of_node;
2517 struct xilinx_dma_device *xdev;
2518 struct device_node *child, *np = pdev->dev.of_node;
2519 struct resource *io;
2520 u32 num_frames, addr_width;
2521 int i, err;
2522
2523 /* Allocate and initialize the DMA engine structure */
2524 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
2525 if (!xdev)
2526 return -ENOMEM;
2527
2528 xdev->dev = &pdev->dev;
2529 if (np) {
2530 const struct of_device_id *match;
2531
2532 match = of_match_node(xilinx_dma_of_ids, np);
2533 if (match && match->data) {
2534 xdev->dma_config = match->data;
2535 clk_init = xdev->dma_config->clk_init;
2536 }
2537 }
2538
2539 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
2540 &xdev->rx_clk, &xdev->rxs_clk);
2541 if (err)
2542 return err;
2543
2544 /* Request and map I/O memory */
2545 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2546 xdev->regs = devm_ioremap_resource(&pdev->dev, io);
2547 if (IS_ERR(xdev->regs))
2548 return PTR_ERR(xdev->regs);
2549
2550 /* Retrieve the DMA engine properties from the device tree */
2551 xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
2552 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
2553 xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
2554
2555 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2556 err = of_property_read_u32(node, "xlnx,num-fstores",
2557 &num_frames);
2558 if (err < 0) {
2559 dev_err(xdev->dev,
2560 "missing xlnx,num-fstores property\n");
2561 return err;
2562 }
2563
2564 err = of_property_read_u32(node, "xlnx,flush-fsync",
2565 &xdev->flush_on_fsync);
2566 if (err < 0)
2567 dev_warn(xdev->dev,
2568 "missing xlnx,flush-fsync property\n");
2569 }
2570
2571 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
2572 if (err < 0)
2573 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
2574
2575 if (addr_width > 32)
2576 xdev->ext_addr = true;
2577 else
2578 xdev->ext_addr = false;
2579
2580 /* Set the dma mask bits */
2581 dma_set_mask(xdev->dev, DMA_BIT_MASK(addr_width));
2582
2583 /* Initialize the DMA engine */
2584 xdev->common.dev = &pdev->dev;
2585
2586 INIT_LIST_HEAD(&xdev->common.channels);
2587 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
2588 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
2589 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
2590 }
2591
2592 xdev->common.device_alloc_chan_resources =
2593 xilinx_dma_alloc_chan_resources;
2594 xdev->common.device_free_chan_resources =
2595 xilinx_dma_free_chan_resources;
2596 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
2597 xdev->common.device_tx_status = xilinx_dma_tx_status;
2598 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
2599 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2600 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
2601 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
2602 xdev->common.device_prep_dma_cyclic =
2603 xilinx_dma_prep_dma_cyclic;
2604 xdev->common.device_prep_interleaved_dma =
2605 xilinx_dma_prep_interleaved;
2606 /* Residue calculation is supported by only AXI DMA */
2607 xdev->common.residue_granularity =
2608 DMA_RESIDUE_GRANULARITY_SEGMENT;
2609 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2610 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
2611 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
2612 } else {
2613 xdev->common.device_prep_interleaved_dma =
2614 xilinx_vdma_dma_prep_interleaved;
2615 }
2616
2617 platform_set_drvdata(pdev, xdev);
2618
2619 /* Initialize the channels */
2620 for_each_child_of_node(node, child) {
2621 err = xilinx_dma_child_probe(xdev, child);
2622 if (err < 0)
2623 goto disable_clks;
2624 }
2625
2626 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2627 for (i = 0; i < xdev->nr_channels; i++)
2628 if (xdev->chan[i])
2629 xdev->chan[i]->num_frms = num_frames;
2630 }
2631
2632 /* Register the DMA engine with the core */
2633 dma_async_device_register(&xdev->common);
2634
2635 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
2636 xdev);
2637 if (err < 0) {
2638 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
2639 dma_async_device_unregister(&xdev->common);
2640 goto error;
2641 }
2642
2643 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
2644
2645 return 0;
2646
2647 disable_clks:
2648 xdma_disable_allclks(xdev);
2649 error:
2650 for (i = 0; i < xdev->nr_channels; i++)
2651 if (xdev->chan[i])
2652 xilinx_dma_chan_remove(xdev->chan[i]);
2653
2654 return err;
2655 }
2656
2657 /**
2658 * xilinx_dma_remove - Driver remove function
2659 * @pdev: Pointer to the platform_device structure
2660 *
2661 * Return: Always '0'
2662 */
2663 static int xilinx_dma_remove(struct platform_device *pdev)
2664 {
2665 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
2666 int i;
2667
2668 of_dma_controller_free(pdev->dev.of_node);
2669
2670 dma_async_device_unregister(&xdev->common);
2671
2672 for (i = 0; i < xdev->nr_channels; i++)
2673 if (xdev->chan[i])
2674 xilinx_dma_chan_remove(xdev->chan[i]);
2675
2676 xdma_disable_allclks(xdev);
2677
2678 return 0;
2679 }
2680
2681 static struct platform_driver xilinx_vdma_driver = {
2682 .driver = {
2683 .name = "xilinx-vdma",
2684 .of_match_table = xilinx_dma_of_ids,
2685 },
2686 .probe = xilinx_dma_probe,
2687 .remove = xilinx_dma_remove,
2688 };
2689
2690 module_platform_driver(xilinx_vdma_driver);
2691
2692 MODULE_AUTHOR("Xilinx, Inc.");
2693 MODULE_DESCRIPTION("Xilinx VDMA driver");
2694 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support