drivers/dma/xilinx/zynqmp_dma.c

   1 /*
   2  * DMA driver for Xilinx ZynqMP DMA Engine
   3  *
   4  * Copyright (C) 2016 Xilinx, Inc. All rights reserved.
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/dmapool.h>
  14 #include <linux/dma/xilinx_dma.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26
  27 #include "../dmaengine.h"
  28
  29 /* Register Offsets */
  30 #define ZYNQMP_DMA_ISR                  0x100
  31 #define ZYNQMP_DMA_IMR                  0x104
  32 #define ZYNQMP_DMA_IER                  0x108
  33 #define ZYNQMP_DMA_IDS                  0x10C
  34 #define ZYNQMP_DMA_CTRL0                0x110
  35 #define ZYNQMP_DMA_CTRL1                0x114
  36 #define ZYNQMP_DMA_DATA_ATTR            0x120
  37 #define ZYNQMP_DMA_DSCR_ATTR            0x124
  38 #define ZYNQMP_DMA_SRC_DSCR_WRD0        0x128
  39 #define ZYNQMP_DMA_SRC_DSCR_WRD1        0x12C
  40 #define ZYNQMP_DMA_SRC_DSCR_WRD2        0x130
  41 #define ZYNQMP_DMA_SRC_DSCR_WRD3        0x134
  42 #define ZYNQMP_DMA_DST_DSCR_WRD0        0x138
  43 #define ZYNQMP_DMA_DST_DSCR_WRD1        0x13C
  44 #define ZYNQMP_DMA_DST_DSCR_WRD2        0x140
  45 #define ZYNQMP_DMA_DST_DSCR_WRD3        0x144
  46 #define ZYNQMP_DMA_SRC_START_LSB        0x158
  47 #define ZYNQMP_DMA_SRC_START_MSB        0x15C
  48 #define ZYNQMP_DMA_DST_START_LSB        0x160
  49 #define ZYNQMP_DMA_DST_START_MSB        0x164
  50 #define ZYNQMP_DMA_RATE_CTRL            0x18C
  51 #define ZYNQMP_DMA_IRQ_SRC_ACCT         0x190
  52 #define ZYNQMP_DMA_IRQ_DST_ACCT         0x194
  53 #define ZYNQMP_DMA_CTRL2                0x200
  54
  55 /* Interrupt registers bit field definitions */
  56 #define ZYNQMP_DMA_DONE                 BIT(10)
  57 #define ZYNQMP_DMA_AXI_WR_DATA          BIT(9)
  58 #define ZYNQMP_DMA_AXI_RD_DATA          BIT(8)
  59 #define ZYNQMP_DMA_AXI_RD_DST_DSCR      BIT(7)
  60 #define ZYNQMP_DMA_AXI_RD_SRC_DSCR      BIT(6)
  61 #define ZYNQMP_DMA_IRQ_DST_ACCT_ERR     BIT(5)
  62 #define ZYNQMP_DMA_IRQ_SRC_ACCT_ERR     BIT(4)
  63 #define ZYNQMP_DMA_BYTE_CNT_OVRFL       BIT(3)
  64 #define ZYNQMP_DMA_DST_DSCR_DONE        BIT(2)
  65 #define ZYNQMP_DMA_INV_APB              BIT(0)
  66
  67 /* Control 0 register bit field definitions */
  68 #define ZYNQMP_DMA_OVR_FETCH            BIT(7)
  69 #define ZYNQMP_DMA_POINT_TYPE_SG        BIT(6)
  70 #define ZYNQMP_DMA_RATE_CTRL_EN         BIT(3)
  71
  72 /* Control 1 register bit field definitions */
  73 #define ZYNQMP_DMA_SRC_ISSUE            GENMASK(4, 0)
  74
  75 /* Data Attribute register bit field definitions */
  76 #define ZYNQMP_DMA_ARBURST              GENMASK(27, 26)
  77 #define ZYNQMP_DMA_ARCACHE              GENMASK(25, 22)
  78 #define ZYNQMP_DMA_ARCACHE_OFST         22
  79 #define ZYNQMP_DMA_ARQOS                GENMASK(21, 18)
  80 #define ZYNQMP_DMA_ARQOS_OFST           18
  81 #define ZYNQMP_DMA_ARLEN                GENMASK(17, 14)
  82 #define ZYNQMP_DMA_ARLEN_OFST           14
  83 #define ZYNQMP_DMA_AWBURST              GENMASK(13, 12)
  84 #define ZYNQMP_DMA_AWCACHE              GENMASK(11, 8)
  85 #define ZYNQMP_DMA_AWCACHE_OFST         8
  86 #define ZYNQMP_DMA_AWQOS                GENMASK(7, 4)
  87 #define ZYNQMP_DMA_AWQOS_OFST           4
  88 #define ZYNQMP_DMA_AWLEN                GENMASK(3, 0)
  89 #define ZYNQMP_DMA_AWLEN_OFST           0
  90
  91 /* Descriptor Attribute register bit field definitions */
  92 #define ZYNQMP_DMA_AXCOHRNT             BIT(8)
  93 #define ZYNQMP_DMA_AXCACHE              GENMASK(7, 4)
  94 #define ZYNQMP_DMA_AXCACHE_OFST         4
  95 #define ZYNQMP_DMA_AXQOS                GENMASK(3, 0)
  96 #define ZYNQMP_DMA_AXQOS_OFST           0
  97
  98 /* Control register 2 bit field definitions */
  99 #define ZYNQMP_DMA_ENABLE               BIT(0)
 100
 101 /* Buffer Descriptor definitions */
 102 #define ZYNQMP_DMA_DESC_CTRL_STOP       0x10
 103 #define ZYNQMP_DMA_DESC_CTRL_COMP_INT   0x4
 104 #define ZYNQMP_DMA_DESC_CTRL_SIZE_256   0x2
 105 #define ZYNQMP_DMA_DESC_CTRL_COHRNT     0x1
 106
 107 /* Interrupt Mask specific definitions */
 108 #define ZYNQMP_DMA_INT_ERR      (ZYNQMP_DMA_AXI_RD_DATA | \
 109                                 ZYNQMP_DMA_AXI_WR_DATA | \
 110                                 ZYNQMP_DMA_AXI_RD_DST_DSCR | \
 111                                 ZYNQMP_DMA_AXI_RD_SRC_DSCR | \
 112                                 ZYNQMP_DMA_INV_APB)
 113 #define ZYNQMP_DMA_INT_OVRFL    (ZYNQMP_DMA_BYTE_CNT_OVRFL | \
 114                                 ZYNQMP_DMA_IRQ_SRC_ACCT_ERR | \
 115                                 ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 116 #define ZYNQMP_DMA_INT_DONE     (ZYNQMP_DMA_DONE | ZYNQMP_DMA_DST_DSCR_DONE)
 117 #define ZYNQMP_DMA_INT_EN_DEFAULT_MASK  (ZYNQMP_DMA_INT_DONE | \
 118                                         ZYNQMP_DMA_INT_ERR | \
 119                                         ZYNQMP_DMA_INT_OVRFL | \
 120                                         ZYNQMP_DMA_DST_DSCR_DONE)
 121
 122 /* Max number of descriptors per channel */
 123 #define ZYNQMP_DMA_NUM_DESCS    32
 124
 125 /* Max transfer size per descriptor */
 126 #define ZYNQMP_DMA_MAX_TRANS_LEN        0x40000000
 127
 128 /* Max burst lengths */
 129 #define ZYNQMP_DMA_MAX_DST_BURST_LEN    32768U
 130 #define ZYNQMP_DMA_MAX_SRC_BURST_LEN    32768U
 131
 132 /* Reset values for data attributes */
 133 #define ZYNQMP_DMA_AXCACHE_VAL          0xF
 134
 135 #define ZYNQMP_DMA_SRC_ISSUE_RST_VAL    0x1F
 136
 137 #define ZYNQMP_DMA_IDS_DEFAULT_MASK     0xFFF
 138
 139 /* Bus width in bits */
 140 #define ZYNQMP_DMA_BUS_WIDTH_64         64
 141 #define ZYNQMP_DMA_BUS_WIDTH_128        128
 142
 143 #define ZYNQMP_DMA_DESC_SIZE(chan)      (chan->desc_size)
 144
 145 #define to_chan(chan)           container_of(chan, struct zynqmp_dma_chan, \
 146                                              common)
 147 #define tx_to_desc(tx)          container_of(tx, struct zynqmp_dma_desc_sw, \
 148                                              async_tx)
 149
 150 /**
 151  * struct zynqmp_dma_desc_ll - Hw linked list descriptor
 152  * @addr: Buffer address
 153  * @size: Size of the buffer
 154  * @ctrl: Control word
 155  * @nxtdscraddr: Next descriptor base address
 156  * @rsvd: Reserved field and for Hw internal use.
 157  */
 158 struct zynqmp_dma_desc_ll {
 159         u64 addr;
 160         u32 size;
 161         u32 ctrl;
 162         u64 nxtdscraddr;
 163         u64 rsvd;
 164 };
 165
 166 /**
 167  * struct zynqmp_dma_desc_sw - Per Transaction structure
 168  * @src: Source address for simple mode dma
 169  * @dst: Destination address for simple mode dma
 170  * @len: Transfer length for simple mode dma
 171  * @node: Node in the channel descriptor list
 172  * @tx_list: List head for the current transfer
 173  * @async_tx: Async transaction descriptor
 174  * @src_v: Virtual address of the src descriptor
 175  * @src_p: Physical address of the src descriptor
 176  * @dst_v: Virtual address of the dst descriptor
 177  * @dst_p: Physical address of the dst descriptor
 178  */
 179 struct zynqmp_dma_desc_sw {
 180         u64 src;
 181         u64 dst;
 182         u32 len;
 183         struct list_head node;
 184         struct list_head tx_list;
 185         struct dma_async_tx_descriptor async_tx;
 186         struct zynqmp_dma_desc_ll *src_v;
 187         dma_addr_t src_p;
 188         struct zynqmp_dma_desc_ll *dst_v;
 189         dma_addr_t dst_p;
 190 };
 191
 192 /**
 193  * struct zynqmp_dma_chan - Driver specific DMA channel structure
 194  * @zdev: Driver specific device structure
 195  * @regs: Control registers offset
 196  * @lock: Descriptor operation lock
 197  * @pending_list: Descriptors waiting
 198  * @free_list: Descriptors free
 199  * @active_list: Descriptors active
 200  * @sw_desc_pool: SW descriptor pool
 201  * @done_list: Complete descriptors
 202  * @common: DMA common channel
 203  * @desc_pool_v: Statically allocated descriptor base
 204  * @desc_pool_p: Physical allocated descriptor base
 205  * @desc_free_cnt: Descriptor available count
 206  * @dev: The dma device
 207  * @irq: Channel IRQ
 208  * @is_dmacoherent: Tells whether dma operations are coherent or not
 209  * @tasklet: Cleanup work after irq
 210  * @idle : Channel status;
 211  * @desc_size: Size of the low level descriptor
 212  * @err: Channel has errors
 213  * @bus_width: Bus width
 214  * @src_burst_len: Source burst length
 215  * @dst_burst_len: Dest burst length
 216  * @clk_main: Pointer to main clock
 217  * @clk_apb: Pointer to apb clock
 218  */
 219 struct zynqmp_dma_chan {
 220         struct zynqmp_dma_device *zdev;
 221         void __iomem *regs;
 222         spinlock_t lock;
 223         struct list_head pending_list;
 224         struct list_head free_list;
 225         struct list_head active_list;
 226         struct zynqmp_dma_desc_sw *sw_desc_pool;
 227         struct list_head done_list;
 228         struct dma_chan common;
 229         void *desc_pool_v;
 230         dma_addr_t desc_pool_p;
 231         u32 desc_free_cnt;
 232         struct device *dev;
 233         int irq;
 234         bool is_dmacoherent;
 235         struct tasklet_struct tasklet;
 236         bool idle;
 237         u32 desc_size;
 238         bool err;
 239         u32 bus_width;
 240         u32 src_burst_len;
 241         u32 dst_burst_len;
 242         struct clk *clk_main;
 243         struct clk *clk_apb;
 244 };
 245
 246 /**
 247  * struct zynqmp_dma_device - DMA device structure
 248  * @dev: Device Structure
 249  * @common: DMA device structure
 250  * @chan: Driver specific DMA channel
 251  */
 252 struct zynqmp_dma_device {
 253         struct device *dev;
 254         struct dma_device common;
 255         struct zynqmp_dma_chan *chan;
 256 };
 257
 258 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
 259                                      u64 value)
 260 {
 261         lo_hi_writeq(value, chan->regs + reg);
 262 }
 263
 264 /**
 265  * zynqmp_dma_update_desc_to_ctrlr - Updates descriptor to the controller
 266  * @chan: ZynqMP DMA DMA channel pointer
 267  * @desc: Transaction descriptor pointer
 268  */
 269 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
 270                                       struct zynqmp_dma_desc_sw *desc)
 271 {
 272         dma_addr_t addr;
 273
 274         addr = desc->src_p;
 275         zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
 276         addr = desc->dst_p;
 277         zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
 278 }
 279
 280 /**
 281  * zynqmp_dma_desc_config_eod - Mark the descriptor as end descriptor
 282  * @chan: ZynqMP DMA channel pointer
 283  * @desc: Hw descriptor pointer
 284  */
 285 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
 286                                        void *desc)
 287 {
 288         struct zynqmp_dma_desc_ll *hw = (struct zynqmp_dma_desc_ll *)desc;
 289
 290         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_STOP;
 291         hw++;
 292         hw->ctrl |= ZYNQMP_DMA_DESC_CTRL_COMP_INT | ZYNQMP_DMA_DESC_CTRL_STOP;
 293 }
 294
 295 /**
 296  * zynqmp_dma_config_sg_ll_desc - Configure the linked list descriptor
 297  * @chan: ZynqMP DMA channel pointer
 298  * @sdesc: Hw descriptor pointer
 299  * @src: Source buffer address
 300  * @dst: Destination buffer address
 301  * @len: Transfer length
 302  * @prev: Previous hw descriptor pointer
 303  */
 304 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
 305                                    struct zynqmp_dma_desc_ll *sdesc,
 306                                    dma_addr_t src, dma_addr_t dst, size_t len,
 307                                    struct zynqmp_dma_desc_ll *prev)
 308 {
 309         struct zynqmp_dma_desc_ll *ddesc = sdesc + 1;
 310
 311         sdesc->size = ddesc->size = len;
 312         sdesc->addr = src;
 313         ddesc->addr = dst;
 314
 315         sdesc->ctrl = ddesc->ctrl = ZYNQMP_DMA_DESC_CTRL_SIZE_256;
 316         if (chan->is_dmacoherent) {
 317                 sdesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 318                 ddesc->ctrl |= ZYNQMP_DMA_DESC_CTRL_COHRNT;
 319         }
 320
 321         if (prev) {
 322                 dma_addr_t addr = chan->desc_pool_p +
 323                             ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
 324                 ddesc = prev + 1;
 325                 prev->nxtdscraddr = addr;
 326                 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
 327         }
 328 }
 329
 330 /**
 331  * zynqmp_dma_init - Initialize the channel
 332  * @chan: ZynqMP DMA channel pointer
 333  */
 334 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
 335 {
 336         u32 val;
 337
 338         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 339         val = readl(chan->regs + ZYNQMP_DMA_ISR);
 340         writel(val, chan->regs + ZYNQMP_DMA_ISR);
 341
 342         if (chan->is_dmacoherent) {
 343                 val = ZYNQMP_DMA_AXCOHRNT;
 344                 val = (val & ~ZYNQMP_DMA_AXCACHE) |
 345                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AXCACHE_OFST);
 346                 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
 347         }
 348
 349         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 350         if (chan->is_dmacoherent) {
 351                 val = (val & ~ZYNQMP_DMA_ARCACHE) |
 352                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_ARCACHE_OFST);
 353                 val = (val & ~ZYNQMP_DMA_AWCACHE) |
 354                         (ZYNQMP_DMA_AXCACHE_VAL << ZYNQMP_DMA_AWCACHE_OFST);
 355         }
 356         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 357
 358         /* Clearing the interrupt account rgisters */
 359         val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 360         val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 361
 362         chan->idle = true;
 363 }
 364
 365 /**
 366  * zynqmp_dma_tx_submit - Submit DMA transaction
 367  * @tx: Async transaction descriptor pointer
 368  *
 369  * Return: cookie value
 370  */
 371 static dma_cookie_t zynqmp_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 372 {
 373         struct zynqmp_dma_chan *chan = to_chan(tx->chan);
 374         struct zynqmp_dma_desc_sw *desc, *new;
 375         dma_cookie_t cookie;
 376
 377         new = tx_to_desc(tx);
 378         spin_lock_bh(&chan->lock);
 379         cookie = dma_cookie_assign(tx);
 380
 381         if (!list_empty(&chan->pending_list)) {
 382                 desc = list_last_entry(&chan->pending_list,
 383                                      struct zynqmp_dma_desc_sw, node);
 384                 if (!list_empty(&desc->tx_list))
 385                         desc = list_last_entry(&desc->tx_list,
 386                                                struct zynqmp_dma_desc_sw, node);
 387                 desc->src_v->nxtdscraddr = new->src_p;
 388                 desc->src_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 389                 desc->dst_v->nxtdscraddr = new->dst_p;
 390                 desc->dst_v->ctrl &= ~ZYNQMP_DMA_DESC_CTRL_STOP;
 391         }
 392
 393         list_add_tail(&new->node, &chan->pending_list);
 394         spin_unlock_bh(&chan->lock);
 395
 396         return cookie;
 397 }
 398
 399 /**
 400  * zynqmp_dma_get_descriptor - Get the sw descriptor from the pool
 401  * @chan: ZynqMP DMA channel pointer
 402  *
 403  * Return: The sw descriptor
 404  */
 405 static struct zynqmp_dma_desc_sw *
 406 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
 407 {
 408         struct zynqmp_dma_desc_sw *desc;
 409
 410         spin_lock_bh(&chan->lock);
 411         desc = list_first_entry(&chan->free_list,
 412                                 struct zynqmp_dma_desc_sw, node);
 413         list_del(&desc->node);
 414         spin_unlock_bh(&chan->lock);
 415
 416         INIT_LIST_HEAD(&desc->tx_list);
 417         /* Clear the src and dst descriptor memory */
 418         memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 419         memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
 420
 421         return desc;
 422 }
 423
 424 /**
 425  * zynqmp_dma_free_descriptor - Issue pending transactions
 426  * @chan: ZynqMP DMA channel pointer
 427  * @sdesc: Transaction descriptor pointer
 428  */
 429 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
 430                                  struct zynqmp_dma_desc_sw *sdesc)
 431 {
 432         struct zynqmp_dma_desc_sw *child, *next;
 433
 434         chan->desc_free_cnt++;
 435         list_add_tail(&sdesc->node, &chan->free_list);
 436         list_for_each_entry_safe(child, next, &sdesc->tx_list, node) {
 437                 chan->desc_free_cnt++;
 438                 list_move_tail(&child->node, &chan->free_list);
 439         }
 440 }
 441
 442 /**
 443  * zynqmp_dma_free_desc_list - Free descriptors list
 444  * @chan: ZynqMP DMA channel pointer
 445  * @list: List to parse and delete the descriptor
 446  */
 447 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
 448                                       struct list_head *list)
 449 {
 450         struct zynqmp_dma_desc_sw *desc, *next;
 451
 452         list_for_each_entry_safe(desc, next, list, node)
 453                 zynqmp_dma_free_descriptor(chan, desc);
 454 }
 455
 456 /**
 457  * zynqmp_dma_alloc_chan_resources - Allocate channel resources
 458  * @dchan: DMA channel
 459  *
 460  * Return: Number of descriptors on success and failure value on error
 461  */
 462 static int zynqmp_dma_alloc_chan_resources(struct dma_chan *dchan)
 463 {
 464         struct zynqmp_dma_chan *chan = to_chan(dchan);
 465         struct zynqmp_dma_desc_sw *desc;
 466         int i;
 467
 468         chan->sw_desc_pool = kzalloc(sizeof(*desc) * ZYNQMP_DMA_NUM_DESCS,
 469                                      GFP_KERNEL);
 470         if (!chan->sw_desc_pool)
 471                 return -ENOMEM;
 472
 473         chan->idle = true;
 474         chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
 475
 476         INIT_LIST_HEAD(&chan->free_list);
 477
 478         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 479                 desc = chan->sw_desc_pool + i;
 480                 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
 481                 desc->async_tx.tx_submit = zynqmp_dma_tx_submit;
 482                 list_add_tail(&desc->node, &chan->free_list);
 483         }
 484
 485         chan->desc_pool_v = dma_zalloc_coherent(chan->dev,
 486                                 (2 * chan->desc_size * ZYNQMP_DMA_NUM_DESCS),
 487                                 &chan->desc_pool_p, GFP_KERNEL);
 488         if (!chan->desc_pool_v)
 489                 return -ENOMEM;
 490
 491         for (i = 0; i < ZYNQMP_DMA_NUM_DESCS; i++) {
 492                 desc = chan->sw_desc_pool + i;
 493                 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
 494                                         (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
 495                 desc->dst_v = (struct zynqmp_dma_desc_ll *) (desc->src_v + 1);
 496                 desc->src_p = chan->desc_pool_p +
 497                                 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
 498                 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
 499         }
 500
 501         return ZYNQMP_DMA_NUM_DESCS;
 502 }
 503
 504 /**
 505  * zynqmp_dma_start - Start DMA channel
 506  * @chan: ZynqMP DMA channel pointer
 507  */
 508 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
 509 {
 510         writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
 511         chan->idle = false;
 512         writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
 513 }
 514
 515 /**
 516  * zynqmp_dma_handle_ovfl_int - Process the overflow interrupt
 517  * @chan: ZynqMP DMA channel pointer
 518  * @status: Interrupt status value
 519  */
 520 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
 521 {
 522         u32 val;
 523
 524         if (status & ZYNQMP_DMA_IRQ_DST_ACCT_ERR)
 525                 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 526         if (status & ZYNQMP_DMA_IRQ_SRC_ACCT_ERR)
 527                 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
 528 }
 529
 530 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
 531 {
 532         u32 val, burst_val;
 533
 534         val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
 535         val |= ZYNQMP_DMA_POINT_TYPE_SG;
 536         writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
 537
 538         val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
 539         burst_val = __ilog2_u32(chan->src_burst_len);
 540         val = (val & ~ZYNQMP_DMA_ARLEN) |
 541                 ((burst_val << ZYNQMP_DMA_ARLEN_OFST) & ZYNQMP_DMA_ARLEN);
 542         burst_val = __ilog2_u32(chan->dst_burst_len);
 543         val = (val & ~ZYNQMP_DMA_AWLEN) |
 544                 ((burst_val << ZYNQMP_DMA_AWLEN_OFST) & ZYNQMP_DMA_AWLEN);
 545         writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
 546 }
 547
 548 /**
 549  * zynqmp_dma_device_config - Zynqmp dma device configuration
 550  * @dchan: DMA channel
 551  * @config: DMA device config
 552  */
 553 static int zynqmp_dma_device_config(struct dma_chan *dchan,
 554                                     struct dma_slave_config *config)
 555 {
 556         struct zynqmp_dma_chan *chan = to_chan(dchan);
 557
 558         chan->src_burst_len = clamp(config->src_maxburst, 1U,
 559                 ZYNQMP_DMA_MAX_SRC_BURST_LEN);
 560         chan->dst_burst_len = clamp(config->dst_maxburst, 1U,
 561                 ZYNQMP_DMA_MAX_DST_BURST_LEN);
 562
 563         return 0;
 564 }
 565
 566 /**
 567  * zynqmp_dma_start_transfer - Initiate the new transfer
 568  * @chan: ZynqMP DMA channel pointer
 569  */
 570 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
 571 {
 572         struct zynqmp_dma_desc_sw *desc;
 573
 574         if (!chan->idle)
 575                 return;
 576
 577         zynqmp_dma_config(chan);
 578
 579         desc = list_first_entry_or_null(&chan->pending_list,
 580                                         struct zynqmp_dma_desc_sw, node);
 581         if (!desc)
 582                 return;
 583
 584         list_splice_tail_init(&chan->pending_list, &chan->active_list);
 585         zynqmp_dma_update_desc_to_ctrlr(chan, desc);
 586         zynqmp_dma_start(chan);
 587 }
 588
 589
 590 /**
 591  * zynqmp_dma_chan_desc_cleanup - Cleanup the completed descriptors
 592  * @chan: ZynqMP DMA channel
 593  */
 594 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
 595 {
 596         struct zynqmp_dma_desc_sw *desc, *next;
 597
 598         list_for_each_entry_safe(desc, next, &chan->done_list, node) {
 599                 dma_async_tx_callback callback;
 600                 void *callback_param;
 601
 602                 list_del(&desc->node);
 603
 604                 callback = desc->async_tx.callback;
 605                 callback_param = desc->async_tx.callback_param;
 606                 if (callback) {
 607                         spin_unlock(&chan->lock);
 608                         callback(callback_param);
 609                         spin_lock(&chan->lock);
 610                 }
 611
 612                 /* Run any dependencies, then free the descriptor */
 613                 zynqmp_dma_free_descriptor(chan, desc);
 614         }
 615 }
 616
 617 /**
 618  * zynqmp_dma_complete_descriptor - Mark the active descriptor as complete
 619  * @chan: ZynqMP DMA channel pointer
 620  */
 621 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
 622 {
 623         struct zynqmp_dma_desc_sw *desc;
 624
 625         desc = list_first_entry_or_null(&chan->active_list,
 626                                         struct zynqmp_dma_desc_sw, node);
 627         if (!desc)
 628                 return;
 629         list_del(&desc->node);
 630         dma_cookie_complete(&desc->async_tx);
 631         list_add_tail(&desc->node, &chan->done_list);
 632 }
 633
 634 /**
 635  * zynqmp_dma_issue_pending - Issue pending transactions
 636  * @dchan: DMA channel pointer
 637  */
 638 static void zynqmp_dma_issue_pending(struct dma_chan *dchan)
 639 {
 640         struct zynqmp_dma_chan *chan = to_chan(dchan);
 641
 642         spin_lock_bh(&chan->lock);
 643         zynqmp_dma_start_transfer(chan);
 644         spin_unlock_bh(&chan->lock);
 645 }
 646
 647 /**
 648  * zynqmp_dma_free_descriptors - Free channel descriptors
 649  * @dchan: DMA channel pointer
 650  */
 651 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
 652 {
 653         zynqmp_dma_free_desc_list(chan, &chan->active_list);
 654         zynqmp_dma_free_desc_list(chan, &chan->pending_list);
 655         zynqmp_dma_free_desc_list(chan, &chan->done_list);
 656 }
 657
 658 /**
 659  * zynqmp_dma_free_chan_resources - Free channel resources
 660  * @dchan: DMA channel pointer
 661  */
 662 static void zynqmp_dma_free_chan_resources(struct dma_chan *dchan)
 663 {
 664         struct zynqmp_dma_chan *chan = to_chan(dchan);
 665
 666         spin_lock_bh(&chan->lock);
 667         zynqmp_dma_free_descriptors(chan);
 668         spin_unlock_bh(&chan->lock);
 669         dma_free_coherent(chan->dev,
 670                 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
 671                 chan->desc_pool_v, chan->desc_pool_p);
 672         kfree(chan->sw_desc_pool);
 673 }
 674
 675 /**
 676  * zynqmp_dma_reset - Reset the channel
 677  * @chan: ZynqMP DMA channel pointer
 678  */
 679 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
 680 {
 681         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 682
 683         zynqmp_dma_complete_descriptor(chan);
 684         zynqmp_dma_chan_desc_cleanup(chan);
 685         zynqmp_dma_free_descriptors(chan);
 686         zynqmp_dma_init(chan);
 687 }
 688
 689 /**
 690  * zynqmp_dma_irq_handler - ZynqMP DMA Interrupt handler
 691  * @irq: IRQ number
 692  * @data: Pointer to the ZynqMP DMA channel structure
 693  *
 694  * Return: IRQ_HANDLED/IRQ_NONE
 695  */
 696 static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
 697 {
 698         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 699         u32 isr, imr, status;
 700         irqreturn_t ret = IRQ_NONE;
 701
 702         isr = readl(chan->regs + ZYNQMP_DMA_ISR);
 703         imr = readl(chan->regs + ZYNQMP_DMA_IMR);
 704         status = isr & ~imr;
 705
 706         writel(isr, chan->regs + ZYNQMP_DMA_ISR);
 707         if (status & ZYNQMP_DMA_INT_DONE) {
 708                 tasklet_schedule(&chan->tasklet);
 709                 ret = IRQ_HANDLED;
 710         }
 711
 712         if (status & ZYNQMP_DMA_DONE)
 713                 chan->idle = true;
 714
 715         if (status & ZYNQMP_DMA_INT_ERR) {
 716                 chan->err = true;
 717                 tasklet_schedule(&chan->tasklet);
 718                 dev_err(chan->dev, "Channel %p has errors\n", chan);
 719                 ret = IRQ_HANDLED;
 720         }
 721
 722         if (status & ZYNQMP_DMA_INT_OVRFL) {
 723                 zynqmp_dma_handle_ovfl_int(chan, status);
 724                 dev_info(chan->dev, "Channel %p overflow interrupt\n", chan);
 725                 ret = IRQ_HANDLED;
 726         }
 727
 728         return ret;
 729 }
 730
 731 /**
 732  * zynqmp_dma_do_tasklet - Schedule completion tasklet
 733  * @data: Pointer to the ZynqMP DMA channel structure
 734  */
 735 static void zynqmp_dma_do_tasklet(unsigned long data)
 736 {
 737         struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
 738         u32 count;
 739
 740         spin_lock(&chan->lock);
 741
 742         if (chan->err) {
 743                 zynqmp_dma_reset(chan);
 744                 chan->err = false;
 745                 goto unlock;
 746         }
 747
 748         count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
 749
 750         while (count) {
 751                 zynqmp_dma_complete_descriptor(chan);
 752                 zynqmp_dma_chan_desc_cleanup(chan);
 753                 count--;
 754         }
 755
 756         if (chan->idle)
 757                 zynqmp_dma_start_transfer(chan);
 758
 759 unlock:
 760         spin_unlock(&chan->lock);
 761 }
 762
 763 /**
 764  * zynqmp_dma_device_terminate_all - Aborts all transfers on a channel
 765  * @dchan: DMA channel pointer
 766  *
 767  * Return: Always '0'
 768  */
 769 static int zynqmp_dma_device_terminate_all(struct dma_chan *dchan)
 770 {
 771         struct zynqmp_dma_chan *chan = to_chan(dchan);
 772
 773         spin_lock_bh(&chan->lock);
 774         writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
 775         zynqmp_dma_free_descriptors(chan);
 776         spin_unlock_bh(&chan->lock);
 777
 778         return 0;
 779 }
 780
 781 /**
 782  * zynqmp_dma_prep_memcpy - prepare descriptors for memcpy transaction
 783  * @dchan: DMA channel
 784  * @dma_dst: Destination buffer address
 785  * @dma_src: Source buffer address
 786  * @len: Transfer length
 787  * @flags: transfer ack flags
 788  *
 789  * Return: Async transaction descriptor on success and NULL on failure
 790  */
 791 static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
 792                                 struct dma_chan *dchan, dma_addr_t dma_dst,
 793                                 dma_addr_t dma_src, size_t len, ulong flags)
 794 {
 795         struct zynqmp_dma_chan *chan;
 796         struct zynqmp_dma_desc_sw *new, *first = NULL;
 797         void *desc = NULL, *prev = NULL;
 798         size_t copy;
 799         u32 desc_cnt;
 800
 801         chan = to_chan(dchan);
 802
 803         if (len > ZYNQMP_DMA_MAX_TRANS_LEN)
 804                 return NULL;
 805
 806         desc_cnt = DIV_ROUND_UP(len, ZYNQMP_DMA_MAX_TRANS_LEN);
 807
 808         spin_lock_bh(&chan->lock);
 809         if (desc_cnt > chan->desc_free_cnt) {
 810                 spin_unlock_bh(&chan->lock);
 811                 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
 812                 return NULL;
 813         }
 814         chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
 815         spin_unlock_bh(&chan->lock);
 816
 817         do {
 818                 /* Allocate and populate the descriptor */
 819                 new = zynqmp_dma_get_descriptor(chan);
 820
 821                 copy = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
 822                 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
 823                 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
 824                                              dma_dst, copy, prev);
 825                 prev = desc;
 826                 len -= copy;
 827                 dma_src += copy;
 828                 dma_dst += copy;
 829                 if (!first)
 830                         first = new;
 831                 else
 832                         list_add_tail(&new->node, &first->tx_list);
 833         } while (len);
 834
 835         zynqmp_dma_desc_config_eod(chan, desc);
 836         async_tx_ack(&first->async_tx);
 837         first->async_tx.flags = flags;
 838         return &first->async_tx;
 839 }
 840
 841 /**
 842  * zynqmp_dma_prep_slave_sg - prepare descriptors for a memory sg transaction
 843  * @dchan: DMA channel
 844  * @dst_sg: Destination scatter list
 845  * @dst_sg_len: Number of entries in destination scatter list
 846  * @src_sg: Source scatter list
 847  * @src_sg_len: Number of entries in source scatter list
 848  * @flags: transfer ack flags
 849  *
 850  * Return: Async transaction descriptor on success and NULL on failure
 851  */
 852 static struct dma_async_tx_descriptor *zynqmp_dma_prep_sg(
 853                         struct dma_chan *dchan, struct scatterlist *dst_sg,
 854                         unsigned int dst_sg_len, struct scatterlist *src_sg,
 855                         unsigned int src_sg_len, unsigned long flags)
 856 {
 857         struct zynqmp_dma_desc_sw *new, *first = NULL;
 858         struct zynqmp_dma_chan *chan = to_chan(dchan);
 859         void *desc = NULL, *prev = NULL;
 860         size_t len, dst_avail, src_avail;
 861         dma_addr_t dma_dst, dma_src;
 862         u32 desc_cnt = 0, i;
 863         struct scatterlist *sg;
 864
 865         for_each_sg(src_sg, sg, src_sg_len, i)
 866                 desc_cnt += DIV_ROUND_UP(sg_dma_len(sg),
 867                                          ZYNQMP_DMA_MAX_TRANS_LEN);
 868
 869         spin_lock_bh(&chan->lock);
 870         if (desc_cnt > chan->desc_free_cnt) {
 871                 spin_unlock_bh(&chan->lock);
 872                 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
 873                 return NULL;
 874         }
 875         chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
 876         spin_unlock_bh(&chan->lock);
 877
 878         dst_avail = sg_dma_len(dst_sg);
 879         src_avail = sg_dma_len(src_sg);
 880
 881         /* Run until we are out of scatterlist entries */
 882         while (true) {
 883                 /* Allocate and populate the descriptor */
 884                 new = zynqmp_dma_get_descriptor(chan);
 885                 desc = (struct zynqmp_dma_desc_ll *)new->src_v;
 886                 len = min_t(size_t, src_avail, dst_avail);
 887                 len = min_t(size_t, len, ZYNQMP_DMA_MAX_TRANS_LEN);
 888                 if (len == 0)
 889                         goto fetch;
 890                 dma_dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) -
 891                         dst_avail;
 892                 dma_src = sg_dma_address(src_sg) + sg_dma_len(src_sg) -
 893                         src_avail;
 894
 895                 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src, dma_dst,
 896                                              len, prev);
 897                 prev = desc;
 898                 dst_avail -= len;
 899                 src_avail -= len;
 900
 901                 if (!first)
 902                         first = new;
 903                 else
 904                         list_add_tail(&new->node, &first->tx_list);
 905 fetch:
 906                 /* Fetch the next dst scatterlist entry */
 907                 if (dst_avail == 0) {
 908                         if (dst_sg_len == 0)
 909                                 break;
 910                         dst_sg = sg_next(dst_sg);
 911                         if (dst_sg == NULL)
 912                                 break;
 913                         dst_sg_len--;
 914                         dst_avail = sg_dma_len(dst_sg);
 915                 }
 916                 /* Fetch the next src scatterlist entry */
 917                 if (src_avail == 0) {
 918                         if (src_sg_len == 0)
 919                                 break;
 920                         src_sg = sg_next(src_sg);
 921                         if (src_sg == NULL)
 922                                 break;
 923                         src_sg_len--;
 924                         src_avail = sg_dma_len(src_sg);
 925                 }
 926         }
 927
 928         zynqmp_dma_desc_config_eod(chan, desc);
 929         first->async_tx.flags = flags;
 930         return &first->async_tx;
 931 }
 932
 933 /**
 934  * zynqmp_dma_chan_remove - Channel remove function
 935  * @chan: ZynqMP DMA channel pointer
 936  */
 937 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
 938 {
 939         if (!chan)
 940                 return;
 941
 942         if (chan->irq)
 943                 devm_free_irq(chan->zdev->dev, chan->irq, chan);
 944         tasklet_kill(&chan->tasklet);
 945         list_del(&chan->common.device_node);
 946         clk_disable_unprepare(chan->clk_apb);
 947         clk_disable_unprepare(chan->clk_main);
 948 }
 949
 950 /**
 951  * zynqmp_dma_chan_probe - Per Channel Probing
 952  * @zdev: Driver specific device structure
 953  * @pdev: Pointer to the platform_device structure
 954  *
 955  * Return: '0' on success and failure value on error
 956  */
 957 static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev,
 958                            struct platform_device *pdev)
 959 {
 960         struct zynqmp_dma_chan *chan;
 961         struct resource *res;
 962         struct device_node *node = pdev->dev.of_node;
 963         int err;
 964
 965         chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
 966         if (!chan)
 967                 return -ENOMEM;
 968         chan->dev = zdev->dev;
 969         chan->zdev = zdev;
 970
 971         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 972         chan->regs = devm_ioremap_resource(&pdev->dev, res);
 973         if (IS_ERR(chan->regs))
 974                 return PTR_ERR(chan->regs);
 975
 976         chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
 977         chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN;
 978         chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN;
 979         err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
 980         if (err < 0) {
 981                 dev_err(&pdev->dev, "missing xlnx,bus-width property\n");
 982                 return err;
 983         }
 984
 985         if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
 986             chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
 987                 dev_err(zdev->dev, "invalid bus-width value");
 988                 return -EINVAL;
 989         }
 990
 991         chan->is_dmacoherent =  of_property_read_bool(node, "dma-coherent");
 992         zdev->chan = chan;
 993         tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
 994         spin_lock_init(&chan->lock);
 995         INIT_LIST_HEAD(&chan->active_list);
 996         INIT_LIST_HEAD(&chan->pending_list);
 997         INIT_LIST_HEAD(&chan->done_list);
 998         INIT_LIST_HEAD(&chan->free_list);
 999
1000         dma_cookie_init(&chan->common);
1001         chan->common.device = &zdev->common;
1002         list_add_tail(&chan->common.device_node, &zdev->common.channels);
1003
1004         zynqmp_dma_init(chan);
1005         chan->irq = platform_get_irq(pdev, 0);
1006         if (chan->irq < 0)
1007                 return -ENXIO;
1008         err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
1009                                "zynqmp-dma", chan);
1010         if (err)
1011                 return err;
1012         chan->clk_main = devm_clk_get(&pdev->dev, "clk_main");
1013         if (IS_ERR(chan->clk_main)) {
1014                 dev_err(&pdev->dev, "main clock not found.\n");
1015                 return PTR_ERR(chan->clk_main);
1016         }
1017
1018         chan->clk_apb = devm_clk_get(&pdev->dev, "clk_apb");
1019         if (IS_ERR(chan->clk_apb)) {
1020                 dev_err(&pdev->dev, "apb clock not found.\n");
1021                 return PTR_ERR(chan->clk_apb);
1022         }
1023
1024         err = clk_prepare_enable(chan->clk_main);
1025         if (err) {
1026                 dev_err(&pdev->dev, "Unable to enable main clock.\n");
1027                 return err;
1028         }
1029
1030         err = clk_prepare_enable(chan->clk_apb);
1031         if (err) {
1032                 clk_disable_unprepare(chan->clk_main);
1033                 dev_err(&pdev->dev, "Unable to enable apb clock.\n");
1034                 return err;
1035         }
1036
1037         chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
1038         chan->idle = true;
1039         return 0;
1040 }
1041
1042 /**
1043  * of_zynqmp_dma_xlate - Translation function
1044  * @dma_spec: Pointer to DMA specifier as found in the device tree
1045  * @ofdma: Pointer to DMA controller data
1046  *
1047  * Return: DMA channel pointer on success and NULL on error
1048  */
1049 static struct dma_chan *of_zynqmp_dma_xlate(struct of_phandle_args *dma_spec,
1050                                             struct of_dma *ofdma)
1051 {
1052         struct zynqmp_dma_device *zdev = ofdma->of_dma_data;
1053
1054         return dma_get_slave_channel(&zdev->chan->common);
1055 }
1056
1057 /**
1058  * zynqmp_dma_probe - Driver probe function
1059  * @pdev: Pointer to the platform_device structure
1060  *
1061  * Return: '0' on success and failure value on error
1062  */
1063 static int zynqmp_dma_probe(struct platform_device *pdev)
1064 {
1065         struct zynqmp_dma_device *zdev;
1066         struct dma_device *p;
1067         int ret;
1068
1069         zdev = devm_kzalloc(&pdev->dev, sizeof(*zdev), GFP_KERNEL);
1070         if (!zdev)
1071                 return -ENOMEM;
1072
1073         zdev->dev = &pdev->dev;
1074         INIT_LIST_HEAD(&zdev->common.channels);
1075
1076         dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1077         dma_cap_set(DMA_SG, zdev->common.cap_mask);
1078         dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
1079
1080         p = &zdev->common;
1081         p->device_prep_dma_sg = zynqmp_dma_prep_sg;
1082         p->device_prep_dma_memcpy = zynqmp_dma_prep_memcpy;
1083         p->device_terminate_all = zynqmp_dma_device_terminate_all;
1084         p->device_issue_pending = zynqmp_dma_issue_pending;
1085         p->device_alloc_chan_resources = zynqmp_dma_alloc_chan_resources;
1086         p->device_free_chan_resources = zynqmp_dma_free_chan_resources;
1087         p->device_tx_status = dma_cookie_status;
1088         p->device_config = zynqmp_dma_device_config;
1089         p->dev = &pdev->dev;
1090
1091         platform_set_drvdata(pdev, zdev);
1092
1093         ret = zynqmp_dma_chan_probe(zdev, pdev);
1094         if (ret) {
1095                 dev_err(&pdev->dev, "Probing channel failed\n");
1096                 goto free_chan_resources;
1097         }
1098
1099         p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1100         p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1101
1102         dma_async_device_register(&zdev->common);
1103
1104         ret = of_dma_controller_register(pdev->dev.of_node,
1105                                          of_zynqmp_dma_xlate, zdev);
1106         if (ret) {
1107                 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
1108                 dma_async_device_unregister(&zdev->common);
1109                 goto free_chan_resources;
1110         }
1111
1112         dev_info(&pdev->dev, "ZynqMP DMA driver Probe success\n");
1113
1114         return 0;
1115
1116 free_chan_resources:
1117         zynqmp_dma_chan_remove(zdev->chan);
1118         return ret;
1119 }
1120
1121 /**
1122  * zynqmp_dma_remove - Driver remove function
1123  * @pdev: Pointer to the platform_device structure
1124  *
1125  * Return: Always '0'
1126  */
1127 static int zynqmp_dma_remove(struct platform_device *pdev)
1128 {
1129         struct zynqmp_dma_device *zdev = platform_get_drvdata(pdev);
1130
1131         of_dma_controller_free(pdev->dev.of_node);
1132         dma_async_device_unregister(&zdev->common);
1133
1134         zynqmp_dma_chan_remove(zdev->chan);
1135
1136         return 0;
1137 }
1138
1139 static const struct of_device_id zynqmp_dma_of_match[] = {
1140         { .compatible = "xlnx,zynqmp-dma-1.0", },
1141         {}
1142 };
1143 MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
1144
1145 static struct platform_driver zynqmp_dma_driver = {
1146         .driver = {
1147                 .name = "xilinx-zynqmp-dma",
1148                 .of_match_table = zynqmp_dma_of_match,
1149         },
1150         .probe = zynqmp_dma_probe,
1151         .remove = zynqmp_dma_remove,
1152 };
1153
1154 module_platform_driver(zynqmp_dma_driver);
1155
1156 MODULE_LICENSE("GPL");
1157 MODULE_AUTHOR("Xilinx, Inc.");
1158 MODULE_DESCRIPTION("Xilinx ZynqMP DMA driver");