x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / arch / frv / include / asm / gpio-regs.h
blob9edf5d5d4d3fc896be8a8314bcd958d510b1ee12
1 /* gpio-regs.h: on-chip general purpose I/O registers
3 * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #ifndef _ASM_GPIO_REGS
13 #define _ASM_GPIO_REGS
15 #define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
17 #define __get_PDR() ({ __reg(0xfeff0400); })
18 #define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
20 #define __get_GPDR() ({ __reg(0xfeff0408); })
21 #define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
23 #define __get_SIR() ({ __reg(0xfeff0410); })
24 #define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
26 #define __get_SOR() ({ __reg(0xfeff0418); })
27 #define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
29 #define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
31 #define __set_PDCR(V) do { __reg(0xfeff0428) = (V); mb(); } while(0)
33 #define __get_RSTR() ({ __reg(0xfeff0500); })
34 #define __set_RSTR(V) do { __reg(0xfeff0500) = (V); mb(); } while(0)
38 /* PDR definitions */
39 #define PDR_GPIO_DATA(X) (1 << (X))
41 /* GPDR definitions */
42 #define GPDR_INPUT 0
43 #define GPDR_OUTPUT 1
44 #define GPDR_DREQ0_BIT 0x00001000
45 #define GPDR_DREQ1_BIT 0x00008000
46 #define GPDR_DREQ2_BIT 0x00040000
47 #define GPDR_DREQ3_BIT 0x00080000
48 #define GPDR_DREQ4_BIT 0x00004000
49 #define GPDR_DREQ5_BIT 0x00020000
50 #define GPDR_DREQ6_BIT 0x00100000
51 #define GPDR_DREQ7_BIT 0x00200000
52 #define GPDR_DACK0_BIT 0x00002000
53 #define GPDR_DACK1_BIT 0x00010000
54 #define GPDR_DACK2_BIT 0x00100000
55 #define GPDR_DACK3_BIT 0x00200000
56 #define GPDR_DONE0_BIT 0x00004000
57 #define GPDR_DONE1_BIT 0x00020000
58 #define GPDR_GPIO_DIR(X,D) ((D) << (X))
60 /* SIR definitions */
61 #define SIR_GPIO_INPUT 0
62 #define SIR_DREQ7_INPUT 0x00200000
63 #define SIR_DREQ6_INPUT 0x00100000
64 #define SIR_DREQ3_INPUT 0x00080000
65 #define SIR_DREQ2_INPUT 0x00040000
66 #define SIR_DREQ5_INPUT 0x00020000
67 #define SIR_DREQ1_INPUT 0x00008000
68 #define SIR_DREQ4_INPUT 0x00004000
69 #define SIR_DREQ0_INPUT 0x00001000
70 #define SIR_RXD1_INPUT 0x00000400
71 #define SIR_CTS0_INPUT 0x00000100
72 #define SIR_RXD0_INPUT 0x00000040
73 #define SIR_GATE1_INPUT 0x00000020
74 #define SIR_GATE0_INPUT 0x00000010
75 #define SIR_IRQ3_INPUT 0x00000008
76 #define SIR_IRQ2_INPUT 0x00000004
77 #define SIR_IRQ1_INPUT 0x00000002
78 #define SIR_IRQ0_INPUT 0x00000001
79 #define SIR_DREQ_BITS (SIR_DREQ0_INPUT | SIR_DREQ1_INPUT | \
80 SIR_DREQ2_INPUT | SIR_DREQ3_INPUT | \
81 SIR_DREQ4_INPUT | SIR_DREQ5_INPUT | \
82 SIR_DREQ6_INPUT | SIR_DREQ7_INPUT)
84 /* SOR definitions */
85 #define SOR_GPIO_OUTPUT 0
86 #define SOR_DACK3_OUTPUT 0x00200000
87 #define SOR_DACK2_OUTPUT 0x00100000
88 #define SOR_DONE1_OUTPUT 0x00020000
89 #define SOR_DACK1_OUTPUT 0x00010000
90 #define SOR_DONE0_OUTPUT 0x00004000
91 #define SOR_DACK0_OUTPUT 0x00002000
92 #define SOR_TXD1_OUTPUT 0x00000800
93 #define SOR_RTS0_OUTPUT 0x00000200
94 #define SOR_TXD0_OUTPUT 0x00000080
95 #define SOR_TOUT1_OUTPUT 0x00000020
96 #define SOR_TOUT0_OUTPUT 0x00000010
97 #define SOR_DONE_BITS (SOR_DONE0_OUTPUT | SOR_DONE1_OUTPUT)
98 #define SOR_DACK_BITS (SOR_DACK0_OUTPUT | SOR_DACK1_OUTPUT | \
99 SOR_DACK2_OUTPUT | SOR_DACK3_OUTPUT)
101 /* PDSR definitions */
102 #define PDSR_UNCHANGED 0
103 #define PDSR_SET_BIT(X) (1 << (X))
105 /* PDCR definitions */
106 #define PDCR_UNCHANGED 0
107 #define PDCR_CLEAR_BIT(X) (1 << (X))
109 /* RSTR definitions */
110 /* Read Only */
111 #define RSTR_POWERON 0x00000400
112 #define RSTR_SOFTRESET_STATUS 0x00000100
113 /* Write Only */
114 #define RSTR_SOFTRESET 0x00000001
116 #endif /* _ASM_GPIO_REGS */