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x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / arch / sh / lib64 / dbg.c
blob6152a6a6d9c6e17309ece74b15dc807c8cd78205
1 /*--------------------------------------------------------------------------
2 --
3 -- Identity : Linux50 Debug Funcions
4 --
5 -- File : arch/sh/lib64/dbg.c
6 --
7 -- Copyright 2000, 2001 STMicroelectronics Limited.
8 -- Copyright 2004 Richard Curnow (evt_debug etc)
9 --
10 --------------------------------------------------------------------------*/
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/mm.h>
15 #include <linux/fs.h>
16 #include <asm/mmu_context.h>
17
18 typedef u64 regType_t;
19
20 static regType_t getConfigReg(u64 id)
21 {
22 register u64 reg __asm__("r2");
23 asm volatile ("getcfg %1, 0, %0":"=r" (reg):"r"(id));
24 return (reg);
25 }
26
27 /* ======================================================================= */
28
29 static char *szTab[] = { "4k", "64k", "1M", "512M" };
30 static char *protTab[] = { "----",
31 "---R",
32 "--X-",
33 "--XR",
34 "-W--",
35 "-W-R",
36 "-WX-",
37 "-WXR",
38 "U---",
39 "U--R",
40 "U-X-",
41 "U-XR",
42 "UW--",
43 "UW-R",
44 "UWX-",
45 "UWXR"
46 };
47 #define ITLB_BASE 0x00000000
48 #define DTLB_BASE 0x00800000
49 #define MAX_TLBs 64
50 /* PTE High */
51 #define GET_VALID(pte) ((pte) & 0x1)
52 #define GET_SHARED(pte) ((pte) & 0x2)
53 #define GET_ASID(pte) ((pte >> 2) & 0x0ff)
54 #define GET_EPN(pte) ((pte) & 0xfffff000)
55
56 /* PTE Low */
57 #define GET_CBEHAVIOR(pte) ((pte) & 0x3)
58 #define GET_PAGE_SIZE(pte) szTab[((pte >> 3) & 0x3)]
59 #define GET_PROTECTION(pte) protTab[((pte >> 6) & 0xf)]
60 #define GET_PPN(pte) ((pte) & 0xfffff000)
61
62 #define PAGE_1K_MASK 0x00000000
63 #define PAGE_4K_MASK 0x00000010
64 #define PAGE_64K_MASK 0x00000080
65 #define MMU_PAGESIZE_MASK (PAGE_64K_MASK | PAGE_4K_MASK)
66 #define PAGE_1MB_MASK MMU_PAGESIZE_MASK
67 #define PAGE_1K (1024)
68 #define PAGE_4K (1024 * 4)
69 #define PAGE_64K (1024 * 64)
70 #define PAGE_1MB (1024 * 1024)
71
72 #define HOW_TO_READ_TLB_CONTENT \
73 "[ ID] PPN EPN ASID Share CB P.Size PROT.\n"
74
75 void print_single_tlb(unsigned long tlb, int single_print)
76 {
77 regType_t pteH;
78 regType_t pteL;
79 unsigned int valid, shared, asid, epn, cb, ppn;
80 char *pSize;
81 char *pProt;
82
83 /*
84 ** in case of single print <single_print> is true, this implies:
85 ** 1) print the TLB in any case also if NOT VALID
86 ** 2) print out the header
87 */
88
89 pteH = getConfigReg(tlb);
90 valid = GET_VALID(pteH);
91 if (single_print)
92 printk(HOW_TO_READ_TLB_CONTENT);
93 else if (!valid)
94 return;
95
96 pteL = getConfigReg(tlb + 1);
97
98 shared = GET_SHARED(pteH);
99 asid = GET_ASID(pteH);
100 epn = GET_EPN(pteH);
101 cb = GET_CBEHAVIOR(pteL);
102 pSize = GET_PAGE_SIZE(pteL);
103 pProt = GET_PROTECTION(pteL);
104 ppn = GET_PPN(pteL);
105 printk("[%c%2ld] 0x%08x 0x%08x %03d %02x %02x %4s %s\n",
106 ((valid) ? ' ' : 'u'), ((tlb & 0x0ffff) / TLB_STEP),
107 ppn, epn, asid, shared, cb, pSize, pProt);
108 }
109
110 void print_dtlb(void)
111 {
112 int count;
113 unsigned long tlb;
114
115 printk(" ================= SH-5 D-TLBs Status ===================\n");
116 printk(HOW_TO_READ_TLB_CONTENT);
117 tlb = DTLB_BASE;
118 for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
119 print_single_tlb(tlb, 0);
120 printk
121 (" =============================================================\n");
122 }
123
124 void print_itlb(void)
125 {
126 int count;
127 unsigned long tlb;
128
129 printk(" ================= SH-5 I-TLBs Status ===================\n");
130 printk(HOW_TO_READ_TLB_CONTENT);
131 tlb = ITLB_BASE;
132 for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
133 print_single_tlb(tlb, 0);
134 printk
135 (" =============================================================\n");
136 }
137
138 void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
139 {
140
141 unsigned long long ah, al, bh, bl, ch, cl;
142
143 printk("\n");
144 printk("EXCEPTION - %s: task %d; Linux trap # %d; signal = %d\n",
145 ((from) ? from : "???"), current->pid, trapnr, signr);
146
147 asm volatile ("getcon " __EXPEVT ", %0":"=r"(ah));
148 asm volatile ("getcon " __EXPEVT ", %0":"=r"(al));
149 ah = (ah) >> 32;
150 al = (al) & 0xffffffff;
151 asm volatile ("getcon " __KCR1 ", %0":"=r"(bh));
152 asm volatile ("getcon " __KCR1 ", %0":"=r"(bl));
153 bh = (bh) >> 32;
154 bl = (bl) & 0xffffffff;
155 asm volatile ("getcon " __INTEVT ", %0":"=r"(ch));
156 asm volatile ("getcon " __INTEVT ", %0":"=r"(cl));
157 ch = (ch) >> 32;
158 cl = (cl) & 0xffffffff;
159 printk("EXPE: %08Lx%08Lx KCR1: %08Lx%08Lx INTE: %08Lx%08Lx\n",
160 ah, al, bh, bl, ch, cl);
161
162 asm volatile ("getcon " __PEXPEVT ", %0":"=r"(ah));
163 asm volatile ("getcon " __PEXPEVT ", %0":"=r"(al));
164 ah = (ah) >> 32;
165 al = (al) & 0xffffffff;
166 asm volatile ("getcon " __PSPC ", %0":"=r"(bh));
167 asm volatile ("getcon " __PSPC ", %0":"=r"(bl));
168 bh = (bh) >> 32;
169 bl = (bl) & 0xffffffff;
170 asm volatile ("getcon " __PSSR ", %0":"=r"(ch));
171 asm volatile ("getcon " __PSSR ", %0":"=r"(cl));
172 ch = (ch) >> 32;
173 cl = (cl) & 0xffffffff;
174 printk("PEXP: %08Lx%08Lx PSPC: %08Lx%08Lx PSSR: %08Lx%08Lx\n",
175 ah, al, bh, bl, ch, cl);
176
177 ah = (regs->pc) >> 32;
178 al = (regs->pc) & 0xffffffff;
179 bh = (regs->regs[18]) >> 32;
180 bl = (regs->regs[18]) & 0xffffffff;
181 ch = (regs->regs[15]) >> 32;
182 cl = (regs->regs[15]) & 0xffffffff;
183 printk("PC : %08Lx%08Lx LINK: %08Lx%08Lx SP : %08Lx%08Lx\n",
184 ah, al, bh, bl, ch, cl);
185
186 ah = (regs->sr) >> 32;
187 al = (regs->sr) & 0xffffffff;
188 asm volatile ("getcon " __TEA ", %0":"=r"(bh));
189 asm volatile ("getcon " __TEA ", %0":"=r"(bl));
190 bh = (bh) >> 32;
191 bl = (bl) & 0xffffffff;
192 asm volatile ("getcon " __KCR0 ", %0":"=r"(ch));
193 asm volatile ("getcon " __KCR0 ", %0":"=r"(cl));
194 ch = (ch) >> 32;
195 cl = (cl) & 0xffffffff;
196 printk("SR : %08Lx%08Lx TEA : %08Lx%08Lx KCR0: %08Lx%08Lx\n",
197 ah, al, bh, bl, ch, cl);
198
199 ah = (regs->regs[0]) >> 32;
200 al = (regs->regs[0]) & 0xffffffff;
201 bh = (regs->regs[1]) >> 32;
202 bl = (regs->regs[1]) & 0xffffffff;
203 ch = (regs->regs[2]) >> 32;
204 cl = (regs->regs[2]) & 0xffffffff;
205 printk("R0 : %08Lx%08Lx R1 : %08Lx%08Lx R2 : %08Lx%08Lx\n",
206 ah, al, bh, bl, ch, cl);
207
208 ah = (regs->regs[3]) >> 32;
209 al = (regs->regs[3]) & 0xffffffff;
210 bh = (regs->regs[4]) >> 32;
211 bl = (regs->regs[4]) & 0xffffffff;
212 ch = (regs->regs[5]) >> 32;
213 cl = (regs->regs[5]) & 0xffffffff;
214 printk("R3 : %08Lx%08Lx R4 : %08Lx%08Lx R5 : %08Lx%08Lx\n",
215 ah, al, bh, bl, ch, cl);
216
217 ah = (regs->regs[6]) >> 32;
218 al = (regs->regs[6]) & 0xffffffff;
219 bh = (regs->regs[7]) >> 32;
220 bl = (regs->regs[7]) & 0xffffffff;
221 ch = (regs->regs[8]) >> 32;
222 cl = (regs->regs[8]) & 0xffffffff;
223 printk("R6 : %08Lx%08Lx R7 : %08Lx%08Lx R8 : %08Lx%08Lx\n",
224 ah, al, bh, bl, ch, cl);
225
226 ah = (regs->regs[9]) >> 32;
227 al = (regs->regs[9]) & 0xffffffff;
228 bh = (regs->regs[10]) >> 32;
229 bl = (regs->regs[10]) & 0xffffffff;
230 ch = (regs->regs[11]) >> 32;
231 cl = (regs->regs[11]) & 0xffffffff;
232 printk("R9 : %08Lx%08Lx R10 : %08Lx%08Lx R11 : %08Lx%08Lx\n",
233 ah, al, bh, bl, ch, cl);
234 printk("....\n");
235
236 ah = (regs->tregs[0]) >> 32;
237 al = (regs->tregs[0]) & 0xffffffff;
238 bh = (regs->tregs[1]) >> 32;
239 bl = (regs->tregs[1]) & 0xffffffff;
240 ch = (regs->tregs[2]) >> 32;
241 cl = (regs->tregs[2]) & 0xffffffff;
242 printk("T0 : %08Lx%08Lx T1 : %08Lx%08Lx T2 : %08Lx%08Lx\n",
243 ah, al, bh, bl, ch, cl);
244 printk("....\n");
245
246 print_dtlb();
247 print_itlb();
248 }
Linux with added FPC-III support