arch/blackfin/mach-bf538/include/mach/portmux.h

   1 /*
   2  * Copyright 2008-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _MACH_PORTMUX_H_
   8 #define _MACH_PORTMUX_H_
   9
  10 #define MAX_RESOURCES   64
  11
  12 #define P_TMR2          (P_DONTCARE)
  13 #define P_TMR1          (P_DONTCARE)
  14 #define P_TMR0          (P_DONTCARE)
  15 #define P_TMRCLK        (P_DONTCARE)
  16 #define P_PPI0_CLK      (P_DONTCARE)
  17 #define P_PPI0_FS1      (P_DONTCARE)
  18 #define P_PPI0_FS2      (P_DONTCARE)
  19
  20 #define P_TWI0_SCL      (P_DONTCARE)
  21 #define P_TWI0_SDA      (P_DONTCARE)
  22 #define P_TWI1_SCL      (P_DONTCARE)
  23 #define P_TWI1_SDA      (P_DONTCARE)
  24
  25 #define P_SPORT1_TSCLK  (P_DONTCARE)
  26 #define P_SPORT1_RSCLK  (P_DONTCARE)
  27 #define P_SPORT0_TSCLK  (P_DONTCARE)
  28 #define P_SPORT0_RSCLK  (P_DONTCARE)
  29 #define P_SPORT1_DRSEC  (P_DONTCARE)
  30 #define P_SPORT1_RFS    (P_DONTCARE)
  31 #define P_SPORT1_DTPRI  (P_DONTCARE)
  32 #define P_SPORT1_DTSEC  (P_DONTCARE)
  33 #define P_SPORT1_TFS    (P_DONTCARE)
  34 #define P_SPORT1_DRPRI  (P_DONTCARE)
  35 #define P_SPORT0_DRSEC  (P_DONTCARE)
  36 #define P_SPORT0_RFS    (P_DONTCARE)
  37 #define P_SPORT0_DTPRI  (P_DONTCARE)
  38 #define P_SPORT0_DTSEC  (P_DONTCARE)
  39 #define P_SPORT0_TFS    (P_DONTCARE)
  40 #define P_SPORT0_DRPRI  (P_DONTCARE)
  41
  42 #define P_UART0_RX      (P_DONTCARE)
  43 #define P_UART0_TX      (P_DONTCARE)
  44
  45 #define P_SPI0_MOSI     (P_DONTCARE)
  46 #define P_SPI0_MISO     (P_DONTCARE)
  47 #define P_SPI0_SCK      (P_DONTCARE)
  48
  49 #define P_PPI0_D0       (P_DONTCARE)
  50 #define P_PPI0_D1       (P_DONTCARE)
  51 #define P_PPI0_D2       (P_DONTCARE)
  52 #define P_PPI0_D3       (P_DONTCARE)
  53
  54 #define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PC0))
  55 #define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PC1))
  56
  57 #define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PD0))
  58 #define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PD1))
  59 #define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PD2))
  60 #define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PD3))
  61 #define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD4))
  62 #define P_SPI2_MOSI     (P_DEFINED | P_IDENT(GPIO_PD5))
  63 #define P_SPI2_MISO     (P_DEFINED | P_IDENT(GPIO_PD6))
  64 #define P_SPI2_SCK      (P_DEFINED | P_IDENT(GPIO_PD7))
  65 #define P_SPI2_SS       (P_DEFINED | P_IDENT(GPIO_PD8))
  66 #define P_SPI2_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD9))
  67 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PD10))
  68 #define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PD11))
  69 #define P_UART2_RX      (P_DEFINED | P_IDENT(GPIO_PD12))
  70 #define P_UART2_TX      (P_DEFINED | P_IDENT(GPIO_PD13))
  71
  72 #define P_SPORT2_RSCLK  (P_DEFINED | P_IDENT(GPIO_PE0))
  73 #define P_SPORT2_RFS    (P_DEFINED | P_IDENT(GPIO_PE1))
  74 #define P_SPORT2_DRPRI  (P_DEFINED | P_IDENT(GPIO_PE2))
  75 #define P_SPORT2_DRSEC  (P_DEFINED | P_IDENT(GPIO_PE3))
  76 #define P_SPORT2_TSCLK  (P_DEFINED | P_IDENT(GPIO_PE4))
  77 #define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PE5))
  78 #define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PE6))
  79 #define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PE7))
  80 #define P_SPORT3_RSCLK  (P_DEFINED | P_IDENT(GPIO_PE8))
  81 #define P_SPORT3_RFS    (P_DEFINED | P_IDENT(GPIO_PE9))
  82 #define P_SPORT3_DRPRI  (P_DEFINED | P_IDENT(GPIO_PE10))
  83 #define P_SPORT3_DRSEC  (P_DEFINED | P_IDENT(GPIO_PE11))
  84 #define P_SPORT3_TSCLK  (P_DEFINED | P_IDENT(GPIO_PE12))
  85 #define P_SPORT3_TFS    (P_DEFINED | P_IDENT(GPIO_PE13))
  86 #define P_SPORT3_DTPRI  (P_DEFINED | P_IDENT(GPIO_PE14))
  87 #define P_SPORT3_DTSEC  (P_DEFINED | P_IDENT(GPIO_PE15))
  88
  89 #define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF3))
  90 #define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF4))
  91 #define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF5))
  92 #define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF6))
  93 #define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF7))
  94 #define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF8))
  95 #define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF9))
  96 #define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF10))
  97 #define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF11))
  98
  99 #define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF15))
 100 #define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF14))
 101 #define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF13))
 102 #define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF12))
 103 #define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
 104 #define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
 105 #define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
 106 #define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
 107 #define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
 108 #define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
 109 #define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
 110 #define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
 111 #define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
 112 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
 113
 114 #endif /* _MACH_PORTMUX_H_ */