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doc: Update rcu_assign_pointer() definition in whatisRCU.txt
[linux/fpc-iii.git] / drivers / usb / gadget / udc / mv_udc_core.c
blob27ebb0d5449d0dda58863ffb28bcbd8f3514f93f
1 /*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/timer.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/moduleparam.h>
27 #include <linux/device.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/otg.h>
31 #include <linux/pm.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/mv_usb.h>
37 #include <asm/unaligned.h>
38
39 #include "mv_udc.h"
40
41 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
42 #define DRIVER_VERSION "8 Nov 2010"
43
44 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
45 ((ep)->udc->ep0_dir) : ((ep)->direction))
46
47 /* timeout value -- usec */
48 #define RESET_TIMEOUT 10000
49 #define FLUSH_TIMEOUT 10000
50 #define EPSTATUS_TIMEOUT 10000
51 #define PRIME_TIMEOUT 10000
52 #define READSAFE_TIMEOUT 1000
53
54 #define LOOPS_USEC_SHIFT 1
55 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
56 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
57
58 static DECLARE_COMPLETION(release_done);
59
60 static const char driver_name[] = "mv_udc";
61 static const char driver_desc[] = DRIVER_DESC;
62
63 static void nuke(struct mv_ep *ep, int status);
64 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
65
66 /* for endpoint 0 operations */
67 static const struct usb_endpoint_descriptor mv_ep0_desc = {
68 .bLength = USB_DT_ENDPOINT_SIZE,
69 .bDescriptorType = USB_DT_ENDPOINT,
70 .bEndpointAddress = 0,
71 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
72 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
73 };
74
75 static void ep0_reset(struct mv_udc *udc)
76 {
77 struct mv_ep *ep;
78 u32 epctrlx;
79 int i = 0;
80
81 /* ep0 in and out */
82 for (i = 0; i < 2; i++) {
83 ep = &udc->eps[i];
84 ep->udc = udc;
85
86 /* ep0 dQH */
87 ep->dqh = &udc->ep_dqh[i];
88
89 /* configure ep0 endpoint capabilities in dQH */
90 ep->dqh->max_packet_length =
91 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
92 | EP_QUEUE_HEAD_IOS;
93
94 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
95
96 epctrlx = readl(&udc->op_regs->epctrlx[0]);
97 if (i) { /* TX */
98 epctrlx |= EPCTRL_TX_ENABLE
99 | (USB_ENDPOINT_XFER_CONTROL
100 << EPCTRL_TX_EP_TYPE_SHIFT);
101
102 } else { /* RX */
103 epctrlx |= EPCTRL_RX_ENABLE
104 | (USB_ENDPOINT_XFER_CONTROL
105 << EPCTRL_RX_EP_TYPE_SHIFT);
106 }
107
108 writel(epctrlx, &udc->op_regs->epctrlx[0]);
109 }
110 }
111
112 /* protocol ep0 stall, will automatically be cleared on new transaction */
113 static void ep0_stall(struct mv_udc *udc)
114 {
115 u32 epctrlx;
116
117 /* set TX and RX to stall */
118 epctrlx = readl(&udc->op_regs->epctrlx[0]);
119 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
120 writel(epctrlx, &udc->op_regs->epctrlx[0]);
121
122 /* update ep0 state */
123 udc->ep0_state = WAIT_FOR_SETUP;
124 udc->ep0_dir = EP_DIR_OUT;
125 }
126
127 static int process_ep_req(struct mv_udc *udc, int index,
128 struct mv_req *curr_req)
129 {
130 struct mv_dtd *curr_dtd;
131 struct mv_dqh *curr_dqh;
132 int actual, remaining_length;
133 int i, direction;
134 int retval = 0;
135 u32 errors;
136 u32 bit_pos;
137
138 curr_dqh = &udc->ep_dqh[index];
139 direction = index % 2;
140
141 curr_dtd = curr_req->head;
142 actual = curr_req->req.length;
143
144 for (i = 0; i < curr_req->dtd_count; i++) {
145 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
146 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
147 udc->eps[index].name);
148 return 1;
149 }
150
151 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
152 if (!errors) {
153 remaining_length =
154 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
155 >> DTD_LENGTH_BIT_POS;
156 actual -= remaining_length;
157
158 if (remaining_length) {
159 if (direction) {
160 dev_dbg(&udc->dev->dev,
161 "TX dTD remains data\n");
162 retval = -EPROTO;
163 break;
164 } else
165 break;
166 }
167 } else {
168 dev_info(&udc->dev->dev,
169 "complete_tr error: ep=%d %s: error = 0x%x\n",
170 index >> 1, direction ? "SEND" : "RECV",
171 errors);
172 if (errors & DTD_STATUS_HALTED) {
173 /* Clear the errors and Halt condition */
174 curr_dqh->size_ioc_int_sts &= ~errors;
175 retval = -EPIPE;
176 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
177 retval = -EPROTO;
178 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
179 retval = -EILSEQ;
180 }
181 }
182 if (i != curr_req->dtd_count - 1)
183 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
184 }
185 if (retval)
186 return retval;
187
188 if (direction == EP_DIR_OUT)
189 bit_pos = 1 << curr_req->ep->ep_num;
190 else
191 bit_pos = 1 << (16 + curr_req->ep->ep_num);
192
193 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
194 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
195 while (readl(&udc->op_regs->epstatus) & bit_pos)
196 udelay(1);
197 break;
198 }
199 udelay(1);
200 }
201
202 curr_req->req.actual = actual;
203
204 return 0;
205 }
206
207 /*
208 * done() - retire a request; caller blocked irqs
209 * @status : request status to be set, only works when
210 * request is still in progress.
211 */
212 static void done(struct mv_ep *ep, struct mv_req *req, int status)
213 __releases(&ep->udc->lock)
214 __acquires(&ep->udc->lock)
215 {
216 struct mv_udc *udc = NULL;
217 unsigned char stopped = ep->stopped;
218 struct mv_dtd *curr_td, *next_td;
219 int j;
220
221 udc = (struct mv_udc *)ep->udc;
222 /* Removed the req from fsl_ep->queue */
223 list_del_init(&req->queue);
224
225 /* req.status should be set as -EINPROGRESS in ep_queue() */
226 if (req->req.status == -EINPROGRESS)
227 req->req.status = status;
228 else
229 status = req->req.status;
230
231 /* Free dtd for the request */
232 next_td = req->head;
233 for (j = 0; j < req->dtd_count; j++) {
234 curr_td = next_td;
235 if (j != req->dtd_count - 1)
236 next_td = curr_td->next_dtd_virt;
237 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
238 }
239
240 usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
241
242 if (status && (status != -ESHUTDOWN))
243 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
244 ep->ep.name, &req->req, status,
245 req->req.actual, req->req.length);
246
247 ep->stopped = 1;
248
249 spin_unlock(&ep->udc->lock);
250
251 usb_gadget_giveback_request(&ep->ep, &req->req);
252
253 spin_lock(&ep->udc->lock);
254 ep->stopped = stopped;
255 }
256
257 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
258 {
259 struct mv_udc *udc;
260 struct mv_dqh *dqh;
261 u32 bit_pos, direction;
262 u32 usbcmd, epstatus;
263 unsigned int loops;
264 int retval = 0;
265
266 udc = ep->udc;
267 direction = ep_dir(ep);
268 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
269 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
270
271 /* check if the pipe is empty */
272 if (!(list_empty(&ep->queue))) {
273 struct mv_req *lastreq;
274 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
275 lastreq->tail->dtd_next =
276 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
277
278 wmb();
279
280 if (readl(&udc->op_regs->epprime) & bit_pos)
281 goto done;
282
283 loops = LOOPS(READSAFE_TIMEOUT);
284 while (1) {
285 /* start with setting the semaphores */
286 usbcmd = readl(&udc->op_regs->usbcmd);
287 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
288 writel(usbcmd, &udc->op_regs->usbcmd);
289
290 /* read the endpoint status */
291 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
292
293 /*
294 * Reread the ATDTW semaphore bit to check if it is
295 * cleared. When hardware see a hazard, it will clear
296 * the bit or else we remain set to 1 and we can
297 * proceed with priming of endpoint if not already
298 * primed.
299 */
300 if (readl(&udc->op_regs->usbcmd)
301 & USBCMD_ATDTW_TRIPWIRE_SET)
302 break;
303
304 loops--;
305 if (loops == 0) {
306 dev_err(&udc->dev->dev,
307 "Timeout for ATDTW_TRIPWIRE...\n");
308 retval = -ETIME;
309 goto done;
310 }
311 udelay(LOOPS_USEC);
312 }
313
314 /* Clear the semaphore */
315 usbcmd = readl(&udc->op_regs->usbcmd);
316 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
317 writel(usbcmd, &udc->op_regs->usbcmd);
318
319 if (epstatus)
320 goto done;
321 }
322
323 /* Write dQH next pointer and terminate bit to 0 */
324 dqh->next_dtd_ptr = req->head->td_dma
325 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
326
327 /* clear active and halt bit, in case set from a previous error */
328 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
329
330 /* Ensure that updates to the QH will occur before priming. */
331 wmb();
332
333 /* Prime the Endpoint */
334 writel(bit_pos, &udc->op_regs->epprime);
335
336 done:
337 return retval;
338 }
339
340 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
341 dma_addr_t *dma, int *is_last)
342 {
343 struct mv_dtd *dtd;
344 struct mv_udc *udc;
345 struct mv_dqh *dqh;
346 u32 temp, mult = 0;
347
348 /* how big will this transfer be? */
349 if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
350 dqh = req->ep->dqh;
351 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
352 & 0x3;
353 *length = min(req->req.length - req->req.actual,
354 (unsigned)(mult * req->ep->ep.maxpacket));
355 } else
356 *length = min(req->req.length - req->req.actual,
357 (unsigned)EP_MAX_LENGTH_TRANSFER);
358
359 udc = req->ep->udc;
360
361 /*
362 * Be careful that no _GFP_HIGHMEM is set,
363 * or we can not use dma_to_virt
364 */
365 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
366 if (dtd == NULL)
367 return dtd;
368
369 dtd->td_dma = *dma;
370 /* initialize buffer page pointers */
371 temp = (u32)(req->req.dma + req->req.actual);
372 dtd->buff_ptr0 = cpu_to_le32(temp);
373 temp &= ~0xFFF;
374 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
375 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
376 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
377 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
378
379 req->req.actual += *length;
380
381 /* zlp is needed if req->req.zero is set */
382 if (req->req.zero) {
383 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
384 *is_last = 1;
385 else
386 *is_last = 0;
387 } else if (req->req.length == req->req.actual)
388 *is_last = 1;
389 else
390 *is_last = 0;
391
392 /* Fill in the transfer size; set active bit */
393 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
394
395 /* Enable interrupt for the last dtd of a request */
396 if (*is_last && !req->req.no_interrupt)
397 temp |= DTD_IOC;
398
399 temp |= mult << 10;
400
401 dtd->size_ioc_sts = temp;
402
403 mb();
404
405 return dtd;
406 }
407
408 /* generate dTD linked list for a request */
409 static int req_to_dtd(struct mv_req *req)
410 {
411 unsigned count;
412 int is_last, is_first = 1;
413 struct mv_dtd *dtd, *last_dtd = NULL;
414 dma_addr_t dma;
415
416 do {
417 dtd = build_dtd(req, &count, &dma, &is_last);
418 if (dtd == NULL)
419 return -ENOMEM;
420
421 if (is_first) {
422 is_first = 0;
423 req->head = dtd;
424 } else {
425 last_dtd->dtd_next = dma;
426 last_dtd->next_dtd_virt = dtd;
427 }
428 last_dtd = dtd;
429 req->dtd_count++;
430 } while (!is_last);
431
432 /* set terminate bit to 1 for the last dTD */
433 dtd->dtd_next = DTD_NEXT_TERMINATE;
434
435 req->tail = dtd;
436
437 return 0;
438 }
439
440 static int mv_ep_enable(struct usb_ep *_ep,
441 const struct usb_endpoint_descriptor *desc)
442 {
443 struct mv_udc *udc;
444 struct mv_ep *ep;
445 struct mv_dqh *dqh;
446 u16 max = 0;
447 u32 bit_pos, epctrlx, direction;
448 unsigned char zlt = 0, ios = 0, mult = 0;
449 unsigned long flags;
450
451 ep = container_of(_ep, struct mv_ep, ep);
452 udc = ep->udc;
453
454 if (!_ep || !desc
455 || desc->bDescriptorType != USB_DT_ENDPOINT)
456 return -EINVAL;
457
458 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
459 return -ESHUTDOWN;
460
461 direction = ep_dir(ep);
462 max = usb_endpoint_maxp(desc);
463
464 /*
465 * disable HW zero length termination select
466 * driver handles zero length packet through req->req.zero
467 */
468 zlt = 1;
469
470 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
471
472 /* Check if the Endpoint is Primed */
473 if ((readl(&udc->op_regs->epprime) & bit_pos)
474 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
475 dev_info(&udc->dev->dev,
476 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
477 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
478 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
479 (unsigned)readl(&udc->op_regs->epprime),
480 (unsigned)readl(&udc->op_regs->epstatus),
481 (unsigned)bit_pos);
482 goto en_done;
483 }
484 /* Set the max packet length, interrupt on Setup and Mult fields */
485 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
486 case USB_ENDPOINT_XFER_BULK:
487 zlt = 1;
488 mult = 0;
489 break;
490 case USB_ENDPOINT_XFER_CONTROL:
491 ios = 1;
492 case USB_ENDPOINT_XFER_INT:
493 mult = 0;
494 break;
495 case USB_ENDPOINT_XFER_ISOC:
496 /* Calculate transactions needed for high bandwidth iso */
497 mult = usb_endpoint_maxp_mult(desc);
498 /* 3 transactions at most */
499 if (mult > 3)
500 goto en_done;
501 break;
502 default:
503 goto en_done;
504 }
505
506 spin_lock_irqsave(&udc->lock, flags);
507 /* Get the endpoint queue head address */
508 dqh = ep->dqh;
509 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
510 | (mult << EP_QUEUE_HEAD_MULT_POS)
511 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
512 | (ios ? EP_QUEUE_HEAD_IOS : 0);
513 dqh->next_dtd_ptr = 1;
514 dqh->size_ioc_int_sts = 0;
515
516 ep->ep.maxpacket = max;
517 ep->ep.desc = desc;
518 ep->stopped = 0;
519
520 /* Enable the endpoint for Rx or Tx and set the endpoint type */
521 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
522 if (direction == EP_DIR_IN) {
523 epctrlx &= ~EPCTRL_TX_ALL_MASK;
524 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
525 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
526 << EPCTRL_TX_EP_TYPE_SHIFT);
527 } else {
528 epctrlx &= ~EPCTRL_RX_ALL_MASK;
529 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
530 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
531 << EPCTRL_RX_EP_TYPE_SHIFT);
532 }
533 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
534
535 /*
536 * Implement Guideline (GL# USB-7) The unused endpoint type must
537 * be programmed to bulk.
538 */
539 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
540 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
541 epctrlx |= (USB_ENDPOINT_XFER_BULK
542 << EPCTRL_RX_EP_TYPE_SHIFT);
543 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
544 }
545
546 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
547 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
548 epctrlx |= (USB_ENDPOINT_XFER_BULK
549 << EPCTRL_TX_EP_TYPE_SHIFT);
550 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
551 }
552
553 spin_unlock_irqrestore(&udc->lock, flags);
554
555 return 0;
556 en_done:
557 return -EINVAL;
558 }
559
560 static int mv_ep_disable(struct usb_ep *_ep)
561 {
562 struct mv_udc *udc;
563 struct mv_ep *ep;
564 struct mv_dqh *dqh;
565 u32 epctrlx, direction;
566 unsigned long flags;
567
568 ep = container_of(_ep, struct mv_ep, ep);
569 if ((_ep == NULL) || !ep->ep.desc)
570 return -EINVAL;
571
572 udc = ep->udc;
573
574 /* Get the endpoint queue head address */
575 dqh = ep->dqh;
576
577 spin_lock_irqsave(&udc->lock, flags);
578
579 direction = ep_dir(ep);
580
581 /* Reset the max packet length and the interrupt on Setup */
582 dqh->max_packet_length = 0;
583
584 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
585 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
586 epctrlx &= ~((direction == EP_DIR_IN)
587 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
588 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
589 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
590
591 /* nuke all pending requests (does flush) */
592 nuke(ep, -ESHUTDOWN);
593
594 ep->ep.desc = NULL;
595 ep->stopped = 1;
596
597 spin_unlock_irqrestore(&udc->lock, flags);
598
599 return 0;
600 }
601
602 static struct usb_request *
603 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
604 {
605 struct mv_req *req = NULL;
606
607 req = kzalloc(sizeof *req, gfp_flags);
608 if (!req)
609 return NULL;
610
611 req->req.dma = DMA_ADDR_INVALID;
612 INIT_LIST_HEAD(&req->queue);
613
614 return &req->req;
615 }
616
617 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
618 {
619 struct mv_req *req = NULL;
620
621 req = container_of(_req, struct mv_req, req);
622
623 if (_req)
624 kfree(req);
625 }
626
627 static void mv_ep_fifo_flush(struct usb_ep *_ep)
628 {
629 struct mv_udc *udc;
630 u32 bit_pos, direction;
631 struct mv_ep *ep;
632 unsigned int loops;
633
634 if (!_ep)
635 return;
636
637 ep = container_of(_ep, struct mv_ep, ep);
638 if (!ep->ep.desc)
639 return;
640
641 udc = ep->udc;
642 direction = ep_dir(ep);
643
644 if (ep->ep_num == 0)
645 bit_pos = (1 << 16) | 1;
646 else if (direction == EP_DIR_OUT)
647 bit_pos = 1 << ep->ep_num;
648 else
649 bit_pos = 1 << (16 + ep->ep_num);
650
651 loops = LOOPS(EPSTATUS_TIMEOUT);
652 do {
653 unsigned int inter_loops;
654
655 if (loops == 0) {
656 dev_err(&udc->dev->dev,
657 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
658 (unsigned)readl(&udc->op_regs->epstatus),
659 (unsigned)bit_pos);
660 return;
661 }
662 /* Write 1 to the Flush register */
663 writel(bit_pos, &udc->op_regs->epflush);
664
665 /* Wait until flushing completed */
666 inter_loops = LOOPS(FLUSH_TIMEOUT);
667 while (readl(&udc->op_regs->epflush)) {
668 /*
669 * ENDPTFLUSH bit should be cleared to indicate this
670 * operation is complete
671 */
672 if (inter_loops == 0) {
673 dev_err(&udc->dev->dev,
674 "TIMEOUT for ENDPTFLUSH=0x%x,"
675 "bit_pos=0x%x\n",
676 (unsigned)readl(&udc->op_regs->epflush),
677 (unsigned)bit_pos);
678 return;
679 }
680 inter_loops--;
681 udelay(LOOPS_USEC);
682 }
683 loops--;
684 } while (readl(&udc->op_regs->epstatus) & bit_pos);
685 }
686
687 /* queues (submits) an I/O request to an endpoint */
688 static int
689 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
690 {
691 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
692 struct mv_req *req = container_of(_req, struct mv_req, req);
693 struct mv_udc *udc = ep->udc;
694 unsigned long flags;
695 int retval;
696
697 /* catch various bogus parameters */
698 if (!_req || !req->req.complete || !req->req.buf
699 || !list_empty(&req->queue)) {
700 dev_err(&udc->dev->dev, "%s, bad params", __func__);
701 return -EINVAL;
702 }
703 if (unlikely(!_ep || !ep->ep.desc)) {
704 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
705 return -EINVAL;
706 }
707
708 udc = ep->udc;
709 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
710 return -ESHUTDOWN;
711
712 req->ep = ep;
713
714 /* map virtual address to hardware */
715 retval = usb_gadget_map_request(&udc->gadget, _req, ep_dir(ep));
716 if (retval)
717 return retval;
718
719 req->req.status = -EINPROGRESS;
720 req->req.actual = 0;
721 req->dtd_count = 0;
722
723 spin_lock_irqsave(&udc->lock, flags);
724
725 /* build dtds and push them to device queue */
726 if (!req_to_dtd(req)) {
727 retval = queue_dtd(ep, req);
728 if (retval) {
729 spin_unlock_irqrestore(&udc->lock, flags);
730 dev_err(&udc->dev->dev, "Failed to queue dtd\n");
731 goto err_unmap_dma;
732 }
733 } else {
734 spin_unlock_irqrestore(&udc->lock, flags);
735 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
736 retval = -ENOMEM;
737 goto err_unmap_dma;
738 }
739
740 /* Update ep0 state */
741 if (ep->ep_num == 0)
742 udc->ep0_state = DATA_STATE_XMIT;
743
744 /* irq handler advances the queue */
745 list_add_tail(&req->queue, &ep->queue);
746 spin_unlock_irqrestore(&udc->lock, flags);
747
748 return 0;
749
750 err_unmap_dma:
751 usb_gadget_unmap_request(&udc->gadget, _req, ep_dir(ep));
752
753 return retval;
754 }
755
756 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
757 {
758 struct mv_dqh *dqh = ep->dqh;
759 u32 bit_pos;
760
761 /* Write dQH next pointer and terminate bit to 0 */
762 dqh->next_dtd_ptr = req->head->td_dma
763 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
764
765 /* clear active and halt bit, in case set from a previous error */
766 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
767
768 /* Ensure that updates to the QH will occure before priming. */
769 wmb();
770
771 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
772
773 /* Prime the Endpoint */
774 writel(bit_pos, &ep->udc->op_regs->epprime);
775 }
776
777 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
778 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
779 {
780 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
781 struct mv_req *req;
782 struct mv_udc *udc = ep->udc;
783 unsigned long flags;
784 int stopped, ret = 0;
785 u32 epctrlx;
786
787 if (!_ep || !_req)
788 return -EINVAL;
789
790 spin_lock_irqsave(&ep->udc->lock, flags);
791 stopped = ep->stopped;
792
793 /* Stop the ep before we deal with the queue */
794 ep->stopped = 1;
795 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
796 if (ep_dir(ep) == EP_DIR_IN)
797 epctrlx &= ~EPCTRL_TX_ENABLE;
798 else
799 epctrlx &= ~EPCTRL_RX_ENABLE;
800 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
801
802 /* make sure it's actually queued on this endpoint */
803 list_for_each_entry(req, &ep->queue, queue) {
804 if (&req->req == _req)
805 break;
806 }
807 if (&req->req != _req) {
808 ret = -EINVAL;
809 goto out;
810 }
811
812 /* The request is in progress, or completed but not dequeued */
813 if (ep->queue.next == &req->queue) {
814 _req->status = -ECONNRESET;
815 mv_ep_fifo_flush(_ep); /* flush current transfer */
816
817 /* The request isn't the last request in this ep queue */
818 if (req->queue.next != &ep->queue) {
819 struct mv_req *next_req;
820
821 next_req = list_entry(req->queue.next,
822 struct mv_req, queue);
823
824 /* Point the QH to the first TD of next request */
825 mv_prime_ep(ep, next_req);
826 } else {
827 struct mv_dqh *qh;
828
829 qh = ep->dqh;
830 qh->next_dtd_ptr = 1;
831 qh->size_ioc_int_sts = 0;
832 }
833
834 /* The request hasn't been processed, patch up the TD chain */
835 } else {
836 struct mv_req *prev_req;
837
838 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
839 writel(readl(&req->tail->dtd_next),
840 &prev_req->tail->dtd_next);
841
842 }
843
844 done(ep, req, -ECONNRESET);
845
846 /* Enable EP */
847 out:
848 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
849 if (ep_dir(ep) == EP_DIR_IN)
850 epctrlx |= EPCTRL_TX_ENABLE;
851 else
852 epctrlx |= EPCTRL_RX_ENABLE;
853 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
854 ep->stopped = stopped;
855
856 spin_unlock_irqrestore(&ep->udc->lock, flags);
857 return ret;
858 }
859
860 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
861 {
862 u32 epctrlx;
863
864 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
865
866 if (stall) {
867 if (direction == EP_DIR_IN)
868 epctrlx |= EPCTRL_TX_EP_STALL;
869 else
870 epctrlx |= EPCTRL_RX_EP_STALL;
871 } else {
872 if (direction == EP_DIR_IN) {
873 epctrlx &= ~EPCTRL_TX_EP_STALL;
874 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
875 } else {
876 epctrlx &= ~EPCTRL_RX_EP_STALL;
877 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
878 }
879 }
880 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
881 }
882
883 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
884 {
885 u32 epctrlx;
886
887 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
888
889 if (direction == EP_DIR_OUT)
890 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
891 else
892 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
893 }
894
895 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
896 {
897 struct mv_ep *ep;
898 unsigned long flags = 0;
899 int status = 0;
900 struct mv_udc *udc;
901
902 ep = container_of(_ep, struct mv_ep, ep);
903 udc = ep->udc;
904 if (!_ep || !ep->ep.desc) {
905 status = -EINVAL;
906 goto out;
907 }
908
909 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
910 status = -EOPNOTSUPP;
911 goto out;
912 }
913
914 /*
915 * Attempt to halt IN ep will fail if any transfer requests
916 * are still queue
917 */
918 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
919 status = -EAGAIN;
920 goto out;
921 }
922
923 spin_lock_irqsave(&ep->udc->lock, flags);
924 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
925 if (halt && wedge)
926 ep->wedge = 1;
927 else if (!halt)
928 ep->wedge = 0;
929 spin_unlock_irqrestore(&ep->udc->lock, flags);
930
931 if (ep->ep_num == 0) {
932 udc->ep0_state = WAIT_FOR_SETUP;
933 udc->ep0_dir = EP_DIR_OUT;
934 }
935 out:
936 return status;
937 }
938
939 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
940 {
941 return mv_ep_set_halt_wedge(_ep, halt, 0);
942 }
943
944 static int mv_ep_set_wedge(struct usb_ep *_ep)
945 {
946 return mv_ep_set_halt_wedge(_ep, 1, 1);
947 }
948
949 static const struct usb_ep_ops mv_ep_ops = {
950 .enable = mv_ep_enable,
951 .disable = mv_ep_disable,
952
953 .alloc_request = mv_alloc_request,
954 .free_request = mv_free_request,
955
956 .queue = mv_ep_queue,
957 .dequeue = mv_ep_dequeue,
958
959 .set_wedge = mv_ep_set_wedge,
960 .set_halt = mv_ep_set_halt,
961 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
962 };
963
964 static void udc_clock_enable(struct mv_udc *udc)
965 {
966 clk_prepare_enable(udc->clk);
967 }
968
969 static void udc_clock_disable(struct mv_udc *udc)
970 {
971 clk_disable_unprepare(udc->clk);
972 }
973
974 static void udc_stop(struct mv_udc *udc)
975 {
976 u32 tmp;
977
978 /* Disable interrupts */
979 tmp = readl(&udc->op_regs->usbintr);
980 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
981 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
982 writel(tmp, &udc->op_regs->usbintr);
983
984 udc->stopped = 1;
985
986 /* Reset the Run the bit in the command register to stop VUSB */
987 tmp = readl(&udc->op_regs->usbcmd);
988 tmp &= ~USBCMD_RUN_STOP;
989 writel(tmp, &udc->op_regs->usbcmd);
990 }
991
992 static void udc_start(struct mv_udc *udc)
993 {
994 u32 usbintr;
995
996 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
997 | USBINTR_PORT_CHANGE_DETECT_EN
998 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
999 /* Enable interrupts */
1000 writel(usbintr, &udc->op_regs->usbintr);
1001
1002 udc->stopped = 0;
1003
1004 /* Set the Run bit in the command register */
1005 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1006 }
1007
1008 static int udc_reset(struct mv_udc *udc)
1009 {
1010 unsigned int loops;
1011 u32 tmp, portsc;
1012
1013 /* Stop the controller */
1014 tmp = readl(&udc->op_regs->usbcmd);
1015 tmp &= ~USBCMD_RUN_STOP;
1016 writel(tmp, &udc->op_regs->usbcmd);
1017
1018 /* Reset the controller to get default values */
1019 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1020
1021 /* wait for reset to complete */
1022 loops = LOOPS(RESET_TIMEOUT);
1023 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1024 if (loops == 0) {
1025 dev_err(&udc->dev->dev,
1026 "Wait for RESET completed TIMEOUT\n");
1027 return -ETIMEDOUT;
1028 }
1029 loops--;
1030 udelay(LOOPS_USEC);
1031 }
1032
1033 /* set controller to device mode */
1034 tmp = readl(&udc->op_regs->usbmode);
1035 tmp |= USBMODE_CTRL_MODE_DEVICE;
1036
1037 /* turn setup lockout off, require setup tripwire in usbcmd */
1038 tmp |= USBMODE_SETUP_LOCK_OFF;
1039
1040 writel(tmp, &udc->op_regs->usbmode);
1041
1042 writel(0x0, &udc->op_regs->epsetupstat);
1043
1044 /* Configure the Endpoint List Address */
1045 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1046 &udc->op_regs->eplistaddr);
1047
1048 portsc = readl(&udc->op_regs->portsc[0]);
1049 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1050 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1051
1052 if (udc->force_fs)
1053 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1054 else
1055 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1056
1057 writel(portsc, &udc->op_regs->portsc[0]);
1058
1059 tmp = readl(&udc->op_regs->epctrlx[0]);
1060 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1061 writel(tmp, &udc->op_regs->epctrlx[0]);
1062
1063 return 0;
1064 }
1065
1066 static int mv_udc_enable_internal(struct mv_udc *udc)
1067 {
1068 int retval;
1069
1070 if (udc->active)
1071 return 0;
1072
1073 dev_dbg(&udc->dev->dev, "enable udc\n");
1074 udc_clock_enable(udc);
1075 if (udc->pdata->phy_init) {
1076 retval = udc->pdata->phy_init(udc->phy_regs);
1077 if (retval) {
1078 dev_err(&udc->dev->dev,
1079 "init phy error %d\n", retval);
1080 udc_clock_disable(udc);
1081 return retval;
1082 }
1083 }
1084 udc->active = 1;
1085
1086 return 0;
1087 }
1088
1089 static int mv_udc_enable(struct mv_udc *udc)
1090 {
1091 if (udc->clock_gating)
1092 return mv_udc_enable_internal(udc);
1093
1094 return 0;
1095 }
1096
1097 static void mv_udc_disable_internal(struct mv_udc *udc)
1098 {
1099 if (udc->active) {
1100 dev_dbg(&udc->dev->dev, "disable udc\n");
1101 if (udc->pdata->phy_deinit)
1102 udc->pdata->phy_deinit(udc->phy_regs);
1103 udc_clock_disable(udc);
1104 udc->active = 0;
1105 }
1106 }
1107
1108 static void mv_udc_disable(struct mv_udc *udc)
1109 {
1110 if (udc->clock_gating)
1111 mv_udc_disable_internal(udc);
1112 }
1113
1114 static int mv_udc_get_frame(struct usb_gadget *gadget)
1115 {
1116 struct mv_udc *udc;
1117 u16 retval;
1118
1119 if (!gadget)
1120 return -ENODEV;
1121
1122 udc = container_of(gadget, struct mv_udc, gadget);
1123
1124 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1125
1126 return retval;
1127 }
1128
1129 /* Tries to wake up the host connected to this gadget */
1130 static int mv_udc_wakeup(struct usb_gadget *gadget)
1131 {
1132 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1133 u32 portsc;
1134
1135 /* Remote wakeup feature not enabled by host */
1136 if (!udc->remote_wakeup)
1137 return -ENOTSUPP;
1138
1139 portsc = readl(&udc->op_regs->portsc);
1140 /* not suspended? */
1141 if (!(portsc & PORTSCX_PORT_SUSPEND))
1142 return 0;
1143 /* trigger force resume */
1144 portsc |= PORTSCX_PORT_FORCE_RESUME;
1145 writel(portsc, &udc->op_regs->portsc[0]);
1146 return 0;
1147 }
1148
1149 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1150 {
1151 struct mv_udc *udc;
1152 unsigned long flags;
1153 int retval = 0;
1154
1155 udc = container_of(gadget, struct mv_udc, gadget);
1156 spin_lock_irqsave(&udc->lock, flags);
1157
1158 udc->vbus_active = (is_active != 0);
1159
1160 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1161 __func__, udc->softconnect, udc->vbus_active);
1162
1163 if (udc->driver && udc->softconnect && udc->vbus_active) {
1164 retval = mv_udc_enable(udc);
1165 if (retval == 0) {
1166 /* Clock is disabled, need re-init registers */
1167 udc_reset(udc);
1168 ep0_reset(udc);
1169 udc_start(udc);
1170 }
1171 } else if (udc->driver && udc->softconnect) {
1172 if (!udc->active)
1173 goto out;
1174
1175 /* stop all the transfer in queue*/
1176 stop_activity(udc, udc->driver);
1177 udc_stop(udc);
1178 mv_udc_disable(udc);
1179 }
1180
1181 out:
1182 spin_unlock_irqrestore(&udc->lock, flags);
1183 return retval;
1184 }
1185
1186 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1187 {
1188 struct mv_udc *udc;
1189 unsigned long flags;
1190 int retval = 0;
1191
1192 udc = container_of(gadget, struct mv_udc, gadget);
1193 spin_lock_irqsave(&udc->lock, flags);
1194
1195 udc->softconnect = (is_on != 0);
1196
1197 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1198 __func__, udc->softconnect, udc->vbus_active);
1199
1200 if (udc->driver && udc->softconnect && udc->vbus_active) {
1201 retval = mv_udc_enable(udc);
1202 if (retval == 0) {
1203 /* Clock is disabled, need re-init registers */
1204 udc_reset(udc);
1205 ep0_reset(udc);
1206 udc_start(udc);
1207 }
1208 } else if (udc->driver && udc->vbus_active) {
1209 /* stop all the transfer in queue*/
1210 stop_activity(udc, udc->driver);
1211 udc_stop(udc);
1212 mv_udc_disable(udc);
1213 }
1214
1215 spin_unlock_irqrestore(&udc->lock, flags);
1216 return retval;
1217 }
1218
1219 static int mv_udc_start(struct usb_gadget *, struct usb_gadget_driver *);
1220 static int mv_udc_stop(struct usb_gadget *);
1221 /* device controller usb_gadget_ops structure */
1222 static const struct usb_gadget_ops mv_ops = {
1223
1224 /* returns the current frame number */
1225 .get_frame = mv_udc_get_frame,
1226
1227 /* tries to wake up the host connected to this gadget */
1228 .wakeup = mv_udc_wakeup,
1229
1230 /* notify controller that VBUS is powered or not */
1231 .vbus_session = mv_udc_vbus_session,
1232
1233 /* D+ pullup, software-controlled connect/disconnect to USB host */
1234 .pullup = mv_udc_pullup,
1235 .udc_start = mv_udc_start,
1236 .udc_stop = mv_udc_stop,
1237 };
1238
1239 static int eps_init(struct mv_udc *udc)
1240 {
1241 struct mv_ep *ep;
1242 char name[14];
1243 int i;
1244
1245 /* initialize ep0 */
1246 ep = &udc->eps[0];
1247 ep->udc = udc;
1248 strncpy(ep->name, "ep0", sizeof(ep->name));
1249 ep->ep.name = ep->name;
1250 ep->ep.ops = &mv_ep_ops;
1251 ep->wedge = 0;
1252 ep->stopped = 0;
1253 usb_ep_set_maxpacket_limit(&ep->ep, EP0_MAX_PKT_SIZE);
1254 ep->ep.caps.type_control = true;
1255 ep->ep.caps.dir_in = true;
1256 ep->ep.caps.dir_out = true;
1257 ep->ep_num = 0;
1258 ep->ep.desc = &mv_ep0_desc;
1259 INIT_LIST_HEAD(&ep->queue);
1260
1261 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1262
1263 /* initialize other endpoints */
1264 for (i = 2; i < udc->max_eps * 2; i++) {
1265 ep = &udc->eps[i];
1266 if (i % 2) {
1267 snprintf(name, sizeof(name), "ep%din", i / 2);
1268 ep->direction = EP_DIR_IN;
1269 ep->ep.caps.dir_in = true;
1270 } else {
1271 snprintf(name, sizeof(name), "ep%dout", i / 2);
1272 ep->direction = EP_DIR_OUT;
1273 ep->ep.caps.dir_out = true;
1274 }
1275 ep->udc = udc;
1276 strncpy(ep->name, name, sizeof(ep->name));
1277 ep->ep.name = ep->name;
1278
1279 ep->ep.caps.type_iso = true;
1280 ep->ep.caps.type_bulk = true;
1281 ep->ep.caps.type_int = true;
1282
1283 ep->ep.ops = &mv_ep_ops;
1284 ep->stopped = 0;
1285 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1286 ep->ep_num = i / 2;
1287
1288 INIT_LIST_HEAD(&ep->queue);
1289 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1290
1291 ep->dqh = &udc->ep_dqh[i];
1292 }
1293
1294 return 0;
1295 }
1296
1297 /* delete all endpoint requests, called with spinlock held */
1298 static void nuke(struct mv_ep *ep, int status)
1299 {
1300 /* called with spinlock held */
1301 ep->stopped = 1;
1302
1303 /* endpoint fifo flush */
1304 mv_ep_fifo_flush(&ep->ep);
1305
1306 while (!list_empty(&ep->queue)) {
1307 struct mv_req *req = NULL;
1308 req = list_entry(ep->queue.next, struct mv_req, queue);
1309 done(ep, req, status);
1310 }
1311 }
1312
1313 static void gadget_reset(struct mv_udc *udc, struct usb_gadget_driver *driver)
1314 {
1315 struct mv_ep *ep;
1316
1317 nuke(&udc->eps[0], -ESHUTDOWN);
1318
1319 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1320 nuke(ep, -ESHUTDOWN);
1321 }
1322
1323 /* report reset; the driver is already quiesced */
1324 if (driver) {
1325 spin_unlock(&udc->lock);
1326 usb_gadget_udc_reset(&udc->gadget, driver);
1327 spin_lock(&udc->lock);
1328 }
1329 }
1330 /* stop all USB activities */
1331 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1332 {
1333 struct mv_ep *ep;
1334
1335 nuke(&udc->eps[0], -ESHUTDOWN);
1336
1337 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1338 nuke(ep, -ESHUTDOWN);
1339 }
1340
1341 /* report disconnect; the driver is already quiesced */
1342 if (driver) {
1343 spin_unlock(&udc->lock);
1344 driver->disconnect(&udc->gadget);
1345 spin_lock(&udc->lock);
1346 }
1347 }
1348
1349 static int mv_udc_start(struct usb_gadget *gadget,
1350 struct usb_gadget_driver *driver)
1351 {
1352 struct mv_udc *udc;
1353 int retval = 0;
1354 unsigned long flags;
1355
1356 udc = container_of(gadget, struct mv_udc, gadget);
1357
1358 if (udc->driver)
1359 return -EBUSY;
1360
1361 spin_lock_irqsave(&udc->lock, flags);
1362
1363 /* hook up the driver ... */
1364 driver->driver.bus = NULL;
1365 udc->driver = driver;
1366
1367 udc->usb_state = USB_STATE_ATTACHED;
1368 udc->ep0_state = WAIT_FOR_SETUP;
1369 udc->ep0_dir = EP_DIR_OUT;
1370
1371 spin_unlock_irqrestore(&udc->lock, flags);
1372
1373 if (udc->transceiver) {
1374 retval = otg_set_peripheral(udc->transceiver->otg,
1375 &udc->gadget);
1376 if (retval) {
1377 dev_err(&udc->dev->dev,
1378 "unable to register peripheral to otg\n");
1379 udc->driver = NULL;
1380 return retval;
1381 }
1382 }
1383
1384 /* When boot with cable attached, there will be no vbus irq occurred */
1385 if (udc->qwork)
1386 queue_work(udc->qwork, &udc->vbus_work);
1387
1388 return 0;
1389 }
1390
1391 static int mv_udc_stop(struct usb_gadget *gadget)
1392 {
1393 struct mv_udc *udc;
1394 unsigned long flags;
1395
1396 udc = container_of(gadget, struct mv_udc, gadget);
1397
1398 spin_lock_irqsave(&udc->lock, flags);
1399
1400 mv_udc_enable(udc);
1401 udc_stop(udc);
1402
1403 /* stop all usb activities */
1404 udc->gadget.speed = USB_SPEED_UNKNOWN;
1405 stop_activity(udc, NULL);
1406 mv_udc_disable(udc);
1407
1408 spin_unlock_irqrestore(&udc->lock, flags);
1409
1410 /* unbind gadget driver */
1411 udc->driver = NULL;
1412
1413 return 0;
1414 }
1415
1416 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1417 {
1418 u32 portsc;
1419
1420 portsc = readl(&udc->op_regs->portsc[0]);
1421 portsc |= mode << 16;
1422 writel(portsc, &udc->op_regs->portsc[0]);
1423 }
1424
1425 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1426 {
1427 struct mv_ep *mvep = container_of(ep, struct mv_ep, ep);
1428 struct mv_req *req = container_of(_req, struct mv_req, req);
1429 struct mv_udc *udc;
1430 unsigned long flags;
1431
1432 udc = mvep->udc;
1433
1434 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1435
1436 spin_lock_irqsave(&udc->lock, flags);
1437 if (req->test_mode) {
1438 mv_set_ptc(udc, req->test_mode);
1439 req->test_mode = 0;
1440 }
1441 spin_unlock_irqrestore(&udc->lock, flags);
1442 }
1443
1444 static int
1445 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1446 {
1447 int retval = 0;
1448 struct mv_req *req;
1449 struct mv_ep *ep;
1450
1451 ep = &udc->eps[0];
1452 udc->ep0_dir = direction;
1453 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1454
1455 req = udc->status_req;
1456
1457 /* fill in the reqest structure */
1458 if (empty == false) {
1459 *((u16 *) req->req.buf) = cpu_to_le16(status);
1460 req->req.length = 2;
1461 } else
1462 req->req.length = 0;
1463
1464 req->ep = ep;
1465 req->req.status = -EINPROGRESS;
1466 req->req.actual = 0;
1467 if (udc->test_mode) {
1468 req->req.complete = prime_status_complete;
1469 req->test_mode = udc->test_mode;
1470 udc->test_mode = 0;
1471 } else
1472 req->req.complete = NULL;
1473 req->dtd_count = 0;
1474
1475 if (req->req.dma == DMA_ADDR_INVALID) {
1476 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1477 req->req.buf, req->req.length,
1478 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1479 req->mapped = 1;
1480 }
1481
1482 /* prime the data phase */
1483 if (!req_to_dtd(req)) {
1484 retval = queue_dtd(ep, req);
1485 if (retval) {
1486 dev_err(&udc->dev->dev,
1487 "Failed to queue dtd when prime status\n");
1488 goto out;
1489 }
1490 } else{ /* no mem */
1491 retval = -ENOMEM;
1492 dev_err(&udc->dev->dev,
1493 "Failed to dma_pool_alloc when prime status\n");
1494 goto out;
1495 }
1496
1497 list_add_tail(&req->queue, &ep->queue);
1498
1499 return 0;
1500 out:
1501 usb_gadget_unmap_request(&udc->gadget, &req->req, ep_dir(ep));
1502
1503 return retval;
1504 }
1505
1506 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1507 {
1508 if (index <= TEST_FORCE_EN) {
1509 udc->test_mode = index;
1510 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1511 ep0_stall(udc);
1512 } else
1513 dev_err(&udc->dev->dev,
1514 "This test mode(%d) is not supported\n", index);
1515 }
1516
1517 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1518 {
1519 udc->dev_addr = (u8)setup->wValue;
1520
1521 /* update usb state */
1522 udc->usb_state = USB_STATE_ADDRESS;
1523
1524 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1525 ep0_stall(udc);
1526 }
1527
1528 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1529 struct usb_ctrlrequest *setup)
1530 {
1531 u16 status = 0;
1532 int retval;
1533
1534 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1535 != (USB_DIR_IN | USB_TYPE_STANDARD))
1536 return;
1537
1538 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1539 status = 1 << USB_DEVICE_SELF_POWERED;
1540 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1541 } else if ((setup->bRequestType & USB_RECIP_MASK)
1542 == USB_RECIP_INTERFACE) {
1543 /* get interface status */
1544 status = 0;
1545 } else if ((setup->bRequestType & USB_RECIP_MASK)
1546 == USB_RECIP_ENDPOINT) {
1547 u8 ep_num, direction;
1548
1549 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1550 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1551 ? EP_DIR_IN : EP_DIR_OUT;
1552 status = ep_is_stall(udc, ep_num, direction)
1553 << USB_ENDPOINT_HALT;
1554 }
1555
1556 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1557 if (retval)
1558 ep0_stall(udc);
1559 else
1560 udc->ep0_state = DATA_STATE_XMIT;
1561 }
1562
1563 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1564 {
1565 u8 ep_num;
1566 u8 direction;
1567 struct mv_ep *ep;
1568
1569 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1570 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1571 switch (setup->wValue) {
1572 case USB_DEVICE_REMOTE_WAKEUP:
1573 udc->remote_wakeup = 0;
1574 break;
1575 default:
1576 goto out;
1577 }
1578 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1579 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1580 switch (setup->wValue) {
1581 case USB_ENDPOINT_HALT:
1582 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1583 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1584 ? EP_DIR_IN : EP_DIR_OUT;
1585 if (setup->wValue != 0 || setup->wLength != 0
1586 || ep_num > udc->max_eps)
1587 goto out;
1588 ep = &udc->eps[ep_num * 2 + direction];
1589 if (ep->wedge == 1)
1590 break;
1591 spin_unlock(&udc->lock);
1592 ep_set_stall(udc, ep_num, direction, 0);
1593 spin_lock(&udc->lock);
1594 break;
1595 default:
1596 goto out;
1597 }
1598 } else
1599 goto out;
1600
1601 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1602 ep0_stall(udc);
1603 out:
1604 return;
1605 }
1606
1607 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1608 {
1609 u8 ep_num;
1610 u8 direction;
1611
1612 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1613 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1614 switch (setup->wValue) {
1615 case USB_DEVICE_REMOTE_WAKEUP:
1616 udc->remote_wakeup = 1;
1617 break;
1618 case USB_DEVICE_TEST_MODE:
1619 if (setup->wIndex & 0xFF
1620 || udc->gadget.speed != USB_SPEED_HIGH)
1621 ep0_stall(udc);
1622
1623 if (udc->usb_state != USB_STATE_CONFIGURED
1624 && udc->usb_state != USB_STATE_ADDRESS
1625 && udc->usb_state != USB_STATE_DEFAULT)
1626 ep0_stall(udc);
1627
1628 mv_udc_testmode(udc, (setup->wIndex >> 8));
1629 goto out;
1630 default:
1631 goto out;
1632 }
1633 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1634 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1635 switch (setup->wValue) {
1636 case USB_ENDPOINT_HALT:
1637 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1638 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1639 ? EP_DIR_IN : EP_DIR_OUT;
1640 if (setup->wValue != 0 || setup->wLength != 0
1641 || ep_num > udc->max_eps)
1642 goto out;
1643 spin_unlock(&udc->lock);
1644 ep_set_stall(udc, ep_num, direction, 1);
1645 spin_lock(&udc->lock);
1646 break;
1647 default:
1648 goto out;
1649 }
1650 } else
1651 goto out;
1652
1653 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1654 ep0_stall(udc);
1655 out:
1656 return;
1657 }
1658
1659 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1660 struct usb_ctrlrequest *setup)
1661 __releases(&ep->udc->lock)
1662 __acquires(&ep->udc->lock)
1663 {
1664 bool delegate = false;
1665
1666 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1667
1668 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1669 setup->bRequestType, setup->bRequest,
1670 setup->wValue, setup->wIndex, setup->wLength);
1671 /* We process some standard setup requests here */
1672 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1673 switch (setup->bRequest) {
1674 case USB_REQ_GET_STATUS:
1675 ch9getstatus(udc, ep_num, setup);
1676 break;
1677
1678 case USB_REQ_SET_ADDRESS:
1679 ch9setaddress(udc, setup);
1680 break;
1681
1682 case USB_REQ_CLEAR_FEATURE:
1683 ch9clearfeature(udc, setup);
1684 break;
1685
1686 case USB_REQ_SET_FEATURE:
1687 ch9setfeature(udc, setup);
1688 break;
1689
1690 default:
1691 delegate = true;
1692 }
1693 } else
1694 delegate = true;
1695
1696 /* delegate USB standard requests to the gadget driver */
1697 if (delegate == true) {
1698 /* USB requests handled by gadget */
1699 if (setup->wLength) {
1700 /* DATA phase from gadget, STATUS phase from udc */
1701 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1702 ? EP_DIR_IN : EP_DIR_OUT;
1703 spin_unlock(&udc->lock);
1704 if (udc->driver->setup(&udc->gadget,
1705 &udc->local_setup_buff) < 0)
1706 ep0_stall(udc);
1707 spin_lock(&udc->lock);
1708 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1709 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1710 } else {
1711 /* no DATA phase, IN STATUS phase from gadget */
1712 udc->ep0_dir = EP_DIR_IN;
1713 spin_unlock(&udc->lock);
1714 if (udc->driver->setup(&udc->gadget,
1715 &udc->local_setup_buff) < 0)
1716 ep0_stall(udc);
1717 spin_lock(&udc->lock);
1718 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1719 }
1720 }
1721 }
1722
1723 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1724 static void ep0_req_complete(struct mv_udc *udc,
1725 struct mv_ep *ep0, struct mv_req *req)
1726 {
1727 u32 new_addr;
1728
1729 if (udc->usb_state == USB_STATE_ADDRESS) {
1730 /* set the new address */
1731 new_addr = (u32)udc->dev_addr;
1732 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1733 &udc->op_regs->deviceaddr);
1734 }
1735
1736 done(ep0, req, 0);
1737
1738 switch (udc->ep0_state) {
1739 case DATA_STATE_XMIT:
1740 /* receive status phase */
1741 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1742 ep0_stall(udc);
1743 break;
1744 case DATA_STATE_RECV:
1745 /* send status phase */
1746 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1747 ep0_stall(udc);
1748 break;
1749 case WAIT_FOR_OUT_STATUS:
1750 udc->ep0_state = WAIT_FOR_SETUP;
1751 break;
1752 case WAIT_FOR_SETUP:
1753 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1754 break;
1755 default:
1756 ep0_stall(udc);
1757 break;
1758 }
1759 }
1760
1761 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1762 {
1763 u32 temp;
1764 struct mv_dqh *dqh;
1765
1766 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1767
1768 /* Clear bit in ENDPTSETUPSTAT */
1769 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1770
1771 /* while a hazard exists when setup package arrives */
1772 do {
1773 /* Set Setup Tripwire */
1774 temp = readl(&udc->op_regs->usbcmd);
1775 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1776
1777 /* Copy the setup packet to local buffer */
1778 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1779 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1780
1781 /* Clear Setup Tripwire */
1782 temp = readl(&udc->op_regs->usbcmd);
1783 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1784 }
1785
1786 static void irq_process_tr_complete(struct mv_udc *udc)
1787 {
1788 u32 tmp, bit_pos;
1789 int i, ep_num = 0, direction = 0;
1790 struct mv_ep *curr_ep;
1791 struct mv_req *curr_req, *temp_req;
1792 int status;
1793
1794 /*
1795 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1796 * because the setup packets are to be read ASAP
1797 */
1798
1799 /* Process all Setup packet received interrupts */
1800 tmp = readl(&udc->op_regs->epsetupstat);
1801
1802 if (tmp) {
1803 for (i = 0; i < udc->max_eps; i++) {
1804 if (tmp & (1 << i)) {
1805 get_setup_data(udc, i,
1806 (u8 *)(&udc->local_setup_buff));
1807 handle_setup_packet(udc, i,
1808 &udc->local_setup_buff);
1809 }
1810 }
1811 }
1812
1813 /* Don't clear the endpoint setup status register here.
1814 * It is cleared as a setup packet is read out of the buffer
1815 */
1816
1817 /* Process non-setup transaction complete interrupts */
1818 tmp = readl(&udc->op_regs->epcomplete);
1819
1820 if (!tmp)
1821 return;
1822
1823 writel(tmp, &udc->op_regs->epcomplete);
1824
1825 for (i = 0; i < udc->max_eps * 2; i++) {
1826 ep_num = i >> 1;
1827 direction = i % 2;
1828
1829 bit_pos = 1 << (ep_num + 16 * direction);
1830
1831 if (!(bit_pos & tmp))
1832 continue;
1833
1834 if (i == 1)
1835 curr_ep = &udc->eps[0];
1836 else
1837 curr_ep = &udc->eps[i];
1838 /* process the req queue until an uncomplete request */
1839 list_for_each_entry_safe(curr_req, temp_req,
1840 &curr_ep->queue, queue) {
1841 status = process_ep_req(udc, i, curr_req);
1842 if (status)
1843 break;
1844
1845 /* write back status to req */
1846 curr_req->req.status = status;
1847
1848 /* ep0 request completion */
1849 if (ep_num == 0) {
1850 ep0_req_complete(udc, curr_ep, curr_req);
1851 break;
1852 } else {
1853 done(curr_ep, curr_req, status);
1854 }
1855 }
1856 }
1857 }
1858
1859 static void irq_process_reset(struct mv_udc *udc)
1860 {
1861 u32 tmp;
1862 unsigned int loops;
1863
1864 udc->ep0_dir = EP_DIR_OUT;
1865 udc->ep0_state = WAIT_FOR_SETUP;
1866 udc->remote_wakeup = 0; /* default to 0 on reset */
1867
1868 /* The address bits are past bit 25-31. Set the address */
1869 tmp = readl(&udc->op_regs->deviceaddr);
1870 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1871 writel(tmp, &udc->op_regs->deviceaddr);
1872
1873 /* Clear all the setup token semaphores */
1874 tmp = readl(&udc->op_regs->epsetupstat);
1875 writel(tmp, &udc->op_regs->epsetupstat);
1876
1877 /* Clear all the endpoint complete status bits */
1878 tmp = readl(&udc->op_regs->epcomplete);
1879 writel(tmp, &udc->op_regs->epcomplete);
1880
1881 /* wait until all endptprime bits cleared */
1882 loops = LOOPS(PRIME_TIMEOUT);
1883 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1884 if (loops == 0) {
1885 dev_err(&udc->dev->dev,
1886 "Timeout for ENDPTPRIME = 0x%x\n",
1887 readl(&udc->op_regs->epprime));
1888 break;
1889 }
1890 loops--;
1891 udelay(LOOPS_USEC);
1892 }
1893
1894 /* Write 1s to the Flush register */
1895 writel((u32)~0, &udc->op_regs->epflush);
1896
1897 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1898 dev_info(&udc->dev->dev, "usb bus reset\n");
1899 udc->usb_state = USB_STATE_DEFAULT;
1900 /* reset all the queues, stop all USB activities */
1901 gadget_reset(udc, udc->driver);
1902 } else {
1903 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1904 readl(&udc->op_regs->portsc));
1905
1906 /*
1907 * re-initialize
1908 * controller reset
1909 */
1910 udc_reset(udc);
1911
1912 /* reset all the queues, stop all USB activities */
1913 stop_activity(udc, udc->driver);
1914
1915 /* reset ep0 dQH and endptctrl */
1916 ep0_reset(udc);
1917
1918 /* enable interrupt and set controller to run state */
1919 udc_start(udc);
1920
1921 udc->usb_state = USB_STATE_ATTACHED;
1922 }
1923 }
1924
1925 static void handle_bus_resume(struct mv_udc *udc)
1926 {
1927 udc->usb_state = udc->resume_state;
1928 udc->resume_state = 0;
1929
1930 /* report resume to the driver */
1931 if (udc->driver) {
1932 if (udc->driver->resume) {
1933 spin_unlock(&udc->lock);
1934 udc->driver->resume(&udc->gadget);
1935 spin_lock(&udc->lock);
1936 }
1937 }
1938 }
1939
1940 static void irq_process_suspend(struct mv_udc *udc)
1941 {
1942 udc->resume_state = udc->usb_state;
1943 udc->usb_state = USB_STATE_SUSPENDED;
1944
1945 if (udc->driver->suspend) {
1946 spin_unlock(&udc->lock);
1947 udc->driver->suspend(&udc->gadget);
1948 spin_lock(&udc->lock);
1949 }
1950 }
1951
1952 static void irq_process_port_change(struct mv_udc *udc)
1953 {
1954 u32 portsc;
1955
1956 portsc = readl(&udc->op_regs->portsc[0]);
1957 if (!(portsc & PORTSCX_PORT_RESET)) {
1958 /* Get the speed */
1959 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1960 switch (speed) {
1961 case PORTSCX_PORT_SPEED_HIGH:
1962 udc->gadget.speed = USB_SPEED_HIGH;
1963 break;
1964 case PORTSCX_PORT_SPEED_FULL:
1965 udc->gadget.speed = USB_SPEED_FULL;
1966 break;
1967 case PORTSCX_PORT_SPEED_LOW:
1968 udc->gadget.speed = USB_SPEED_LOW;
1969 break;
1970 default:
1971 udc->gadget.speed = USB_SPEED_UNKNOWN;
1972 break;
1973 }
1974 }
1975
1976 if (portsc & PORTSCX_PORT_SUSPEND) {
1977 udc->resume_state = udc->usb_state;
1978 udc->usb_state = USB_STATE_SUSPENDED;
1979 if (udc->driver->suspend) {
1980 spin_unlock(&udc->lock);
1981 udc->driver->suspend(&udc->gadget);
1982 spin_lock(&udc->lock);
1983 }
1984 }
1985
1986 if (!(portsc & PORTSCX_PORT_SUSPEND)
1987 && udc->usb_state == USB_STATE_SUSPENDED) {
1988 handle_bus_resume(udc);
1989 }
1990
1991 if (!udc->resume_state)
1992 udc->usb_state = USB_STATE_DEFAULT;
1993 }
1994
1995 static void irq_process_error(struct mv_udc *udc)
1996 {
1997 /* Increment the error count */
1998 udc->errors++;
1999 }
2000
2001 static irqreturn_t mv_udc_irq(int irq, void *dev)
2002 {
2003 struct mv_udc *udc = (struct mv_udc *)dev;
2004 u32 status, intr;
2005
2006 /* Disable ISR when stopped bit is set */
2007 if (udc->stopped)
2008 return IRQ_NONE;
2009
2010 spin_lock(&udc->lock);
2011
2012 status = readl(&udc->op_regs->usbsts);
2013 intr = readl(&udc->op_regs->usbintr);
2014 status &= intr;
2015
2016 if (status == 0) {
2017 spin_unlock(&udc->lock);
2018 return IRQ_NONE;
2019 }
2020
2021 /* Clear all the interrupts occurred */
2022 writel(status, &udc->op_regs->usbsts);
2023
2024 if (status & USBSTS_ERR)
2025 irq_process_error(udc);
2026
2027 if (status & USBSTS_RESET)
2028 irq_process_reset(udc);
2029
2030 if (status & USBSTS_PORT_CHANGE)
2031 irq_process_port_change(udc);
2032
2033 if (status & USBSTS_INT)
2034 irq_process_tr_complete(udc);
2035
2036 if (status & USBSTS_SUSPEND)
2037 irq_process_suspend(udc);
2038
2039 spin_unlock(&udc->lock);
2040
2041 return IRQ_HANDLED;
2042 }
2043
2044 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2045 {
2046 struct mv_udc *udc = (struct mv_udc *)dev;
2047
2048 /* polling VBUS and init phy may cause too much time*/
2049 if (udc->qwork)
2050 queue_work(udc->qwork, &udc->vbus_work);
2051
2052 return IRQ_HANDLED;
2053 }
2054
2055 static void mv_udc_vbus_work(struct work_struct *work)
2056 {
2057 struct mv_udc *udc;
2058 unsigned int vbus;
2059
2060 udc = container_of(work, struct mv_udc, vbus_work);
2061 if (!udc->pdata->vbus)
2062 return;
2063
2064 vbus = udc->pdata->vbus->poll();
2065 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2066
2067 if (vbus == VBUS_HIGH)
2068 mv_udc_vbus_session(&udc->gadget, 1);
2069 else if (vbus == VBUS_LOW)
2070 mv_udc_vbus_session(&udc->gadget, 0);
2071 }
2072
2073 /* release device structure */
2074 static void gadget_release(struct device *_dev)
2075 {
2076 struct mv_udc *udc;
2077
2078 udc = dev_get_drvdata(_dev);
2079
2080 complete(udc->done);
2081 }
2082
2083 static int mv_udc_remove(struct platform_device *pdev)
2084 {
2085 struct mv_udc *udc;
2086
2087 udc = platform_get_drvdata(pdev);
2088
2089 usb_del_gadget_udc(&udc->gadget);
2090
2091 if (udc->qwork) {
2092 flush_workqueue(udc->qwork);
2093 destroy_workqueue(udc->qwork);
2094 }
2095
2096 /* free memory allocated in probe */
2097 dma_pool_destroy(udc->dtd_pool);
2098
2099 if (udc->ep_dqh)
2100 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2101 udc->ep_dqh, udc->ep_dqh_dma);
2102
2103 mv_udc_disable(udc);
2104
2105 /* free dev, wait for the release() finished */
2106 wait_for_completion(udc->done);
2107
2108 return 0;
2109 }
2110
2111 static int mv_udc_probe(struct platform_device *pdev)
2112 {
2113 struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
2114 struct mv_udc *udc;
2115 int retval = 0;
2116 struct resource *r;
2117 size_t size;
2118
2119 if (pdata == NULL) {
2120 dev_err(&pdev->dev, "missing platform_data\n");
2121 return -ENODEV;
2122 }
2123
2124 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2125 if (udc == NULL)
2126 return -ENOMEM;
2127
2128 udc->done = &release_done;
2129 udc->pdata = dev_get_platdata(&pdev->dev);
2130 spin_lock_init(&udc->lock);
2131
2132 udc->dev = pdev;
2133
2134 if (pdata->mode == MV_USB_MODE_OTG) {
2135 udc->transceiver = devm_usb_get_phy(&pdev->dev,
2136 USB_PHY_TYPE_USB2);
2137 if (IS_ERR(udc->transceiver)) {
2138 retval = PTR_ERR(udc->transceiver);
2139
2140 if (retval == -ENXIO)
2141 return retval;
2142
2143 udc->transceiver = NULL;
2144 return -EPROBE_DEFER;
2145 }
2146 }
2147
2148 /* udc only have one sysclk. */
2149 udc->clk = devm_clk_get(&pdev->dev, NULL);
2150 if (IS_ERR(udc->clk))
2151 return PTR_ERR(udc->clk);
2152
2153 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2154 if (r == NULL) {
2155 dev_err(&pdev->dev, "no I/O memory resource defined\n");
2156 return -ENODEV;
2157 }
2158
2159 udc->cap_regs = (struct mv_cap_regs __iomem *)
2160 devm_ioremap(&pdev->dev, r->start, resource_size(r));
2161 if (udc->cap_regs == NULL) {
2162 dev_err(&pdev->dev, "failed to map I/O memory\n");
2163 return -EBUSY;
2164 }
2165
2166 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2167 if (r == NULL) {
2168 dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
2169 return -ENODEV;
2170 }
2171
2172 udc->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
2173 if (udc->phy_regs == NULL) {
2174 dev_err(&pdev->dev, "failed to map phy I/O memory\n");
2175 return -EBUSY;
2176 }
2177
2178 /* we will acces controller register, so enable the clk */
2179 retval = mv_udc_enable_internal(udc);
2180 if (retval)
2181 return retval;
2182
2183 udc->op_regs =
2184 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2185 + (readl(&udc->cap_regs->caplength_hciversion)
2186 & CAPLENGTH_MASK));
2187 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2188
2189 /*
2190 * some platform will use usb to download image, it may not disconnect
2191 * usb gadget before loading kernel. So first stop udc here.
2192 */
2193 udc_stop(udc);
2194 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2195
2196 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2197 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2198 udc->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
2199 &udc->ep_dqh_dma, GFP_KERNEL);
2200
2201 if (udc->ep_dqh == NULL) {
2202 dev_err(&pdev->dev, "allocate dQH memory failed\n");
2203 retval = -ENOMEM;
2204 goto err_disable_clock;
2205 }
2206 udc->ep_dqh_size = size;
2207
2208 /* create dTD dma_pool resource */
2209 udc->dtd_pool = dma_pool_create("mv_dtd",
2210 &pdev->dev,
2211 sizeof(struct mv_dtd),
2212 DTD_ALIGNMENT,
2213 DMA_BOUNDARY);
2214
2215 if (!udc->dtd_pool) {
2216 retval = -ENOMEM;
2217 goto err_free_dma;
2218 }
2219
2220 size = udc->max_eps * sizeof(struct mv_ep) *2;
2221 udc->eps = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2222 if (udc->eps == NULL) {
2223 retval = -ENOMEM;
2224 goto err_destroy_dma;
2225 }
2226
2227 /* initialize ep0 status request structure */
2228 udc->status_req = devm_kzalloc(&pdev->dev, sizeof(struct mv_req),
2229 GFP_KERNEL);
2230 if (!udc->status_req) {
2231 retval = -ENOMEM;
2232 goto err_destroy_dma;
2233 }
2234 INIT_LIST_HEAD(&udc->status_req->queue);
2235
2236 /* allocate a small amount of memory to get valid address */
2237 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2238 udc->status_req->req.dma = DMA_ADDR_INVALID;
2239
2240 udc->resume_state = USB_STATE_NOTATTACHED;
2241 udc->usb_state = USB_STATE_POWERED;
2242 udc->ep0_dir = EP_DIR_OUT;
2243 udc->remote_wakeup = 0;
2244
2245 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2246 if (r == NULL) {
2247 dev_err(&pdev->dev, "no IRQ resource defined\n");
2248 retval = -ENODEV;
2249 goto err_destroy_dma;
2250 }
2251 udc->irq = r->start;
2252 if (devm_request_irq(&pdev->dev, udc->irq, mv_udc_irq,
2253 IRQF_SHARED, driver_name, udc)) {
2254 dev_err(&pdev->dev, "Request irq %d for UDC failed\n",
2255 udc->irq);
2256 retval = -ENODEV;
2257 goto err_destroy_dma;
2258 }
2259
2260 /* initialize gadget structure */
2261 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2262 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2263 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2264 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2265 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2266
2267 /* the "gadget" abstracts/virtualizes the controller */
2268 udc->gadget.name = driver_name; /* gadget name */
2269
2270 eps_init(udc);
2271
2272 /* VBUS detect: we can disable/enable clock on demand.*/
2273 if (udc->transceiver)
2274 udc->clock_gating = 1;
2275 else if (pdata->vbus) {
2276 udc->clock_gating = 1;
2277 retval = devm_request_threaded_irq(&pdev->dev,
2278 pdata->vbus->irq, NULL,
2279 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2280 if (retval) {
2281 dev_info(&pdev->dev,
2282 "Can not request irq for VBUS, "
2283 "disable clock gating\n");
2284 udc->clock_gating = 0;
2285 }
2286
2287 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2288 if (!udc->qwork) {
2289 dev_err(&pdev->dev, "cannot create workqueue\n");
2290 retval = -ENOMEM;
2291 goto err_destroy_dma;
2292 }
2293
2294 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2295 }
2296
2297 /*
2298 * When clock gating is supported, we can disable clk and phy.
2299 * If not, it means that VBUS detection is not supported, we
2300 * have to enable vbus active all the time to let controller work.
2301 */
2302 if (udc->clock_gating)
2303 mv_udc_disable_internal(udc);
2304 else
2305 udc->vbus_active = 1;
2306
2307 retval = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2308 gadget_release);
2309 if (retval)
2310 goto err_create_workqueue;
2311
2312 platform_set_drvdata(pdev, udc);
2313 dev_info(&pdev->dev, "successful probe UDC device %s clock gating.\n",
2314 udc->clock_gating ? "with" : "without");
2315
2316 return 0;
2317
2318 err_create_workqueue:
2319 destroy_workqueue(udc->qwork);
2320 err_destroy_dma:
2321 dma_pool_destroy(udc->dtd_pool);
2322 err_free_dma:
2323 dma_free_coherent(&pdev->dev, udc->ep_dqh_size,
2324 udc->ep_dqh, udc->ep_dqh_dma);
2325 err_disable_clock:
2326 mv_udc_disable_internal(udc);
2327
2328 return retval;
2329 }
2330
2331 #ifdef CONFIG_PM
2332 static int mv_udc_suspend(struct device *dev)
2333 {
2334 struct mv_udc *udc;
2335
2336 udc = dev_get_drvdata(dev);
2337
2338 /* if OTG is enabled, the following will be done in OTG driver*/
2339 if (udc->transceiver)
2340 return 0;
2341
2342 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2343 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2344 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2345 return -EAGAIN;
2346 }
2347
2348 /*
2349 * only cable is unplugged, udc can suspend.
2350 * So do not care about clock_gating == 1.
2351 */
2352 if (!udc->clock_gating) {
2353 udc_stop(udc);
2354
2355 spin_lock_irq(&udc->lock);
2356 /* stop all usb activities */
2357 stop_activity(udc, udc->driver);
2358 spin_unlock_irq(&udc->lock);
2359
2360 mv_udc_disable_internal(udc);
2361 }
2362
2363 return 0;
2364 }
2365
2366 static int mv_udc_resume(struct device *dev)
2367 {
2368 struct mv_udc *udc;
2369 int retval;
2370
2371 udc = dev_get_drvdata(dev);
2372
2373 /* if OTG is enabled, the following will be done in OTG driver*/
2374 if (udc->transceiver)
2375 return 0;
2376
2377 if (!udc->clock_gating) {
2378 retval = mv_udc_enable_internal(udc);
2379 if (retval)
2380 return retval;
2381
2382 if (udc->driver && udc->softconnect) {
2383 udc_reset(udc);
2384 ep0_reset(udc);
2385 udc_start(udc);
2386 }
2387 }
2388
2389 return 0;
2390 }
2391
2392 static const struct dev_pm_ops mv_udc_pm_ops = {
2393 .suspend = mv_udc_suspend,
2394 .resume = mv_udc_resume,
2395 };
2396 #endif
2397
2398 static void mv_udc_shutdown(struct platform_device *pdev)
2399 {
2400 struct mv_udc *udc;
2401 u32 mode;
2402
2403 udc = platform_get_drvdata(pdev);
2404 /* reset controller mode to IDLE */
2405 mv_udc_enable(udc);
2406 mode = readl(&udc->op_regs->usbmode);
2407 mode &= ~3;
2408 writel(mode, &udc->op_regs->usbmode);
2409 mv_udc_disable(udc);
2410 }
2411
2412 static struct platform_driver udc_driver = {
2413 .probe = mv_udc_probe,
2414 .remove = mv_udc_remove,
2415 .shutdown = mv_udc_shutdown,
2416 .driver = {
2417 .name = "mv-udc",
2418 #ifdef CONFIG_PM
2419 .pm = &mv_udc_pm_ops,
2420 #endif
2421 },
2422 };
2423
2424 module_platform_driver(udc_driver);
2425 MODULE_ALIAS("platform:mv-udc");
2426 MODULE_DESCRIPTION(DRIVER_DESC);
2427 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2428 MODULE_VERSION(DRIVER_VERSION);
2429 MODULE_LICENSE("GPL");
Linux with added FPC-III support