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amd64_edac: check NB MCE bank enable on the current node properly
[linux/fpc-iii.git] / drivers / ide / pdc202xx_old.c
blobcb812f3700e8b70853fd7bea9c63173fa55f3adb
1 /*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
9 */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ide.h>
19
20 #include <asm/io.h>
21
22 #define DRV_NAME "pdc202xx_old"
23
24 #define PDC202XX_DEBUG_DRIVE_INFO 0
25
26 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
27
28 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
29 {
30 ide_hwif_t *hwif = drive->hwif;
31 struct pci_dev *dev = to_pci_dev(hwif->dev);
32 u8 drive_pci = 0x60 + (drive->dn << 2);
33
34 u8 AP = 0, BP = 0, CP = 0;
35 u8 TA = 0, TB = 0, TC = 0;
36
37 #if PDC202XX_DEBUG_DRIVE_INFO
38 u32 drive_conf = 0;
39 pci_read_config_dword(dev, drive_pci, &drive_conf);
40 #endif
41
42 /*
43 * TODO: do this once per channel
44 */
45 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
46 pdc_old_disable_66MHz_clock(hwif);
47
48 pci_read_config_byte(dev, drive_pci, &AP);
49 pci_read_config_byte(dev, drive_pci + 1, &BP);
50 pci_read_config_byte(dev, drive_pci + 2, &CP);
51
52 switch(speed) {
53 case XFER_UDMA_5:
54 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
55 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
56 case XFER_UDMA_3:
57 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
58 case XFER_UDMA_0:
59 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
60 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
61 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
62 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
63 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
64 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
65 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
66 case XFER_PIO_0:
67 default: TA = 0x09; TB = 0x13; break;
68 }
69
70 if (speed < XFER_SW_DMA_0) {
71 /*
72 * preserve SYNC_INT / ERDDY_EN bits while clearing
73 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
74 */
75 AP &= ~0x3f;
76 if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
77 AP |= 0x20; /* set IORDY_EN bit */
78 if (drive->media == ide_disk)
79 AP |= 0x10; /* set Prefetch_EN bit */
80 /* clear PB[4:0] bits of register B */
81 BP &= ~0x1f;
82 pci_write_config_byte(dev, drive_pci, AP | TA);
83 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
84 } else {
85 /* clear MB[2:0] bits of register B */
86 BP &= ~0xe0;
87 /* clear MC[3:0] bits of register C */
88 CP &= ~0x0f;
89 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
90 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
91 }
92
93 #if PDC202XX_DEBUG_DRIVE_INFO
94 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
95 drive->name, ide_xfer_verbose(speed),
96 drive->dn, drive_conf);
97 pci_read_config_dword(dev, drive_pci, &drive_conf);
98 printk("0x%08x\n", drive_conf);
99 #endif
100 }
101
102 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
105 }
106
107 static int pdc202xx_test_irq(ide_hwif_t *hwif)
108 {
109 struct pci_dev *dev = to_pci_dev(hwif->dev);
110 unsigned long high_16 = pci_resource_start(dev, 4);
111 u8 sc1d = inb(high_16 + 0x1d);
112
113 if (hwif->channel) {
114 /*
115 * bit 7: error, bit 6: interrupting,
116 * bit 5: FIFO full, bit 4: FIFO empty
117 */
118 return ((sc1d & 0x50) == 0x40) ? 1 : 0;
119 } else {
120 /*
121 * bit 3: error, bit 2: interrupting,
122 * bit 1: FIFO full, bit 0: FIFO empty
123 */
124 return ((sc1d & 0x05) == 0x04) ? 1 : 0;
125 }
126 }
127
128 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
129 {
130 struct pci_dev *dev = to_pci_dev(hwif->dev);
131 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
132
133 pci_read_config_word(dev, 0x50, &CIS);
134
135 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
136 }
137
138 /*
139 * Set the control register to use the 66MHz system
140 * clock for UDMA 3/4/5 mode operation when necessary.
141 *
142 * FIXME: this register is shared by both channels, some locking is needed
143 *
144 * It may also be possible to leave the 66MHz clock on
145 * and readjust the timing parameters.
146 */
147 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
148 {
149 unsigned long clock_reg = hwif->extra_base + 0x01;
150 u8 clock = inb(clock_reg);
151
152 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
153 }
154
155 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
156 {
157 unsigned long clock_reg = hwif->extra_base + 0x01;
158 u8 clock = inb(clock_reg);
159
160 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
161 }
162
163 static void pdc202xx_dma_start(ide_drive_t *drive)
164 {
165 if (drive->current_speed > XFER_UDMA_2)
166 pdc_old_enable_66MHz_clock(drive->hwif);
167 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
168 ide_hwif_t *hwif = drive->hwif;
169 struct request *rq = hwif->rq;
170 unsigned long high_16 = hwif->extra_base - 16;
171 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
172 u32 word_count = 0;
173 u8 clock = inb(high_16 + 0x11);
174
175 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
176 word_count = (blk_rq_sectors(rq) << 8);
177 word_count = (rq_data_dir(rq) == READ) ?
178 word_count | 0x05000000 :
179 word_count | 0x06000000;
180 outl(word_count, atapi_reg);
181 }
182 ide_dma_start(drive);
183 }
184
185 static int pdc202xx_dma_end(ide_drive_t *drive)
186 {
187 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
188 ide_hwif_t *hwif = drive->hwif;
189 unsigned long high_16 = hwif->extra_base - 16;
190 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
191 u8 clock = 0;
192
193 outl(0, atapi_reg); /* zero out extra */
194 clock = inb(high_16 + 0x11);
195 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
196 }
197 if (drive->current_speed > XFER_UDMA_2)
198 pdc_old_disable_66MHz_clock(drive->hwif);
199 return ide_dma_end(drive);
200 }
201
202 static int init_chipset_pdc202xx(struct pci_dev *dev)
203 {
204 unsigned long dmabase = pci_resource_start(dev, 4);
205 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
206
207 if (dmabase == 0)
208 goto out;
209
210 udma_speed_flag = inb(dmabase | 0x1f);
211 primary_mode = inb(dmabase | 0x1a);
212 secondary_mode = inb(dmabase | 0x1b);
213 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
214 "Primary %s Mode " \
215 "Secondary %s Mode.\n", pci_name(dev),
216 (udma_speed_flag & 1) ? "EN" : "DIS",
217 (primary_mode & 1) ? "MASTER" : "PCI",
218 (secondary_mode & 1) ? "MASTER" : "PCI" );
219
220 if (!(udma_speed_flag & 1)) {
221 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
222 pci_name(dev), udma_speed_flag,
223 (udma_speed_flag|1));
224 outb(udma_speed_flag | 1, dmabase | 0x1f);
225 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
226 }
227 out:
228 return 0;
229 }
230
231 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
232 const char *name)
233 {
234 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
235 u8 irq = 0, irq2 = 0;
236 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
237 /* 0xbc */
238 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
239 if (irq != irq2) {
240 pci_write_config_byte(dev,
241 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
242 printk(KERN_INFO "%s %s: PCI config space interrupt "
243 "mirror fixed\n", name, pci_name(dev));
244 }
245 }
246 }
247
248 #define IDE_HFLAGS_PDC202XX \
249 (IDE_HFLAG_ERROR_STOPS_FIFO | \
250 IDE_HFLAG_OFF_BOARD)
251
252 static const struct ide_port_ops pdc20246_port_ops = {
253 .set_pio_mode = pdc202xx_set_pio_mode,
254 .set_dma_mode = pdc202xx_set_mode,
255 .test_irq = pdc202xx_test_irq,
256 };
257
258 static const struct ide_port_ops pdc2026x_port_ops = {
259 .set_pio_mode = pdc202xx_set_pio_mode,
260 .set_dma_mode = pdc202xx_set_mode,
261 .cable_detect = pdc2026x_cable_detect,
262 };
263
264 static const struct ide_dma_ops pdc2026x_dma_ops = {
265 .dma_host_set = ide_dma_host_set,
266 .dma_setup = ide_dma_setup,
267 .dma_start = pdc202xx_dma_start,
268 .dma_end = pdc202xx_dma_end,
269 .dma_test_irq = ide_dma_test_irq,
270 .dma_lost_irq = ide_dma_lost_irq,
271 .dma_timer_expiry = ide_dma_sff_timer_expiry,
272 .dma_sff_read_status = ide_dma_sff_read_status,
273 };
274
275 #define DECLARE_PDC2026X_DEV(udma, sectors) \
276 { \
277 .name = DRV_NAME, \
278 .init_chipset = init_chipset_pdc202xx, \
279 .port_ops = &pdc2026x_port_ops, \
280 .dma_ops = &pdc2026x_dma_ops, \
281 .host_flags = IDE_HFLAGS_PDC202XX, \
282 .pio_mask = ATA_PIO4, \
283 .mwdma_mask = ATA_MWDMA2, \
284 .udma_mask = udma, \
285 .max_sectors = sectors, \
286 }
287
288 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
289 { /* 0: PDC20246 */
290 .name = DRV_NAME,
291 .init_chipset = init_chipset_pdc202xx,
292 .port_ops = &pdc20246_port_ops,
293 .dma_ops = &sff_dma_ops,
294 .host_flags = IDE_HFLAGS_PDC202XX,
295 .pio_mask = ATA_PIO4,
296 .mwdma_mask = ATA_MWDMA2,
297 .udma_mask = ATA_UDMA2,
298 },
299
300 /* 1: PDC2026{2,3} */
301 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
302 /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
303 DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
304 };
305
306 /**
307 * pdc202xx_init_one - called when a PDC202xx is found
308 * @dev: the pdc202xx device
309 * @id: the matching pci id
310 *
311 * Called when the PCI registration layer (or the IDE initialization)
312 * finds a device matching our IDE device tables.
313 */
314
315 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
316 {
317 const struct ide_port_info *d;
318 u8 idx = id->driver_data;
319
320 d = &pdc202xx_chipsets[idx];
321
322 if (idx < 2)
323 pdc202ata4_fixup_irq(dev, d->name);
324
325 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
326 struct pci_dev *bridge = dev->bus->self;
327
328 if (bridge &&
329 bridge->vendor == PCI_VENDOR_ID_INTEL &&
330 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
331 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
332 printk(KERN_INFO DRV_NAME " %s: skipping Promise "
333 "PDC20265 attached to I2O RAID controller\n",
334 pci_name(dev));
335 return -ENODEV;
336 }
337 }
338
339 return ide_pci_init_one(dev, d, NULL);
340 }
341
342 static const struct pci_device_id pdc202xx_pci_tbl[] = {
343 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
344 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
345 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
346 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
347 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
348 { 0, },
349 };
350 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
351
352 static struct pci_driver pdc202xx_pci_driver = {
353 .name = "Promise_Old_IDE",
354 .id_table = pdc202xx_pci_tbl,
355 .probe = pdc202xx_init_one,
356 .remove = ide_pci_remove,
357 .suspend = ide_pci_suspend,
358 .resume = ide_pci_resume,
359 };
360
361 static int __init pdc202xx_ide_init(void)
362 {
363 return ide_pci_register_driver(&pdc202xx_pci_driver);
364 }
365
366 static void __exit pdc202xx_ide_exit(void)
367 {
368 pci_unregister_driver(&pdc202xx_pci_driver);
369 }
370
371 module_init(pdc202xx_ide_init);
372 module_exit(pdc202xx_ide_exit);
373
374 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
375 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
376 MODULE_LICENSE("GPL");
Linux with added FPC-III support