drivers/rtc/rtc-stm32.c

   1 /*
   2  * Copyright (C) Amelie Delaunay 2016
   3  * Author:  Amelie Delaunay <amelie.delaunay@st.com>
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/bcd.h>
   8 #include <linux/clk.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/ioport.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/rtc.h>
  16
  17 #define DRIVER_NAME "stm32_rtc"
  18
  19 /* STM32 RTC registers */
  20 #define STM32_RTC_TR            0x00
  21 #define STM32_RTC_DR            0x04
  22 #define STM32_RTC_CR            0x08
  23 #define STM32_RTC_ISR           0x0C
  24 #define STM32_RTC_PRER          0x10
  25 #define STM32_RTC_ALRMAR        0x1C
  26 #define STM32_RTC_WPR           0x24
  27
  28 /* STM32_RTC_TR bit fields  */
  29 #define STM32_RTC_TR_SEC_SHIFT          0
  30 #define STM32_RTC_TR_SEC                GENMASK(6, 0)
  31 #define STM32_RTC_TR_MIN_SHIFT          8
  32 #define STM32_RTC_TR_MIN                GENMASK(14, 8)
  33 #define STM32_RTC_TR_HOUR_SHIFT         16
  34 #define STM32_RTC_TR_HOUR               GENMASK(21, 16)
  35
  36 /* STM32_RTC_DR bit fields */
  37 #define STM32_RTC_DR_DATE_SHIFT         0
  38 #define STM32_RTC_DR_DATE               GENMASK(5, 0)
  39 #define STM32_RTC_DR_MONTH_SHIFT        8
  40 #define STM32_RTC_DR_MONTH              GENMASK(12, 8)
  41 #define STM32_RTC_DR_WDAY_SHIFT         13
  42 #define STM32_RTC_DR_WDAY               GENMASK(15, 13)
  43 #define STM32_RTC_DR_YEAR_SHIFT         16
  44 #define STM32_RTC_DR_YEAR               GENMASK(23, 16)
  45
  46 /* STM32_RTC_CR bit fields */
  47 #define STM32_RTC_CR_FMT                BIT(6)
  48 #define STM32_RTC_CR_ALRAE              BIT(8)
  49 #define STM32_RTC_CR_ALRAIE             BIT(12)
  50
  51 /* STM32_RTC_ISR bit fields */
  52 #define STM32_RTC_ISR_ALRAWF            BIT(0)
  53 #define STM32_RTC_ISR_INITS             BIT(4)
  54 #define STM32_RTC_ISR_RSF               BIT(5)
  55 #define STM32_RTC_ISR_INITF             BIT(6)
  56 #define STM32_RTC_ISR_INIT              BIT(7)
  57 #define STM32_RTC_ISR_ALRAF             BIT(8)
  58
  59 /* STM32_RTC_PRER bit fields */
  60 #define STM32_RTC_PRER_PRED_S_SHIFT     0
  61 #define STM32_RTC_PRER_PRED_S           GENMASK(14, 0)
  62 #define STM32_RTC_PRER_PRED_A_SHIFT     16
  63 #define STM32_RTC_PRER_PRED_A           GENMASK(22, 16)
  64
  65 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
  66 #define STM32_RTC_ALRMXR_SEC_SHIFT      0
  67 #define STM32_RTC_ALRMXR_SEC            GENMASK(6, 0)
  68 #define STM32_RTC_ALRMXR_SEC_MASK       BIT(7)
  69 #define STM32_RTC_ALRMXR_MIN_SHIFT      8
  70 #define STM32_RTC_ALRMXR_MIN            GENMASK(14, 8)
  71 #define STM32_RTC_ALRMXR_MIN_MASK       BIT(15)
  72 #define STM32_RTC_ALRMXR_HOUR_SHIFT     16
  73 #define STM32_RTC_ALRMXR_HOUR           GENMASK(21, 16)
  74 #define STM32_RTC_ALRMXR_PM             BIT(22)
  75 #define STM32_RTC_ALRMXR_HOUR_MASK      BIT(23)
  76 #define STM32_RTC_ALRMXR_DATE_SHIFT     24
  77 #define STM32_RTC_ALRMXR_DATE           GENMASK(29, 24)
  78 #define STM32_RTC_ALRMXR_WDSEL          BIT(30)
  79 #define STM32_RTC_ALRMXR_WDAY_SHIFT     24
  80 #define STM32_RTC_ALRMXR_WDAY           GENMASK(27, 24)
  81 #define STM32_RTC_ALRMXR_DATE_MASK      BIT(31)
  82
  83 /* STM32_RTC_WPR key constants */
  84 #define RTC_WPR_1ST_KEY                 0xCA
  85 #define RTC_WPR_2ND_KEY                 0x53
  86 #define RTC_WPR_WRONG_KEY               0xFF
  87
  88 /*
  89  * RTC registers are protected against parasitic write access.
  90  * PWR_CR_DBP bit must be set to enable write access to RTC registers.
  91  */
  92 /* STM32_PWR_CR */
  93 #define PWR_CR                          0x00
  94 /* STM32_PWR_CR bit field */
  95 #define PWR_CR_DBP                      BIT(8)
  96
  97 struct stm32_rtc_data {
  98         bool has_pclk;
  99 };
 100
 101 struct stm32_rtc {
 102         struct rtc_device *rtc_dev;
 103         void __iomem *base;
 104         struct regmap *dbp;
 105         struct stm32_rtc_data *data;
 106         struct clk *pclk;
 107         struct clk *rtc_ck;
 108         int irq_alarm;
 109 };
 110
 111 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
 112 {
 113         writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + STM32_RTC_WPR);
 114         writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + STM32_RTC_WPR);
 115 }
 116
 117 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
 118 {
 119         writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + STM32_RTC_WPR);
 120 }
 121
 122 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
 123 {
 124         unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 125
 126         if (!(isr & STM32_RTC_ISR_INITF)) {
 127                 isr |= STM32_RTC_ISR_INIT;
 128                 writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
 129
 130                 /*
 131                  * It takes around 2 rtc_ck clock cycles to enter in
 132                  * initialization phase mode (and have INITF flag set). As
 133                  * slowest rtc_ck frequency may be 32kHz and highest should be
 134                  * 1MHz, we poll every 10 us with a timeout of 100ms.
 135                  */
 136                 return readl_relaxed_poll_timeout_atomic(
 137                                         rtc->base + STM32_RTC_ISR,
 138                                         isr, (isr & STM32_RTC_ISR_INITF),
 139                                         10, 100000);
 140         }
 141
 142         return 0;
 143 }
 144
 145 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
 146 {
 147         unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 148
 149         isr &= ~STM32_RTC_ISR_INIT;
 150         writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
 151 }
 152
 153 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
 154 {
 155         unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 156
 157         isr &= ~STM32_RTC_ISR_RSF;
 158         writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
 159
 160         /*
 161          * Wait for RSF to be set to ensure the calendar registers are
 162          * synchronised, it takes around 2 rtc_ck clock cycles
 163          */
 164         return readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
 165                                                  isr,
 166                                                  (isr & STM32_RTC_ISR_RSF),
 167                                                  10, 100000);
 168 }
 169
 170 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
 171 {
 172         struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
 173         unsigned int isr, cr;
 174
 175         mutex_lock(&rtc->rtc_dev->ops_lock);
 176
 177         isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 178         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 179
 180         if ((isr & STM32_RTC_ISR_ALRAF) &&
 181             (cr & STM32_RTC_CR_ALRAIE)) {
 182                 /* Alarm A flag - Alarm interrupt */
 183                 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
 184
 185                 /* Pass event to the kernel */
 186                 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
 187
 188                 /* Clear event flag, otherwise new events won't be received */
 189                 writel_relaxed(isr & ~STM32_RTC_ISR_ALRAF,
 190                                rtc->base + STM32_RTC_ISR);
 191         }
 192
 193         mutex_unlock(&rtc->rtc_dev->ops_lock);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 /* Convert rtc_time structure from bin to bcd format */
 199 static void tm2bcd(struct rtc_time *tm)
 200 {
 201         tm->tm_sec = bin2bcd(tm->tm_sec);
 202         tm->tm_min = bin2bcd(tm->tm_min);
 203         tm->tm_hour = bin2bcd(tm->tm_hour);
 204
 205         tm->tm_mday = bin2bcd(tm->tm_mday);
 206         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 207         tm->tm_year = bin2bcd(tm->tm_year - 100);
 208         /*
 209          * Number of days since Sunday
 210          * - on kernel side, 0=Sunday...6=Saturday
 211          * - on rtc side, 0=invalid,1=Monday...7=Sunday
 212          */
 213         tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
 214 }
 215
 216 /* Convert rtc_time structure from bcd to bin format */
 217 static void bcd2tm(struct rtc_time *tm)
 218 {
 219         tm->tm_sec = bcd2bin(tm->tm_sec);
 220         tm->tm_min = bcd2bin(tm->tm_min);
 221         tm->tm_hour = bcd2bin(tm->tm_hour);
 222
 223         tm->tm_mday = bcd2bin(tm->tm_mday);
 224         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 225         tm->tm_year = bcd2bin(tm->tm_year) + 100;
 226         /*
 227          * Number of days since Sunday
 228          * - on kernel side, 0=Sunday...6=Saturday
 229          * - on rtc side, 0=invalid,1=Monday...7=Sunday
 230          */
 231         tm->tm_wday %= 7;
 232 }
 233
 234 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
 235 {
 236         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 237         unsigned int tr, dr;
 238
 239         /* Time and Date in BCD format */
 240         tr = readl_relaxed(rtc->base + STM32_RTC_TR);
 241         dr = readl_relaxed(rtc->base + STM32_RTC_DR);
 242
 243         tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
 244         tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
 245         tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
 246
 247         tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
 248         tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
 249         tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
 250         tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
 251
 252         /* We don't report tm_yday and tm_isdst */
 253
 254         bcd2tm(tm);
 255
 256         return 0;
 257 }
 258
 259 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
 260 {
 261         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 262         unsigned int tr, dr;
 263         int ret = 0;
 264
 265         tm2bcd(tm);
 266
 267         /* Time in BCD format */
 268         tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
 269              ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
 270              ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
 271
 272         /* Date in BCD format */
 273         dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
 274              ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
 275              ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
 276              ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
 277
 278         stm32_rtc_wpr_unlock(rtc);
 279
 280         ret = stm32_rtc_enter_init_mode(rtc);
 281         if (ret) {
 282                 dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
 283                 goto end;
 284         }
 285
 286         writel_relaxed(tr, rtc->base + STM32_RTC_TR);
 287         writel_relaxed(dr, rtc->base + STM32_RTC_DR);
 288
 289         stm32_rtc_exit_init_mode(rtc);
 290
 291         ret = stm32_rtc_wait_sync(rtc);
 292 end:
 293         stm32_rtc_wpr_lock(rtc);
 294
 295         return ret;
 296 }
 297
 298 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 299 {
 300         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 301         struct rtc_time *tm = &alrm->time;
 302         unsigned int alrmar, cr, isr;
 303
 304         alrmar = readl_relaxed(rtc->base + STM32_RTC_ALRMAR);
 305         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 306         isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 307
 308         if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
 309                 /*
 310                  * Date/day doesn't matter in Alarm comparison so alarm
 311                  * triggers every day
 312                  */
 313                 tm->tm_mday = -1;
 314                 tm->tm_wday = -1;
 315         } else {
 316                 if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
 317                         /* Alarm is set to a day of week */
 318                         tm->tm_mday = -1;
 319                         tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
 320                                       STM32_RTC_ALRMXR_WDAY_SHIFT;
 321                         tm->tm_wday %= 7;
 322                 } else {
 323                         /* Alarm is set to a day of month */
 324                         tm->tm_wday = -1;
 325                         tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
 326                                        STM32_RTC_ALRMXR_DATE_SHIFT;
 327                 }
 328         }
 329
 330         if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
 331                 /* Hours don't matter in Alarm comparison */
 332                 tm->tm_hour = -1;
 333         } else {
 334                 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
 335                                STM32_RTC_ALRMXR_HOUR_SHIFT;
 336                 if (alrmar & STM32_RTC_ALRMXR_PM)
 337                         tm->tm_hour += 12;
 338         }
 339
 340         if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
 341                 /* Minutes don't matter in Alarm comparison */
 342                 tm->tm_min = -1;
 343         } else {
 344                 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
 345                               STM32_RTC_ALRMXR_MIN_SHIFT;
 346         }
 347
 348         if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
 349                 /* Seconds don't matter in Alarm comparison */
 350                 tm->tm_sec = -1;
 351         } else {
 352                 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
 353                               STM32_RTC_ALRMXR_SEC_SHIFT;
 354         }
 355
 356         bcd2tm(tm);
 357
 358         alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
 359         alrm->pending = (isr & STM32_RTC_ISR_ALRAF) ? 1 : 0;
 360
 361         return 0;
 362 }
 363
 364 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 365 {
 366         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 367         unsigned int isr, cr;
 368
 369         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 370
 371         stm32_rtc_wpr_unlock(rtc);
 372
 373         /* We expose Alarm A to the kernel */
 374         if (enabled)
 375                 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
 376         else
 377                 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
 378         writel_relaxed(cr, rtc->base + STM32_RTC_CR);
 379
 380         /* Clear event flag, otherwise new events won't be received */
 381         isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
 382         isr &= ~STM32_RTC_ISR_ALRAF;
 383         writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
 384
 385         stm32_rtc_wpr_lock(rtc);
 386
 387         return 0;
 388 }
 389
 390 static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
 391 {
 392         int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
 393         unsigned int dr = readl_relaxed(rtc->base + STM32_RTC_DR);
 394         unsigned int tr = readl_relaxed(rtc->base + STM32_RTC_TR);
 395
 396         cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
 397         cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
 398         cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
 399         cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
 400         cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
 401         cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
 402
 403         /*
 404          * Assuming current date is M-D-Y H:M:S.
 405          * RTC alarm can't be set on a specific month and year.
 406          * So the valid alarm range is:
 407          *      M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
 408          * with a specific case for December...
 409          */
 410         if ((((tm->tm_year > cur_year) &&
 411               (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
 412              ((tm->tm_year == cur_year) &&
 413               (tm->tm_mon <= cur_mon + 1))) &&
 414             ((tm->tm_mday > cur_day) ||
 415              ((tm->tm_mday == cur_day) &&
 416              ((tm->tm_hour > cur_hour) ||
 417               ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
 418               ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
 419                (tm->tm_sec >= cur_sec))))))
 420                 return 0;
 421
 422         return -EINVAL;
 423 }
 424
 425 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 426 {
 427         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 428         struct rtc_time *tm = &alrm->time;
 429         unsigned int cr, isr, alrmar;
 430         int ret = 0;
 431
 432         tm2bcd(tm);
 433
 434         /*
 435          * RTC alarm can't be set on a specific date, unless this date is
 436          * up to the same day of month next month.
 437          */
 438         if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
 439                 dev_err(dev, "Alarm can be set only on upcoming month.\n");
 440                 return -EINVAL;
 441         }
 442
 443         alrmar = 0;
 444         /* tm_year and tm_mon are not used because not supported by RTC */
 445         alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
 446                   STM32_RTC_ALRMXR_DATE;
 447         /* 24-hour format */
 448         alrmar &= ~STM32_RTC_ALRMXR_PM;
 449         alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
 450                   STM32_RTC_ALRMXR_HOUR;
 451         alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
 452                   STM32_RTC_ALRMXR_MIN;
 453         alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
 454                   STM32_RTC_ALRMXR_SEC;
 455
 456         stm32_rtc_wpr_unlock(rtc);
 457
 458         /* Disable Alarm */
 459         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 460         cr &= ~STM32_RTC_CR_ALRAE;
 461         writel_relaxed(cr, rtc->base + STM32_RTC_CR);
 462
 463         /*
 464          * Poll Alarm write flag to be sure that Alarm update is allowed: it
 465          * takes around 2 rtc_ck clock cycles
 466          */
 467         ret = readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
 468                                                 isr,
 469                                                 (isr & STM32_RTC_ISR_ALRAWF),
 470                                                 10, 100000);
 471
 472         if (ret) {
 473                 dev_err(dev, "Alarm update not allowed\n");
 474                 goto end;
 475         }
 476
 477         /* Write to Alarm register */
 478         writel_relaxed(alrmar, rtc->base + STM32_RTC_ALRMAR);
 479
 480         if (alrm->enabled)
 481                 stm32_rtc_alarm_irq_enable(dev, 1);
 482         else
 483                 stm32_rtc_alarm_irq_enable(dev, 0);
 484
 485 end:
 486         stm32_rtc_wpr_lock(rtc);
 487
 488         return ret;
 489 }
 490
 491 static const struct rtc_class_ops stm32_rtc_ops = {
 492         .read_time      = stm32_rtc_read_time,
 493         .set_time       = stm32_rtc_set_time,
 494         .read_alarm     = stm32_rtc_read_alarm,
 495         .set_alarm      = stm32_rtc_set_alarm,
 496         .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
 497 };
 498
 499 static const struct stm32_rtc_data stm32_rtc_data = {
 500         .has_pclk = false,
 501 };
 502
 503 static const struct stm32_rtc_data stm32h7_rtc_data = {
 504         .has_pclk = true,
 505 };
 506
 507 static const struct of_device_id stm32_rtc_of_match[] = {
 508         { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
 509         { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
 510         {}
 511 };
 512 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
 513
 514 static int stm32_rtc_init(struct platform_device *pdev,
 515                           struct stm32_rtc *rtc)
 516 {
 517         unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
 518         unsigned int rate;
 519         int ret = 0;
 520
 521         rate = clk_get_rate(rtc->rtc_ck);
 522
 523         /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
 524         pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
 525         pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
 526
 527         for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
 528                 pred_s = (rate / (pred_a + 1)) - 1;
 529
 530                 if (((pred_s + 1) * (pred_a + 1)) == rate)
 531                         break;
 532         }
 533
 534         /*
 535          * Can't find a 1Hz, so give priority to RTC power consumption
 536          * by choosing the higher possible value for prediv_a
 537          */
 538         if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
 539                 pred_a = pred_a_max;
 540                 pred_s = (rate / (pred_a + 1)) - 1;
 541
 542                 dev_warn(&pdev->dev, "rtc_ck is %s\n",
 543                          (rate < ((pred_a + 1) * (pred_s + 1))) ?
 544                          "fast" : "slow");
 545         }
 546
 547         stm32_rtc_wpr_unlock(rtc);
 548
 549         ret = stm32_rtc_enter_init_mode(rtc);
 550         if (ret) {
 551                 dev_err(&pdev->dev,
 552                         "Can't enter in init mode. Prescaler config failed.\n");
 553                 goto end;
 554         }
 555
 556         prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
 557         writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
 558         prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
 559         writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
 560
 561         /* Force 24h time format */
 562         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 563         cr &= ~STM32_RTC_CR_FMT;
 564         writel_relaxed(cr, rtc->base + STM32_RTC_CR);
 565
 566         stm32_rtc_exit_init_mode(rtc);
 567
 568         ret = stm32_rtc_wait_sync(rtc);
 569 end:
 570         stm32_rtc_wpr_lock(rtc);
 571
 572         return ret;
 573 }
 574
 575 static int stm32_rtc_probe(struct platform_device *pdev)
 576 {
 577         struct stm32_rtc *rtc;
 578         struct resource *res;
 579         const struct of_device_id *match;
 580         int ret;
 581
 582         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 583         if (!rtc)
 584                 return -ENOMEM;
 585
 586         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 587         rtc->base = devm_ioremap_resource(&pdev->dev, res);
 588         if (IS_ERR(rtc->base))
 589                 return PTR_ERR(rtc->base);
 590
 591         rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 592                                                    "st,syscfg");
 593         if (IS_ERR(rtc->dbp)) {
 594                 dev_err(&pdev->dev, "no st,syscfg\n");
 595                 return PTR_ERR(rtc->dbp);
 596         }
 597
 598         match = of_match_device(stm32_rtc_of_match, &pdev->dev);
 599         rtc->data = (struct stm32_rtc_data *)match->data;
 600
 601         if (!rtc->data->has_pclk) {
 602                 rtc->pclk = NULL;
 603                 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
 604         } else {
 605                 rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
 606                 if (IS_ERR(rtc->pclk)) {
 607                         dev_err(&pdev->dev, "no pclk clock");
 608                         return PTR_ERR(rtc->pclk);
 609                 }
 610                 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
 611         }
 612         if (IS_ERR(rtc->rtc_ck)) {
 613                 dev_err(&pdev->dev, "no rtc_ck clock");
 614                 return PTR_ERR(rtc->rtc_ck);
 615         }
 616
 617         if (rtc->data->has_pclk) {
 618                 ret = clk_prepare_enable(rtc->pclk);
 619                 if (ret)
 620                         return ret;
 621         }
 622
 623         ret = clk_prepare_enable(rtc->rtc_ck);
 624         if (ret)
 625                 goto err;
 626
 627         regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
 628
 629         /*
 630          * After a system reset, RTC_ISR.INITS flag can be read to check if
 631          * the calendar has been initalized or not. INITS flag is reset by a
 632          * power-on reset (no vbat, no power-supply). It is not reset if
 633          * rtc_ck parent clock has changed (so RTC prescalers need to be
 634          * changed). That's why we cannot rely on this flag to know if RTC
 635          * init has to be done.
 636          */
 637         ret = stm32_rtc_init(pdev, rtc);
 638         if (ret)
 639                 goto err;
 640
 641         rtc->irq_alarm = platform_get_irq(pdev, 0);
 642         if (rtc->irq_alarm <= 0) {
 643                 dev_err(&pdev->dev, "no alarm irq\n");
 644                 ret = rtc->irq_alarm;
 645                 goto err;
 646         }
 647
 648         platform_set_drvdata(pdev, rtc);
 649
 650         ret = device_init_wakeup(&pdev->dev, true);
 651         if (ret)
 652                 dev_warn(&pdev->dev,
 653                          "alarm won't be able to wake up the system");
 654
 655         rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
 656                         &stm32_rtc_ops, THIS_MODULE);
 657         if (IS_ERR(rtc->rtc_dev)) {
 658                 ret = PTR_ERR(rtc->rtc_dev);
 659                 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
 660                         ret);
 661                 goto err;
 662         }
 663
 664         /* Handle RTC alarm interrupts */
 665         ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
 666                                         stm32_rtc_alarm_irq,
 667                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 668                                         pdev->name, rtc);
 669         if (ret) {
 670                 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
 671                         rtc->irq_alarm);
 672                 goto err;
 673         }
 674
 675         /*
 676          * If INITS flag is reset (calendar year field set to 0x00), calendar
 677          * must be initialized
 678          */
 679         if (!(readl_relaxed(rtc->base + STM32_RTC_ISR) & STM32_RTC_ISR_INITS))
 680                 dev_warn(&pdev->dev, "Date/Time must be initialized\n");
 681
 682         return 0;
 683 err:
 684         if (rtc->data->has_pclk)
 685                 clk_disable_unprepare(rtc->pclk);
 686         clk_disable_unprepare(rtc->rtc_ck);
 687
 688         regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0);
 689
 690         device_init_wakeup(&pdev->dev, false);
 691
 692         return ret;
 693 }
 694
 695 static int stm32_rtc_remove(struct platform_device *pdev)
 696 {
 697         struct stm32_rtc *rtc = platform_get_drvdata(pdev);
 698         unsigned int cr;
 699
 700         /* Disable interrupts */
 701         stm32_rtc_wpr_unlock(rtc);
 702         cr = readl_relaxed(rtc->base + STM32_RTC_CR);
 703         cr &= ~STM32_RTC_CR_ALRAIE;
 704         writel_relaxed(cr, rtc->base + STM32_RTC_CR);
 705         stm32_rtc_wpr_lock(rtc);
 706
 707         clk_disable_unprepare(rtc->rtc_ck);
 708         if (rtc->data->has_pclk)
 709                 clk_disable_unprepare(rtc->pclk);
 710
 711         /* Enable backup domain write protection */
 712         regmap_update_bits(rtc->dbp, PWR_CR, PWR_CR_DBP, 0);
 713
 714         device_init_wakeup(&pdev->dev, false);
 715
 716         return 0;
 717 }
 718
 719 #ifdef CONFIG_PM_SLEEP
 720 static int stm32_rtc_suspend(struct device *dev)
 721 {
 722         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 723
 724         if (rtc->data->has_pclk)
 725                 clk_disable_unprepare(rtc->pclk);
 726
 727         if (device_may_wakeup(dev))
 728                 return enable_irq_wake(rtc->irq_alarm);
 729
 730         return 0;
 731 }
 732
 733 static int stm32_rtc_resume(struct device *dev)
 734 {
 735         struct stm32_rtc *rtc = dev_get_drvdata(dev);
 736         int ret = 0;
 737
 738         if (rtc->data->has_pclk) {
 739                 ret = clk_prepare_enable(rtc->pclk);
 740                 if (ret)
 741                         return ret;
 742         }
 743
 744         ret = stm32_rtc_wait_sync(rtc);
 745         if (ret < 0)
 746                 return ret;
 747
 748         if (device_may_wakeup(dev))
 749                 return disable_irq_wake(rtc->irq_alarm);
 750
 751         return ret;
 752 }
 753 #endif
 754
 755 static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
 756                          stm32_rtc_suspend, stm32_rtc_resume);
 757
 758 static struct platform_driver stm32_rtc_driver = {
 759         .probe          = stm32_rtc_probe,
 760         .remove         = stm32_rtc_remove,
 761         .driver         = {
 762                 .name   = DRIVER_NAME,
 763                 .pm     = &stm32_rtc_pm_ops,
 764                 .of_match_table = stm32_rtc_of_match,
 765         },
 766 };
 767
 768 module_platform_driver(stm32_rtc_driver);
 769
 770 MODULE_ALIAS("platform:" DRIVER_NAME);
 771 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 772 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
 773 MODULE_LICENSE("GPL v2");