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[S390] Remove error checking from copy_oldmem_page()
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv50_display.c
blobd23ca00e7d627c65e3814891c0a8aa0136f58395
1 /*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28 #include "nv50_display.h"
29 #include "nouveau_crtc.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nouveau_ramht.h"
35 #include "drm_crtc_helper.h"
36
37 static void nv50_display_isr(struct drm_device *);
38 static void nv50_display_bh(unsigned long);
39
40 static inline int
41 nv50_sor_nr(struct drm_device *dev)
42 {
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44
45 if (dev_priv->chipset < 0x90 ||
46 dev_priv->chipset == 0x92 ||
47 dev_priv->chipset == 0xa0)
48 return 2;
49
50 return 4;
51 }
52
53 int
54 nv50_display_early_init(struct drm_device *dev)
55 {
56 return 0;
57 }
58
59 void
60 nv50_display_late_takedown(struct drm_device *dev)
61 {
62 }
63
64 int
65 nv50_display_init(struct drm_device *dev)
66 {
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
69 struct drm_connector *connector;
70 struct nouveau_channel *evo;
71 int ret, i;
72 u32 val;
73
74 NV_DEBUG_KMS(dev, "\n");
75
76 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
77
78 /*
79 * I think the 0x006101XX range is some kind of main control area
80 * that enables things.
81 */
82 /* CRTC? */
83 for (i = 0; i < 2; i++) {
84 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
85 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
86 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
87 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
88 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
89 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
90 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
91 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
92 }
93
94 /* DAC */
95 for (i = 0; i < 3; i++) {
96 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
97 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
98 }
99
100 /* SOR */
101 for (i = 0; i < nv50_sor_nr(dev); i++) {
102 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
103 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
104 }
105
106 /* EXT */
107 for (i = 0; i < 3; i++) {
108 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
109 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
110 }
111
112 for (i = 0; i < 3; i++) {
113 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
114 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
115 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
116 }
117
118 /* The precise purpose is unknown, i suspect it has something to do
119 * with text mode.
120 */
121 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
122 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
123 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
124 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
125 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
126 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
127 nv_rd32(dev, 0x6194e8));
128 return -EBUSY;
129 }
130 }
131
132 for (i = 0; i < 2; i++) {
133 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
134 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
135 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
136 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
137 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
138 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
139 return -EBUSY;
140 }
141
142 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
143 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
144 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
145 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
146 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
147 NV_ERROR(dev, "timeout: "
148 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
149 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
150 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
151 return -EBUSY;
152 }
153 }
154
155 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
156 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
157 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
158 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
159 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
160 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
161 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
162 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
163
164 /* enable hotplug interrupts */
165 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
166 struct nouveau_connector *conn = nouveau_connector(connector);
167
168 if (conn->dcb->gpio_tag == 0xff)
169 continue;
170
171 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
172 }
173
174 ret = nv50_evo_init(dev);
175 if (ret)
176 return ret;
177 evo = nv50_display(dev)->master;
178
179 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
180
181 ret = RING_SPACE(evo, 15);
182 if (ret)
183 return ret;
184 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
185 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
186 OUT_RING(evo, NvEvoSync);
187 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
188 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
189 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
190 OUT_RING(evo, 0);
191 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
192 OUT_RING(evo, 0);
193 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
194 OUT_RING(evo, 0);
195 /* required to make display sync channels not hate life */
196 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
197 OUT_RING (evo, 0x00000311);
198 BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
199 OUT_RING (evo, 0x00000311);
200 FIRE_RING(evo);
201 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
202 NV_ERROR(dev, "evo pushbuf stalled\n");
203
204
205 return 0;
206 }
207
208 static int nv50_display_disable(struct drm_device *dev)
209 {
210 struct drm_nouveau_private *dev_priv = dev->dev_private;
211 struct nv50_display *disp = nv50_display(dev);
212 struct nouveau_channel *evo = disp->master;
213 struct drm_crtc *drm_crtc;
214 int ret, i;
215
216 NV_DEBUG_KMS(dev, "\n");
217
218 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
219 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
220
221 nv50_crtc_blank(crtc, true);
222 }
223
224 ret = RING_SPACE(evo, 2);
225 if (ret == 0) {
226 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
227 OUT_RING(evo, 0);
228 }
229 FIRE_RING(evo);
230
231 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
232 * cleaning up?
233 */
234 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
235 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
236 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
237
238 if (!crtc->base.enabled)
239 continue;
240
241 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
242 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
243 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
244 "0x%08x\n", mask, mask);
245 NV_ERROR(dev, "0x610024 = 0x%08x\n",
246 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
247 }
248 }
249
250 for (i = 0; i < 2; i++) {
251 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
252 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
253 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
254 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
255 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
256 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
257 }
258 }
259
260 nv50_evo_fini(dev);
261
262 for (i = 0; i < 3; i++) {
263 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
264 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
265 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
266 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
267 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
268 }
269 }
270
271 /* disable interrupts. */
272 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
273
274 /* disable hotplug interrupts */
275 nv_wr32(dev, 0xe054, 0xffffffff);
276 nv_wr32(dev, 0xe050, 0x00000000);
277 if (dev_priv->chipset >= 0x90) {
278 nv_wr32(dev, 0xe074, 0xffffffff);
279 nv_wr32(dev, 0xe070, 0x00000000);
280 }
281 return 0;
282 }
283
284 int nv50_display_create(struct drm_device *dev)
285 {
286 struct drm_nouveau_private *dev_priv = dev->dev_private;
287 struct dcb_table *dcb = &dev_priv->vbios.dcb;
288 struct drm_connector *connector, *ct;
289 struct nv50_display *priv;
290 int ret, i;
291
292 NV_DEBUG_KMS(dev, "\n");
293
294 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
295 if (!priv)
296 return -ENOMEM;
297 dev_priv->engine.display.priv = priv;
298
299 /* Create CRTC objects */
300 for (i = 0; i < 2; i++)
301 nv50_crtc_create(dev, i);
302
303 /* We setup the encoders from the BIOS table */
304 for (i = 0 ; i < dcb->entries; i++) {
305 struct dcb_entry *entry = &dcb->entry[i];
306
307 if (entry->location != DCB_LOC_ON_CHIP) {
308 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
309 entry->type, ffs(entry->or) - 1);
310 continue;
311 }
312
313 connector = nouveau_connector_create(dev, entry->connector);
314 if (IS_ERR(connector))
315 continue;
316
317 switch (entry->type) {
318 case OUTPUT_TMDS:
319 case OUTPUT_LVDS:
320 case OUTPUT_DP:
321 nv50_sor_create(connector, entry);
322 break;
323 case OUTPUT_ANALOG:
324 nv50_dac_create(connector, entry);
325 break;
326 default:
327 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
328 continue;
329 }
330 }
331
332 list_for_each_entry_safe(connector, ct,
333 &dev->mode_config.connector_list, head) {
334 if (!connector->encoder_ids[0]) {
335 NV_WARN(dev, "%s has no encoders, removing\n",
336 drm_get_connector_name(connector));
337 connector->funcs->destroy(connector);
338 }
339 }
340
341 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
342 nouveau_irq_register(dev, 26, nv50_display_isr);
343
344 ret = nv50_display_init(dev);
345 if (ret) {
346 nv50_display_destroy(dev);
347 return ret;
348 }
349
350 return 0;
351 }
352
353 void
354 nv50_display_destroy(struct drm_device *dev)
355 {
356 struct nv50_display *disp = nv50_display(dev);
357
358 NV_DEBUG_KMS(dev, "\n");
359
360 nv50_display_disable(dev);
361 nouveau_irq_unregister(dev, 26);
362 kfree(disp);
363 }
364
365 void
366 nv50_display_flip_stop(struct drm_crtc *crtc)
367 {
368 struct nv50_display *disp = nv50_display(crtc->dev);
369 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
370 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
371 struct nouveau_channel *evo = dispc->sync;
372 int ret;
373
374 ret = RING_SPACE(evo, 8);
375 if (ret) {
376 WARN_ON(1);
377 return;
378 }
379
380 BEGIN_RING(evo, 0, 0x0084, 1);
381 OUT_RING (evo, 0x00000000);
382 BEGIN_RING(evo, 0, 0x0094, 1);
383 OUT_RING (evo, 0x00000000);
384 BEGIN_RING(evo, 0, 0x00c0, 1);
385 OUT_RING (evo, 0x00000000);
386 BEGIN_RING(evo, 0, 0x0080, 1);
387 OUT_RING (evo, 0x00000000);
388 FIRE_RING (evo);
389 }
390
391 int
392 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
393 struct nouveau_channel *chan)
394 {
395 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
396 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
397 struct nv50_display *disp = nv50_display(crtc->dev);
398 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
399 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
400 struct nouveau_channel *evo = dispc->sync;
401 int ret;
402
403 ret = RING_SPACE(evo, chan ? 25 : 27);
404 if (unlikely(ret))
405 return ret;
406
407 /* synchronise with the rendering channel, if necessary */
408 if (likely(chan)) {
409 ret = RING_SPACE(chan, 10);
410 if (ret) {
411 WIND_RING(evo);
412 return ret;
413 }
414
415 if (dev_priv->chipset < 0xc0) {
416 BEGIN_RING(chan, NvSubSw, 0x0060, 2);
417 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
418 OUT_RING (chan, dispc->sem.offset);
419 BEGIN_RING(chan, NvSubSw, 0x006c, 1);
420 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
421 BEGIN_RING(chan, NvSubSw, 0x0064, 2);
422 OUT_RING (chan, dispc->sem.offset ^ 0x10);
423 OUT_RING (chan, 0x74b1e000);
424 BEGIN_RING(chan, NvSubSw, 0x0060, 1);
425 if (dev_priv->chipset < 0x84)
426 OUT_RING (chan, NvSema);
427 else
428 OUT_RING (chan, chan->vram_handle);
429 } else {
430 u64 offset = chan->dispc_vma[nv_crtc->index].offset;
431 offset += dispc->sem.offset;
432 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
433 OUT_RING (chan, upper_32_bits(offset));
434 OUT_RING (chan, lower_32_bits(offset));
435 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
436 OUT_RING (chan, 0x1002);
437 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
438 OUT_RING (chan, upper_32_bits(offset));
439 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
440 OUT_RING (chan, 0x74b1e000);
441 OUT_RING (chan, 0x1001);
442 }
443 FIRE_RING (chan);
444 } else {
445 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
446 0xf00d0000 | dispc->sem.value);
447 }
448
449 /* queue the flip on the crtc's "display sync" channel */
450 BEGIN_RING(evo, 0, 0x0100, 1);
451 OUT_RING (evo, 0xfffe0000);
452 if (chan) {
453 BEGIN_RING(evo, 0, 0x0084, 1);
454 OUT_RING (evo, 0x00000100);
455 } else {
456 BEGIN_RING(evo, 0, 0x0084, 1);
457 OUT_RING (evo, 0x00000010);
458 /* allows gamma somehow, PDISP will bitch at you if
459 * you don't wait for vblank before changing this..
460 */
461 BEGIN_RING(evo, 0, 0x00e0, 1);
462 OUT_RING (evo, 0x40000000);
463 }
464 BEGIN_RING(evo, 0, 0x0088, 4);
465 OUT_RING (evo, dispc->sem.offset);
466 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
467 OUT_RING (evo, 0x74b1e000);
468 OUT_RING (evo, NvEvoSync);
469 BEGIN_RING(evo, 0, 0x00a0, 2);
470 OUT_RING (evo, 0x00000000);
471 OUT_RING (evo, 0x00000000);
472 BEGIN_RING(evo, 0, 0x00c0, 1);
473 OUT_RING (evo, nv_fb->r_dma);
474 BEGIN_RING(evo, 0, 0x0110, 2);
475 OUT_RING (evo, 0x00000000);
476 OUT_RING (evo, 0x00000000);
477 BEGIN_RING(evo, 0, 0x0800, 5);
478 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8);
479 OUT_RING (evo, 0);
480 OUT_RING (evo, (fb->height << 16) | fb->width);
481 OUT_RING (evo, nv_fb->r_pitch);
482 OUT_RING (evo, nv_fb->r_format);
483 BEGIN_RING(evo, 0, 0x0080, 1);
484 OUT_RING (evo, 0x00000000);
485 FIRE_RING (evo);
486
487 dispc->sem.offset ^= 0x10;
488 dispc->sem.value++;
489 return 0;
490 }
491
492 static u16
493 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
494 u32 mc, int pxclk)
495 {
496 struct drm_nouveau_private *dev_priv = dev->dev_private;
497 struct nouveau_connector *nv_connector = NULL;
498 struct drm_encoder *encoder;
499 struct nvbios *bios = &dev_priv->vbios;
500 u32 script = 0, or;
501
502 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
503 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
504
505 if (nv_encoder->dcb != dcb)
506 continue;
507
508 nv_connector = nouveau_encoder_connector_get(nv_encoder);
509 break;
510 }
511
512 or = ffs(dcb->or) - 1;
513 switch (dcb->type) {
514 case OUTPUT_LVDS:
515 script = (mc >> 8) & 0xf;
516 if (bios->fp_no_ddc) {
517 if (bios->fp.dual_link)
518 script |= 0x0100;
519 if (bios->fp.if_is_24bit)
520 script |= 0x0200;
521 } else {
522 /* determine number of lvds links */
523 if (nv_connector && nv_connector->edid &&
524 nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG) {
525 /* http://www.spwg.org */
526 if (((u8 *)nv_connector->edid)[121] == 2)
527 script |= 0x0100;
528 } else
529 if (pxclk >= bios->fp.duallink_transition_clk) {
530 script |= 0x0100;
531 }
532
533 /* determine panel depth */
534 if (script & 0x0100) {
535 if (bios->fp.strapless_is_24bit & 2)
536 script |= 0x0200;
537 } else {
538 if (bios->fp.strapless_is_24bit & 1)
539 script |= 0x0200;
540 }
541
542 if (nv_connector && nv_connector->edid &&
543 (nv_connector->edid->revision >= 4) &&
544 (nv_connector->edid->input & 0x70) >= 0x20)
545 script |= 0x0200;
546 }
547
548 if (nouveau_uscript_lvds >= 0) {
549 NV_INFO(dev, "override script 0x%04x with 0x%04x "
550 "for output LVDS-%d\n", script,
551 nouveau_uscript_lvds, or);
552 script = nouveau_uscript_lvds;
553 }
554 break;
555 case OUTPUT_TMDS:
556 script = (mc >> 8) & 0xf;
557 if (pxclk >= 165000)
558 script |= 0x0100;
559
560 if (nouveau_uscript_tmds >= 0) {
561 NV_INFO(dev, "override script 0x%04x with 0x%04x "
562 "for output TMDS-%d\n", script,
563 nouveau_uscript_tmds, or);
564 script = nouveau_uscript_tmds;
565 }
566 break;
567 case OUTPUT_DP:
568 script = (mc >> 8) & 0xf;
569 break;
570 case OUTPUT_ANALOG:
571 script = 0xff;
572 break;
573 default:
574 NV_ERROR(dev, "modeset on unsupported output type!\n");
575 break;
576 }
577
578 return script;
579 }
580
581 static void
582 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
583 {
584 struct drm_nouveau_private *dev_priv = dev->dev_private;
585 struct nouveau_channel *chan, *tmp;
586
587 list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
588 nvsw.vbl_wait) {
589 if (chan->nvsw.vblsem_head != crtc)
590 continue;
591
592 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
593 chan->nvsw.vblsem_rval);
594 list_del(&chan->nvsw.vbl_wait);
595 drm_vblank_put(dev, crtc);
596 }
597
598 drm_handle_vblank(dev, crtc);
599 }
600
601 static void
602 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
603 {
604 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
605 nv50_display_vblank_crtc_handler(dev, 0);
606
607 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
608 nv50_display_vblank_crtc_handler(dev, 1);
609
610 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
611 }
612
613 static void
614 nv50_display_unk10_handler(struct drm_device *dev)
615 {
616 struct drm_nouveau_private *dev_priv = dev->dev_private;
617 struct nv50_display *disp = nv50_display(dev);
618 u32 unk30 = nv_rd32(dev, 0x610030), mc;
619 int i, crtc, or, type = OUTPUT_ANY;
620
621 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
622 disp->irq.dcb = NULL;
623
624 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
625
626 /* Determine which CRTC we're dealing with, only 1 ever will be
627 * signalled at the same time with the current nouveau code.
628 */
629 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
630 if (crtc < 0)
631 goto ack;
632
633 /* Nothing needs to be done for the encoder */
634 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
635 if (crtc < 0)
636 goto ack;
637
638 /* Find which encoder was connected to the CRTC */
639 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
640 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
641 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
642 if (!(mc & (1 << crtc)))
643 continue;
644
645 switch ((mc & 0x00000f00) >> 8) {
646 case 0: type = OUTPUT_ANALOG; break;
647 case 1: type = OUTPUT_TV; break;
648 default:
649 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
650 goto ack;
651 }
652
653 or = i;
654 }
655
656 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
657 if (dev_priv->chipset < 0x90 ||
658 dev_priv->chipset == 0x92 ||
659 dev_priv->chipset == 0xa0)
660 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
661 else
662 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
663
664 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
665 if (!(mc & (1 << crtc)))
666 continue;
667
668 switch ((mc & 0x00000f00) >> 8) {
669 case 0: type = OUTPUT_LVDS; break;
670 case 1: type = OUTPUT_TMDS; break;
671 case 2: type = OUTPUT_TMDS; break;
672 case 5: type = OUTPUT_TMDS; break;
673 case 8: type = OUTPUT_DP; break;
674 case 9: type = OUTPUT_DP; break;
675 default:
676 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
677 goto ack;
678 }
679
680 or = i;
681 }
682
683 /* There was no encoder to disable */
684 if (type == OUTPUT_ANY)
685 goto ack;
686
687 /* Disable the encoder */
688 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
689 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
690
691 if (dcb->type == type && (dcb->or & (1 << or))) {
692 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
693 disp->irq.dcb = dcb;
694 goto ack;
695 }
696 }
697
698 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
699 ack:
700 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
701 nv_wr32(dev, 0x610030, 0x80000000);
702 }
703
704 static void
705 nv50_display_unk20_handler(struct drm_device *dev)
706 {
707 struct drm_nouveau_private *dev_priv = dev->dev_private;
708 struct nv50_display *disp = nv50_display(dev);
709 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
710 struct dcb_entry *dcb;
711 int i, crtc, or, type = OUTPUT_ANY;
712
713 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
714 dcb = disp->irq.dcb;
715 if (dcb) {
716 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
717 disp->irq.dcb = NULL;
718 }
719
720 /* CRTC clock change requested? */
721 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
722 if (crtc >= 0) {
723 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
724 pclk &= 0x003fffff;
725
726 nv50_crtc_set_clock(dev, crtc, pclk);
727
728 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
729 tmp &= ~0x000000f;
730 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
731 }
732
733 /* Nothing needs to be done for the encoder */
734 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
735 if (crtc < 0)
736 goto ack;
737 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
738
739 /* Find which encoder is connected to the CRTC */
740 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
741 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
742 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
743 if (!(mc & (1 << crtc)))
744 continue;
745
746 switch ((mc & 0x00000f00) >> 8) {
747 case 0: type = OUTPUT_ANALOG; break;
748 case 1: type = OUTPUT_TV; break;
749 default:
750 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
751 goto ack;
752 }
753
754 or = i;
755 }
756
757 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
758 if (dev_priv->chipset < 0x90 ||
759 dev_priv->chipset == 0x92 ||
760 dev_priv->chipset == 0xa0)
761 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
762 else
763 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
764
765 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
766 if (!(mc & (1 << crtc)))
767 continue;
768
769 switch ((mc & 0x00000f00) >> 8) {
770 case 0: type = OUTPUT_LVDS; break;
771 case 1: type = OUTPUT_TMDS; break;
772 case 2: type = OUTPUT_TMDS; break;
773 case 5: type = OUTPUT_TMDS; break;
774 case 8: type = OUTPUT_DP; break;
775 case 9: type = OUTPUT_DP; break;
776 default:
777 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
778 goto ack;
779 }
780
781 or = i;
782 }
783
784 if (type == OUTPUT_ANY)
785 goto ack;
786
787 /* Enable the encoder */
788 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
789 dcb = &dev_priv->vbios.dcb.entry[i];
790 if (dcb->type == type && (dcb->or & (1 << or)))
791 break;
792 }
793
794 if (i == dev_priv->vbios.dcb.entries) {
795 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
796 goto ack;
797 }
798
799 script = nv50_display_script_select(dev, dcb, mc, pclk);
800 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
801
802 if (type == OUTPUT_DP) {
803 int link = !(dcb->dpconf.sor.link & 1);
804 if ((mc & 0x000f0000) == 0x00020000)
805 nouveau_dp_tu_update(dev, or, link, pclk, 18);
806 else
807 nouveau_dp_tu_update(dev, or, link, pclk, 24);
808 }
809
810 if (dcb->type != OUTPUT_ANALOG) {
811 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
812 tmp &= ~0x00000f0f;
813 if (script & 0x0100)
814 tmp |= 0x00000101;
815 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
816 } else {
817 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
818 }
819
820 disp->irq.dcb = dcb;
821 disp->irq.pclk = pclk;
822 disp->irq.script = script;
823
824 ack:
825 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
826 nv_wr32(dev, 0x610030, 0x80000000);
827 }
828
829 /* If programming a TMDS output on a SOR that can also be configured for
830 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
831 *
832 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
833 * the VBIOS scripts on at least one board I have only switch it off on
834 * link 0, causing a blank display if the output has previously been
835 * programmed for DisplayPort.
836 */
837 static void
838 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
839 {
840 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
841 struct drm_encoder *encoder;
842 u32 tmp;
843
844 if (dcb->type != OUTPUT_TMDS)
845 return;
846
847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
848 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
849
850 if (nv_encoder->dcb->type == OUTPUT_DP &&
851 nv_encoder->dcb->or & (1 << or)) {
852 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
853 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
854 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
855 break;
856 }
857 }
858 }
859
860 static void
861 nv50_display_unk40_handler(struct drm_device *dev)
862 {
863 struct nv50_display *disp = nv50_display(dev);
864 struct dcb_entry *dcb = disp->irq.dcb;
865 u16 script = disp->irq.script;
866 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
867
868 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
869 disp->irq.dcb = NULL;
870 if (!dcb)
871 goto ack;
872
873 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
874 nv50_display_unk40_dp_set_tmds(dev, dcb);
875
876 ack:
877 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
878 nv_wr32(dev, 0x610030, 0x80000000);
879 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
880 }
881
882 static void
883 nv50_display_bh(unsigned long data)
884 {
885 struct drm_device *dev = (struct drm_device *)data;
886
887 for (;;) {
888 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
889 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
890
891 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
892
893 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
894 nv50_display_unk10_handler(dev);
895 else
896 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
897 nv50_display_unk20_handler(dev);
898 else
899 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
900 nv50_display_unk40_handler(dev);
901 else
902 break;
903 }
904
905 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
906 }
907
908 static void
909 nv50_display_error_handler(struct drm_device *dev)
910 {
911 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
912 u32 addr, data;
913 int chid;
914
915 for (chid = 0; chid < 5; chid++) {
916 if (!(channels & (1 << chid)))
917 continue;
918
919 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
920 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
921 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
922 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
923 "(0x%04x 0x%02x)\n", chid,
924 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
925
926 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
927 }
928 }
929
930 static void
931 nv50_display_isr(struct drm_device *dev)
932 {
933 struct nv50_display *disp = nv50_display(dev);
934 uint32_t delayed = 0;
935
936 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
937 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
938 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
939 uint32_t clock;
940
941 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
942
943 if (!intr0 && !(intr1 & ~delayed))
944 break;
945
946 if (intr0 & 0x001f0000) {
947 nv50_display_error_handler(dev);
948 intr0 &= ~0x001f0000;
949 }
950
951 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
952 nv50_display_vblank_handler(dev, intr1);
953 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
954 }
955
956 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
957 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
958 NV50_PDISPLAY_INTR_1_CLK_UNK40));
959 if (clock) {
960 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
961 tasklet_schedule(&disp->tasklet);
962 delayed |= clock;
963 intr1 &= ~clock;
964 }
965
966 if (intr0) {
967 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
968 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
969 }
970
971 if (intr1) {
972 NV_ERROR(dev,
973 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
974 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
975 }
976 }
977 }
Linux with added FPC-III support