drivers/gpu/drm/nouveau/nvc0_pm.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_bios.h"
  28 #include "nouveau_pm.h"
  29
  30 static u32 read_div(struct drm_device *, int, u32, u32);
  31 static u32 read_pll(struct drm_device *, u32);
  32
  33 static u32
  34 read_vco(struct drm_device *dev, u32 dsrc)
  35 {
  36         u32 ssrc = nv_rd32(dev, dsrc);
  37         if (!(ssrc & 0x00000100))
  38                 return read_pll(dev, 0x00e800);
  39         return read_pll(dev, 0x00e820);
  40 }
  41
  42 static u32
  43 read_pll(struct drm_device *dev, u32 pll)
  44 {
  45         u32 ctrl = nv_rd32(dev, pll + 0);
  46         u32 coef = nv_rd32(dev, pll + 4);
  47         u32 P = (coef & 0x003f0000) >> 16;
  48         u32 N = (coef & 0x0000ff00) >> 8;
  49         u32 M = (coef & 0x000000ff) >> 0;
  50         u32 sclk, doff;
  51
  52         if (!(ctrl & 0x00000001))
  53                 return 0;
  54
  55         switch (pll & 0xfff000) {
  56         case 0x00e000:
  57                 sclk = 27000;
  58                 P = 1;
  59                 break;
  60         case 0x137000:
  61                 doff = (pll - 0x137000) / 0x20;
  62                 sclk = read_div(dev, doff, 0x137120, 0x137140);
  63                 break;
  64         case 0x132000:
  65                 switch (pll) {
  66                 case 0x132000:
  67                         sclk = read_pll(dev, 0x132020);
  68                         break;
  69                 case 0x132020:
  70                         sclk = read_div(dev, 0, 0x137320, 0x137330);
  71                         break;
  72                 default:
  73                         return 0;
  74                 }
  75                 break;
  76         default:
  77                 return 0;
  78         }
  79
  80         return sclk * N / M / P;
  81 }
  82
  83 static u32
  84 read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
  85 {
  86         u32 ssrc = nv_rd32(dev, dsrc + (doff * 4));
  87         u32 sctl = nv_rd32(dev, dctl + (doff * 4));
  88
  89         switch (ssrc & 0x00000003) {
  90         case 0:
  91                 if ((ssrc & 0x00030000) != 0x00030000)
  92                         return 27000;
  93                 return 108000;
  94         case 2:
  95                 return 100000;
  96         case 3:
  97                 if (sctl & 0x80000000) {
  98                         u32 sclk = read_vco(dev, dsrc + (doff * 4));
  99                         u32 sdiv = (sctl & 0x0000003f) + 2;
 100                         return (sclk * 2) / sdiv;
 101                 }
 102
 103                 return read_vco(dev, dsrc + (doff * 4));
 104         default:
 105                 return 0;
 106         }
 107 }
 108
 109 static u32
 110 read_mem(struct drm_device *dev)
 111 {
 112         u32 ssel = nv_rd32(dev, 0x1373f0);
 113         if (ssel & 0x00000001)
 114                 return read_div(dev, 0, 0x137300, 0x137310);
 115         return read_pll(dev, 0x132000);
 116 }
 117
 118 static u32
 119 read_clk(struct drm_device *dev, int clk)
 120 {
 121         u32 sctl = nv_rd32(dev, 0x137250 + (clk * 4));
 122         u32 ssel = nv_rd32(dev, 0x137100);
 123         u32 sclk, sdiv;
 124
 125         if (ssel & (1 << clk)) {
 126                 if (clk < 7)
 127                         sclk = read_pll(dev, 0x137000 + (clk * 0x20));
 128                 else
 129                         sclk = read_pll(dev, 0x1370e0);
 130                 sdiv = ((sctl & 0x00003f00) >> 8) + 2;
 131         } else {
 132                 sclk = read_div(dev, clk, 0x137160, 0x1371d0);
 133                 sdiv = ((sctl & 0x0000003f) >> 0) + 2;
 134         }
 135
 136         if (sctl & 0x80000000)
 137                 return (sclk * 2) / sdiv;
 138         return sclk;
 139 }
 140
 141 int
 142 nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
 143 {
 144         perflvl->shader = read_clk(dev, 0x00);
 145         perflvl->core   = perflvl->shader / 2;
 146         perflvl->memory = read_mem(dev);
 147         perflvl->rop    = read_clk(dev, 0x01);
 148         perflvl->hub07  = read_clk(dev, 0x02);
 149         perflvl->hub06  = read_clk(dev, 0x07);
 150         perflvl->hub01  = read_clk(dev, 0x08);
 151         perflvl->copy   = read_clk(dev, 0x09);
 152         perflvl->daemon = read_clk(dev, 0x0c);
 153         perflvl->vdec   = read_clk(dev, 0x0e);
 154         return 0;
 155 }