drivers/net/ethernet/ti/tlan.h

   1 #ifndef TLAN_H
   2 #define TLAN_H
   3 /********************************************************************
   4  *
   5  *  Linux ThunderLAN Driver
   6  *
   7  *  tlan.h
   8  *  by James Banks
   9  *
  10  *  (C) 1997-1998 Caldera, Inc.
  11  *  (C) 1999-2001 Torben Mathiasen
  12  *
  13  *  This software may be used and distributed according to the terms
  14  *  of the GNU General Public License, incorporated herein by reference.
  15  *
  16  *
  17  *  Dec 10, 1999        Torben Mathiasen <torben.mathiasen@compaq.com>
  18  *                      New Maintainer
  19  *
  20  ********************************************************************/
  21
  22
  23 #include <linux/io.h>
  24 #include <linux/types.h>
  25 #include <linux/netdevice.h>
  26
  27
  28
  29         /*****************************************************************
  30          * TLan Definitions
  31          *
  32          ****************************************************************/
  33
  34 #define TLAN_MIN_FRAME_SIZE     64
  35 #define TLAN_MAX_FRAME_SIZE     1600
  36
  37 #define TLAN_NUM_RX_LISTS       32
  38 #define TLAN_NUM_TX_LISTS       64
  39
  40 #define TLAN_IGNORE             0
  41 #define TLAN_RECORD             1
  42
  43 #define TLAN_DBG(lvl, format, args...)                                  \
  44         do {                                                            \
  45                 if (debug&lvl)                                          \
  46                         printk(KERN_DEBUG "TLAN: " format, ##args);     \
  47         } while (0)
  48
  49 #define TLAN_DEBUG_GNRL         0x0001
  50 #define TLAN_DEBUG_TX           0x0002
  51 #define TLAN_DEBUG_RX           0x0004
  52 #define TLAN_DEBUG_LIST         0x0008
  53 #define TLAN_DEBUG_PROBE        0x0010
  54
  55 #define TX_TIMEOUT              (10*HZ)  /* We need time for auto-neg */
  56 #define MAX_TLAN_BOARDS         8        /* Max number of boards installed
  57                                             at a time */
  58
  59
  60         /*****************************************************************
  61          * Device Identification Definitions
  62          *
  63          ****************************************************************/
  64
  65 #define PCI_DEVICE_ID_NETELLIGENT_10_T2                 0xB012
  66 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100        0xB030
  67 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
  68 #define PCI_DEVICE_ID_OLICOM_OC2183                     0x0013
  69 #endif
  70 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
  71 #define PCI_DEVICE_ID_OLICOM_OC2325                     0x0012
  72 #endif
  73 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
  74 #define PCI_DEVICE_ID_OLICOM_OC2326                     0x0014
  75 #endif
  76
  77 struct tlan_adapter_entry {
  78         u16     vendor_id;
  79         u16     device_id;
  80         char    *device_label;
  81         u32     flags;
  82         u16     addr_ofs;
  83 };
  84
  85 #define TLAN_ADAPTER_NONE               0x00000000
  86 #define TLAN_ADAPTER_UNMANAGED_PHY      0x00000001
  87 #define TLAN_ADAPTER_BIT_RATE_PHY       0x00000002
  88 #define TLAN_ADAPTER_USE_INTERN_10      0x00000004
  89 #define TLAN_ADAPTER_ACTIVITY_LED       0x00000008
  90
  91 #define TLAN_SPEED_DEFAULT      0
  92 #define TLAN_SPEED_10           10
  93 #define TLAN_SPEED_100          100
  94
  95 #define TLAN_DUPLEX_DEFAULT     0
  96 #define TLAN_DUPLEX_HALF        1
  97 #define TLAN_DUPLEX_FULL        2
  98
  99
 100
 101         /*****************************************************************
 102          * EISA Definitions
 103          *
 104          ****************************************************************/
 105
 106 #define EISA_ID      0xc80   /* EISA ID Registers */
 107 #define EISA_ID0     0xc80   /* EISA ID Register 0 */
 108 #define EISA_ID1     0xc81   /* EISA ID Register 1 */
 109 #define EISA_ID2     0xc82   /* EISA ID Register 2 */
 110 #define EISA_ID3     0xc83   /* EISA ID Register 3 */
 111 #define EISA_CR      0xc84   /* EISA Control Register */
 112 #define EISA_REG0    0xc88   /* EISA Configuration Register 0 */
 113 #define EISA_REG1    0xc89   /* EISA Configuration Register 1 */
 114 #define EISA_REG2    0xc8a   /* EISA Configuration Register 2 */
 115 #define EISA_REG3    0xc8f   /* EISA Configuration Register 3 */
 116 #define EISA_APROM   0xc90   /* Ethernet Address PROM */
 117
 118
 119
 120         /*****************************************************************
 121          * Rx/Tx List Definitions
 122          *
 123          ****************************************************************/
 124
 125 #define TLAN_BUFFERS_PER_LIST   10
 126 #define TLAN_LAST_BUFFER        0x80000000
 127 #define TLAN_CSTAT_UNUSED       0x8000
 128 #define TLAN_CSTAT_FRM_CMP      0x4000
 129 #define TLAN_CSTAT_READY        0x3000
 130 #define TLAN_CSTAT_EOC          0x0800
 131 #define TLAN_CSTAT_RX_ERROR     0x0400
 132 #define TLAN_CSTAT_PASS_CRC     0x0200
 133 #define TLAN_CSTAT_DP_PR        0x0100
 134
 135
 136 struct tlan_buffer {
 137         u32     count;
 138         u32     address;
 139 };
 140
 141
 142 struct tlan_list {
 143         u32             forward;
 144         u16             c_stat;
 145         u16             frame_size;
 146         struct tlan_buffer buffer[TLAN_BUFFERS_PER_LIST];
 147 };
 148
 149
 150 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
 151
 152
 153
 154
 155         /*****************************************************************
 156          * PHY definitions
 157          *
 158          ****************************************************************/
 159
 160 #define TLAN_PHY_MAX_ADDR       0x1F
 161 #define TLAN_PHY_NONE           0x20
 162
 163
 164
 165
 166         /*****************************************************************
 167          * TLAN Private Information Structure
 168          *
 169          ****************************************************************/
 170
 171 struct tlan_priv {
 172         struct net_device       *next_device;
 173         struct pci_dev          *pci_dev;
 174         struct net_device       *dev;
 175         void                    *dma_storage;
 176         dma_addr_t              dma_storage_dma;
 177         unsigned int            dma_size;
 178         u8                      *pad_buffer;
 179         struct tlan_list        *rx_list;
 180         dma_addr_t              rx_list_dma;
 181         u8                      *rx_buffer;
 182         dma_addr_t              rx_buffer_dma;
 183         u32                     rx_head;
 184         u32                     rx_tail;
 185         u32                     rx_eoc_count;
 186         struct tlan_list        *tx_list;
 187         dma_addr_t              tx_list_dma;
 188         u8                      *tx_buffer;
 189         dma_addr_t              tx_buffer_dma;
 190         u32                     tx_head;
 191         u32                     tx_in_progress;
 192         u32                     tx_tail;
 193         u32                     tx_busy_count;
 194         u32                     phy_online;
 195         u32                     timer_set_at;
 196         u32                     timer_type;
 197         struct timer_list       timer;
 198         struct board            *adapter;
 199         u32                     adapter_rev;
 200         u32                     aui;
 201         u32                     debug;
 202         u32                     duplex;
 203         u32                     phy[2];
 204         u32                     phy_num;
 205         u32                     speed;
 206         u8                      tlan_rev;
 207         u8                      tlan_full_duplex;
 208         spinlock_t              lock;
 209         u8                      link;
 210         u8                      is_eisa;
 211         struct work_struct                      tlan_tqueue;
 212         u8                      neg_be_verbose;
 213 };
 214
 215
 216
 217
 218         /*****************************************************************
 219          * TLan Driver Timer Definitions
 220          *
 221          ****************************************************************/
 222
 223 #define TLAN_TIMER_LINK_BEAT            1
 224 #define TLAN_TIMER_ACTIVITY             2
 225 #define TLAN_TIMER_PHY_PDOWN            3
 226 #define TLAN_TIMER_PHY_PUP              4
 227 #define TLAN_TIMER_PHY_RESET            5
 228 #define TLAN_TIMER_PHY_START_LINK       6
 229 #define TLAN_TIMER_PHY_FINISH_AN        7
 230 #define TLAN_TIMER_FINISH_RESET         8
 231
 232 #define TLAN_TIMER_ACT_DELAY            (HZ/10)
 233
 234
 235
 236
 237         /*****************************************************************
 238          * TLan Driver Eeprom Definitions
 239          *
 240          ****************************************************************/
 241
 242 #define TLAN_EEPROM_ACK         0
 243 #define TLAN_EEPROM_STOP        1
 244
 245
 246
 247
 248         /*****************************************************************
 249          * Host Register Offsets and Contents
 250          *
 251          ****************************************************************/
 252
 253 #define TLAN_HOST_CMD                   0x00
 254 #define TLAN_HC_GO              0x80000000
 255 #define         TLAN_HC_STOP            0x40000000
 256 #define         TLAN_HC_ACK             0x20000000
 257 #define         TLAN_HC_CS_MASK         0x1FE00000
 258 #define         TLAN_HC_EOC             0x00100000
 259 #define         TLAN_HC_RT              0x00080000
 260 #define         TLAN_HC_NES             0x00040000
 261 #define         TLAN_HC_AD_RST          0x00008000
 262 #define         TLAN_HC_LD_TMR          0x00004000
 263 #define         TLAN_HC_LD_THR          0x00002000
 264 #define         TLAN_HC_REQ_INT         0x00001000
 265 #define         TLAN_HC_INT_OFF         0x00000800
 266 #define         TLAN_HC_INT_ON          0x00000400
 267 #define         TLAN_HC_AC_MASK         0x000000FF
 268 #define TLAN_CH_PARM                    0x04
 269 #define TLAN_DIO_ADR                    0x08
 270 #define         TLAN_DA_ADR_INC         0x8000
 271 #define         TLAN_DA_RAM_ADR         0x4000
 272 #define TLAN_HOST_INT                   0x0A
 273 #define         TLAN_HI_IV_MASK         0x1FE0
 274 #define         TLAN_HI_IT_MASK         0x001C
 275 #define TLAN_DIO_DATA                   0x0C
 276
 277
 278 /* ThunderLAN Internal Register DIO Offsets */
 279
 280 #define TLAN_NET_CMD                    0x00
 281 #define         TLAN_NET_CMD_NRESET     0x80
 282 #define         TLAN_NET_CMD_NWRAP      0x40
 283 #define         TLAN_NET_CMD_CSF        0x20
 284 #define         TLAN_NET_CMD_CAF        0x10
 285 #define         TLAN_NET_CMD_NOBRX      0x08
 286 #define         TLAN_NET_CMD_DUPLEX     0x04
 287 #define         TLAN_NET_CMD_TRFRAM     0x02
 288 #define         TLAN_NET_CMD_TXPACE     0x01
 289 #define TLAN_NET_SIO                    0x01
 290 #define TLAN_NET_SIO_MINTEN     0x80
 291 #define         TLAN_NET_SIO_ECLOK      0x40
 292 #define         TLAN_NET_SIO_ETXEN      0x20
 293 #define         TLAN_NET_SIO_EDATA      0x10
 294 #define         TLAN_NET_SIO_NMRST      0x08
 295 #define         TLAN_NET_SIO_MCLK       0x04
 296 #define         TLAN_NET_SIO_MTXEN      0x02
 297 #define         TLAN_NET_SIO_MDATA      0x01
 298 #define TLAN_NET_STS                    0x02
 299 #define         TLAN_NET_STS_MIRQ       0x80
 300 #define         TLAN_NET_STS_HBEAT      0x40
 301 #define         TLAN_NET_STS_TXSTOP     0x20
 302 #define         TLAN_NET_STS_RXSTOP     0x10
 303 #define         TLAN_NET_STS_RSRVD      0x0F
 304 #define TLAN_NET_MASK                   0x03
 305 #define         TLAN_NET_MASK_MASK7     0x80
 306 #define         TLAN_NET_MASK_MASK6     0x40
 307 #define         TLAN_NET_MASK_MASK5     0x20
 308 #define         TLAN_NET_MASK_MASK4     0x10
 309 #define         TLAN_NET_MASK_RSRVD     0x0F
 310 #define TLAN_NET_CONFIG                 0x04
 311 #define TLAN_NET_CFG_RCLK       0x8000
 312 #define         TLAN_NET_CFG_TCLK       0x4000
 313 #define         TLAN_NET_CFG_BIT        0x2000
 314 #define         TLAN_NET_CFG_RXCRC      0x1000
 315 #define         TLAN_NET_CFG_PEF        0x0800
 316 #define         TLAN_NET_CFG_1FRAG      0x0400
 317 #define         TLAN_NET_CFG_1CHAN      0x0200
 318 #define         TLAN_NET_CFG_MTEST      0x0100
 319 #define         TLAN_NET_CFG_PHY_EN     0x0080
 320 #define         TLAN_NET_CFG_MSMASK     0x007F
 321 #define TLAN_MAN_TEST                   0x06
 322 #define TLAN_DEF_VENDOR_ID              0x08
 323 #define TLAN_DEF_DEVICE_ID              0x0A
 324 #define TLAN_DEF_REVISION               0x0C
 325 #define TLAN_DEF_SUBCLASS               0x0D
 326 #define TLAN_DEF_MIN_LAT                0x0E
 327 #define TLAN_DEF_MAX_LAT                0x0F
 328 #define TLAN_AREG_0                     0x10
 329 #define TLAN_AREG_1                     0x16
 330 #define TLAN_AREG_2                     0x1C
 331 #define TLAN_AREG_3                     0x22
 332 #define TLAN_HASH_1                     0x28
 333 #define TLAN_HASH_2                     0x2C
 334 #define TLAN_GOOD_TX_FRMS               0x30
 335 #define TLAN_TX_UNDERUNS                0x33
 336 #define TLAN_GOOD_RX_FRMS               0x34
 337 #define TLAN_RX_OVERRUNS                0x37
 338 #define TLAN_DEFERRED_TX                0x38
 339 #define TLAN_CRC_ERRORS                 0x3A
 340 #define TLAN_CODE_ERRORS                0x3B
 341 #define TLAN_MULTICOL_FRMS              0x3C
 342 #define TLAN_SINGLECOL_FRMS             0x3E
 343 #define TLAN_EXCESSCOL_FRMS             0x40
 344 #define TLAN_LATE_COLS                  0x41
 345 #define TLAN_CARRIER_LOSS               0x42
 346 #define TLAN_ACOMMIT                    0x43
 347 #define TLAN_LED_REG                    0x44
 348 #define         TLAN_LED_ACT            0x10
 349 #define         TLAN_LED_LINK           0x01
 350 #define TLAN_BSIZE_REG                  0x45
 351 #define TLAN_MAX_RX                     0x46
 352 #define TLAN_INT_DIS                    0x48
 353 #define         TLAN_ID_TX_EOC          0x04
 354 #define         TLAN_ID_RX_EOF          0x02
 355 #define         TLAN_ID_RX_EOC          0x01
 356
 357
 358
 359 /* ThunderLAN Interrupt Codes */
 360
 361 #define TLAN_INT_NUMBER_OF_INTS 8
 362
 363 #define TLAN_INT_NONE                   0x0000
 364 #define TLAN_INT_TX_EOF                 0x0001
 365 #define TLAN_INT_STAT_OVERFLOW          0x0002
 366 #define TLAN_INT_RX_EOF                 0x0003
 367 #define TLAN_INT_DUMMY                  0x0004
 368 #define TLAN_INT_TX_EOC                 0x0005
 369 #define TLAN_INT_STATUS_CHECK           0x0006
 370 #define TLAN_INT_RX_EOC                 0x0007
 371
 372
 373
 374 /* ThunderLAN MII Registers */
 375
 376 /* Generic MII/PHY Registers */
 377
 378 #define MII_GEN_CTL                     0x00
 379 #define MII_GC_RESET            0x8000
 380 #define         MII_GC_LOOPBK           0x4000
 381 #define         MII_GC_SPEEDSEL         0x2000
 382 #define         MII_GC_AUTOENB          0x1000
 383 #define         MII_GC_PDOWN            0x0800
 384 #define         MII_GC_ISOLATE          0x0400
 385 #define         MII_GC_AUTORSRT         0x0200
 386 #define         MII_GC_DUPLEX           0x0100
 387 #define         MII_GC_COLTEST          0x0080
 388 #define         MII_GC_RESERVED         0x007F
 389 #define MII_GEN_STS                     0x01
 390 #define         MII_GS_100BT4           0x8000
 391 #define         MII_GS_100BTXFD         0x4000
 392 #define         MII_GS_100BTXHD         0x2000
 393 #define         MII_GS_10BTFD           0x1000
 394 #define         MII_GS_10BTHD           0x0800
 395 #define         MII_GS_RESERVED         0x07C0
 396 #define         MII_GS_AUTOCMPLT        0x0020
 397 #define         MII_GS_RFLT             0x0010
 398 #define         MII_GS_AUTONEG          0x0008
 399 #define         MII_GS_LINK             0x0004
 400 #define         MII_GS_JABBER           0x0002
 401 #define         MII_GS_EXTCAP           0x0001
 402 #define MII_GEN_ID_HI                   0x02
 403 #define MII_GEN_ID_LO                   0x03
 404 #define MII_GIL_OUI             0xFC00
 405 #define MII_GIL_MODEL           0x03F0
 406 #define MII_GIL_REVISION        0x000F
 407 #define MII_AN_ADV                      0x04
 408 #define MII_AN_LPA                      0x05
 409 #define MII_AN_EXP                      0x06
 410
 411 /* ThunderLAN Specific MII/PHY Registers */
 412
 413 #define TLAN_TLPHY_ID                   0x10
 414 #define TLAN_TLPHY_CTL                  0x11
 415 #define TLAN_TC_IGLINK          0x8000
 416 #define         TLAN_TC_SWAPOL          0x4000
 417 #define         TLAN_TC_AUISEL          0x2000
 418 #define         TLAN_TC_SQEEN           0x1000
 419 #define         TLAN_TC_MTEST           0x0800
 420 #define         TLAN_TC_RESERVED        0x07F8
 421 #define         TLAN_TC_NFEW            0x0004
 422 #define         TLAN_TC_INTEN           0x0002
 423 #define         TLAN_TC_TINT            0x0001
 424 #define TLAN_TLPHY_STS                  0x12
 425 #define         TLAN_TS_MINT            0x8000
 426 #define         TLAN_TS_PHOK            0x4000
 427 #define         TLAN_TS_POLOK           0x2000
 428 #define         TLAN_TS_TPENERGY        0x1000
 429 #define         TLAN_TS_RESERVED        0x0FFF
 430 #define TLAN_TLPHY_PAR                  0x19
 431 #define         TLAN_PHY_CIM_STAT       0x0020
 432 #define         TLAN_PHY_SPEED_100      0x0040
 433 #define         TLAN_PHY_DUPLEX_FULL    0x0080
 434 #define         TLAN_PHY_AN_EN_STAT     0x0400
 435
 436 /* National Sem. & Level1 PHY id's */
 437 #define NAT_SEM_ID1                     0x2000
 438 #define NAT_SEM_ID2                     0x5C01
 439 #define LEVEL1_ID1                      0x7810
 440 #define LEVEL1_ID2                      0x0000
 441
 442 #define CIRC_INC(a, b) if (++a >= b) a = 0
 443
 444 /* Routines to access internal registers. */
 445
 446 static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr)
 447 {
 448         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 449         return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3));
 450
 451 }
 452
 453
 454
 455
 456 static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr)
 457 {
 458         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 459         return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2));
 460
 461 }
 462
 463
 464
 465
 466 static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr)
 467 {
 468         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 469         return inl(base_addr + TLAN_DIO_DATA);
 470
 471 }
 472
 473
 474
 475
 476 static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data)
 477 {
 478         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 479         outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
 480
 481 }
 482
 483
 484
 485
 486 static inline void tlan_dio_write16(u16 base_addr, u16 internal_addr, u16 data)
 487 {
 488         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 489         outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
 490
 491 }
 492
 493
 494
 495
 496 static inline void tlan_dio_write32(u16 base_addr, u16 internal_addr, u32 data)
 497 {
 498         outw(internal_addr, base_addr + TLAN_DIO_ADR);
 499         outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
 500
 501 }
 502
 503 #define tlan_clear_bit(bit, port)       outb_p(inb_p(port) & ~bit, port)
 504 #define tlan_get_bit(bit, port) ((int) (inb_p(port) & bit))
 505 #define tlan_set_bit(bit, port) outb_p(inb_p(port) | bit, port)
 506
 507 /*
 508  * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
 509  * the code below is about seven times as fast as the original code
 510  *
 511  * The original code was:
 512  *
 513  * u32  xor(u32 a, u32 b) {     return ((a && !b ) || (! a && b )); }
 514  *
 515  * #define XOR8(a, b, c, d, e, f, g, h) \
 516  *      xor(a, xor(b, xor(c, xor(d, xor(e, xor(f, xor(g, h)) ) ) ) ) )
 517  * #define DA(a, bit)           (( (u8) a[bit/8] ) & ( (u8) (1 << bit%8)) )
 518  *
 519  *      hash  = XOR8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
 520  *                    DA(a,30), DA(a,36), DA(a,42));
 521  *      hash |= XOR8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25),
 522  *                    DA(a,31), DA(a,37), DA(a,43)) << 1;
 523  *      hash |= XOR8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26),
 524  *                    DA(a,32), DA(a,38), DA(a,44)) << 2;
 525  *      hash |= XOR8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27),
 526  *                    DA(a,33), DA(a,39), DA(a,45)) << 3;
 527  *      hash |= XOR8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28),
 528  *                    DA(a,34), DA(a,40), DA(a,46)) << 4;
 529  *      hash |= XOR8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29),
 530  *                    DA(a,35), DA(a,41), DA(a,47)) << 5;
 531  *
 532  */
 533 static inline u32 tlan_hash_func(const u8 *a)
 534 {
 535         u8     hash;
 536
 537         hash = (a[0]^a[3]);             /* & 077 */
 538         hash ^= ((a[0]^a[3])>>6);       /* & 003 */
 539         hash ^= ((a[1]^a[4])<<2);       /* & 074 */
 540         hash ^= ((a[1]^a[4])>>4);       /* & 017 */
 541         hash ^= ((a[2]^a[5])<<4);       /* & 060 */
 542         hash ^= ((a[2]^a[5])>>2);       /* & 077 */
 543
 544         return hash & 077;
 545 }
 546 #endif