drivers/net/chelsio/mv88x201x.c

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: mv88x201x.c                                                         *
   4  * $Revision: 1.12 $                                                         *
   5  * $Date: 2005/04/15 19:27:14 $                                              *
   6  * Description:                                                              *
   7  *  Marvell PHY (mv88x201x) functionality.                                   *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  17  *                                                                           *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  21  *                                                                           *
  22  * http://www.chelsio.com                                                    *
  23  *                                                                           *
  24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  25  * All rights reserved.                                                      *
  26  *                                                                           *
  27  * Maintainers: maintainers@chelsio.com                                      *
  28  *                                                                           *
  29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  30  *          Tina Yang               <tainay@chelsio.com>                     *
  31  *          Felix Marti             <felix@chelsio.com>                      *
  32  *          Scott Bardone           <sbardone@chelsio.com>                   *
  33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  34  *          Frank DiMambro          <frank@chelsio.com>                      *
  35  *                                                                           *
  36  * History:                                                                  *
  37  *                                                                           *
  38  ****************************************************************************/
  39
  40 #include "cphy.h"
  41 #include "elmer0.h"
  42
  43 /*
  44  * The 88x2010 Rev C. requires some link status registers * to be read
  45  * twice in order to get the right values. Future * revisions will fix
  46  * this problem and then this macro * can disappear.
  47  */
  48 #define MV88x2010_LINK_STATUS_BUGS    1
  49
  50 static int led_init(struct cphy *cphy)
  51 {
  52         /* Setup the LED registers so we can turn on/off.
  53          * Writing these bits maps control to another
  54          * register. mmd(0x1) addr(0x7)
  55          */
  56         mdio_write(cphy, 0x3, 0x8304, 0xdddd);
  57         return 0;
  58 }
  59
  60 static int led_link(struct cphy *cphy, u32 do_enable)
  61 {
  62         u32 led = 0;
  63 #define LINK_ENABLE_BIT 0x1
  64
  65         mdio_read(cphy, 0x1, 0x7, &led);
  66
  67         if (do_enable & LINK_ENABLE_BIT) {
  68                 led |= LINK_ENABLE_BIT;
  69                 mdio_write(cphy, 0x1, 0x7, led);
  70         } else {
  71                 led &= ~LINK_ENABLE_BIT;
  72                 mdio_write(cphy, 0x1, 0x7, led);
  73         }
  74         return 0;
  75 }
  76
  77 /* Port Reset */
  78 static int mv88x201x_reset(struct cphy *cphy, int wait)
  79 {
  80         /* This can be done through registers.  It is not required since
  81          * a full chip reset is used.
  82          */
  83         return 0;
  84 }
  85
  86 static int mv88x201x_interrupt_enable(struct cphy *cphy)
  87 {
  88         u32 elmer;
  89
  90         /* Enable PHY LASI interrupts. */
  91         mdio_write(cphy, 0x1, 0x9002, 0x1);
  92
  93         /* Enable Marvell interrupts through Elmer0. */
  94         t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
  95         elmer |= ELMER0_GP_BIT6;
  96         t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
  97         return 0;
  98 }
  99
 100 static int mv88x201x_interrupt_disable(struct cphy *cphy)
 101 {
 102         u32 elmer;
 103
 104         /* Disable PHY LASI interrupts. */
 105         mdio_write(cphy, 0x1, 0x9002, 0x0);
 106
 107         /* Disable Marvell interrupts through Elmer0. */
 108         t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
 109         elmer &= ~ELMER0_GP_BIT6;
 110         t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
 111         return 0;
 112 }
 113
 114 static int mv88x201x_interrupt_clear(struct cphy *cphy)
 115 {
 116         u32 elmer;
 117         u32 val;
 118
 119 #ifdef MV88x2010_LINK_STATUS_BUGS
 120         /* Required to read twice before clear takes affect. */
 121         mdio_read(cphy, 0x1, 0x9003, &val);
 122         mdio_read(cphy, 0x1, 0x9004, &val);
 123         mdio_read(cphy, 0x1, 0x9005, &val);
 124
 125         /* Read this register after the others above it else
 126          * the register doesn't clear correctly.
 127          */
 128         mdio_read(cphy, 0x1, 0x1, &val);
 129 #endif
 130
 131         /* Clear link status. */
 132         mdio_read(cphy, 0x1, 0x1, &val);
 133         /* Clear PHY LASI interrupts. */
 134         mdio_read(cphy, 0x1, 0x9005, &val);
 135
 136 #ifdef MV88x2010_LINK_STATUS_BUGS
 137         /* Do it again. */
 138         mdio_read(cphy, 0x1, 0x9003, &val);
 139         mdio_read(cphy, 0x1, 0x9004, &val);
 140 #endif
 141
 142         /* Clear Marvell interrupts through Elmer0. */
 143         t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
 144         elmer |= ELMER0_GP_BIT6;
 145         t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
 146         return 0;
 147 }
 148
 149 static int mv88x201x_interrupt_handler(struct cphy *cphy)
 150 {
 151         /* Clear interrupts */
 152         mv88x201x_interrupt_clear(cphy);
 153
 154         /* We have only enabled link change interrupts and so
 155          * cphy_cause must be a link change interrupt.
 156          */
 157         return cphy_cause_link_change;
 158 }
 159
 160 static int mv88x201x_set_loopback(struct cphy *cphy, int on)
 161 {
 162         return 0;
 163 }
 164
 165 static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
 166                                      int *speed, int *duplex, int *fc)
 167 {
 168         u32 val = 0;
 169 #define LINK_STATUS_BIT 0x4
 170
 171         if (link_ok) {
 172                 /* Read link status. */
 173                 mdio_read(cphy, 0x1, 0x1, &val);
 174                 val &= LINK_STATUS_BIT;
 175                 *link_ok = (val == LINK_STATUS_BIT);
 176                 /* Turn on/off Link LED */
 177                 led_link(cphy, *link_ok);
 178         }
 179         if (speed)
 180                 *speed = SPEED_10000;
 181         if (duplex)
 182                 *duplex = DUPLEX_FULL;
 183         if (fc)
 184                 *fc = PAUSE_RX | PAUSE_TX;
 185         return 0;
 186 }
 187
 188 static void mv88x201x_destroy(struct cphy *cphy)
 189 {
 190         kfree(cphy);
 191 }
 192
 193 static struct cphy_ops mv88x201x_ops = {
 194         .destroy           = mv88x201x_destroy,
 195         .reset             = mv88x201x_reset,
 196         .interrupt_enable  = mv88x201x_interrupt_enable,
 197         .interrupt_disable = mv88x201x_interrupt_disable,
 198         .interrupt_clear   = mv88x201x_interrupt_clear,
 199         .interrupt_handler = mv88x201x_interrupt_handler,
 200         .get_link_status   = mv88x201x_get_link_status,
 201         .set_loopback      = mv88x201x_set_loopback,
 202 };
 203
 204 static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr,
 205                                          struct mdio_ops *mdio_ops)
 206 {
 207         u32 val;
 208         struct cphy *cphy = kmalloc(sizeof(*cphy), GFP_KERNEL);
 209
 210         if (!cphy)
 211                 return NULL;
 212         memset(cphy, 0, sizeof(*cphy));
 213         cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops);
 214
 215         /* Commands the PHY to enable XFP's clock. */
 216         mdio_read(cphy, 0x3, 0x8300, &val);
 217         mdio_write(cphy, 0x3, 0x8300, val | 1);
 218
 219         /* Clear link status. Required because of a bug in the PHY.  */
 220         mdio_read(cphy, 0x1, 0x8, &val);
 221         mdio_read(cphy, 0x3, 0x8, &val);
 222
 223         /* Allows for Link,Ack LED turn on/off */
 224         led_init(cphy);
 225         return cphy;
 226 }
 227
 228 /* Chip Reset */
 229 static int mv88x201x_phy_reset(adapter_t *adapter)
 230 {
 231         u32 val;
 232
 233         t1_tpi_read(adapter, A_ELMER0_GPO, &val);
 234         val &= ~4;
 235         t1_tpi_write(adapter, A_ELMER0_GPO, val);
 236         msleep(100);
 237
 238         t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
 239         msleep(1000);
 240
 241         /* Now lets enable the Laser. Delay 100us */
 242         t1_tpi_read(adapter, A_ELMER0_GPO, &val);
 243         val |= 0x8000;
 244         t1_tpi_write(adapter, A_ELMER0_GPO, val);
 245         udelay(100);
 246         return 0;
 247 }
 248
 249 struct gphy t1_mv88x201x_ops = {
 250         mv88x201x_phy_create,
 251         mv88x201x_phy_reset
 252 };