drivers/net/gianfar.h

   1 /*
   2  * drivers/net/gianfar.h
   3  *
   4  * Gianfar Ethernet Driver
   5  * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala (kumar.gala@freescale.com)
  10  *
  11  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  *  Still left to do:
  19  *      -Add support for module parameters
  20  *      -Add patch for ethtool phys id
  21  */
  22 #ifndef __GIANFAR_H
  23 #define __GIANFAR_H
  24
  25 #include <linux/config.h>
  26 #include <linux/kernel.h>
  27 #include <linux/sched.h>
  28 #include <linux/string.h>
  29 #include <linux/errno.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/mm.h>
  39 #include <linux/mii.h>
  40 #include <linux/phy.h>
  41
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44 #include <asm/uaccess.h>
  45 #include <linux/module.h>
  46 #include <linux/version.h>
  47 #include <linux/crc32.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/ethtool.h>
  50 #include <linux/netdevice.h>
  51 #include <linux/fsl_devices.h>
  52 #include "gianfar_mii.h"
  53
  54 /* The maximum number of packets to be handled in one call of gfar_poll */
  55 #define GFAR_DEV_WEIGHT 64
  56
  57 /* Length for FCB */
  58 #define GMAC_FCB_LEN 8
  59
  60 /* Default padding amount */
  61 #define DEFAULT_PADDING 2
  62
  63 /* Number of bytes to align the rx bufs to */
  64 #define RXBUF_ALIGNMENT 64
  65
  66 /* The number of bytes which composes a unit for the purpose of
  67  * allocating data buffers.  ie-for any given MTU, the data buffer
  68  * will be the next highest multiple of 512 bytes. */
  69 #define INCREMENTAL_BUFFER_SIZE 512
  70
  71
  72 #define MAC_ADDR_LEN 6
  73
  74 #define PHY_INIT_TIMEOUT 100000
  75 #define GFAR_PHY_CHANGE_TIME 2
  76
  77 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
  78 #define DRV_NAME "gfar-enet"
  79 extern const char gfar_driver_name[];
  80 extern const char gfar_driver_version[];
  81
  82 /* These need to be powers of 2 for this driver */
  83 #ifdef CONFIG_GFAR_NAPI
  84 #define DEFAULT_TX_RING_SIZE    256
  85 #define DEFAULT_RX_RING_SIZE    256
  86 #else
  87 #define DEFAULT_TX_RING_SIZE    64
  88 #define DEFAULT_RX_RING_SIZE    64
  89 #endif
  90
  91 #define GFAR_RX_MAX_RING_SIZE   256
  92 #define GFAR_TX_MAX_RING_SIZE   256
  93
  94 #define DEFAULT_RX_BUFFER_SIZE  1536
  95 #define TX_RING_MOD_MASK(size) (size-1)
  96 #define RX_RING_MOD_MASK(size) (size-1)
  97 #define JUMBO_BUFFER_SIZE 9728
  98 #define JUMBO_FRAME_SIZE 9600
  99
 100 /* Latency of interface clock in nanoseconds */
 101 /* Interface clock latency , in this case, means the
 102  * time described by a value of 1 in the interrupt
 103  * coalescing registers' time fields.  Since those fields
 104  * refer to the time it takes for 64 clocks to pass, the
 105  * latencies are as such:
 106  * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 107  * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 108  * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 109  */
 110 #define GFAR_GBIT_TIME  512
 111 #define GFAR_100_TIME   2560
 112 #define GFAR_10_TIME    25600
 113
 114 #define DEFAULT_TX_COALESCE 1
 115 #define DEFAULT_TXCOUNT 16
 116 #define DEFAULT_TXTIME  400
 117
 118 #define DEFAULT_RX_COALESCE 1
 119 #define DEFAULT_RXCOUNT 16
 120 #define DEFAULT_RXTIME  400
 121
 122 #define TBIPA_VALUE             0x1f
 123 #define MIIMCFG_INIT_VALUE      0x00000007
 124 #define MIIMCFG_RESET           0x80000000
 125 #define MIIMIND_BUSY            0x00000001
 126
 127 /* MAC register bits */
 128 #define MACCFG1_SOFT_RESET      0x80000000
 129 #define MACCFG1_RESET_RX_MC     0x00080000
 130 #define MACCFG1_RESET_TX_MC     0x00040000
 131 #define MACCFG1_RESET_RX_FUN    0x00020000
 132 #define MACCFG1_RESET_TX_FUN    0x00010000
 133 #define MACCFG1_LOOPBACK        0x00000100
 134 #define MACCFG1_RX_FLOW         0x00000020
 135 #define MACCFG1_TX_FLOW         0x00000010
 136 #define MACCFG1_SYNCD_RX_EN     0x00000008
 137 #define MACCFG1_RX_EN           0x00000004
 138 #define MACCFG1_SYNCD_TX_EN     0x00000002
 139 #define MACCFG1_TX_EN           0x00000001
 140
 141 #define MACCFG2_INIT_SETTINGS   0x00007205
 142 #define MACCFG2_FULL_DUPLEX     0x00000001
 143 #define MACCFG2_IF              0x00000300
 144 #define MACCFG2_MII             0x00000100
 145 #define MACCFG2_GMII            0x00000200
 146 #define MACCFG2_HUGEFRAME       0x00000020
 147 #define MACCFG2_LENGTHCHECK     0x00000010
 148
 149 #define ECNTRL_INIT_SETTINGS    0x00001000
 150 #define ECNTRL_TBI_MODE         0x00000020
 151
 152 #define MRBLR_INIT_SETTINGS     DEFAULT_RX_BUFFER_SIZE
 153
 154 #define MINFLR_INIT_SETTINGS    0x00000040
 155
 156 /* Init to do tx snooping for buffers and descriptors */
 157 #define DMACTRL_INIT_SETTINGS   0x000000c3
 158 #define DMACTRL_GRS             0x00000010
 159 #define DMACTRL_GTS             0x00000008
 160
 161 #define TSTAT_CLEAR_THALT       0x80000000
 162
 163 /* Interrupt coalescing macros */
 164 #define IC_ICEN                 0x80000000
 165 #define IC_ICFT_MASK            0x1fe00000
 166 #define IC_ICFT_SHIFT           21
 167 #define mk_ic_icft(x)           \
 168         (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
 169 #define IC_ICTT_MASK            0x0000ffff
 170 #define mk_ic_ictt(x)           (x&IC_ICTT_MASK)
 171
 172 #define mk_ic_value(count, time) (IC_ICEN | \
 173                                 mk_ic_icft(count) | \
 174                                 mk_ic_ictt(time))
 175
 176 #define RCTRL_PAL_MASK          0x001f0000
 177 #define RCTRL_VLEX              0x00002000
 178 #define RCTRL_FILREN            0x00001000
 179 #define RCTRL_GHTX              0x00000400
 180 #define RCTRL_IPCSEN            0x00000200
 181 #define RCTRL_TUCSEN            0x00000100
 182 #define RCTRL_PRSDEP_MASK       0x000000c0
 183 #define RCTRL_PRSDEP_INIT       0x000000c0
 184 #define RCTRL_PROM              0x00000008
 185 #define RCTRL_CHECKSUMMING      (RCTRL_IPCSEN \
 186                 | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
 187 #define RCTRL_EXTHASH           (RCTRL_GHTX)
 188 #define RCTRL_VLAN              (RCTRL_PRSDEP_INIT)
 189
 190
 191 #define RSTAT_CLEAR_RHALT       0x00800000
 192
 193 #define TCTRL_IPCSEN            0x00004000
 194 #define TCTRL_TUCSEN            0x00002000
 195 #define TCTRL_VLINS             0x00001000
 196 #define TCTRL_INIT_CSUM         (TCTRL_TUCSEN | TCTRL_IPCSEN)
 197
 198 #define IEVENT_INIT_CLEAR       0xffffffff
 199 #define IEVENT_BABR             0x80000000
 200 #define IEVENT_RXC              0x40000000
 201 #define IEVENT_BSY              0x20000000
 202 #define IEVENT_EBERR            0x10000000
 203 #define IEVENT_MSRO             0x04000000
 204 #define IEVENT_GTSC             0x02000000
 205 #define IEVENT_BABT             0x01000000
 206 #define IEVENT_TXC              0x00800000
 207 #define IEVENT_TXE              0x00400000
 208 #define IEVENT_TXB              0x00200000
 209 #define IEVENT_TXF              0x00100000
 210 #define IEVENT_LC               0x00040000
 211 #define IEVENT_CRL              0x00020000
 212 #define IEVENT_XFUN             0x00010000
 213 #define IEVENT_RXB0             0x00008000
 214 #define IEVENT_GRSC             0x00000100
 215 #define IEVENT_RXF0             0x00000080
 216 #define IEVENT_FIR              0x00000008
 217 #define IEVENT_FIQ              0x00000004
 218 #define IEVENT_DPE              0x00000002
 219 #define IEVENT_PERR             0x00000001
 220 #define IEVENT_RX_MASK          (IEVENT_RXB0 | IEVENT_RXF0)
 221 #define IEVENT_TX_MASK          (IEVENT_TXB | IEVENT_TXF)
 222 #define IEVENT_ERR_MASK         \
 223 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
 224  IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
 225  | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
 226
 227 #define IMASK_INIT_CLEAR        0x00000000
 228 #define IMASK_BABR              0x80000000
 229 #define IMASK_RXC               0x40000000
 230 #define IMASK_BSY               0x20000000
 231 #define IMASK_EBERR             0x10000000
 232 #define IMASK_MSRO              0x04000000
 233 #define IMASK_GRSC              0x02000000
 234 #define IMASK_BABT              0x01000000
 235 #define IMASK_TXC               0x00800000
 236 #define IMASK_TXEEN             0x00400000
 237 #define IMASK_TXBEN             0x00200000
 238 #define IMASK_TXFEN             0x00100000
 239 #define IMASK_LC                0x00040000
 240 #define IMASK_CRL               0x00020000
 241 #define IMASK_XFUN              0x00010000
 242 #define IMASK_RXB0              0x00008000
 243 #define IMASK_GTSC              0x00000100
 244 #define IMASK_RXFEN0            0x00000080
 245 #define IMASK_FIR               0x00000008
 246 #define IMASK_FIQ               0x00000004
 247 #define IMASK_DPE               0x00000002
 248 #define IMASK_PERR              0x00000001
 249 #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
 250 #define IMASK_DEFAULT  (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
 251                 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
 252                 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
 253                 | IMASK_PERR)
 254
 255
 256 /* Attribute fields */
 257
 258 /* This enables rx snooping for buffers and descriptors */
 259 #ifdef CONFIG_GFAR_BDSTASH
 260 #define ATTR_BDSTASH            0x00000800
 261 #else
 262 #define ATTR_BDSTASH            0x00000000
 263 #endif
 264
 265 #ifdef CONFIG_GFAR_BUFSTASH
 266 #define ATTR_BUFSTASH           0x00004000
 267 #define STASH_LENGTH            64
 268 #else
 269 #define ATTR_BUFSTASH           0x00000000
 270 #endif
 271
 272 #define ATTR_SNOOPING           0x000000c0
 273 #define ATTR_INIT_SETTINGS      (ATTR_SNOOPING \
 274                 | ATTR_BDSTASH | ATTR_BUFSTASH)
 275
 276 #define ATTRELI_INIT_SETTINGS   0x0
 277
 278
 279 /* TxBD status field bits */
 280 #define TXBD_READY              0x8000
 281 #define TXBD_PADCRC             0x4000
 282 #define TXBD_WRAP               0x2000
 283 #define TXBD_INTERRUPT          0x1000
 284 #define TXBD_LAST               0x0800
 285 #define TXBD_CRC                0x0400
 286 #define TXBD_DEF                0x0200
 287 #define TXBD_HUGEFRAME          0x0080
 288 #define TXBD_LATECOLLISION      0x0080
 289 #define TXBD_RETRYLIMIT         0x0040
 290 #define TXBD_RETRYCOUNTMASK     0x003c
 291 #define TXBD_UNDERRUN           0x0002
 292 #define TXBD_TOE                0x0002
 293
 294 /* Tx FCB param bits */
 295 #define TXFCB_VLN               0x80
 296 #define TXFCB_IP                0x40
 297 #define TXFCB_IP6               0x20
 298 #define TXFCB_TUP               0x10
 299 #define TXFCB_UDP               0x08
 300 #define TXFCB_CIP               0x04
 301 #define TXFCB_CTU               0x02
 302 #define TXFCB_NPH               0x01
 303 #define TXFCB_DEFAULT           (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
 304
 305 /* RxBD status field bits */
 306 #define RXBD_EMPTY              0x8000
 307 #define RXBD_RO1                0x4000
 308 #define RXBD_WRAP               0x2000
 309 #define RXBD_INTERRUPT          0x1000
 310 #define RXBD_LAST               0x0800
 311 #define RXBD_FIRST              0x0400
 312 #define RXBD_MISS               0x0100
 313 #define RXBD_BROADCAST          0x0080
 314 #define RXBD_MULTICAST          0x0040
 315 #define RXBD_LARGE              0x0020
 316 #define RXBD_NONOCTET           0x0010
 317 #define RXBD_SHORT              0x0008
 318 #define RXBD_CRCERR             0x0004
 319 #define RXBD_OVERRUN            0x0002
 320 #define RXBD_TRUNCATED          0x0001
 321 #define RXBD_STATS              0x01ff
 322
 323 /* Rx FCB status field bits */
 324 #define RXFCB_VLN               0x8000
 325 #define RXFCB_IP                0x4000
 326 #define RXFCB_IP6               0x2000
 327 #define RXFCB_TUP               0x1000
 328 #define RXFCB_CIP               0x0800
 329 #define RXFCB_CTU               0x0400
 330 #define RXFCB_EIP               0x0200
 331 #define RXFCB_ETU               0x0100
 332 #define RXFCB_PERR_MASK         0x000c
 333 #define RXFCB_PERR_BADL3        0x0008
 334
 335 struct txbd8
 336 {
 337         u16     status; /* Status Fields */
 338         u16     length; /* Buffer length */
 339         u32     bufPtr; /* Buffer Pointer */
 340 };
 341
 342 struct txfcb {
 343         u8      vln:1,
 344                 ip:1,
 345                 ip6:1,
 346                 tup:1,
 347                 udp:1,
 348                 cip:1,
 349                 ctu:1,
 350                 nph:1;
 351         u8      reserved;
 352         u8      l4os;   /* Level 4 Header Offset */
 353         u8      l3os;   /* Level 3 Header Offset */
 354         u16     phcs;   /* Pseudo-header Checksum */
 355         u16     vlctl;  /* VLAN control word */
 356 };
 357
 358 struct rxbd8
 359 {
 360         u16     status; /* Status Fields */
 361         u16     length; /* Buffer Length */
 362         u32     bufPtr; /* Buffer Pointer */
 363 };
 364
 365 struct rxfcb {
 366         u16     vln:1,
 367                 ip:1,
 368                 ip6:1,
 369                 tup:1,
 370                 cip:1,
 371                 ctu:1,
 372                 eip:1,
 373                 etu:1;
 374         u8      rq;     /* Receive Queue index */
 375         u8      pro;    /* Layer 4 Protocol */
 376         u16     reserved;
 377         u16     vlctl;  /* VLAN control word */
 378 };
 379
 380 struct rmon_mib
 381 {
 382         u32     tr64;   /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
 383         u32     tr127;  /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
 384         u32     tr255;  /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
 385         u32     tr511;  /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
 386         u32     tr1k;   /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
 387         u32     trmax;  /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
 388         u32     trmgv;  /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 389         u32     rbyt;   /* 0x.69c - Receive Byte Counter */
 390         u32     rpkt;   /* 0x.6a0 - Receive Packet Counter */
 391         u32     rfcs;   /* 0x.6a4 - Receive FCS Error Counter */
 392         u32     rmca;   /* 0x.6a8 - Receive Multicast Packet Counter */
 393         u32     rbca;   /* 0x.6ac - Receive Broadcast Packet Counter */
 394         u32     rxcf;   /* 0x.6b0 - Receive Control Frame Packet Counter */
 395         u32     rxpf;   /* 0x.6b4 - Receive Pause Frame Packet Counter */
 396         u32     rxuo;   /* 0x.6b8 - Receive Unknown OP Code Counter */
 397         u32     raln;   /* 0x.6bc - Receive Alignment Error Counter */
 398         u32     rflr;   /* 0x.6c0 - Receive Frame Length Error Counter */
 399         u32     rcde;   /* 0x.6c4 - Receive Code Error Counter */
 400         u32     rcse;   /* 0x.6c8 - Receive Carrier Sense Error Counter */
 401         u32     rund;   /* 0x.6cc - Receive Undersize Packet Counter */
 402         u32     rovr;   /* 0x.6d0 - Receive Oversize Packet Counter */
 403         u32     rfrg;   /* 0x.6d4 - Receive Fragments Counter */
 404         u32     rjbr;   /* 0x.6d8 - Receive Jabber Counter */
 405         u32     rdrp;   /* 0x.6dc - Receive Drop Counter */
 406         u32     tbyt;   /* 0x.6e0 - Transmit Byte Counter Counter */
 407         u32     tpkt;   /* 0x.6e4 - Transmit Packet Counter */
 408         u32     tmca;   /* 0x.6e8 - Transmit Multicast Packet Counter */
 409         u32     tbca;   /* 0x.6ec - Transmit Broadcast Packet Counter */
 410         u32     txpf;   /* 0x.6f0 - Transmit Pause Control Frame Counter */
 411         u32     tdfr;   /* 0x.6f4 - Transmit Deferral Packet Counter */
 412         u32     tedf;   /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
 413         u32     tscl;   /* 0x.6fc - Transmit Single Collision Packet Counter */
 414         u32     tmcl;   /* 0x.700 - Transmit Multiple Collision Packet Counter */
 415         u32     tlcl;   /* 0x.704 - Transmit Late Collision Packet Counter */
 416         u32     txcl;   /* 0x.708 - Transmit Excessive Collision Packet Counter */
 417         u32     tncl;   /* 0x.70c - Transmit Total Collision Counter */
 418         u8      res1[4];
 419         u32     tdrp;   /* 0x.714 - Transmit Drop Frame Counter */
 420         u32     tjbr;   /* 0x.718 - Transmit Jabber Frame Counter */
 421         u32     tfcs;   /* 0x.71c - Transmit FCS Error Counter */
 422         u32     txcf;   /* 0x.720 - Transmit Control Frame Counter */
 423         u32     tovr;   /* 0x.724 - Transmit Oversize Frame Counter */
 424         u32     tund;   /* 0x.728 - Transmit Undersize Frame Counter */
 425         u32     tfrg;   /* 0x.72c - Transmit Fragments Frame Counter */
 426         u32     car1;   /* 0x.730 - Carry Register One */
 427         u32     car2;   /* 0x.734 - Carry Register Two */
 428         u32     cam1;   /* 0x.738 - Carry Mask Register One */
 429         u32     cam2;   /* 0x.73c - Carry Mask Register Two */
 430 };
 431
 432 struct gfar_extra_stats {
 433         u64 kernel_dropped;
 434         u64 rx_large;
 435         u64 rx_short;
 436         u64 rx_nonoctet;
 437         u64 rx_crcerr;
 438         u64 rx_overrun;
 439         u64 rx_bsy;
 440         u64 rx_babr;
 441         u64 rx_trunc;
 442         u64 eberr;
 443         u64 tx_babt;
 444         u64 tx_underrun;
 445         u64 rx_skbmissing;
 446         u64 tx_timeout;
 447 };
 448
 449 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
 450 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
 451
 452 /* Number of stats in the stats structure (ignore car and cam regs)*/
 453 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
 454
 455 #define GFAR_INFOSTR_LEN 32
 456
 457 struct gfar_stats {
 458         u64 extra[GFAR_EXTRA_STATS_LEN];
 459         u64 rmon[GFAR_RMON_LEN];
 460 };
 461
 462
 463 struct gfar {
 464         u32     tsec_id;        /* 0x.000 - Controller ID register */
 465         u8      res1[12];
 466         u32     ievent;         /* 0x.010 - Interrupt Event Register */
 467         u32     imask;          /* 0x.014 - Interrupt Mask Register */
 468         u32     edis;           /* 0x.018 - Error Disabled Register */
 469         u8      res2[4];
 470         u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
 471         u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
 472         u32     ptv;            /* 0x.028 - Pause Time Value Register */
 473         u32     dmactrl;        /* 0x.02c - DMA Control Register */
 474         u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
 475         u8      res3[88];
 476         u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
 477         u8      res4[8];
 478         u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
 479         u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
 480         u8      res5[4];
 481         u32     fifo_rx_pause;  /* 0x.0a4 - FIFO receive pause threshold register */
 482         u32     fifo_rx_alarm;  /* 0x.0a8 - FIFO receive alarm threshold register */
 483         u8      res6[84];
 484         u32     tctrl;          /* 0x.100 - Transmit Control Register */
 485         u32     tstat;          /* 0x.104 - Transmit Status Register */
 486         u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
 487         u32     tbdlen;         /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
 488         u32     txic;           /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
 489         u32     tqueue;         /* 0x.114 - Transmit queue control register */
 490         u8      res7[40];
 491         u32     tr03wt;         /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
 492         u32     tr47wt;         /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
 493         u8      res8[52];
 494         u32     tbdbph;         /* 0x.17c - Tx data buffer pointer high */
 495         u8      res9a[4];
 496         u32     tbptr0;         /* 0x.184 - TxBD Pointer for ring 0 */
 497         u8      res9b[4];
 498         u32     tbptr1;         /* 0x.18c - TxBD Pointer for ring 1 */
 499         u8      res9c[4];
 500         u32     tbptr2;         /* 0x.194 - TxBD Pointer for ring 2 */
 501         u8      res9d[4];
 502         u32     tbptr3;         /* 0x.19c - TxBD Pointer for ring 3 */
 503         u8      res9e[4];
 504         u32     tbptr4;         /* 0x.1a4 - TxBD Pointer for ring 4 */
 505         u8      res9f[4];
 506         u32     tbptr5;         /* 0x.1ac - TxBD Pointer for ring 5 */
 507         u8      res9g[4];
 508         u32     tbptr6;         /* 0x.1b4 - TxBD Pointer for ring 6 */
 509         u8      res9h[4];
 510         u32     tbptr7;         /* 0x.1bc - TxBD Pointer for ring 7 */
 511         u8      res9[64];
 512         u32     tbaseh;         /* 0x.200 - TxBD base address high */
 513         u32     tbase0;         /* 0x.204 - TxBD Base Address of ring 0 */
 514         u8      res10a[4];
 515         u32     tbase1;         /* 0x.20c - TxBD Base Address of ring 1 */
 516         u8      res10b[4];
 517         u32     tbase2;         /* 0x.214 - TxBD Base Address of ring 2 */
 518         u8      res10c[4];
 519         u32     tbase3;         /* 0x.21c - TxBD Base Address of ring 3 */
 520         u8      res10d[4];
 521         u32     tbase4;         /* 0x.224 - TxBD Base Address of ring 4 */
 522         u8      res10e[4];
 523         u32     tbase5;         /* 0x.22c - TxBD Base Address of ring 5 */
 524         u8      res10f[4];
 525         u32     tbase6;         /* 0x.234 - TxBD Base Address of ring 6 */
 526         u8      res10g[4];
 527         u32     tbase7;         /* 0x.23c - TxBD Base Address of ring 7 */
 528         u8      res10[192];
 529         u32     rctrl;          /* 0x.300 - Receive Control Register */
 530         u32     rstat;          /* 0x.304 - Receive Status Register */
 531         u8      res12[8];
 532         u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
 533         u32     rqueue;         /* 0x.314 - Receive queue control register */
 534         u8      res13[24];
 535         u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
 536         u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
 537         u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
 538         u32     rqfpr;          /* 0x.33c - Receive queue filing table property register */
 539         u32     mrblr;          /* 0x.340 - Maximum Receive Buffer Length Register */
 540         u8      res14[56];
 541         u32     rbdbph;         /* 0x.37c - Rx data buffer pointer high */
 542         u8      res15a[4];
 543         u32     rbptr0;         /* 0x.384 - RxBD pointer for ring 0 */
 544         u8      res15b[4];
 545         u32     rbptr1;         /* 0x.38c - RxBD pointer for ring 1 */
 546         u8      res15c[4];
 547         u32     rbptr2;         /* 0x.394 - RxBD pointer for ring 2 */
 548         u8      res15d[4];
 549         u32     rbptr3;         /* 0x.39c - RxBD pointer for ring 3 */
 550         u8      res15e[4];
 551         u32     rbptr4;         /* 0x.3a4 - RxBD pointer for ring 4 */
 552         u8      res15f[4];
 553         u32     rbptr5;         /* 0x.3ac - RxBD pointer for ring 5 */
 554         u8      res15g[4];
 555         u32     rbptr6;         /* 0x.3b4 - RxBD pointer for ring 6 */
 556         u8      res15h[4];
 557         u32     rbptr7;         /* 0x.3bc - RxBD pointer for ring 7 */
 558         u8      res16[64];
 559         u32     rbaseh;         /* 0x.400 - RxBD base address high */
 560         u32     rbase0;         /* 0x.404 - RxBD base address of ring 0 */
 561         u8      res17a[4];
 562         u32     rbase1;         /* 0x.40c - RxBD base address of ring 1 */
 563         u8      res17b[4];
 564         u32     rbase2;         /* 0x.414 - RxBD base address of ring 2 */
 565         u8      res17c[4];
 566         u32     rbase3;         /* 0x.41c - RxBD base address of ring 3 */
 567         u8      res17d[4];
 568         u32     rbase4;         /* 0x.424 - RxBD base address of ring 4 */
 569         u8      res17e[4];
 570         u32     rbase5;         /* 0x.42c - RxBD base address of ring 5 */
 571         u8      res17f[4];
 572         u32     rbase6;         /* 0x.434 - RxBD base address of ring 6 */
 573         u8      res17g[4];
 574         u32     rbase7;         /* 0x.43c - RxBD base address of ring 7 */
 575         u8      res17[192];
 576         u32     maccfg1;        /* 0x.500 - MAC Configuration 1 Register */
 577         u32     maccfg2;        /* 0x.504 - MAC Configuration 2 Register */
 578         u32     ipgifg;         /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
 579         u32     hafdup;         /* 0x.50c - Half Duplex Register */
 580         u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
 581         u8      res18[12];
 582         u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
 583         u8      res19[4];
 584         u32     ifstat;         /* 0x.53c - Interface Status Register */
 585         u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
 586         u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
 587         u32     mac01addr1;     /* 0x.548 - MAC exact match address 1, part 1 */
 588         u32     mac01addr2;     /* 0x.54c - MAC exact match address 1, part 2 */
 589         u32     mac02addr1;     /* 0x.550 - MAC exact match address 2, part 1 */
 590         u32     mac02addr2;     /* 0x.554 - MAC exact match address 2, part 2 */
 591         u32     mac03addr1;     /* 0x.558 - MAC exact match address 3, part 1 */
 592         u32     mac03addr2;     /* 0x.55c - MAC exact match address 3, part 2 */
 593         u32     mac04addr1;     /* 0x.560 - MAC exact match address 4, part 1 */
 594         u32     mac04addr2;     /* 0x.564 - MAC exact match address 4, part 2 */
 595         u32     mac05addr1;     /* 0x.568 - MAC exact match address 5, part 1 */
 596         u32     mac05addr2;     /* 0x.56c - MAC exact match address 5, part 2 */
 597         u32     mac06addr1;     /* 0x.570 - MAC exact match address 6, part 1 */
 598         u32     mac06addr2;     /* 0x.574 - MAC exact match address 6, part 2 */
 599         u32     mac07addr1;     /* 0x.578 - MAC exact match address 7, part 1 */
 600         u32     mac07addr2;     /* 0x.57c - MAC exact match address 7, part 2 */
 601         u32     mac08addr1;     /* 0x.580 - MAC exact match address 8, part 1 */
 602         u32     mac08addr2;     /* 0x.584 - MAC exact match address 8, part 2 */
 603         u32     mac09addr1;     /* 0x.588 - MAC exact match address 9, part 1 */
 604         u32     mac09addr2;     /* 0x.58c - MAC exact match address 9, part 2 */
 605         u32     mac10addr1;     /* 0x.590 - MAC exact match address 10, part 1*/
 606         u32     mac10addr2;     /* 0x.594 - MAC exact match address 10, part 2*/
 607         u32     mac11addr1;     /* 0x.598 - MAC exact match address 11, part 1*/
 608         u32     mac11addr2;     /* 0x.59c - MAC exact match address 11, part 2*/
 609         u32     mac12addr1;     /* 0x.5a0 - MAC exact match address 12, part 1*/
 610         u32     mac12addr2;     /* 0x.5a4 - MAC exact match address 12, part 2*/
 611         u32     mac13addr1;     /* 0x.5a8 - MAC exact match address 13, part 1*/
 612         u32     mac13addr2;     /* 0x.5ac - MAC exact match address 13, part 2*/
 613         u32     mac14addr1;     /* 0x.5b0 - MAC exact match address 14, part 1*/
 614         u32     mac14addr2;     /* 0x.5b4 - MAC exact match address 14, part 2*/
 615         u32     mac15addr1;     /* 0x.5b8 - MAC exact match address 15, part 1*/
 616         u32     mac15addr2;     /* 0x.5bc - MAC exact match address 15, part 2*/
 617         u8      res20[192];
 618         struct rmon_mib rmon;   /* 0x.680-0x.73c */
 619         u32     rrej;           /* 0x.740 - Receive filer rejected packet counter */
 620         u8      res21[188];
 621         u32     igaddr0;        /* 0x.800 - Indivdual/Group address register 0*/
 622         u32     igaddr1;        /* 0x.804 - Indivdual/Group address register 1*/
 623         u32     igaddr2;        /* 0x.808 - Indivdual/Group address register 2*/
 624         u32     igaddr3;        /* 0x.80c - Indivdual/Group address register 3*/
 625         u32     igaddr4;        /* 0x.810 - Indivdual/Group address register 4*/
 626         u32     igaddr5;        /* 0x.814 - Indivdual/Group address register 5*/
 627         u32     igaddr6;        /* 0x.818 - Indivdual/Group address register 6*/
 628         u32     igaddr7;        /* 0x.81c - Indivdual/Group address register 7*/
 629         u8      res22[96];
 630         u32     gaddr0;         /* 0x.880 - Group address register 0 */
 631         u32     gaddr1;         /* 0x.884 - Group address register 1 */
 632         u32     gaddr2;         /* 0x.888 - Group address register 2 */
 633         u32     gaddr3;         /* 0x.88c - Group address register 3 */
 634         u32     gaddr4;         /* 0x.890 - Group address register 4 */
 635         u32     gaddr5;         /* 0x.894 - Group address register 5 */
 636         u32     gaddr6;         /* 0x.898 - Group address register 6 */
 637         u32     gaddr7;         /* 0x.89c - Group address register 7 */
 638         u8      res23a[352];
 639         u32     fifocfg;        /* 0x.a00 - FIFO interface config register */
 640         u8      res23b[252];
 641         u8      res23c[248];
 642         u32     attr;           /* 0x.bf8 - Attributes Register */
 643         u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
 644         u8      res24[1024];
 645
 646 };
 647
 648 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
 649  * (Ok, that's not so true anymore, but there is a family resemblence)
 650  * The GFAR buffer descriptors track the ring buffers.  The rx_bd_base
 651  * and tx_bd_base always point to the currently available buffer.
 652  * The dirty_tx tracks the current buffer that is being sent by the
 653  * controller.  The cur_tx and dirty_tx are equal under both completely
 654  * empty and completely full conditions.  The empty/ready indicator in
 655  * the buffer descriptor determines the actual condition.
 656  */
 657 struct gfar_private {
 658         /* pointers to arrays of skbuffs for tx and rx */
 659         struct sk_buff ** tx_skbuff;
 660         struct sk_buff ** rx_skbuff;
 661
 662         /* indices pointing to the next free sbk in skb arrays */
 663         u16 skb_curtx;
 664         u16 skb_currx;
 665
 666         /* index of the first skb which hasn't been transmitted
 667          * yet. */
 668         u16 skb_dirtytx;
 669
 670         /* Configuration info for the coalescing features */
 671         unsigned char txcoalescing;
 672         unsigned short txcount;
 673         unsigned short txtime;
 674         unsigned char rxcoalescing;
 675         unsigned short rxcount;
 676         unsigned short rxtime;
 677
 678         /* GFAR addresses */
 679         struct rxbd8 *rx_bd_base;       /* Base addresses of Rx and Tx Buffers */
 680         struct txbd8 *tx_bd_base;
 681         struct rxbd8 *cur_rx;           /* Next free rx ring entry */
 682         struct txbd8 *cur_tx;           /* Next free ring entry */
 683         struct txbd8 *dirty_tx;         /* The Ring entry to be freed. */
 684         struct gfar *regs;      /* Pointer to the GFAR memory mapped Registers */
 685         u32 *hash_regs[16];
 686         int hash_width;
 687         struct net_device_stats stats; /* linux network statistics */
 688         struct gfar_extra_stats extra_stats;
 689         spinlock_t lock;
 690         unsigned int rx_buffer_size;
 691         unsigned int rx_stash_size;
 692         unsigned int tx_ring_size;
 693         unsigned int rx_ring_size;
 694
 695         unsigned char vlan_enable:1,
 696                 rx_csum_enable:1,
 697                 extended_hash:1;
 698         unsigned short padding;
 699         struct vlan_group *vlgrp;
 700         /* Info structure initialized by board setup code */
 701         unsigned int interruptTransmit;
 702         unsigned int interruptReceive;
 703         unsigned int interruptError;
 704         struct gianfar_platform_data *einfo;
 705
 706         struct phy_device *phydev;
 707         struct mii_bus *mii_bus;
 708         int oldspeed;
 709         int oldduplex;
 710         int oldlink;
 711
 712         uint32_t msg_enable;
 713 };
 714
 715 extern inline u32 gfar_read(volatile unsigned *addr)
 716 {
 717         u32 val;
 718         val = in_be32(addr);
 719         return val;
 720 }
 721
 722 extern inline void gfar_write(volatile unsigned *addr, u32 val)
 723 {
 724         out_be32(addr, val);
 725 }
 726
 727 extern struct ethtool_ops *gfar_op_array[];
 728
 729 extern irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
 730 extern int startup_gfar(struct net_device *dev);
 731 extern void stop_gfar(struct net_device *dev);
 732 extern void gfar_halt(struct net_device *dev);
 733 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
 734                 int enable, u32 regnum, u32 read);
 735 void gfar_setup_stashing(struct net_device *dev);
 736
 737 #endif /* __GIANFAR_H */