arm64: dts: Revert "specify console via command line"
[linux/fpc-iii.git] / arch / m68k / coldfire / m523x.c
blobddf2496ed117424c49e06a35c34bbe9f7e4bddc5
1 // SPDX-License-Identifier: GPL-2.0
2 /***************************************************************************/
4 /*
5 * m523x.c -- platform support for ColdFire 523x based boards
7 * Sub-architcture dependent initialization code for the Freescale
8 * 523x CPUs.
10 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
14 /***************************************************************************/
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <asm/machdep.h>
21 #include <asm/coldfire.h>
22 #include <asm/mcfsim.h>
23 #include <asm/mcfclk.h>
25 /***************************************************************************/
27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
28 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
37 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
40 struct clk *mcf_clks[] = {
41 &clk_pll,
42 &clk_sys,
43 &clk_mcfpit0,
44 &clk_mcfpit1,
45 &clk_mcfpit2,
46 &clk_mcfpit3,
47 &clk_mcfuart0,
48 &clk_mcfuart1,
49 &clk_mcfuart2,
50 &clk_mcfqspi0,
51 &clk_fec0,
52 &clk_mcfi2c0,
53 NULL
56 /***************************************************************************/
58 static void __init m523x_qspi_init(void)
60 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
61 u16 par;
63 /* setup QSPS pins for QSPI with gpio CS control */
64 writeb(0x1f, MCFGPIO_PAR_QSPI);
65 /* and CS2 & CS3 as gpio */
66 par = readw(MCFGPIO_PAR_TIMER);
67 par &= 0x3f3f;
68 writew(par, MCFGPIO_PAR_TIMER);
69 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
72 /***************************************************************************/
74 static void __init m523x_i2c_init(void)
76 #if IS_ENABLED(CONFIG_I2C_IMX)
77 u8 par;
79 /* setup Port AS Pin Assignment Register for I2C */
80 /* set PASPA0 to SCL and PASPA1 to SDA */
81 par = readb(MCFGPIO_PAR_FECI2C);
82 par |= 0x0f;
83 writeb(par, MCFGPIO_PAR_FECI2C);
84 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
87 /***************************************************************************/
89 static void __init m523x_fec_init(void)
91 /* Set multi-function pins to ethernet use */
92 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
95 /***************************************************************************/
97 void __init config_BSP(char *commandp, int size)
99 mach_sched_init = hw_timer_init;
100 m523x_fec_init();
101 m523x_qspi_init();
102 m523x_i2c_init();
105 /***************************************************************************/