1 // SPDX-License-Identifier: GPL-2.0
5 * Exposes all configurable internal clock sources to the clk framework.
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
13 * * selectable source [one of the PLLs],
14 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
15 * or [1 .. 256 in steps of 1] (Au1300),
16 * * can be enabled individually.
18 * - up to 6 "internal" (fixed) consumers which:
19 * * take either AUXPLL or one of the above 6 dividers as input,
20 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
21 * * can be disabled separately.
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
28 * - memory clock: clk rate to main memory chips, depends on board
29 * design and is read-only,
30 * - lrclk: the static bus clock signal for synchronous operation.
31 * depends on board design, must be set by bootloader,
32 * but may be required to correctly configure devices attached to
33 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
34 * later models it's called RCLK.
37 #include <linux/init.h>
39 #include <linux/clk.h>
40 #include <linux/clk-provider.h>
41 #include <linux/clkdev.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/types.h>
45 #include <asm/mach-au1x00/au1000.h>
47 /* Base clock: 12MHz is the default in all databooks, and I haven't
48 * found any board yet which uses a different rate.
50 #define ALCHEMY_ROOTCLK_RATE 12000000
53 * the internal sources which can be driven by the PLLs and dividers.
54 * Names taken from the databooks, refer to them for more information,
55 * especially which ones are share a clock line.
57 static const char * const alchemy_au1300_intclknames
[] = {
58 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
62 static const char * const alchemy_au1200_intclknames
[] = {
63 "lcd_intclk", NULL
, NULL
, NULL
, "EXTCLK0", "EXTCLK1"
66 static const char * const alchemy_au1550_intclknames
[] = {
67 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
71 static const char * const alchemy_au1100_intclknames
[] = {
72 "usb_clk", "lcd_intclk", NULL
, "i2s_clk", "EXTCLK0", "EXTCLK1"
75 static const char * const alchemy_au1500_intclknames
[] = {
76 NULL
, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
79 static const char * const alchemy_au1000_intclknames
[] = {
80 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
84 /* aliases for a few on-chip sources which are either shared
85 * or have gone through name changes.
87 static struct clk_aliastable
{
91 } alchemy_clk_aliases
[] __initdata
= {
92 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
93 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
94 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
95 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
96 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
97 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550
},
98 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550
},
99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200
},
100 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200
},
101 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
102 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
103 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
104 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
109 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
111 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
112 static spinlock_t alchemy_clk_fg0_lock
;
113 static spinlock_t alchemy_clk_fg1_lock
;
114 static spinlock_t alchemy_clk_csrc_lock
;
116 /* CPU Core clock *****************************************************/
118 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw
*hw
,
119 unsigned long parent_rate
)
124 * On early Au1000, sys_cpupll was write-only. Since these
125 * silicon versions of Au1000 are not sold, we don't bend
126 * over backwards trying to determine the frequency.
128 if (unlikely(au1xxx_cpu_has_pll_wo()))
131 t
= alchemy_rdsys(AU1000_SYS_CPUPLL
) & 0x7f;
132 if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300
)
140 void __init
alchemy_set_lpj(void)
142 preset_lpj
= alchemy_clk_cpu_recalc(NULL
, ALCHEMY_ROOTCLK_RATE
);
143 preset_lpj
/= 2 * HZ
;
146 static const struct clk_ops alchemy_clkops_cpu
= {
147 .recalc_rate
= alchemy_clk_cpu_recalc
,
150 static struct clk __init
*alchemy_clk_setup_cpu(const char *parent_name
,
153 struct clk_init_data id
;
156 h
= kzalloc(sizeof(*h
), GFP_KERNEL
);
158 return ERR_PTR(-ENOMEM
);
160 id
.name
= ALCHEMY_CPU_CLK
;
161 id
.parent_names
= &parent_name
;
164 id
.ops
= &alchemy_clkops_cpu
;
167 return clk_register(NULL
, h
);
170 /* AUXPLLs ************************************************************/
172 struct alchemy_auxpll_clk
{
174 unsigned long reg
; /* au1300 has also AUXPLL2 */
175 int maxmult
; /* max multiplier */
177 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
179 static unsigned long alchemy_clk_aux_recalc(struct clk_hw
*hw
,
180 unsigned long parent_rate
)
182 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
184 return (alchemy_rdsys(a
->reg
) & 0xff) * parent_rate
;
187 static int alchemy_clk_aux_setr(struct clk_hw
*hw
,
189 unsigned long parent_rate
)
191 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
192 unsigned long d
= rate
;
199 /* minimum is 84MHz, max is 756-1032 depending on variant */
200 if (((d
< 7) && (d
!= 0)) || (d
> a
->maxmult
))
203 alchemy_wrsys(d
, a
->reg
);
207 static long alchemy_clk_aux_roundr(struct clk_hw
*hw
,
209 unsigned long *parent_rate
)
211 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
214 if (!rate
|| !*parent_rate
)
217 mult
= rate
/ (*parent_rate
);
219 if (mult
&& (mult
< 7))
221 if (mult
> a
->maxmult
)
224 return (*parent_rate
) * mult
;
227 static const struct clk_ops alchemy_clkops_aux
= {
228 .recalc_rate
= alchemy_clk_aux_recalc
,
229 .set_rate
= alchemy_clk_aux_setr
,
230 .round_rate
= alchemy_clk_aux_roundr
,
233 static struct clk __init
*alchemy_clk_setup_aux(const char *parent_name
,
234 char *name
, int maxmult
,
237 struct clk_init_data id
;
239 struct alchemy_auxpll_clk
*a
;
241 a
= kzalloc(sizeof(*a
), GFP_KERNEL
);
243 return ERR_PTR(-ENOMEM
);
246 id
.parent_names
= &parent_name
;
248 id
.flags
= CLK_GET_RATE_NOCACHE
;
249 id
.ops
= &alchemy_clkops_aux
;
252 a
->maxmult
= maxmult
;
255 c
= clk_register(NULL
, &a
->hw
);
257 clk_register_clkdev(c
, name
, NULL
);
264 /* sysbus_clk *********************************************************/
266 static struct clk __init
*alchemy_clk_setup_sysbus(const char *pn
)
268 unsigned long v
= (alchemy_rdsys(AU1000_SYS_POWERCTRL
) & 3) + 2;
271 c
= clk_register_fixed_factor(NULL
, ALCHEMY_SYSBUS_CLK
,
274 clk_register_clkdev(c
, ALCHEMY_SYSBUS_CLK
, NULL
);
278 /* Peripheral Clock ***************************************************/
280 static struct clk __init
*alchemy_clk_setup_periph(const char *pn
)
282 /* Peripheral clock runs at half the rate of sysbus clk */
285 c
= clk_register_fixed_factor(NULL
, ALCHEMY_PERIPH_CLK
,
288 clk_register_clkdev(c
, ALCHEMY_PERIPH_CLK
, NULL
);
292 /* mem clock **********************************************************/
294 static struct clk __init
*alchemy_clk_setup_mem(const char *pn
, int ct
)
296 void __iomem
*addr
= IOMEM(AU1000_MEM_PHYS_ADDR
);
302 case ALCHEMY_CPU_AU1550
:
303 case ALCHEMY_CPU_AU1200
:
304 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
305 div
= (v
& (1 << 15)) ? 1 : 2;
307 case ALCHEMY_CPU_AU1300
:
308 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
309 div
= (v
& (1 << 31)) ? 1 : 2;
311 case ALCHEMY_CPU_AU1000
:
312 case ALCHEMY_CPU_AU1500
:
313 case ALCHEMY_CPU_AU1100
:
319 c
= clk_register_fixed_factor(NULL
, ALCHEMY_MEM_CLK
, pn
,
322 clk_register_clkdev(c
, ALCHEMY_MEM_CLK
, NULL
);
326 /* lrclk: external synchronous static bus clock ***********************/
328 static struct clk __init
*alchemy_clk_setup_lrclk(const char *pn
, int t
)
330 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
331 * otherwise lrclk=pclk/4.
332 * All other variants: MEM_STCFG0[15:13] = divisor.
333 * L/RCLK = periph_clk / (divisor + 1)
334 * On Au1000, Au1500, Au1100 it's called LCLK,
335 * on later models it's called RCLK, but it's the same thing.
338 unsigned long v
= alchemy_rdsmem(AU1000_MEM_STCFG0
);
341 case ALCHEMY_CPU_AU1000
:
342 case ALCHEMY_CPU_AU1500
:
343 v
= 4 + ((v
>> 11) & 1);
345 default: /* all other models */
346 v
= ((v
>> 13) & 7) + 1;
348 c
= clk_register_fixed_factor(NULL
, ALCHEMY_LR_CLK
,
351 clk_register_clkdev(c
, ALCHEMY_LR_CLK
, NULL
);
355 /* Clock dividers and muxes *******************************************/
357 /* data for fgen and csrc mux-dividers */
358 struct alchemy_fgcs_clk
{
360 spinlock_t
*reglock
; /* register lock */
361 unsigned long reg
; /* SYS_FREQCTRL0/1 */
362 int shift
; /* offset in register */
363 int parent
; /* parent before disable [Au1300] */
364 int isen
; /* is it enabled? */
365 int *dt
; /* dividertable for csrc */
367 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
369 static long alchemy_calc_div(unsigned long rate
, unsigned long prate
,
370 int scale
, int maxdiv
, unsigned long *rv
)
375 if ((prate
/ div1
) > rate
)
378 if (scale
== 2) { /* only div-by-multiple-of-2 possible */
380 div1
++; /* stay <=prate */
383 div2
= (div1
/ scale
) - 1; /* value to write to register */
390 div1
= ((div2
+ 1) * scale
);
394 static int alchemy_clk_fgcs_detr(struct clk_hw
*hw
,
395 struct clk_rate_request
*req
,
396 int scale
, int maxdiv
)
398 struct clk_hw
*pc
, *bpc
, *free
;
399 long tdv
, tpr
, pr
, nr
, br
, bpr
, diff
, lastdiff
;
408 /* look at the rates each enabled parent supplies and select
409 * the one that gets closest to but not over the requested rate.
411 for (j
= 0; j
< 7; j
++) {
412 pc
= clk_hw_get_parent_by_index(hw
, j
);
416 /* if this parent is currently unused, remember it.
417 * XXX: we would actually want clk_has_active_children()
418 * but this is a good-enough approximation for now.
420 if (!clk_hw_is_prepared(pc
)) {
425 pr
= clk_hw_get_rate(pc
);
429 /* what can hardware actually provide */
430 tdv
= alchemy_calc_div(req
->rate
, pr
, scale
, maxdiv
, NULL
);
432 diff
= req
->rate
- nr
;
436 if (diff
< lastdiff
) {
446 /* if we couldn't get the exact rate we wanted from the enabled
447 * parents, maybe we can tell an available disabled/inactive one
448 * to give us a rate we can divide down to the requested rate.
450 if (lastdiff
&& free
) {
451 for (j
= (maxdiv
== 4) ? 1 : scale
; j
<= maxdiv
; j
+= scale
) {
455 pr
= clk_hw_round_rate(free
, tpr
);
457 tdv
= alchemy_calc_div(req
->rate
, pr
, scale
, maxdiv
,
460 diff
= req
->rate
- nr
;
463 if (diff
< lastdiff
) {
477 req
->best_parent_rate
= bpr
;
478 req
->best_parent_hw
= bpc
;
484 static int alchemy_clk_fgv1_en(struct clk_hw
*hw
)
486 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
487 unsigned long v
, flags
;
489 spin_lock_irqsave(c
->reglock
, flags
);
490 v
= alchemy_rdsys(c
->reg
);
491 v
|= (1 << 1) << c
->shift
;
492 alchemy_wrsys(v
, c
->reg
);
493 spin_unlock_irqrestore(c
->reglock
, flags
);
498 static int alchemy_clk_fgv1_isen(struct clk_hw
*hw
)
500 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
501 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 1);
506 static void alchemy_clk_fgv1_dis(struct clk_hw
*hw
)
508 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
509 unsigned long v
, flags
;
511 spin_lock_irqsave(c
->reglock
, flags
);
512 v
= alchemy_rdsys(c
->reg
);
513 v
&= ~((1 << 1) << c
->shift
);
514 alchemy_wrsys(v
, c
->reg
);
515 spin_unlock_irqrestore(c
->reglock
, flags
);
518 static int alchemy_clk_fgv1_setp(struct clk_hw
*hw
, u8 index
)
520 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
521 unsigned long v
, flags
;
523 spin_lock_irqsave(c
->reglock
, flags
);
524 v
= alchemy_rdsys(c
->reg
);
526 v
|= (1 << c
->shift
);
528 v
&= ~(1 << c
->shift
);
529 alchemy_wrsys(v
, c
->reg
);
530 spin_unlock_irqrestore(c
->reglock
, flags
);
535 static u8
alchemy_clk_fgv1_getp(struct clk_hw
*hw
)
537 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
539 return (alchemy_rdsys(c
->reg
) >> c
->shift
) & 1;
542 static int alchemy_clk_fgv1_setr(struct clk_hw
*hw
, unsigned long rate
,
543 unsigned long parent_rate
)
545 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
546 unsigned long div
, v
, flags
, ret
;
547 int sh
= c
->shift
+ 2;
549 if (!rate
|| !parent_rate
|| rate
> (parent_rate
/ 2))
551 ret
= alchemy_calc_div(rate
, parent_rate
, 2, 512, &div
);
552 spin_lock_irqsave(c
->reglock
, flags
);
553 v
= alchemy_rdsys(c
->reg
);
556 alchemy_wrsys(v
, c
->reg
);
557 spin_unlock_irqrestore(c
->reglock
, flags
);
562 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw
*hw
,
563 unsigned long parent_rate
)
565 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
566 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 2);
568 v
= ((v
& 0xff) + 1) * 2;
569 return parent_rate
/ v
;
572 static int alchemy_clk_fgv1_detr(struct clk_hw
*hw
,
573 struct clk_rate_request
*req
)
575 return alchemy_clk_fgcs_detr(hw
, req
, 2, 512);
578 /* Au1000, Au1100, Au15x0, Au12x0 */
579 static const struct clk_ops alchemy_clkops_fgenv1
= {
580 .recalc_rate
= alchemy_clk_fgv1_recalc
,
581 .determine_rate
= alchemy_clk_fgv1_detr
,
582 .set_rate
= alchemy_clk_fgv1_setr
,
583 .set_parent
= alchemy_clk_fgv1_setp
,
584 .get_parent
= alchemy_clk_fgv1_getp
,
585 .enable
= alchemy_clk_fgv1_en
,
586 .disable
= alchemy_clk_fgv1_dis
,
587 .is_enabled
= alchemy_clk_fgv1_isen
,
590 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk
*c
)
592 unsigned long v
= alchemy_rdsys(c
->reg
);
594 v
&= ~(3 << c
->shift
);
595 v
|= (c
->parent
& 3) << c
->shift
;
596 alchemy_wrsys(v
, c
->reg
);
600 static int alchemy_clk_fgv2_en(struct clk_hw
*hw
)
602 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
605 /* enable by setting the previous parent clock */
606 spin_lock_irqsave(c
->reglock
, flags
);
607 __alchemy_clk_fgv2_en(c
);
608 spin_unlock_irqrestore(c
->reglock
, flags
);
613 static int alchemy_clk_fgv2_isen(struct clk_hw
*hw
)
615 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
617 return ((alchemy_rdsys(c
->reg
) >> c
->shift
) & 3) != 0;
620 static void alchemy_clk_fgv2_dis(struct clk_hw
*hw
)
622 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
623 unsigned long v
, flags
;
625 spin_lock_irqsave(c
->reglock
, flags
);
626 v
= alchemy_rdsys(c
->reg
);
627 v
&= ~(3 << c
->shift
); /* set input mux to "disabled" state */
628 alchemy_wrsys(v
, c
->reg
);
630 spin_unlock_irqrestore(c
->reglock
, flags
);
633 static int alchemy_clk_fgv2_setp(struct clk_hw
*hw
, u8 index
)
635 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
638 spin_lock_irqsave(c
->reglock
, flags
);
639 c
->parent
= index
+ 1; /* value to write to register */
641 __alchemy_clk_fgv2_en(c
);
642 spin_unlock_irqrestore(c
->reglock
, flags
);
647 static u8
alchemy_clk_fgv2_getp(struct clk_hw
*hw
)
649 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
650 unsigned long flags
, v
;
652 spin_lock_irqsave(c
->reglock
, flags
);
654 spin_unlock_irqrestore(c
->reglock
, flags
);
658 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
659 * dividers behave exactly as on previous models (dividers are multiples
660 * of 2); with the bit set, dividers are multiples of 1, halving their
661 * range, but making them also much more flexible.
663 static int alchemy_clk_fgv2_setr(struct clk_hw
*hw
, unsigned long rate
,
664 unsigned long parent_rate
)
666 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
667 int sh
= c
->shift
+ 2;
668 unsigned long div
, v
, flags
, ret
;
670 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
673 v
= alchemy_rdsys(c
->reg
) & (1 << 30); /* test "scale" bit */
674 ret
= alchemy_calc_div(rate
, parent_rate
, v
? 1 : 2,
675 v
? 256 : 512, &div
);
677 spin_lock_irqsave(c
->reglock
, flags
);
678 v
= alchemy_rdsys(c
->reg
);
680 v
|= (div
& 0xff) << sh
;
681 alchemy_wrsys(v
, c
->reg
);
682 spin_unlock_irqrestore(c
->reglock
, flags
);
687 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw
*hw
,
688 unsigned long parent_rate
)
690 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
691 int sh
= c
->shift
+ 2;
694 v
= alchemy_rdsys(c
->reg
);
695 t
= parent_rate
/ (((v
>> sh
) & 0xff) + 1);
696 if ((v
& (1 << 30)) == 0) /* test scale bit */
702 static int alchemy_clk_fgv2_detr(struct clk_hw
*hw
,
703 struct clk_rate_request
*req
)
705 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
708 if (alchemy_rdsys(c
->reg
) & (1 << 30)) {
716 return alchemy_clk_fgcs_detr(hw
, req
, scale
, maxdiv
);
719 /* Au1300 larger input mux, no separate disable bit, flexible divider */
720 static const struct clk_ops alchemy_clkops_fgenv2
= {
721 .recalc_rate
= alchemy_clk_fgv2_recalc
,
722 .determine_rate
= alchemy_clk_fgv2_detr
,
723 .set_rate
= alchemy_clk_fgv2_setr
,
724 .set_parent
= alchemy_clk_fgv2_setp
,
725 .get_parent
= alchemy_clk_fgv2_getp
,
726 .enable
= alchemy_clk_fgv2_en
,
727 .disable
= alchemy_clk_fgv2_dis
,
728 .is_enabled
= alchemy_clk_fgv2_isen
,
731 static const char * const alchemy_clk_fgv1_parents
[] = {
732 ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
735 static const char * const alchemy_clk_fgv2_parents
[] = {
736 ALCHEMY_AUXPLL2_CLK
, ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
739 static const char * const alchemy_clk_fgen_names
[] = {
740 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
741 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
};
743 static int __init
alchemy_clk_init_fgens(int ctype
)
746 struct clk_init_data id
;
747 struct alchemy_fgcs_clk
*a
;
752 case ALCHEMY_CPU_AU1000
...ALCHEMY_CPU_AU1200
:
753 id
.ops
= &alchemy_clkops_fgenv1
;
754 id
.parent_names
= alchemy_clk_fgv1_parents
;
757 case ALCHEMY_CPU_AU1300
:
758 id
.ops
= &alchemy_clkops_fgenv2
;
759 id
.parent_names
= alchemy_clk_fgv2_parents
;
765 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
767 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
771 spin_lock_init(&alchemy_clk_fg0_lock
);
772 spin_lock_init(&alchemy_clk_fg1_lock
);
774 for (i
= 0; i
< 6; i
++) {
775 id
.name
= alchemy_clk_fgen_names
[i
];
776 a
->shift
= 10 * (i
< 3 ? i
: i
- 3);
778 a
->reg
= AU1000_SYS_FREQCTRL1
;
779 a
->reglock
= &alchemy_clk_fg1_lock
;
781 a
->reg
= AU1000_SYS_FREQCTRL0
;
782 a
->reglock
= &alchemy_clk_fg0_lock
;
785 /* default to first parent if bootloader has set
786 * the mux to disabled state.
788 if (ctype
== ALCHEMY_CPU_AU1300
) {
789 v
= alchemy_rdsys(a
->reg
);
790 a
->parent
= (v
>> a
->shift
) & 3;
799 c
= clk_register(NULL
, &a
->hw
);
803 clk_register_clkdev(c
, id
.name
, NULL
);
810 /* internal sources muxes *********************************************/
812 static int alchemy_clk_csrc_isen(struct clk_hw
*hw
)
814 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
815 unsigned long v
= alchemy_rdsys(c
->reg
);
817 return (((v
>> c
->shift
) >> 2) & 7) != 0;
820 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk
*c
)
822 unsigned long v
= alchemy_rdsys(c
->reg
);
824 v
&= ~((7 << 2) << c
->shift
);
825 v
|= ((c
->parent
& 7) << 2) << c
->shift
;
826 alchemy_wrsys(v
, c
->reg
);
830 static int alchemy_clk_csrc_en(struct clk_hw
*hw
)
832 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
835 /* enable by setting the previous parent clock */
836 spin_lock_irqsave(c
->reglock
, flags
);
837 __alchemy_clk_csrc_en(c
);
838 spin_unlock_irqrestore(c
->reglock
, flags
);
843 static void alchemy_clk_csrc_dis(struct clk_hw
*hw
)
845 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
846 unsigned long v
, flags
;
848 spin_lock_irqsave(c
->reglock
, flags
);
849 v
= alchemy_rdsys(c
->reg
);
850 v
&= ~((3 << 2) << c
->shift
); /* mux to "disabled" state */
851 alchemy_wrsys(v
, c
->reg
);
853 spin_unlock_irqrestore(c
->reglock
, flags
);
856 static int alchemy_clk_csrc_setp(struct clk_hw
*hw
, u8 index
)
858 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
861 spin_lock_irqsave(c
->reglock
, flags
);
862 c
->parent
= index
+ 1; /* value to write to register */
864 __alchemy_clk_csrc_en(c
);
865 spin_unlock_irqrestore(c
->reglock
, flags
);
870 static u8
alchemy_clk_csrc_getp(struct clk_hw
*hw
)
872 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
874 return c
->parent
- 1;
877 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw
*hw
,
878 unsigned long parent_rate
)
880 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
881 unsigned long v
= (alchemy_rdsys(c
->reg
) >> c
->shift
) & 3;
883 return parent_rate
/ c
->dt
[v
];
886 static int alchemy_clk_csrc_setr(struct clk_hw
*hw
, unsigned long rate
,
887 unsigned long parent_rate
)
889 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
890 unsigned long d
, v
, flags
;
893 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
896 d
= (parent_rate
+ (rate
/ 2)) / rate
;
899 if ((d
== 3) && (c
->dt
[2] != 3))
902 for (i
= 0; i
< 4; i
++)
907 return -EINVAL
; /* oops */
909 spin_lock_irqsave(c
->reglock
, flags
);
910 v
= alchemy_rdsys(c
->reg
);
911 v
&= ~(3 << c
->shift
);
912 v
|= (i
& 3) << c
->shift
;
913 alchemy_wrsys(v
, c
->reg
);
914 spin_unlock_irqrestore(c
->reglock
, flags
);
919 static int alchemy_clk_csrc_detr(struct clk_hw
*hw
,
920 struct clk_rate_request
*req
)
922 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
923 int scale
= c
->dt
[2] == 3 ? 1 : 2; /* au1300 check */
925 return alchemy_clk_fgcs_detr(hw
, req
, scale
, 4);
928 static const struct clk_ops alchemy_clkops_csrc
= {
929 .recalc_rate
= alchemy_clk_csrc_recalc
,
930 .determine_rate
= alchemy_clk_csrc_detr
,
931 .set_rate
= alchemy_clk_csrc_setr
,
932 .set_parent
= alchemy_clk_csrc_setp
,
933 .get_parent
= alchemy_clk_csrc_getp
,
934 .enable
= alchemy_clk_csrc_en
,
935 .disable
= alchemy_clk_csrc_dis
,
936 .is_enabled
= alchemy_clk_csrc_isen
,
939 static const char * const alchemy_clk_csrc_parents
[] = {
940 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK
,
941 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
942 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
946 static int alchemy_csrc_dt1
[] = { 1, 4, 1, 2 }; /* rest */
947 static int alchemy_csrc_dt2
[] = { 1, 4, 3, 2 }; /* Au1300 */
949 static int __init
alchemy_clk_setup_imux(int ctype
)
951 struct alchemy_fgcs_clk
*a
;
952 const char * const *names
;
953 struct clk_init_data id
;
958 id
.ops
= &alchemy_clkops_csrc
;
959 id
.parent_names
= alchemy_clk_csrc_parents
;
961 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
963 dt
= alchemy_csrc_dt1
;
965 case ALCHEMY_CPU_AU1000
:
966 names
= alchemy_au1000_intclknames
;
968 case ALCHEMY_CPU_AU1500
:
969 names
= alchemy_au1500_intclknames
;
971 case ALCHEMY_CPU_AU1100
:
972 names
= alchemy_au1100_intclknames
;
974 case ALCHEMY_CPU_AU1550
:
975 names
= alchemy_au1550_intclknames
;
977 case ALCHEMY_CPU_AU1200
:
978 names
= alchemy_au1200_intclknames
;
980 case ALCHEMY_CPU_AU1300
:
981 dt
= alchemy_csrc_dt2
;
982 names
= alchemy_au1300_intclknames
;
988 a
= kcalloc(6, sizeof(*a
), GFP_KERNEL
);
992 spin_lock_init(&alchemy_clk_csrc_lock
);
995 for (i
= 0; i
< 6; i
++) {
1001 a
->reg
= AU1000_SYS_CLKSRC
;
1002 a
->reglock
= &alchemy_clk_csrc_lock
;
1005 /* default to first parent clock if mux is initially
1006 * set to disabled state.
1008 v
= alchemy_rdsys(a
->reg
);
1009 a
->parent
= ((v
>> a
->shift
) >> 2) & 7;
1017 c
= clk_register(NULL
, &a
->hw
);
1021 clk_register_clkdev(c
, id
.name
, NULL
);
1030 /**********************************************************************/
1039 static int __init
alchemy_clk_init(void)
1041 int ctype
= alchemy_get_cputype(), ret
, i
;
1042 struct clk_aliastable
*t
= alchemy_clk_aliases
;
1045 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1046 c
= clk_register_fixed_rate(NULL
, ALCHEMY_ROOT_CLK
, NULL
,
1047 0, ALCHEMY_ROOTCLK_RATE
);
1050 /* CPU core clock */
1051 c
= alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK
, ctype
);
1054 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1055 i
= (ctype
== ALCHEMY_CPU_AU1300
) ? 84 : 63;
1056 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
, ALCHEMY_AUXPLL_CLK
,
1057 i
, AU1000_SYS_AUXPLL
);
1060 if (ctype
== ALCHEMY_CPU_AU1300
) {
1061 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
,
1062 ALCHEMY_AUXPLL2_CLK
, i
,
1063 AU1300_SYS_AUXPLL2
);
1067 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1068 c
= alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK
);
1071 /* peripheral clock: runs at half rate of sysbus clk */
1072 c
= alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK
);
1075 /* SDR/DDR memory clock */
1076 c
= alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK
, ctype
);
1079 /* L/RCLK: external static bus clock for synchronous mode */
1080 c
= alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK
, ctype
);
1083 /* Frequency dividers 0-5 */
1084 ret
= alchemy_clk_init_fgens(ctype
);
1090 /* diving muxes for internal sources */
1091 ret
= alchemy_clk_setup_imux(ctype
);
1097 /* set up aliases drivers might look for */
1099 if (t
->cputype
== ctype
)
1100 clk_add_alias(t
->alias
, NULL
, t
->base
, NULL
);
1104 pr_info("Alchemy clocktree installed\n");
1110 postcore_initcall(alchemy_clk_init
);