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vfio/pci: Pull BAR mapping setup from read-write path
[linux/fpc-iii.git] / drivers / scsi / gdth.h
blob95fc720c1b30450a3f2696f1cecebbfe8b107830
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _GDTH_H
3 #define _GDTH_H
4
5 /*
6 * Header file for the GDT Disk Array/Storage RAID controllers driver for Linux
7 *
8 * gdth.h Copyright (C) 1995-06 ICP vortex, Achim Leubner
9 * See gdth.c for further informations and
10 * below for supported controller types
11 *
12 * <achim_leubner@adaptec.com>
13 *
14 * $Id: gdth.h,v 1.58 2006/01/11 16:14:09 achim Exp $
15 */
16
17 #include <linux/types.h>
18
19 #ifndef TRUE
20 #define TRUE 1
21 #endif
22 #ifndef FALSE
23 #define FALSE 0
24 #endif
25
26 /* defines, macros */
27
28 /* driver version */
29 #define GDTH_VERSION_STR "3.05"
30 #define GDTH_VERSION 3
31 #define GDTH_SUBVERSION 5
32
33 /* protocol version */
34 #define PROTOCOL_VERSION 1
35
36 /* OEM IDs */
37 #define OEM_ID_ICP 0x941c
38 #define OEM_ID_INTEL 0x8000
39
40 /* controller classes */
41 #define GDT_ISA 0x01 /* ISA controller */
42 #define GDT_EISA 0x02 /* EISA controller */
43 #define GDT_PCI 0x03 /* PCI controller */
44 #define GDT_PCINEW 0x04 /* new PCI controller */
45 #define GDT_PCIMPR 0x05 /* PCI MPR controller */
46 /* GDT_EISA, controller subtypes EISA */
47 #define GDT3_ID 0x0130941c /* GDT3000/3020 */
48 #define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
49 #define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
50 /* GDT_ISA */
51 #define GDT2_ID 0x0120941c /* GDT2000/2020 */
52
53 #ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
54 /* GDT_PCI */
55 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
56 #define PCI_DEVICE_ID_VORTEX_GDT6000B 1 /* GDT6000B/6010 */
57 /* GDT_PCINEW */
58 #define PCI_DEVICE_ID_VORTEX_GDT6x10 2 /* GDT6110/6510 */
59 #define PCI_DEVICE_ID_VORTEX_GDT6x20 3 /* GDT6120/6520 */
60 #define PCI_DEVICE_ID_VORTEX_GDT6530 4 /* GDT6530 */
61 #define PCI_DEVICE_ID_VORTEX_GDT6550 5 /* GDT6550 */
62 /* GDT_PCINEW, wide/ultra SCSI controllers */
63 #define PCI_DEVICE_ID_VORTEX_GDT6x17 6 /* GDT6117/6517 */
64 #define PCI_DEVICE_ID_VORTEX_GDT6x27 7 /* GDT6127/6527 */
65 #define PCI_DEVICE_ID_VORTEX_GDT6537 8 /* GDT6537 */
66 #define PCI_DEVICE_ID_VORTEX_GDT6557 9 /* GDT6557/6557-ECC */
67 /* GDT_PCINEW, wide SCSI controllers */
68 #define PCI_DEVICE_ID_VORTEX_GDT6x15 10 /* GDT6115/6515 */
69 #define PCI_DEVICE_ID_VORTEX_GDT6x25 11 /* GDT6125/6525 */
70 #define PCI_DEVICE_ID_VORTEX_GDT6535 12 /* GDT6535 */
71 #define PCI_DEVICE_ID_VORTEX_GDT6555 13 /* GDT6555/6555-ECC */
72 #endif
73
74 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RP
75 /* GDT_MPR, RP series, wide/ultra SCSI */
76 #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
77 #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
78 #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
79 #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
80 /* GDT_MPR, RP series, narrow/ultra SCSI */
81 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
82 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
83 #endif
84 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x17RD
85 /* GDT_MPR, RD series, wide/ultra SCSI */
86 #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
87 #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
88 #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
89 #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
90 /* GDT_MPR, RD series, narrow/ultra SCSI */
91 #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
92 #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
93 /* GDT_MPR, RD series, wide/ultra2 SCSI */
94 #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
95 GDT6618RD */
96 #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
97 GDT6628RD */
98 #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
99 #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
100 /* GDT_MPR, RN series (64-bit PCI), wide/ultra2 SCSI */
101 #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
102 GDT7618RN */
103 #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
104 GDT7628RN */
105 #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
106 #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
107 #endif
108
109 #ifndef PCI_DEVICE_ID_VORTEX_GDT6x19RD
110 /* GDT_MPR, RD series, Fibre Channel */
111 #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
112 #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
113 /* GDT_MPR, RN series (64-bit PCI), Fibre Channel */
114 #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
115 #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
116 #endif
117
118 #ifndef PCI_DEVICE_ID_VORTEX_GDTMAXRP
119 /* GDT_MPR, last device ID */
120 #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
121 #endif
122
123 #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX
124 /* new GDT Rx Controller */
125 #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
126 #endif
127
128 #ifndef PCI_DEVICE_ID_VORTEX_GDTNEWRX2
129 /* new(2) GDT Rx Controller */
130 #define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301
131 #endif
132
133 #ifndef PCI_DEVICE_ID_INTEL_SRC
134 /* Intel Storage RAID Controller */
135 #define PCI_DEVICE_ID_INTEL_SRC 0x600
136 #endif
137
138 #ifndef PCI_DEVICE_ID_INTEL_SRC_XSCALE
139 /* Intel Storage RAID Controller */
140 #define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601
141 #endif
142
143 /* limits */
144 #define GDTH_SCRATCH PAGE_SIZE /* 4KB scratch buffer */
145 #define GDTH_MAXCMDS 120
146 #define GDTH_MAXC_P_L 16 /* max. cmds per lun */
147 #define GDTH_MAX_RAW 2 /* max. cmds per raw device */
148 #define MAXOFFSETS 128
149 #define MAXHA 16
150 #define MAXID 127
151 #define MAXLUN 8
152 #define MAXBUS 6
153 #define MAX_EVENTS 100 /* event buffer count */
154 #define MAX_RES_ARGS 40 /* device reservation,
155 must be a multiple of 4 */
156 #define MAXCYLS 1024
157 #define HEADS 64
158 #define SECS 32 /* mapping 64*32 */
159 #define MEDHEADS 127
160 #define MEDSECS 63 /* mapping 127*63 */
161 #define BIGHEADS 255
162 #define BIGSECS 63 /* mapping 255*63 */
163
164 /* special command ptr. */
165 #define UNUSED_CMND ((Scsi_Cmnd *)-1)
166 #define INTERNAL_CMND ((Scsi_Cmnd *)-2)
167 #define SCREEN_CMND ((Scsi_Cmnd *)-3)
168 #define SPECIAL_SCP(p) (p==UNUSED_CMND || p==INTERNAL_CMND || p==SCREEN_CMND)
169
170 /* controller services */
171 #define SCSIRAWSERVICE 3
172 #define CACHESERVICE 9
173 #define SCREENSERVICE 11
174
175 /* screenservice defines */
176 #define MSG_INV_HANDLE -1 /* special message handle */
177 #define MSGLEN 16 /* size of message text */
178 #define MSG_SIZE 34 /* size of message structure */
179 #define MSG_REQUEST 0 /* async. event: message */
180
181 /* cacheservice defines */
182 #define SECTOR_SIZE 0x200 /* always 512 bytes per sec. */
183
184 /* DPMEM constants */
185 #define DPMEM_MAGIC 0xC0FFEE11
186 #define IC_HEADER_BYTES 48
187 #define IC_QUEUE_BYTES 4
188 #define DPMEM_COMMAND_OFFSET IC_HEADER_BYTES+IC_QUEUE_BYTES*MAXOFFSETS
189
190 /* cluster_type constants */
191 #define CLUSTER_DRIVE 1
192 #define CLUSTER_MOUNTED 2
193 #define CLUSTER_RESERVED 4
194 #define CLUSTER_RESERVE_STATE (CLUSTER_DRIVE|CLUSTER_MOUNTED|CLUSTER_RESERVED)
195
196 /* commands for all services, cache service */
197 #define GDT_INIT 0 /* service initialization */
198 #define GDT_READ 1 /* read command */
199 #define GDT_WRITE 2 /* write command */
200 #define GDT_INFO 3 /* information about devices */
201 #define GDT_FLUSH 4 /* flush dirty cache buffers */
202 #define GDT_IOCTL 5 /* ioctl command */
203 #define GDT_DEVTYPE 9 /* additional information */
204 #define GDT_MOUNT 10 /* mount cache device */
205 #define GDT_UNMOUNT 11 /* unmount cache device */
206 #define GDT_SET_FEAT 12 /* set feat. (scatter/gather) */
207 #define GDT_GET_FEAT 13 /* get features */
208 #define GDT_WRITE_THR 16 /* write through */
209 #define GDT_READ_THR 17 /* read through */
210 #define GDT_EXT_INFO 18 /* extended info */
211 #define GDT_RESET 19 /* controller reset */
212 #define GDT_RESERVE_DRV 20 /* reserve host drive */
213 #define GDT_RELEASE_DRV 21 /* release host drive */
214 #define GDT_CLUST_INFO 22 /* cluster info */
215 #define GDT_RW_ATTRIBS 23 /* R/W attribs (write thru,..)*/
216 #define GDT_CLUST_RESET 24 /* releases the cluster drives*/
217 #define GDT_FREEZE_IO 25 /* freezes all IOs */
218 #define GDT_UNFREEZE_IO 26 /* unfreezes all IOs */
219 #define GDT_X_INIT_HOST 29 /* ext. init: 64 bit support */
220 #define GDT_X_INFO 30 /* ext. info for drives>2TB */
221
222 /* raw service commands */
223 #define GDT_RESERVE 14 /* reserve dev. to raw serv. */
224 #define GDT_RELEASE 15 /* release device */
225 #define GDT_RESERVE_ALL 16 /* reserve all devices */
226 #define GDT_RELEASE_ALL 17 /* release all devices */
227 #define GDT_RESET_BUS 18 /* reset bus */
228 #define GDT_SCAN_START 19 /* start device scan */
229 #define GDT_SCAN_END 20 /* stop device scan */
230 #define GDT_X_INIT_RAW 21 /* ext. init: 64 bit support */
231
232 /* screen service commands */
233 #define GDT_REALTIME 3 /* realtime clock to screens. */
234 #define GDT_X_INIT_SCR 4 /* ext. init: 64 bit support */
235
236 /* IOCTL command defines */
237 #define SCSI_DR_INFO 0x00 /* SCSI drive info */
238 #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
239 #define SCSI_DR_LIST 0x06 /* SCSI drive list */
240 #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
241 #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
242 #define IOCHAN_DESC 0x5d /* description of IO channel */
243 #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
244 #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
245 #define ARRAY_INFO 0x12 /* array drive info */
246 #define ARRAY_DRV_LIST 0x0f /* array drive list */
247 #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
248 #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
249 #define CACHE_DRV_CNT 0x01 /* cache drive count */
250 #define CACHE_DRV_LIST 0x02 /* cache drive list */
251 #define CACHE_INFO 0x04 /* cache info */
252 #define CACHE_CONFIG 0x05 /* cache configuration */
253 #define CACHE_DRV_INFO 0x07 /* cache drive info */
254 #define BOARD_FEATURES 0x15 /* controller features */
255 #define BOARD_INFO 0x28 /* controller info */
256 #define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */
257 #define GET_PERF_MODES 0x83 /* get mode */
258 #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */
259 #define HOST_GET 0x10001L /* get host drive list */
260 #define IO_CHANNEL 0x00020000L /* default IO channel */
261 #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
262
263 /* service errors */
264 #define S_OK 1 /* no error */
265 #define S_GENERR 6 /* general error */
266 #define S_BSY 7 /* controller busy */
267 #define S_CACHE_UNKNOWN 12 /* cache serv.: drive unknown */
268 #define S_RAW_SCSI 12 /* raw serv.: target error */
269 #define S_RAW_ILL 0xff /* raw serv.: illegal */
270 #define S_NOFUNC -2 /* unknown function */
271 #define S_CACHE_RESERV -24 /* cache: reserv. conflict */
272
273 /* timeout values */
274 #define INIT_RETRIES 100000 /* 100000 * 1ms = 100s */
275 #define INIT_TIMEOUT 100000 /* 100000 * 1ms = 100s */
276 #define POLL_TIMEOUT 10000 /* 10000 * 1ms = 10s */
277
278 /* priorities */
279 #define DEFAULT_PRI 0x20
280 #define IOCTL_PRI 0x10
281 #define HIGH_PRI 0x08
282
283 /* data directions */
284 #define GDTH_DATA_IN 0x01000000L /* data from target */
285 #define GDTH_DATA_OUT 0x00000000L /* data to target */
286
287 /* BMIC registers (EISA controllers) */
288 #define ID0REG 0x0c80 /* board ID */
289 #define EINTENABREG 0x0c89 /* interrupt enable */
290 #define SEMA0REG 0x0c8a /* command semaphore */
291 #define SEMA1REG 0x0c8b /* status semaphore */
292 #define LDOORREG 0x0c8d /* local doorbell */
293 #define EDENABREG 0x0c8e /* EISA system doorbell enab. */
294 #define EDOORREG 0x0c8f /* EISA system doorbell */
295 #define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
296 #define EISAREG 0x0cc0 /* EISA configuration */
297
298 /* other defines */
299 #define LINUX_OS 8 /* used for cache optim. */
300 #define SECS32 0x1f /* round capacity */
301 #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
302 #define LOCALBOARD 0 /* board node always 0 */
303 #define ASYNCINDEX 0 /* cmd index async. event */
304 #define SPEZINDEX 1 /* cmd index unknown service */
305 #define COALINDEX (GDTH_MAXCMDS + 2)
306
307 /* features */
308 #define SCATTER_GATHER 1 /* s/g feature */
309 #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
310 #define GDT_64BIT 0x200 /* 64bit / drv>2TB support */
311
312 #include "gdth_ioctl.h"
313
314 /* screenservice message */
315 typedef struct {
316 u32 msg_handle; /* message handle */
317 u32 msg_len; /* size of message */
318 u32 msg_alen; /* answer length */
319 u8 msg_answer; /* answer flag */
320 u8 msg_ext; /* more messages */
321 u8 msg_reserved[2];
322 char msg_text[MSGLEN+2]; /* the message text */
323 } __attribute__((packed)) gdth_msg_str;
324
325
326 /* IOCTL data structures */
327
328 /* Status coalescing buffer for returning multiple requests per interrupt */
329 typedef struct {
330 u32 status;
331 u32 ext_status;
332 u32 info0;
333 u32 info1;
334 } __attribute__((packed)) gdth_coal_status;
335
336 /* performance mode data structure */
337 typedef struct {
338 u32 version; /* The version of this IOCTL structure. */
339 u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */
340 u32 st_buff_addr1; /* physical address of status buffer 1 */
341 u32 st_buff_u_addr1; /* reserved for 64 bit addressing */
342 u32 st_buff_indx1; /* reserved command idx. for this buffer */
343 u32 st_buff_addr2; /* physical address of status buffer 1 */
344 u32 st_buff_u_addr2; /* reserved for 64 bit addressing */
345 u32 st_buff_indx2; /* reserved command idx. for this buffer */
346 u32 st_buff_size; /* size of each buffer in bytes */
347 u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */
348 u32 cmd_buff_addr1; /* physical address of cmd buffer 1 */
349 u32 cmd_buff_u_addr1; /* reserved for 64 bit addressing */
350 u32 cmd_buff_indx1; /* cmd buf addr1 unique identifier */
351 u32 cmd_buff_addr2; /* physical address of cmd buffer 1 */
352 u32 cmd_buff_u_addr2; /* reserved for 64 bit addressing */
353 u32 cmd_buff_indx2; /* cmd buf addr1 unique identifier */
354 u32 cmd_buff_size; /* size of each cmd buffer in bytes */
355 u32 reserved1;
356 u32 reserved2;
357 } __attribute__((packed)) gdth_perf_modes;
358
359 /* SCSI drive info */
360 typedef struct {
361 u8 vendor[8]; /* vendor string */
362 u8 product[16]; /* product string */
363 u8 revision[4]; /* revision */
364 u32 sy_rate; /* current rate for sync. tr. */
365 u32 sy_max_rate; /* max. rate for sync. tr. */
366 u32 no_ldrive; /* belongs to this log. drv.*/
367 u32 blkcnt; /* number of blocks */
368 u16 blksize; /* size of block in bytes */
369 u8 available; /* flag: access is available */
370 u8 init; /* medium is initialized */
371 u8 devtype; /* SCSI devicetype */
372 u8 rm_medium; /* medium is removable */
373 u8 wp_medium; /* medium is write protected */
374 u8 ansi; /* SCSI I/II or III? */
375 u8 protocol; /* same as ansi */
376 u8 sync; /* flag: sync. transfer enab. */
377 u8 disc; /* flag: disconnect enabled */
378 u8 queueing; /* flag: command queing enab. */
379 u8 cached; /* flag: caching enabled */
380 u8 target_id; /* target ID of device */
381 u8 lun; /* LUN id of device */
382 u8 orphan; /* flag: drive fragment */
383 u32 last_error; /* sense key or drive state */
384 u32 last_result; /* result of last command */
385 u32 check_errors; /* err. in last surface check */
386 u8 percent; /* progress for surface check */
387 u8 last_check; /* IOCTRL operation */
388 u8 res[2];
389 u32 flags; /* from 1.19/2.19: raw reserv.*/
390 u8 multi_bus; /* multi bus dev? (fibre ch.) */
391 u8 mb_status; /* status: available? */
392 u8 res2[2];
393 u8 mb_alt_status; /* status on second bus */
394 u8 mb_alt_bid; /* number of second bus */
395 u8 mb_alt_tid; /* target id on second bus */
396 u8 res3;
397 u8 fc_flag; /* from 1.22/2.22: info valid?*/
398 u8 res4;
399 u16 fc_frame_size; /* frame size (bytes) */
400 char wwn[8]; /* world wide name */
401 } __attribute__((packed)) gdth_diskinfo_str;
402
403 /* get SCSI channel count */
404 typedef struct {
405 u32 channel_no; /* number of channel */
406 u32 drive_cnt; /* drive count */
407 u8 siop_id; /* SCSI processor ID */
408 u8 siop_state; /* SCSI processor state */
409 } __attribute__((packed)) gdth_getch_str;
410
411 /* get SCSI drive numbers */
412 typedef struct {
413 u32 sc_no; /* SCSI channel */
414 u32 sc_cnt; /* sc_list[] elements */
415 u32 sc_list[MAXID]; /* minor device numbers */
416 } __attribute__((packed)) gdth_drlist_str;
417
418 /* get grown/primary defect count */
419 typedef struct {
420 u8 sddc_type; /* 0x08: grown, 0x10: prim. */
421 u8 sddc_format; /* list entry format */
422 u8 sddc_len; /* list entry length */
423 u8 sddc_res;
424 u32 sddc_cnt; /* entry count */
425 } __attribute__((packed)) gdth_defcnt_str;
426
427 /* disk statistics */
428 typedef struct {
429 u32 bid; /* SCSI channel */
430 u32 first; /* first SCSI disk */
431 u32 entries; /* number of elements */
432 u32 count; /* (R) number of init. el. */
433 u32 mon_time; /* time stamp */
434 struct {
435 u8 tid; /* target ID */
436 u8 lun; /* LUN */
437 u8 res[2];
438 u32 blk_size; /* block size in bytes */
439 u32 rd_count; /* bytes read */
440 u32 wr_count; /* bytes written */
441 u32 rd_blk_count; /* blocks read */
442 u32 wr_blk_count; /* blocks written */
443 u32 retries; /* retries */
444 u32 reassigns; /* reassigns */
445 } __attribute__((packed)) list[1];
446 } __attribute__((packed)) gdth_dskstat_str;
447
448 /* IO channel header */
449 typedef struct {
450 u32 version; /* version (-1UL: newest) */
451 u8 list_entries; /* list entry count */
452 u8 first_chan; /* first channel number */
453 u8 last_chan; /* last channel number */
454 u8 chan_count; /* (R) channel count */
455 u32 list_offset; /* offset of list[0] */
456 } __attribute__((packed)) gdth_iochan_header;
457
458 /* get IO channel description */
459 typedef struct {
460 gdth_iochan_header hdr;
461 struct {
462 u32 address; /* channel address */
463 u8 type; /* type (SCSI, FCAL) */
464 u8 local_no; /* local number */
465 u16 features; /* channel features */
466 } __attribute__((packed)) list[MAXBUS];
467 } __attribute__((packed)) gdth_iochan_str;
468
469 /* get raw IO channel description */
470 typedef struct {
471 gdth_iochan_header hdr;
472 struct {
473 u8 proc_id; /* processor id */
474 u8 proc_defect; /* defect ? */
475 u8 reserved[2];
476 } __attribute__((packed)) list[MAXBUS];
477 } __attribute__((packed)) gdth_raw_iochan_str;
478
479 /* array drive component */
480 typedef struct {
481 u32 al_controller; /* controller ID */
482 u8 al_cache_drive; /* cache drive number */
483 u8 al_status; /* cache drive state */
484 u8 al_res[2];
485 } __attribute__((packed)) gdth_arraycomp_str;
486
487 /* array drive information */
488 typedef struct {
489 u8 ai_type; /* array type (RAID0,4,5) */
490 u8 ai_cache_drive_cnt; /* active cachedrives */
491 u8 ai_state; /* array drive state */
492 u8 ai_master_cd; /* master cachedrive */
493 u32 ai_master_controller; /* ID of master controller */
494 u32 ai_size; /* user capacity [sectors] */
495 u32 ai_striping_size; /* striping size [sectors] */
496 u32 ai_secsize; /* sector size [bytes] */
497 u32 ai_err_info; /* failed cache drive */
498 u8 ai_name[8]; /* name of the array drive */
499 u8 ai_controller_cnt; /* number of controllers */
500 u8 ai_removable; /* flag: removable */
501 u8 ai_write_protected; /* flag: write protected */
502 u8 ai_devtype; /* type: always direct access */
503 gdth_arraycomp_str ai_drives[35]; /* drive components: */
504 u8 ai_drive_entries; /* number of drive components */
505 u8 ai_protected; /* protection flag */
506 u8 ai_verify_state; /* state of a parity verify */
507 u8 ai_ext_state; /* extended array drive state */
508 u8 ai_expand_state; /* array expand state (>=2.18)*/
509 u8 ai_reserved[3];
510 } __attribute__((packed)) gdth_arrayinf_str;
511
512 /* get array drive list */
513 typedef struct {
514 u32 controller_no; /* controller no. */
515 u8 cd_handle; /* master cachedrive */
516 u8 is_arrayd; /* Flag: is array drive? */
517 u8 is_master; /* Flag: is array master? */
518 u8 is_parity; /* Flag: is parity drive? */
519 u8 is_hotfix; /* Flag: is hotfix drive? */
520 u8 res[3];
521 } __attribute__((packed)) gdth_alist_str;
522
523 typedef struct {
524 u32 entries_avail; /* allocated entries */
525 u32 entries_init; /* returned entries */
526 u32 first_entry; /* first entry number */
527 u32 list_offset; /* offset of following list */
528 gdth_alist_str list[1]; /* list */
529 } __attribute__((packed)) gdth_arcdl_str;
530
531 /* cache info/config IOCTL */
532 typedef struct {
533 u32 version; /* firmware version */
534 u16 state; /* cache state (on/off) */
535 u16 strategy; /* cache strategy */
536 u16 write_back; /* write back state (on/off) */
537 u16 block_size; /* cache block size */
538 } __attribute__((packed)) gdth_cpar_str;
539
540 typedef struct {
541 u32 csize; /* cache size */
542 u32 read_cnt; /* read/write counter */
543 u32 write_cnt;
544 u32 tr_hits; /* hits */
545 u32 sec_hits;
546 u32 sec_miss; /* misses */
547 } __attribute__((packed)) gdth_cstat_str;
548
549 typedef struct {
550 gdth_cpar_str cpar;
551 gdth_cstat_str cstat;
552 } __attribute__((packed)) gdth_cinfo_str;
553
554 /* cache drive info */
555 typedef struct {
556 u8 cd_name[8]; /* cache drive name */
557 u32 cd_devtype; /* SCSI devicetype */
558 u32 cd_ldcnt; /* number of log. drives */
559 u32 cd_last_error; /* last error */
560 u8 cd_initialized; /* drive is initialized */
561 u8 cd_removable; /* media is removable */
562 u8 cd_write_protected; /* write protected */
563 u8 cd_flags; /* Pool Hot Fix? */
564 u32 ld_blkcnt; /* number of blocks */
565 u32 ld_blksize; /* blocksize */
566 u32 ld_dcnt; /* number of disks */
567 u32 ld_slave; /* log. drive index */
568 u32 ld_dtype; /* type of logical drive */
569 u32 ld_last_error; /* last error */
570 u8 ld_name[8]; /* log. drive name */
571 u8 ld_error; /* error */
572 } __attribute__((packed)) gdth_cdrinfo_str;
573
574 /* OEM string */
575 typedef struct {
576 u32 ctl_version;
577 u32 file_major_version;
578 u32 file_minor_version;
579 u32 buffer_size;
580 u32 cpy_count;
581 u32 ext_error;
582 u32 oem_id;
583 u32 board_id;
584 } __attribute__((packed)) gdth_oem_str_params;
585
586 typedef struct {
587 u8 product_0_1_name[16];
588 u8 product_4_5_name[16];
589 u8 product_cluster_name[16];
590 u8 product_reserved[16];
591 u8 scsi_cluster_target_vendor_id[16];
592 u8 cluster_raid_fw_name[16];
593 u8 oem_brand_name[16];
594 u8 oem_raid_type[16];
595 u8 bios_type[13];
596 u8 bios_title[50];
597 u8 oem_company_name[37];
598 u32 pci_id_1;
599 u32 pci_id_2;
600 u8 validation_status[80];
601 u8 reserved_1[4];
602 u8 scsi_host_drive_inquiry_vendor_id[16];
603 u8 library_file_template[16];
604 u8 reserved_2[16];
605 u8 tool_name_1[32];
606 u8 tool_name_2[32];
607 u8 tool_name_3[32];
608 u8 oem_contact_1[84];
609 u8 oem_contact_2[84];
610 u8 oem_contact_3[84];
611 } __attribute__((packed)) gdth_oem_str;
612
613 typedef struct {
614 gdth_oem_str_params params;
615 gdth_oem_str text;
616 } __attribute__((packed)) gdth_oem_str_ioctl;
617
618 /* board features */
619 typedef struct {
620 u8 chaining; /* Chaining supported */
621 u8 striping; /* Striping (RAID-0) supp. */
622 u8 mirroring; /* Mirroring (RAID-1) supp. */
623 u8 raid; /* RAID-4/5/10 supported */
624 } __attribute__((packed)) gdth_bfeat_str;
625
626 /* board info IOCTL */
627 typedef struct {
628 u32 ser_no; /* serial no. */
629 u8 oem_id[2]; /* OEM ID */
630 u16 ep_flags; /* eprom flags */
631 u32 proc_id; /* processor ID */
632 u32 memsize; /* memory size (bytes) */
633 u8 mem_banks; /* memory banks */
634 u8 chan_type; /* channel type */
635 u8 chan_count; /* channel count */
636 u8 rdongle_pres; /* dongle present? */
637 u32 epr_fw_ver; /* (eprom) firmware version */
638 u32 upd_fw_ver; /* (update) firmware version */
639 u32 upd_revision; /* update revision */
640 char type_string[16]; /* controller name */
641 char raid_string[16]; /* RAID firmware name */
642 u8 update_pres; /* update present? */
643 u8 xor_pres; /* XOR engine present? */
644 u8 prom_type; /* ROM type (eprom/flash) */
645 u8 prom_count; /* number of ROM devices */
646 u32 dup_pres; /* duplexing module present? */
647 u32 chan_pres; /* number of expansion chn. */
648 u32 mem_pres; /* memory expansion inst. ? */
649 u8 ft_bus_system; /* fault bus supported? */
650 u8 subtype_valid; /* board_subtype valid? */
651 u8 board_subtype; /* subtype/hardware level */
652 u8 ramparity_pres; /* RAM parity check hardware? */
653 } __attribute__((packed)) gdth_binfo_str;
654
655 /* get host drive info */
656 typedef struct {
657 char name[8]; /* host drive name */
658 u32 size; /* size (sectors) */
659 u8 host_drive; /* host drive number */
660 u8 log_drive; /* log. drive (master) */
661 u8 reserved;
662 u8 rw_attribs; /* r/w attribs */
663 u32 start_sec; /* start sector */
664 } __attribute__((packed)) gdth_hentry_str;
665
666 typedef struct {
667 u32 entries; /* entry count */
668 u32 offset; /* offset of entries */
669 u8 secs_p_head; /* sectors/head */
670 u8 heads_p_cyl; /* heads/cylinder */
671 u8 reserved;
672 u8 clust_drvtype; /* cluster drive type */
673 u32 location; /* controller number */
674 gdth_hentry_str entry[MAX_HDRIVES]; /* entries */
675 } __attribute__((packed)) gdth_hget_str;
676
677
678 /* DPRAM structures */
679
680 /* interface area ISA/PCI */
681 typedef struct {
682 u8 S_Cmd_Indx; /* special command */
683 u8 volatile S_Status; /* status special command */
684 u16 reserved1;
685 u32 S_Info[4]; /* add. info special command */
686 u8 volatile Sema0; /* command semaphore */
687 u8 reserved2[3];
688 u8 Cmd_Index; /* command number */
689 u8 reserved3[3];
690 u16 volatile Status; /* command status */
691 u16 Service; /* service(for async.events) */
692 u32 Info[2]; /* additional info */
693 struct {
694 u16 offset; /* command offs. in the DPRAM*/
695 u16 serv_id; /* service */
696 } __attribute__((packed)) comm_queue[MAXOFFSETS]; /* command queue */
697 u32 bios_reserved[2];
698 u8 gdt_dpr_cmd[1]; /* commands */
699 } __attribute__((packed)) gdt_dpr_if;
700
701 /* SRAM structure PCI controllers */
702 typedef struct {
703 u32 magic; /* controller ID from BIOS */
704 u16 need_deinit; /* switch betw. BIOS/driver */
705 u8 switch_support; /* see need_deinit */
706 u8 padding[9];
707 u8 os_used[16]; /* OS code per service */
708 u8 unused[28];
709 u8 fw_magic; /* contr. ID from firmware */
710 } __attribute__((packed)) gdt_pci_sram;
711
712 /* SRAM structure EISA controllers (but NOT GDT3000/3020) */
713 typedef struct {
714 u8 os_used[16]; /* OS code per service */
715 u16 need_deinit; /* switch betw. BIOS/driver */
716 u8 switch_support; /* see need_deinit */
717 u8 padding;
718 } __attribute__((packed)) gdt_eisa_sram;
719
720
721 /* DPRAM ISA controllers */
722 typedef struct {
723 union {
724 struct {
725 u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
726 u32 magic; /* controller (EISA) ID */
727 u16 need_deinit; /* switch betw. BIOS/driver */
728 u8 switch_support; /* see need_deinit */
729 u8 padding[9];
730 u8 os_used[16]; /* OS code per service */
731 } __attribute__((packed)) dp_sram;
732 u8 bios_area[0x4000]; /* 16KB reserved for BIOS */
733 } bu;
734 union {
735 gdt_dpr_if ic; /* interface area */
736 u8 if_area[0x3000]; /* 12KB for interface */
737 } u;
738 struct {
739 u8 memlock; /* write protection DPRAM */
740 u8 event; /* release event */
741 u8 irqen; /* board interrupts enable */
742 u8 irqdel; /* acknowledge board int. */
743 u8 volatile Sema1; /* status semaphore */
744 u8 rq; /* IRQ/DRQ configuration */
745 } __attribute__((packed)) io;
746 } __attribute__((packed)) gdt2_dpram_str;
747
748 /* DPRAM PCI controllers */
749 typedef struct {
750 union {
751 gdt_dpr_if ic; /* interface area */
752 u8 if_area[0xff0-sizeof(gdt_pci_sram)];
753 } u;
754 gdt_pci_sram gdt6sr; /* SRAM structure */
755 struct {
756 u8 unused0[1];
757 u8 volatile Sema1; /* command semaphore */
758 u8 unused1[3];
759 u8 irqen; /* board interrupts enable */
760 u8 unused2[2];
761 u8 event; /* release event */
762 u8 unused3[3];
763 u8 irqdel; /* acknowledge board int. */
764 u8 unused4[3];
765 } __attribute__((packed)) io;
766 } __attribute__((packed)) gdt6_dpram_str;
767
768 /* PLX register structure (new PCI controllers) */
769 typedef struct {
770 u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
771 u8 unused1[0x3f];
772 u8 volatile sema0_reg; /* command semaphore */
773 u8 volatile sema1_reg; /* status semaphore */
774 u8 unused2[2];
775 u16 volatile status; /* command status */
776 u16 service; /* service */
777 u32 info[2]; /* additional info */
778 u8 unused3[0x10];
779 u8 ldoor_reg; /* PCI to local doorbell */
780 u8 unused4[3];
781 u8 volatile edoor_reg; /* local to PCI doorbell */
782 u8 unused5[3];
783 u8 control0; /* control0 register(unused) */
784 u8 control1; /* board interrupts enable */
785 u8 unused6[0x16];
786 } __attribute__((packed)) gdt6c_plx_regs;
787
788 /* DPRAM new PCI controllers */
789 typedef struct {
790 union {
791 gdt_dpr_if ic; /* interface area */
792 u8 if_area[0x4000-sizeof(gdt_pci_sram)];
793 } u;
794 gdt_pci_sram gdt6sr; /* SRAM structure */
795 } __attribute__((packed)) gdt6c_dpram_str;
796
797 /* i960 register structure (PCI MPR controllers) */
798 typedef struct {
799 u8 unused1[16];
800 u8 volatile sema0_reg; /* command semaphore */
801 u8 unused2;
802 u8 volatile sema1_reg; /* status semaphore */
803 u8 unused3;
804 u16 volatile status; /* command status */
805 u16 service; /* service */
806 u32 info[2]; /* additional info */
807 u8 ldoor_reg; /* PCI to local doorbell */
808 u8 unused4[11];
809 u8 volatile edoor_reg; /* local to PCI doorbell */
810 u8 unused5[7];
811 u8 edoor_en_reg; /* board interrupts enable */
812 u8 unused6[27];
813 u32 unused7[939];
814 u32 severity;
815 char evt_str[256]; /* event string */
816 } __attribute__((packed)) gdt6m_i960_regs;
817
818 /* DPRAM PCI MPR controllers */
819 typedef struct {
820 gdt6m_i960_regs i960r; /* 4KB i960 registers */
821 union {
822 gdt_dpr_if ic; /* interface area */
823 u8 if_area[0x3000-sizeof(gdt_pci_sram)];
824 } u;
825 gdt_pci_sram gdt6sr; /* SRAM structure */
826 } __attribute__((packed)) gdt6m_dpram_str;
827
828
829 /* PCI resources */
830 typedef struct {
831 struct pci_dev *pdev;
832 unsigned long dpmem; /* DPRAM address */
833 unsigned long io; /* IO address */
834 } gdth_pci_str;
835
836
837 /* controller information structure */
838 typedef struct {
839 struct Scsi_Host *shost;
840 struct list_head list;
841 u16 hanum;
842 u16 oem_id; /* OEM */
843 u16 type; /* controller class */
844 u32 stype; /* subtype (PCI: device ID) */
845 u16 fw_vers; /* firmware version */
846 u16 cache_feat; /* feat. cache serv. (s/g,..)*/
847 u16 raw_feat; /* feat. raw service (s/g,..)*/
848 u16 screen_feat; /* feat. raw service (s/g,..)*/
849 u16 bmic; /* BMIC address (EISA) */
850 void __iomem *brd; /* DPRAM address */
851 u32 brd_phys; /* slot number/BIOS address */
852 gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
853 gdth_cmd_str cmdext;
854 gdth_cmd_str *pccb; /* address command structure */
855 u32 ccb_phys; /* phys. address */
856 #ifdef INT_COAL
857 gdth_coal_status *coal_stat; /* buffer for coalescing int.*/
858 u64 coal_stat_phys; /* phys. address */
859 #endif
860 char *pscratch; /* scratch (DMA) buffer */
861 u64 scratch_phys; /* phys. address */
862 u8 scratch_busy; /* in use? */
863 u8 dma64_support; /* 64-bit DMA supported? */
864 gdth_msg_str *pmsg; /* message buffer */
865 u64 msg_phys; /* phys. address */
866 u8 scan_mode; /* current scan mode */
867 u8 irq; /* IRQ */
868 u8 drq; /* DRQ (ISA controllers) */
869 u16 status; /* command status */
870 u16 service; /* service/firmware ver./.. */
871 u32 info;
872 u32 info2; /* additional info */
873 Scsi_Cmnd *req_first; /* top of request queue */
874 struct {
875 u8 present; /* Flag: host drive present? */
876 u8 is_logdrv; /* Flag: log. drive (master)? */
877 u8 is_arraydrv; /* Flag: array drive? */
878 u8 is_master; /* Flag: array drive master? */
879 u8 is_parity; /* Flag: parity drive? */
880 u8 is_hotfix; /* Flag: hotfix drive? */
881 u8 master_no; /* number of master drive */
882 u8 lock; /* drive locked? (hot plug) */
883 u8 heads; /* mapping */
884 u8 secs;
885 u16 devtype; /* further information */
886 u64 size; /* capacity */
887 u8 ldr_no; /* log. drive no. */
888 u8 rw_attribs; /* r/w attributes */
889 u8 cluster_type; /* cluster properties */
890 u8 media_changed; /* Flag:MOUNT/UNMOUNT occurred */
891 u32 start_sec; /* start sector */
892 } hdr[MAX_LDRIVES]; /* host drives */
893 struct {
894 u8 lock; /* channel locked? (hot plug) */
895 u8 pdev_cnt; /* physical device count */
896 u8 local_no; /* local channel number */
897 u8 io_cnt[MAXID]; /* current IO count */
898 u32 address; /* channel address */
899 u32 id_list[MAXID]; /* IDs of the phys. devices */
900 } raw[MAXBUS]; /* SCSI channels */
901 struct {
902 Scsi_Cmnd *cmnd; /* pending request */
903 u16 service; /* service */
904 } cmd_tab[GDTH_MAXCMDS]; /* table of pend. requests */
905 struct gdth_cmndinfo { /* per-command private info */
906 int index;
907 int internal_command; /* don't call scsi_done */
908 gdth_cmd_str *internal_cmd_str; /* crier for internal messages*/
909 dma_addr_t sense_paddr; /* sense dma-addr */
910 u8 priority;
911 int timeout_count; /* # of timeout calls */
912 volatile int wait_for_completion;
913 u16 status;
914 u32 info;
915 enum dma_data_direction dma_dir;
916 int phase; /* ???? */
917 int OpCode;
918 } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */
919 u8 bus_cnt; /* SCSI bus count */
920 u8 tid_cnt; /* Target ID count */
921 u8 bus_id[MAXBUS]; /* IOP IDs */
922 u8 virt_bus; /* number of virtual bus */
923 u8 more_proc; /* more /proc info supported */
924 u16 cmd_cnt; /* command count in DPRAM */
925 u16 cmd_len; /* length of actual command */
926 u16 cmd_offs_dpmem; /* actual offset in DPRAM */
927 u16 ic_all_size; /* sizeof DPRAM interf. area */
928 gdth_cpar_str cpar; /* controller cache par. */
929 gdth_bfeat_str bfeat; /* controller features */
930 gdth_binfo_str binfo; /* controller info */
931 gdth_evt_data dvr; /* event structure */
932 spinlock_t smp_lock;
933 struct pci_dev *pdev;
934 char oem_name[8];
935 #ifdef GDTH_DMA_STATISTICS
936 unsigned long dma32_cnt, dma64_cnt; /* statistics: DMA buffer */
937 #endif
938 struct scsi_device *sdev;
939 } gdth_ha_str;
940
941 static inline struct gdth_cmndinfo *gdth_cmnd_priv(struct scsi_cmnd* cmd)
942 {
943 return (struct gdth_cmndinfo *)cmd->host_scribble;
944 }
945
946 /* INQUIRY data format */
947 typedef struct {
948 u8 type_qual;
949 u8 modif_rmb;
950 u8 version;
951 u8 resp_aenc;
952 u8 add_length;
953 u8 reserved1;
954 u8 reserved2;
955 u8 misc;
956 u8 vendor[8];
957 u8 product[16];
958 u8 revision[4];
959 } __attribute__((packed)) gdth_inq_data;
960
961 /* READ_CAPACITY data format */
962 typedef struct {
963 u32 last_block_no;
964 u32 block_length;
965 } __attribute__((packed)) gdth_rdcap_data;
966
967 /* READ_CAPACITY (16) data format */
968 typedef struct {
969 u64 last_block_no;
970 u32 block_length;
971 } __attribute__((packed)) gdth_rdcap16_data;
972
973 /* REQUEST_SENSE data format */
974 typedef struct {
975 u8 errorcode;
976 u8 segno;
977 u8 key;
978 u32 info;
979 u8 add_length;
980 u32 cmd_info;
981 u8 adsc;
982 u8 adsq;
983 u8 fruc;
984 u8 key_spec[3];
985 } __attribute__((packed)) gdth_sense_data;
986
987 /* MODE_SENSE data format */
988 typedef struct {
989 struct {
990 u8 data_length;
991 u8 med_type;
992 u8 dev_par;
993 u8 bd_length;
994 } __attribute__((packed)) hd;
995 struct {
996 u8 dens_code;
997 u8 block_count[3];
998 u8 reserved;
999 u8 block_length[3];
1000 } __attribute__((packed)) bd;
1001 } __attribute__((packed)) gdth_modep_data;
1002
1003 /* stack frame */
1004 typedef struct {
1005 unsigned long b[10]; /* 32/64 bit compiler ! */
1006 } __attribute__((packed)) gdth_stackframe;
1007
1008
1009 /* function prototyping */
1010
1011 int gdth_show_info(struct seq_file *, struct Scsi_Host *);
1012 int gdth_set_info(struct Scsi_Host *, char *, int);
1013
1014 #endif
Linux with added FPC-III support