mm: treewide: remove GFP_TEMPORARY allocation flag
[linux/fpc-iii.git] / drivers / gpu / drm / tegra / vic.c
blob2448229fa653b2b226fd6e9decb90f873dd10eed
1 /*
2 * Copyright (c) 2015, NVIDIA Corporation.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <linux/clk.h>
10 #include <linux/host1x.h>
11 #include <linux/iommu.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
20 #include <soc/tegra/pmc.h>
22 #include "drm.h"
23 #include "falcon.h"
24 #include "vic.h"
26 struct vic_config {
27 const char *firmware;
30 struct vic {
31 struct falcon falcon;
32 bool booted;
34 void __iomem *regs;
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
37 struct iommu_domain *domain;
38 struct device *dev;
39 struct clk *clk;
41 /* Platform configuration */
42 const struct vic_config *config;
45 static inline struct vic *to_vic(struct tegra_drm_client *client)
47 return container_of(client, struct vic, client);
50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
52 writel(value, vic->regs + offset);
55 static int vic_runtime_resume(struct device *dev)
57 struct vic *vic = dev_get_drvdata(dev);
59 return clk_prepare_enable(vic->clk);
62 static int vic_runtime_suspend(struct device *dev)
64 struct vic *vic = dev_get_drvdata(dev);
66 clk_disable_unprepare(vic->clk);
68 vic->booted = false;
70 return 0;
73 static int vic_boot(struct vic *vic)
75 u32 fce_ucode_size, fce_bin_data_offset;
76 void *hdr;
77 int err = 0;
79 if (vic->booted)
80 return 0;
82 /* setup clockgating registers */
83 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
84 CG_IDLE_CG_EN |
85 CG_WAKEUP_DLY_CNT(4),
86 NV_PVIC_MISC_PRI_VIC_CG);
88 err = falcon_boot(&vic->falcon);
89 if (err < 0)
90 return err;
92 hdr = vic->falcon.firmware.vaddr;
93 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
94 hdr = vic->falcon.firmware.vaddr +
95 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
96 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
98 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
99 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
100 fce_ucode_size);
101 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
102 (vic->falcon.firmware.paddr + fce_bin_data_offset)
103 >> 8);
105 err = falcon_wait_idle(&vic->falcon);
106 if (err < 0) {
107 dev_err(vic->dev,
108 "failed to set application ID and FCE base\n");
109 return err;
112 vic->booted = true;
114 return 0;
117 static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
118 dma_addr_t *iova)
120 struct tegra_drm *tegra = falcon->data;
122 return tegra_drm_alloc(tegra, size, iova);
125 static void vic_falcon_free(struct falcon *falcon, size_t size,
126 dma_addr_t iova, void *va)
128 struct tegra_drm *tegra = falcon->data;
130 return tegra_drm_free(tegra, size, va, iova);
133 static const struct falcon_ops vic_falcon_ops = {
134 .alloc = vic_falcon_alloc,
135 .free = vic_falcon_free
138 static int vic_init(struct host1x_client *client)
140 struct tegra_drm_client *drm = host1x_to_drm_client(client);
141 struct drm_device *dev = dev_get_drvdata(client->parent);
142 struct tegra_drm *tegra = dev->dev_private;
143 struct vic *vic = to_vic(drm);
144 int err;
146 if (tegra->domain) {
147 err = iommu_attach_device(tegra->domain, vic->dev);
148 if (err < 0) {
149 dev_err(vic->dev, "failed to attach to domain: %d\n",
150 err);
151 return err;
154 vic->domain = tegra->domain;
157 if (!vic->falcon.data) {
158 vic->falcon.data = tegra;
159 err = falcon_load_firmware(&vic->falcon);
160 if (err < 0)
161 goto detach_device;
164 vic->channel = host1x_channel_request(client->dev);
165 if (!vic->channel) {
166 err = -ENOMEM;
167 goto detach_device;
170 client->syncpts[0] = host1x_syncpt_request(client->dev, 0);
171 if (!client->syncpts[0]) {
172 err = -ENOMEM;
173 goto free_channel;
176 err = tegra_drm_register_client(tegra, drm);
177 if (err < 0)
178 goto free_syncpt;
180 return 0;
182 free_syncpt:
183 host1x_syncpt_free(client->syncpts[0]);
184 free_channel:
185 host1x_channel_put(vic->channel);
186 detach_device:
187 if (tegra->domain)
188 iommu_detach_device(tegra->domain, vic->dev);
190 return err;
193 static int vic_exit(struct host1x_client *client)
195 struct tegra_drm_client *drm = host1x_to_drm_client(client);
196 struct drm_device *dev = dev_get_drvdata(client->parent);
197 struct tegra_drm *tegra = dev->dev_private;
198 struct vic *vic = to_vic(drm);
199 int err;
201 err = tegra_drm_unregister_client(tegra, drm);
202 if (err < 0)
203 return err;
205 host1x_syncpt_free(client->syncpts[0]);
206 host1x_channel_put(vic->channel);
208 if (vic->domain) {
209 iommu_detach_device(vic->domain, vic->dev);
210 vic->domain = NULL;
213 return 0;
216 static const struct host1x_client_ops vic_client_ops = {
217 .init = vic_init,
218 .exit = vic_exit,
221 static int vic_open_channel(struct tegra_drm_client *client,
222 struct tegra_drm_context *context)
224 struct vic *vic = to_vic(client);
225 int err;
227 err = pm_runtime_get_sync(vic->dev);
228 if (err < 0)
229 return err;
231 err = vic_boot(vic);
232 if (err < 0) {
233 pm_runtime_put(vic->dev);
234 return err;
237 context->channel = host1x_channel_get(vic->channel);
238 if (!context->channel) {
239 pm_runtime_put(vic->dev);
240 return -ENOMEM;
243 return 0;
246 static void vic_close_channel(struct tegra_drm_context *context)
248 struct vic *vic = to_vic(context->client);
250 host1x_channel_put(context->channel);
252 pm_runtime_put(vic->dev);
255 static const struct tegra_drm_client_ops vic_ops = {
256 .open_channel = vic_open_channel,
257 .close_channel = vic_close_channel,
258 .submit = tegra_drm_submit,
261 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
263 static const struct vic_config vic_t124_config = {
264 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
267 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
269 static const struct vic_config vic_t210_config = {
270 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
273 static const struct of_device_id vic_match[] = {
274 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
275 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
276 { },
279 static int vic_probe(struct platform_device *pdev)
281 struct vic_config *vic_config = NULL;
282 struct device *dev = &pdev->dev;
283 struct host1x_syncpt **syncpts;
284 struct resource *regs;
285 const struct of_device_id *match;
286 struct vic *vic;
287 int err;
289 match = of_match_device(vic_match, dev);
290 vic_config = (struct vic_config *)match->data;
292 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
293 if (!vic)
294 return -ENOMEM;
296 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
297 if (!syncpts)
298 return -ENOMEM;
300 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301 if (!regs) {
302 dev_err(&pdev->dev, "failed to get registers\n");
303 return -ENXIO;
306 vic->regs = devm_ioremap_resource(dev, regs);
307 if (IS_ERR(vic->regs))
308 return PTR_ERR(vic->regs);
310 vic->clk = devm_clk_get(dev, NULL);
311 if (IS_ERR(vic->clk)) {
312 dev_err(&pdev->dev, "failed to get clock\n");
313 return PTR_ERR(vic->clk);
316 vic->falcon.dev = dev;
317 vic->falcon.regs = vic->regs;
318 vic->falcon.ops = &vic_falcon_ops;
320 err = falcon_init(&vic->falcon);
321 if (err < 0)
322 return err;
324 err = falcon_read_firmware(&vic->falcon, vic_config->firmware);
325 if (err < 0)
326 goto exit_falcon;
328 platform_set_drvdata(pdev, vic);
330 INIT_LIST_HEAD(&vic->client.base.list);
331 vic->client.base.ops = &vic_client_ops;
332 vic->client.base.dev = dev;
333 vic->client.base.class = HOST1X_CLASS_VIC;
334 vic->client.base.syncpts = syncpts;
335 vic->client.base.num_syncpts = 1;
336 vic->dev = dev;
337 vic->config = vic_config;
339 INIT_LIST_HEAD(&vic->client.list);
340 vic->client.ops = &vic_ops;
342 err = host1x_client_register(&vic->client.base);
343 if (err < 0) {
344 dev_err(dev, "failed to register host1x client: %d\n", err);
345 platform_set_drvdata(pdev, NULL);
346 goto exit_falcon;
349 pm_runtime_enable(&pdev->dev);
350 if (!pm_runtime_enabled(&pdev->dev)) {
351 err = vic_runtime_resume(&pdev->dev);
352 if (err < 0)
353 goto unregister_client;
356 return 0;
358 unregister_client:
359 host1x_client_unregister(&vic->client.base);
360 exit_falcon:
361 falcon_exit(&vic->falcon);
363 return err;
366 static int vic_remove(struct platform_device *pdev)
368 struct vic *vic = platform_get_drvdata(pdev);
369 int err;
371 err = host1x_client_unregister(&vic->client.base);
372 if (err < 0) {
373 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
374 err);
375 return err;
378 if (pm_runtime_enabled(&pdev->dev))
379 pm_runtime_disable(&pdev->dev);
380 else
381 vic_runtime_suspend(&pdev->dev);
383 falcon_exit(&vic->falcon);
385 return 0;
388 static const struct dev_pm_ops vic_pm_ops = {
389 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
392 struct platform_driver tegra_vic_driver = {
393 .driver = {
394 .name = "tegra-vic",
395 .of_match_table = vic_match,
396 .pm = &vic_pm_ops
398 .probe = vic_probe,
399 .remove = vic_remove,
402 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
403 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
404 #endif
405 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
406 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
407 #endif