2 * MPC5200 General Purpose Timer device driver
4 * Copyright (c) 2009 Secret Lab Technologies Ltd.
5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This file is a driver for the the General Purpose Timer (gpt) devices
13 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
14 * for GPIO or can be used to raise interrupts. The timer function can
15 * be used independently from the IO pin, or it can be used to control
16 * output signals or measure input signals.
18 * This driver supports the GPIO and IRQ controller functions of the GPT
19 * device. Timer functions are not yet supported.
21 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
22 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
23 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
24 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
25 * this means that gpt0 is locked in wdt mode until the next reboot - this
26 * may be a requirement in safety applications.
28 * To use the GPIO function, the following two properties must be added
29 * to the device tree node for the gpt device (typically in the .dts file
32 * #gpio-cells = < 2 >;
33 * This driver will register the GPIO pin if it finds the gpio-controller
34 * property in the device tree.
36 * To use the IRQ controller function, the following two properties must
37 * be added to the device tree node for the gpt device:
38 * interrupt-controller;
39 * #interrupt-cells = < 1 >;
40 * The IRQ controller binding only uses one cell to specify the interrupt,
41 * and the IRQ flags are encoded in the cell. A cell is not used to encode
42 * the IRQ number because the GPT only has a single IRQ source. For flags,
43 * a value of '1' means rising edge sensitive and '2' means falling edge.
45 * The GPIO and the IRQ controller functions can be used at the same time,
46 * but in this use case the IO line will only work as an input. Trying to
47 * use it as a GPIO output will not work.
49 * When using the GPIO line as an output, it can either be driven as normal
50 * IO, or it can be an Open Collector (OC) output. At the moment it is the
51 * responsibility of either the bootloader or the platform setup code to set
52 * the output mode. This driver does not change the output mode setting.
55 #include <linux/device.h>
56 #include <linux/irq.h>
57 #include <linux/interrupt.h>
59 #include <linux/list.h>
60 #include <linux/mutex.h>
62 #include <linux/of_platform.h>
63 #include <linux/of_gpio.h>
64 #include <linux/kernel.h>
65 #include <linux/slab.h>
67 #include <linux/watchdog.h>
68 #include <linux/miscdevice.h>
69 #include <linux/uaccess.h>
70 #include <linux/module.h>
71 #include <asm/div64.h>
72 #include <asm/mpc52xx.h>
74 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
75 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
76 MODULE_LICENSE("GPL");
79 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
80 * @dev: pointer to device structure
81 * @regs: virtual address of GPT registers
82 * @lock: spinlock to coordinate between different functions.
83 * @gc: gpio_chip instance structure; used when GPIO is enabled
84 * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
85 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
86 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
87 * if the timer is actively used as wdt which blocks gpt functions
89 struct mpc52xx_gpt_priv
{
90 struct list_head list
; /* List of all GPT devices */
92 struct mpc52xx_gpt __iomem
*regs
;
94 struct irq_domain
*irqhost
;
98 #if defined(CONFIG_GPIOLIB)
103 LIST_HEAD(mpc52xx_gpt_list
);
104 DEFINE_MUTEX(mpc52xx_gpt_list_mutex
);
106 #define MPC52xx_GPT_MODE_MS_MASK (0x07)
107 #define MPC52xx_GPT_MODE_MS_IC (0x01)
108 #define MPC52xx_GPT_MODE_MS_OC (0x02)
109 #define MPC52xx_GPT_MODE_MS_PWM (0x03)
110 #define MPC52xx_GPT_MODE_MS_GPIO (0x04)
112 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
113 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
114 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
116 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
117 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
118 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
119 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
120 #define MPC52xx_GPT_MODE_WDT_EN (0x8000)
122 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
123 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
124 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
125 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
127 #define MPC52xx_GPT_MODE_WDT_PING (0xa5)
129 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
131 #define MPC52xx_GPT_CAN_WDT (1 << 0)
132 #define MPC52xx_GPT_IS_WDT (1 << 1)
135 /* ---------------------------------------------------------------------
136 * Cascaded interrupt controller hooks
139 static void mpc52xx_gpt_irq_unmask(struct irq_data
*d
)
141 struct mpc52xx_gpt_priv
*gpt
= irq_data_get_irq_chip_data(d
);
144 spin_lock_irqsave(&gpt
->lock
, flags
);
145 setbits32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_IRQ_EN
);
146 spin_unlock_irqrestore(&gpt
->lock
, flags
);
149 static void mpc52xx_gpt_irq_mask(struct irq_data
*d
)
151 struct mpc52xx_gpt_priv
*gpt
= irq_data_get_irq_chip_data(d
);
154 spin_lock_irqsave(&gpt
->lock
, flags
);
155 clrbits32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_IRQ_EN
);
156 spin_unlock_irqrestore(&gpt
->lock
, flags
);
159 static void mpc52xx_gpt_irq_ack(struct irq_data
*d
)
161 struct mpc52xx_gpt_priv
*gpt
= irq_data_get_irq_chip_data(d
);
163 out_be32(&gpt
->regs
->status
, MPC52xx_GPT_STATUS_IRQMASK
);
166 static int mpc52xx_gpt_irq_set_type(struct irq_data
*d
, unsigned int flow_type
)
168 struct mpc52xx_gpt_priv
*gpt
= irq_data_get_irq_chip_data(d
);
172 dev_dbg(gpt
->dev
, "%s: virq=%i type=%x\n", __func__
, d
->irq
, flow_type
);
174 spin_lock_irqsave(&gpt
->lock
, flags
);
175 reg
= in_be32(&gpt
->regs
->mode
) & ~MPC52xx_GPT_MODE_ICT_MASK
;
176 if (flow_type
& IRQF_TRIGGER_RISING
)
177 reg
|= MPC52xx_GPT_MODE_ICT_RISING
;
178 if (flow_type
& IRQF_TRIGGER_FALLING
)
179 reg
|= MPC52xx_GPT_MODE_ICT_FALLING
;
180 out_be32(&gpt
->regs
->mode
, reg
);
181 spin_unlock_irqrestore(&gpt
->lock
, flags
);
186 static struct irq_chip mpc52xx_gpt_irq_chip
= {
187 .name
= "MPC52xx GPT",
188 .irq_unmask
= mpc52xx_gpt_irq_unmask
,
189 .irq_mask
= mpc52xx_gpt_irq_mask
,
190 .irq_ack
= mpc52xx_gpt_irq_ack
,
191 .irq_set_type
= mpc52xx_gpt_irq_set_type
,
194 static void mpc52xx_gpt_irq_cascade(struct irq_desc
*desc
)
196 struct mpc52xx_gpt_priv
*gpt
= irq_desc_get_handler_data(desc
);
200 status
= in_be32(&gpt
->regs
->status
) & MPC52xx_GPT_STATUS_IRQMASK
;
202 sub_virq
= irq_linear_revmap(gpt
->irqhost
, 0);
203 generic_handle_irq(sub_virq
);
207 static int mpc52xx_gpt_irq_map(struct irq_domain
*h
, unsigned int virq
,
210 struct mpc52xx_gpt_priv
*gpt
= h
->host_data
;
212 dev_dbg(gpt
->dev
, "%s: h=%p, virq=%i\n", __func__
, h
, virq
);
213 irq_set_chip_data(virq
, gpt
);
214 irq_set_chip_and_handler(virq
, &mpc52xx_gpt_irq_chip
, handle_edge_irq
);
219 static int mpc52xx_gpt_irq_xlate(struct irq_domain
*h
, struct device_node
*ct
,
220 const u32
*intspec
, unsigned int intsize
,
221 irq_hw_number_t
*out_hwirq
,
222 unsigned int *out_flags
)
224 struct mpc52xx_gpt_priv
*gpt
= h
->host_data
;
226 dev_dbg(gpt
->dev
, "%s: flags=%i\n", __func__
, intspec
[0]);
228 if ((intsize
< 1) || (intspec
[0] > 3)) {
229 dev_err(gpt
->dev
, "bad irq specifier in %s\n", ct
->full_name
);
233 *out_hwirq
= 0; /* The GPT only has 1 IRQ line */
234 *out_flags
= intspec
[0];
239 static const struct irq_domain_ops mpc52xx_gpt_irq_ops
= {
240 .map
= mpc52xx_gpt_irq_map
,
241 .xlate
= mpc52xx_gpt_irq_xlate
,
245 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv
*gpt
, struct device_node
*node
)
251 cascade_virq
= irq_of_parse_and_map(node
, 0);
255 gpt
->irqhost
= irq_domain_add_linear(node
, 1, &mpc52xx_gpt_irq_ops
, gpt
);
257 dev_err(gpt
->dev
, "irq_domain_add_linear() failed\n");
261 irq_set_handler_data(cascade_virq
, gpt
);
262 irq_set_chained_handler(cascade_virq
, mpc52xx_gpt_irq_cascade
);
264 /* If the GPT is currently disabled, then change it to be in Input
265 * Capture mode. If the mode is non-zero, then the pin could be
266 * already in use for something. */
267 spin_lock_irqsave(&gpt
->lock
, flags
);
268 mode
= in_be32(&gpt
->regs
->mode
);
269 if ((mode
& MPC52xx_GPT_MODE_MS_MASK
) == 0)
270 out_be32(&gpt
->regs
->mode
, mode
| MPC52xx_GPT_MODE_MS_IC
);
271 spin_unlock_irqrestore(&gpt
->lock
, flags
);
273 dev_dbg(gpt
->dev
, "%s() complete. virq=%i\n", __func__
, cascade_virq
);
277 /* ---------------------------------------------------------------------
280 #if defined(CONFIG_GPIOLIB)
281 static int mpc52xx_gpt_gpio_get(struct gpio_chip
*gc
, unsigned int gpio
)
283 struct mpc52xx_gpt_priv
*gpt
= gpiochip_get_data(gc
);
285 return (in_be32(&gpt
->regs
->status
) >> 8) & 1;
289 mpc52xx_gpt_gpio_set(struct gpio_chip
*gc
, unsigned int gpio
, int v
)
291 struct mpc52xx_gpt_priv
*gpt
= gpiochip_get_data(gc
);
295 dev_dbg(gpt
->dev
, "%s: gpio:%d v:%d\n", __func__
, gpio
, v
);
296 r
= v
? MPC52xx_GPT_MODE_GPIO_OUT_HIGH
: MPC52xx_GPT_MODE_GPIO_OUT_LOW
;
298 spin_lock_irqsave(&gpt
->lock
, flags
);
299 clrsetbits_be32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_GPIO_MASK
, r
);
300 spin_unlock_irqrestore(&gpt
->lock
, flags
);
303 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip
*gc
, unsigned int gpio
)
305 struct mpc52xx_gpt_priv
*gpt
= gpiochip_get_data(gc
);
308 dev_dbg(gpt
->dev
, "%s: gpio:%d\n", __func__
, gpio
);
310 spin_lock_irqsave(&gpt
->lock
, flags
);
311 clrbits32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_GPIO_MASK
);
312 spin_unlock_irqrestore(&gpt
->lock
, flags
);
318 mpc52xx_gpt_gpio_dir_out(struct gpio_chip
*gc
, unsigned int gpio
, int val
)
320 mpc52xx_gpt_gpio_set(gc
, gpio
, val
);
325 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv
*gpt
, struct device_node
*node
)
329 /* Only setup GPIO if the device tree claims the GPT is
330 * a GPIO controller */
331 if (!of_find_property(node
, "gpio-controller", NULL
))
334 gpt
->gc
.label
= kstrdup(node
->full_name
, GFP_KERNEL
);
335 if (!gpt
->gc
.label
) {
336 dev_err(gpt
->dev
, "out of memory\n");
341 gpt
->gc
.direction_input
= mpc52xx_gpt_gpio_dir_in
;
342 gpt
->gc
.direction_output
= mpc52xx_gpt_gpio_dir_out
;
343 gpt
->gc
.get
= mpc52xx_gpt_gpio_get
;
344 gpt
->gc
.set
= mpc52xx_gpt_gpio_set
;
346 gpt
->gc
.of_node
= node
;
348 /* Setup external pin in GPIO mode */
349 clrsetbits_be32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_MS_MASK
,
350 MPC52xx_GPT_MODE_MS_GPIO
);
352 rc
= gpiochip_add_data(&gpt
->gc
, gpt
);
354 dev_err(gpt
->dev
, "gpiochip_add_data() failed; rc=%i\n", rc
);
356 dev_dbg(gpt
->dev
, "%s() complete.\n", __func__
);
358 #else /* defined(CONFIG_GPIOLIB) */
360 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv
*p
, struct device_node
*np
) { }
361 #endif /* defined(CONFIG_GPIOLIB) */
363 /***********************************************************************
368 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
369 * @irq: irq of timer.
371 struct mpc52xx_gpt_priv
*mpc52xx_gpt_from_irq(int irq
)
373 struct mpc52xx_gpt_priv
*gpt
;
374 struct list_head
*pos
;
376 /* Iterate over the list of timers looking for a matching device */
377 mutex_lock(&mpc52xx_gpt_list_mutex
);
378 list_for_each(pos
, &mpc52xx_gpt_list
) {
379 gpt
= container_of(pos
, struct mpc52xx_gpt_priv
, list
);
380 if (gpt
->irqhost
&& irq
== irq_linear_revmap(gpt
->irqhost
, 0)) {
381 mutex_unlock(&mpc52xx_gpt_list_mutex
);
385 mutex_unlock(&mpc52xx_gpt_list_mutex
);
389 EXPORT_SYMBOL(mpc52xx_gpt_from_irq
);
391 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv
*gpt
, u64 period
,
392 int continuous
, int as_wdt
)
399 clear
= MPC52xx_GPT_MODE_MS_MASK
| MPC52xx_GPT_MODE_CONTINUOUS
;
400 set
= MPC52xx_GPT_MODE_MS_GPIO
| MPC52xx_GPT_MODE_COUNTER_ENABLE
;
402 clear
|= MPC52xx_GPT_MODE_IRQ_EN
;
403 set
|= MPC52xx_GPT_MODE_WDT_EN
;
404 } else if (continuous
)
405 set
|= MPC52xx_GPT_MODE_CONTINUOUS
;
407 /* Determine the number of clocks in the requested period. 64 bit
408 * arithmatic is done here to preserve the precision until the value
409 * is scaled back down into the u32 range. Period is in 'ns', bus
410 * frequency is in Hz. */
411 clocks
= period
* (u64
)gpt
->ipb_freq
;
412 do_div(clocks
, 1000000000); /* Scale it down to ns range */
414 /* This device cannot handle a clock count greater than 32 bits */
415 if (clocks
> 0xffffffff)
418 /* Calculate the prescaler and count values from the clocks value.
419 * 'clocks' is the number of clock ticks in the period. The timer
420 * has 16 bit precision and a 16 bit prescaler. Prescaler is
421 * calculated by integer dividing the clocks by 0x10000 (shifting
422 * down 16 bits) to obtain the smallest possible divisor for clocks
423 * to get a 16 bit count value.
425 * Note: the prescale register is '1' based, not '0' based. ie. a
426 * value of '1' means divide the clock by one. 0xffff divides the
427 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
428 * around and divides by 0x10000. That is why prescale must be
429 * a u32 variable, not a u16, for this calculation. */
430 prescale
= (clocks
>> 16) + 1;
431 do_div(clocks
, prescale
);
432 if (clocks
> 0xffff) {
433 pr_err("calculation error; prescale:%x clocks:%llx\n",
438 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
439 spin_lock_irqsave(&gpt
->lock
, flags
);
441 gpt
->wdt_mode
|= MPC52xx_GPT_IS_WDT
;
442 else if ((gpt
->wdt_mode
& MPC52xx_GPT_IS_WDT
) != 0) {
443 spin_unlock_irqrestore(&gpt
->lock
, flags
);
446 out_be32(&gpt
->regs
->count
, prescale
<< 16 | clocks
);
447 clrsetbits_be32(&gpt
->regs
->mode
, clear
, set
);
448 spin_unlock_irqrestore(&gpt
->lock
, flags
);
454 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
455 * @gpt: Pointer to gpt private data structure
456 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
457 * @continuous: set to 1 to make timer continuous free running
459 * An interrupt will be generated every time the timer fires
461 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv
*gpt
, u64 period
,
464 return mpc52xx_gpt_do_start(gpt
, period
, continuous
, 0);
466 EXPORT_SYMBOL(mpc52xx_gpt_start_timer
);
469 * mpc52xx_gpt_stop_timer - Stop a gpt
470 * @gpt: Pointer to gpt private data structure
472 * Returns an error if attempting to stop a wdt
474 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv
*gpt
)
478 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
479 spin_lock_irqsave(&gpt
->lock
, flags
);
480 if ((gpt
->wdt_mode
& MPC52xx_GPT_IS_WDT
) != 0) {
481 spin_unlock_irqrestore(&gpt
->lock
, flags
);
485 clrbits32(&gpt
->regs
->mode
, MPC52xx_GPT_MODE_COUNTER_ENABLE
);
486 spin_unlock_irqrestore(&gpt
->lock
, flags
);
489 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer
);
492 * mpc52xx_gpt_timer_period - Read the timer period
493 * @gpt: Pointer to gpt private data structure
495 * Returns the timer period in ns
497 u64
mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv
*gpt
)
503 spin_lock_irqsave(&gpt
->lock
, flags
);
504 period
= in_be32(&gpt
->regs
->count
);
505 spin_unlock_irqrestore(&gpt
->lock
, flags
);
507 prescale
= period
>> 16;
511 period
= period
* prescale
* 1000000000ULL;
512 do_div(period
, (u64
)gpt
->ipb_freq
);
515 EXPORT_SYMBOL(mpc52xx_gpt_timer_period
);
517 #if defined(CONFIG_MPC5200_WDT)
518 /***********************************************************************
519 * Watchdog API for gpt0
522 #define WDT_IDENTITY "mpc52xx watchdog on GPT0"
524 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
525 static unsigned long wdt_is_active
;
527 /* wdt-capable gpt */
528 static struct mpc52xx_gpt_priv
*mpc52xx_gpt_wdt
;
530 /* low-level wdt functions */
531 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv
*gpt_wdt
)
535 spin_lock_irqsave(&gpt_wdt
->lock
, flags
);
536 out_8((u8
*) &gpt_wdt
->regs
->mode
, MPC52xx_GPT_MODE_WDT_PING
);
537 spin_unlock_irqrestore(&gpt_wdt
->lock
, flags
);
540 /* wdt misc device api */
541 static ssize_t
mpc52xx_wdt_write(struct file
*file
, const char __user
*data
,
542 size_t len
, loff_t
*ppos
)
544 struct mpc52xx_gpt_priv
*gpt_wdt
= file
->private_data
;
545 mpc52xx_gpt_wdt_ping(gpt_wdt
);
549 static const struct watchdog_info mpc5200_wdt_info
= {
550 .options
= WDIOF_SETTIMEOUT
| WDIOF_KEEPALIVEPING
,
551 .identity
= WDT_IDENTITY
,
554 static long mpc52xx_wdt_ioctl(struct file
*file
, unsigned int cmd
,
557 struct mpc52xx_gpt_priv
*gpt_wdt
= file
->private_data
;
558 int __user
*data
= (int __user
*)arg
;
564 case WDIOC_GETSUPPORT
:
565 ret
= copy_to_user(data
, &mpc5200_wdt_info
,
566 sizeof(mpc5200_wdt_info
));
571 case WDIOC_GETSTATUS
:
572 case WDIOC_GETBOOTSTATUS
:
573 ret
= put_user(0, data
);
576 case WDIOC_KEEPALIVE
:
577 mpc52xx_gpt_wdt_ping(gpt_wdt
);
580 case WDIOC_SETTIMEOUT
:
581 ret
= get_user(timeout
, data
);
584 real_timeout
= (u64
) timeout
* 1000000000ULL;
585 ret
= mpc52xx_gpt_do_start(gpt_wdt
, real_timeout
, 0, 1);
588 /* fall through and return the timeout */
590 case WDIOC_GETTIMEOUT
:
591 /* we need to round here as to avoid e.g. the following
593 * - timeout requested is 1 second;
594 * - real timeout @33MHz is 999997090ns
595 * - the int divide by 10^9 will return 0.
598 mpc52xx_gpt_timer_period(gpt_wdt
) + 500000000ULL;
599 do_div(real_timeout
, 1000000000ULL);
600 timeout
= (int) real_timeout
;
601 ret
= put_user(timeout
, data
);
610 static int mpc52xx_wdt_open(struct inode
*inode
, struct file
*file
)
615 if (!mpc52xx_gpt_wdt
)
618 /* /dev/watchdog can only be opened once */
619 if (test_and_set_bit(0, &wdt_is_active
))
622 /* Set and activate the watchdog with 30 seconds timeout */
623 ret
= mpc52xx_gpt_do_start(mpc52xx_gpt_wdt
, 30ULL * 1000000000ULL,
626 clear_bit(0, &wdt_is_active
);
630 file
->private_data
= mpc52xx_gpt_wdt
;
631 return nonseekable_open(inode
, file
);
634 static int mpc52xx_wdt_release(struct inode
*inode
, struct file
*file
)
636 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
637 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
638 struct mpc52xx_gpt_priv
*gpt_wdt
= file
->private_data
;
641 spin_lock_irqsave(&gpt_wdt
->lock
, flags
);
642 clrbits32(&gpt_wdt
->regs
->mode
,
643 MPC52xx_GPT_MODE_COUNTER_ENABLE
| MPC52xx_GPT_MODE_WDT_EN
);
644 gpt_wdt
->wdt_mode
&= ~MPC52xx_GPT_IS_WDT
;
645 spin_unlock_irqrestore(&gpt_wdt
->lock
, flags
);
647 clear_bit(0, &wdt_is_active
);
652 static const struct file_operations mpc52xx_wdt_fops
= {
653 .owner
= THIS_MODULE
,
655 .write
= mpc52xx_wdt_write
,
656 .unlocked_ioctl
= mpc52xx_wdt_ioctl
,
657 .open
= mpc52xx_wdt_open
,
658 .release
= mpc52xx_wdt_release
,
661 static struct miscdevice mpc52xx_wdt_miscdev
= {
662 .minor
= WATCHDOG_MINOR
,
664 .fops
= &mpc52xx_wdt_fops
,
667 static int mpc52xx_gpt_wdt_init(void)
671 /* try to register the watchdog misc device */
672 err
= misc_register(&mpc52xx_wdt_miscdev
);
674 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY
);
676 pr_info("%s: watchdog device registered\n", WDT_IDENTITY
);
680 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv
*gpt
,
685 /* remember the gpt for the wdt operation */
686 mpc52xx_gpt_wdt
= gpt
;
688 /* configure the wdt if the device tree contained a timeout */
689 if (!period
|| *period
== 0)
692 real_timeout
= (u64
) *period
* 1000000000ULL;
693 if (mpc52xx_gpt_do_start(gpt
, real_timeout
, 0, 1))
694 dev_warn(gpt
->dev
, "starting as wdt failed\n");
696 dev_info(gpt
->dev
, "watchdog set to %us timeout\n", *period
);
702 static int mpc52xx_gpt_wdt_init(void)
707 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv
*gpt
,
713 #endif /* CONFIG_MPC5200_WDT */
715 /* ---------------------------------------------------------------------
716 * of_platform bus binding code
718 static int mpc52xx_gpt_probe(struct platform_device
*ofdev
)
720 struct mpc52xx_gpt_priv
*gpt
;
722 gpt
= devm_kzalloc(&ofdev
->dev
, sizeof *gpt
, GFP_KERNEL
);
726 spin_lock_init(&gpt
->lock
);
727 gpt
->dev
= &ofdev
->dev
;
728 gpt
->ipb_freq
= mpc5xxx_get_bus_frequency(ofdev
->dev
.of_node
);
729 gpt
->regs
= of_iomap(ofdev
->dev
.of_node
, 0);
733 dev_set_drvdata(&ofdev
->dev
, gpt
);
735 mpc52xx_gpt_gpio_setup(gpt
, ofdev
->dev
.of_node
);
736 mpc52xx_gpt_irq_setup(gpt
, ofdev
->dev
.of_node
);
738 mutex_lock(&mpc52xx_gpt_list_mutex
);
739 list_add(&gpt
->list
, &mpc52xx_gpt_list
);
740 mutex_unlock(&mpc52xx_gpt_list_mutex
);
742 /* check if this device could be a watchdog */
743 if (of_get_property(ofdev
->dev
.of_node
, "fsl,has-wdt", NULL
) ||
744 of_get_property(ofdev
->dev
.of_node
, "has-wdt", NULL
)) {
745 const u32
*on_boot_wdt
;
747 gpt
->wdt_mode
= MPC52xx_GPT_CAN_WDT
;
748 on_boot_wdt
= of_get_property(ofdev
->dev
.of_node
,
749 "fsl,wdt-on-boot", NULL
);
751 dev_info(gpt
->dev
, "used as watchdog\n");
752 gpt
->wdt_mode
|= MPC52xx_GPT_IS_WDT
;
754 dev_info(gpt
->dev
, "can function as watchdog\n");
755 mpc52xx_gpt_wdt_setup(gpt
, on_boot_wdt
);
761 static int mpc52xx_gpt_remove(struct platform_device
*ofdev
)
766 static const struct of_device_id mpc52xx_gpt_match
[] = {
767 { .compatible
= "fsl,mpc5200-gpt", },
769 /* Depreciated compatible values; don't use for new dts files */
770 { .compatible
= "fsl,mpc5200-gpt-gpio", },
771 { .compatible
= "mpc5200-gpt", },
775 static struct platform_driver mpc52xx_gpt_driver
= {
777 .name
= "mpc52xx-gpt",
778 .of_match_table
= mpc52xx_gpt_match
,
780 .probe
= mpc52xx_gpt_probe
,
781 .remove
= mpc52xx_gpt_remove
,
784 static int __init
mpc52xx_gpt_init(void)
786 return platform_driver_register(&mpc52xx_gpt_driver
);
789 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
790 subsys_initcall(mpc52xx_gpt_init
);
791 device_initcall(mpc52xx_gpt_wdt_init
);