arch/powerpc/platforms/85xx/twr_p102x.c

   1 /*
   2  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Michael Johnston <michael.johnston@freescale.com>
   5  *
   6  * Description:
   7  * TWR-P102x Board Setup
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/fsl/guts.h>
  19 #include <linux/pci.h>
  20 #include <linux/of_platform.h>
  21
  22 #include <asm/pci-bridge.h>
  23 #include <asm/udbg.h>
  24 #include <asm/mpic.h>
  25 #include <soc/fsl/qe/qe.h>
  26 #include <soc/fsl/qe/qe_ic.h>
  27
  28 #include <sysdev/fsl_soc.h>
  29 #include <sysdev/fsl_pci.h>
  30 #include "smp.h"
  31
  32 #include "mpc85xx.h"
  33
  34 static void __init twr_p1025_pic_init(void)
  35 {
  36         struct mpic *mpic;
  37
  38 #ifdef CONFIG_QUICC_ENGINE
  39         struct device_node *np;
  40 #endif
  41
  42         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
  43                         MPIC_SINGLE_DEST_CPU,
  44                         0, 256, " OpenPIC  ");
  45
  46         BUG_ON(mpic == NULL);
  47         mpic_init(mpic);
  48
  49 #ifdef CONFIG_QUICC_ENGINE
  50         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  51         if (np) {
  52                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  53                                 qe_ic_cascade_high_mpic);
  54                 of_node_put(np);
  55         } else
  56                 pr_err("Could not find qe-ic node\n");
  57 #endif
  58 }
  59
  60 /* ************************************************************************
  61  *
  62  * Setup the architecture
  63  *
  64  */
  65 static void __init twr_p1025_setup_arch(void)
  66 {
  67 #ifdef CONFIG_QUICC_ENGINE
  68         struct device_node *np;
  69 #endif
  70
  71         if (ppc_md.progress)
  72                 ppc_md.progress("twr_p1025_setup_arch()", 0);
  73
  74         mpc85xx_smp_init();
  75
  76         fsl_pci_assign_primary();
  77
  78 #ifdef CONFIG_QUICC_ENGINE
  79         mpc85xx_qe_init();
  80         mpc85xx_qe_par_io_init();
  81
  82 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
  83         if (machine_is(twr_p1025)) {
  84                 struct ccsr_guts __iomem *guts;
  85
  86                 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
  87                 if (np) {
  88                         guts = of_iomap(np, 0);
  89                         if (!guts)
  90                                 pr_err("twr_p1025: could not map global utilities register\n");
  91                         else {
  92                         /* P1025 has pins muxed for QE and other functions. To
  93                          * enable QE UEC mode, we need to set bit QE0 for UCC1
  94                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  95                          * and QE12 for QE MII management signals in PMUXCR
  96                          * register.
  97                          * Set QE mux bits in PMUXCR */
  98                         setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  99                                         MPC85xx_PMUXCR_QE(3) |
 100                                         MPC85xx_PMUXCR_QE(9) |
 101                                         MPC85xx_PMUXCR_QE(12));
 102                         iounmap(guts);
 103
 104 #if IS_ENABLED(CONFIG_SERIAL_QE)
 105                         /* On P1025TWR board, the UCC7 acted as UART port.
 106                          * However, The UCC7's CTS pin is low level in default,
 107                          * it will impact the transmission in full duplex
 108                          * communication. So disable the Flow control pin PA18.
 109                          * The UCC7 UART just can use RXD and TXD pins.
 110                          */
 111                         par_io_config_pin(0, 18, 0, 0, 0, 0);
 112 #endif
 113                         /* Drive PB29 to CPLD low - CPLD will then change
 114                          * muxing from LBC to QE */
 115                         par_io_config_pin(1, 29, 1, 0, 0, 0);
 116                         par_io_data_set(1, 29, 0);
 117                         }
 118                         of_node_put(np);
 119                 }
 120         }
 121 #endif
 122 #endif  /* CONFIG_QUICC_ENGINE */
 123
 124         pr_info("TWR-P1025 board from Freescale Semiconductor\n");
 125 }
 126
 127 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
 128
 129 static int __init twr_p1025_probe(void)
 130 {
 131         return of_machine_is_compatible("fsl,TWR-P1025");
 132 }
 133
 134 define_machine(twr_p1025) {
 135         .name                   = "TWR-P1025",
 136         .probe                  = twr_p1025_probe,
 137         .setup_arch             = twr_p1025_setup_arch,
 138         .init_IRQ               = twr_p1025_pic_init,
 139 #ifdef CONFIG_PCI
 140         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 141 #endif
 142         .get_irq                = mpic_get_irq,
 143         .calibrate_decr         = generic_calibrate_decr,
 144         .progress               = udbg_progress,
 145 };