arch/powerpc/platforms/85xx/xes_mpc85xx.c

   1 /*
   2  * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
   3  *
   4  * X-ES board-specific functionality
   5  *
   6  * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
   7  *
   8  * Author: Nate Case <ncase@xes-inc.com>
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of_platform.h>
  23
  24 #include <asm/time.h>
  25 #include <asm/machdep.h>
  26 #include <asm/pci-bridge.h>
  27 #include <mm/mmu_decl.h>
  28 #include <asm/prom.h>
  29 #include <asm/udbg.h>
  30 #include <asm/mpic.h>
  31
  32 #include <sysdev/fsl_soc.h>
  33 #include <sysdev/fsl_pci.h>
  34 #include "smp.h"
  35
  36 #include "mpc85xx.h"
  37
  38 /* A few bit definitions needed for fixups on some boards */
  39 #define MPC85xx_L2CTL_L2E               0x80000000 /* L2 enable */
  40 #define MPC85xx_L2CTL_L2I               0x40000000 /* L2 flash invalidate */
  41 #define MPC85xx_L2CTL_L2SIZ_MASK        0x30000000 /* L2 SRAM size (R/O) */
  42
  43 void __init xes_mpc85xx_pic_init(void)
  44 {
  45         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
  46                         0, 256, " OpenPIC  ");
  47         BUG_ON(mpic == NULL);
  48         mpic_init(mpic);
  49 }
  50
  51 static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
  52 {
  53         volatile uint32_t ctl, tmp;
  54
  55         asm volatile("msync; isync");
  56         tmp = in_be32(l2_base);
  57
  58         /*
  59          * xMon may have enabled part of L2 as SRAM, so we need to set it
  60          * up for all cache mode just to be safe.
  61          */
  62         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
  63
  64         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
  65         if (of_machine_is_compatible("MPC8540") ||
  66             of_machine_is_compatible("MPC8560"))
  67                 /*
  68                  * Assume L2 SRAM is used fully for cache, so set
  69                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
  70                  */
  71                 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
  72
  73         asm volatile("msync; isync");
  74         out_be32(l2_base, ctl);
  75         asm volatile("msync; isync");
  76 }
  77
  78 static void xes_mpc85xx_fixups(void)
  79 {
  80         struct device_node *np;
  81         int err;
  82
  83         /*
  84          * Legacy xMon firmware on some X-ES boards does not enable L2
  85          * as cache.  We must ensure that they get enabled here.
  86          */
  87         for_each_node_by_name(np, "l2-cache-controller") {
  88                 struct resource r[2];
  89                 void __iomem *l2_base;
  90
  91                 /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
  92                 if (!of_device_is_compatible(np,
  93                                     "fsl,mpc8548-l2-cache-controller") &&
  94                     !of_device_is_compatible(np,
  95                                     "fsl,mpc8540-l2-cache-controller") &&
  96                     !of_device_is_compatible(np,
  97                                     "fsl,mpc8560-l2-cache-controller"))
  98                         continue;
  99
 100                 err = of_address_to_resource(np, 0, &r[0]);
 101                 if (err) {
 102                         printk(KERN_WARNING "xes_mpc85xx: Could not get "
 103                                "resource for device tree node '%s'",
 104                                np->full_name);
 105                         continue;
 106                 }
 107
 108                 l2_base = ioremap(r[0].start, resource_size(&r[0]));
 109
 110                 xes_mpc85xx_configure_l2(l2_base);
 111         }
 112 }
 113
 114 /*
 115  * Setup the architecture
 116  */
 117 static void __init xes_mpc85xx_setup_arch(void)
 118 {
 119         struct device_node *root;
 120         const char *model = "Unknown";
 121
 122         root = of_find_node_by_path("/");
 123         if (root == NULL)
 124                 return;
 125
 126         model = of_get_property(root, "model", NULL);
 127
 128         printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
 129                model + strlen("xes,"));
 130
 131         xes_mpc85xx_fixups();
 132
 133         mpc85xx_smp_init();
 134
 135         fsl_pci_assign_primary();
 136 }
 137
 138 machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices);
 139 machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
 140 machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
 141
 142 /*
 143  * Called very early, device-tree isn't unflattened
 144  */
 145 static int __init xes_mpc8572_probe(void)
 146 {
 147         return of_machine_is_compatible("xes,MPC8572");
 148 }
 149
 150 static int __init xes_mpc8548_probe(void)
 151 {
 152         return of_machine_is_compatible("xes,MPC8548");
 153 }
 154
 155 static int __init xes_mpc8540_probe(void)
 156 {
 157         return of_machine_is_compatible("xes,MPC8540");
 158 }
 159
 160 define_machine(xes_mpc8572) {
 161         .name                   = "X-ES MPC8572",
 162         .probe                  = xes_mpc8572_probe,
 163         .setup_arch             = xes_mpc85xx_setup_arch,
 164         .init_IRQ               = xes_mpc85xx_pic_init,
 165 #ifdef CONFIG_PCI
 166         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 167         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 168 #endif
 169         .get_irq                = mpic_get_irq,
 170         .calibrate_decr         = generic_calibrate_decr,
 171         .progress               = udbg_progress,
 172 };
 173
 174 define_machine(xes_mpc8548) {
 175         .name                   = "X-ES MPC8548",
 176         .probe                  = xes_mpc8548_probe,
 177         .setup_arch             = xes_mpc85xx_setup_arch,
 178         .init_IRQ               = xes_mpc85xx_pic_init,
 179 #ifdef CONFIG_PCI
 180         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 181         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 182 #endif
 183         .get_irq                = mpic_get_irq,
 184         .calibrate_decr         = generic_calibrate_decr,
 185         .progress               = udbg_progress,
 186 };
 187
 188 define_machine(xes_mpc8540) {
 189         .name                   = "X-ES MPC8540",
 190         .probe                  = xes_mpc8540_probe,
 191         .setup_arch             = xes_mpc85xx_setup_arch,
 192         .init_IRQ               = xes_mpc85xx_pic_init,
 193 #ifdef CONFIG_PCI
 194         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 195         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 196 #endif
 197         .get_irq                = mpic_get_irq,
 198         .calibrate_decr         = generic_calibrate_decr,
 199         .progress               = udbg_progress,
 200 };