?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mmc: sdhci-of-esdhc: use of_property_read_bool
[linux/fpc-iii.git] / drivers / ata / sata_fsl.c
bloba723ae92978310f64e65eeef44509337a027c8a5
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30
31 static unsigned int intr_coalescing_count;
32 module_param(intr_coalescing_count, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_count,
34 "INT coalescing count threshold (1..31)");
35
36 static unsigned int intr_coalescing_ticks;
37 module_param(intr_coalescing_ticks, int, S_IRUGO);
38 MODULE_PARM_DESC(intr_coalescing_ticks,
39 "INT coalescing timer threshold in AHB ticks");
40 /* Controller information */
41 enum {
42 SATA_FSL_QUEUE_DEPTH = 16,
43 SATA_FSL_MAX_PRD = 63,
44 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
45 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
46
47 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
48 ATA_FLAG_PMP | ATA_FLAG_NCQ |
49 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
50
51 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
52 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
53 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
54
55 /*
56 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
57 * chained indirect PRDEs up to a max count of 63.
58 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
59 * be setup as an indirect descriptor, pointing to it's next
60 * (contiguous) PRDE. Though chained indirect PRDE arrays are
61 * supported,it will be more efficient to use a direct PRDT and
62 * a single chain/link to indirect PRDE array/PRDT.
63 */
64
65 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
66 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
67 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
68 SATA_FSL_CMD_DESC_RSRVD = 16,
69
70 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
71 SATA_FSL_CMD_DESC_SFIS_SZ +
72 SATA_FSL_CMD_DESC_ACMD_SZ +
73 SATA_FSL_CMD_DESC_RSRVD +
74 SATA_FSL_MAX_PRD * 16),
75
76 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
77 (SATA_FSL_CMD_DESC_CFIS_SZ +
78 SATA_FSL_CMD_DESC_SFIS_SZ +
79 SATA_FSL_CMD_DESC_ACMD_SZ +
80 SATA_FSL_CMD_DESC_RSRVD),
81
82 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
83 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
84 SATA_FSL_CMD_DESC_AR_SZ),
85
86 /*
87 * MPC8315 has two SATA controllers, SATA1 & SATA2
88 * (one port per controller)
89 * MPC837x has 2/4 controllers, one port per controller
90 */
91
92 SATA_FSL_MAX_PORTS = 1,
93
94 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
95 };
96
97 /*
98 * Interrupt Coalescing Control Register bitdefs */
99 enum {
100 ICC_MIN_INT_COUNT_THRESHOLD = 1,
101 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
102 ICC_MIN_INT_TICKS_THRESHOLD = 0,
103 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
104 ICC_SAFE_INT_TICKS = 1,
105 };
106
107 /*
108 * Host Controller command register set - per port
109 */
110 enum {
111 CQ = 0,
112 CA = 8,
113 CC = 0x10,
114 CE = 0x18,
115 DE = 0x20,
116 CHBA = 0x24,
117 HSTATUS = 0x28,
118 HCONTROL = 0x2C,
119 CQPMP = 0x30,
120 SIGNATURE = 0x34,
121 ICC = 0x38,
122
123 /*
124 * Host Status Register (HStatus) bitdefs
125 */
126 ONLINE = (1 << 31),
127 GOING_OFFLINE = (1 << 30),
128 BIST_ERR = (1 << 29),
129 CLEAR_ERROR = (1 << 27),
130
131 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
132 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
133 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
134 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
135 FATAL_ERR_DATA_OVERRUN = (1 << 12),
136 FATAL_ERR_CRC_ERR_TX = (1 << 11),
137 FATAL_ERR_CRC_ERR_RX = (1 << 10),
138 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
139 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
140
141 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
142 FATAL_ERR_PARITY_ERR_TX |
143 FATAL_ERR_PARITY_ERR_RX |
144 FATAL_ERR_DATA_UNDERRUN |
145 FATAL_ERR_DATA_OVERRUN |
146 FATAL_ERR_CRC_ERR_TX |
147 FATAL_ERR_CRC_ERR_RX |
148 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
149
150 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
151 INT_ON_FATAL_ERR = (1 << 5),
152 INT_ON_PHYRDY_CHG = (1 << 4),
153
154 INT_ON_SIGNATURE_UPDATE = (1 << 3),
155 INT_ON_SNOTIFY_UPDATE = (1 << 2),
156 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
157 INT_ON_CMD_COMPLETE = 1,
158
159 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
160 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
161
162 /*
163 * Host Control Register (HControl) bitdefs
164 */
165 HCONTROL_ONLINE_PHY_RST = (1 << 31),
166 HCONTROL_FORCE_OFFLINE = (1 << 30),
167 HCONTROL_LEGACY = (1 << 28),
168 HCONTROL_PARITY_PROT_MOD = (1 << 14),
169 HCONTROL_DPATH_PARITY = (1 << 12),
170 HCONTROL_SNOOP_ENABLE = (1 << 10),
171 HCONTROL_PMP_ATTACHED = (1 << 9),
172 HCONTROL_COPYOUT_STATFIS = (1 << 8),
173 IE_ON_FATAL_ERR = (1 << 5),
174 IE_ON_PHYRDY_CHG = (1 << 4),
175 IE_ON_SIGNATURE_UPDATE = (1 << 3),
176 IE_ON_SNOTIFY_UPDATE = (1 << 2),
177 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
178 IE_ON_CMD_COMPLETE = 1,
179
180 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
181 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
182 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
183
184 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
185 DATA_SNOOP_ENABLE_V1 = (1 << 22),
186 DATA_SNOOP_ENABLE_V2 = (1 << 28),
187 };
188
189 /*
190 * SATA Superset Registers
191 */
192 enum {
193 SSTATUS = 0,
194 SERROR = 4,
195 SCONTROL = 8,
196 SNOTIFY = 0xC,
197 };
198
199 /*
200 * Control Status Register Set
201 */
202 enum {
203 TRANSCFG = 0,
204 TRANSSTATUS = 4,
205 LINKCFG = 8,
206 LINKCFG1 = 0xC,
207 LINKCFG2 = 0x10,
208 LINKSTATUS = 0x14,
209 LINKSTATUS1 = 0x18,
210 PHYCTRLCFG = 0x1C,
211 COMMANDSTAT = 0x20,
212 };
213
214 /* TRANSCFG (transport-layer) configuration control */
215 enum {
216 TRANSCFG_RX_WATER_MARK = (1 << 4),
217 };
218
219 /* PHY (link-layer) configuration control */
220 enum {
221 PHY_BIST_ENABLE = 0x01,
222 };
223
224 /*
225 * Command Header Table entry, i.e, command slot
226 * 4 Dwords per command slot, command header size == 64 Dwords.
227 */
228 struct cmdhdr_tbl_entry {
229 u32 cda;
230 u32 prde_fis_len;
231 u32 ttl;
232 u32 desc_info;
233 };
234
235 /*
236 * Description information bitdefs
237 */
238 enum {
239 CMD_DESC_RES = (1 << 11),
240 VENDOR_SPECIFIC_BIST = (1 << 10),
241 CMD_DESC_SNOOP_ENABLE = (1 << 9),
242 FPDMA_QUEUED_CMD = (1 << 8),
243 SRST_CMD = (1 << 7),
244 BIST = (1 << 6),
245 ATAPI_CMD = (1 << 5),
246 };
247
248 /*
249 * Command Descriptor
250 */
251 struct command_desc {
252 u8 cfis[8 * 4];
253 u8 sfis[8 * 4];
254 u8 acmd[4 * 4];
255 u8 fill[4 * 4];
256 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
257 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
258 };
259
260 /*
261 * Physical region table descriptor(PRD)
262 */
263
264 struct prde {
265 u32 dba;
266 u8 fill[2 * 4];
267 u32 ddc_and_ext;
268 };
269
270 /*
271 * ata_port private data
272 * This is our per-port instance data.
273 */
274 struct sata_fsl_port_priv {
275 struct cmdhdr_tbl_entry *cmdslot;
276 dma_addr_t cmdslot_paddr;
277 struct command_desc *cmdentry;
278 dma_addr_t cmdentry_paddr;
279 };
280
281 /*
282 * ata_port->host_set private data
283 */
284 struct sata_fsl_host_priv {
285 void __iomem *hcr_base;
286 void __iomem *ssr_base;
287 void __iomem *csr_base;
288 int irq;
289 int data_snoop;
290 struct device_attribute intr_coalescing;
291 struct device_attribute rx_watermark;
292 };
293
294 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
295 unsigned int count, unsigned int ticks)
296 {
297 struct sata_fsl_host_priv *host_priv = host->private_data;
298 void __iomem *hcr_base = host_priv->hcr_base;
299 unsigned long flags;
300
301 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
302 count = ICC_MAX_INT_COUNT_THRESHOLD;
303 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
304 count = ICC_MIN_INT_COUNT_THRESHOLD;
305
306 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
307 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
308 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
309 (count > ICC_MIN_INT_COUNT_THRESHOLD))
310 ticks = ICC_SAFE_INT_TICKS;
311
312 spin_lock_irqsave(&host->lock, flags);
313 iowrite32((count << 24 | ticks), hcr_base + ICC);
314
315 intr_coalescing_count = count;
316 intr_coalescing_ticks = ticks;
317 spin_unlock_irqrestore(&host->lock, flags);
318
319 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
320 intr_coalescing_count, intr_coalescing_ticks);
321 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
322 hcr_base, ioread32(hcr_base + ICC));
323 }
324
325 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
326 struct device_attribute *attr, char *buf)
327 {
328 return sprintf(buf, "%d %d\n",
329 intr_coalescing_count, intr_coalescing_ticks);
330 }
331
332 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335 {
336 unsigned int coalescing_count, coalescing_ticks;
337
338 if (sscanf(buf, "%d%d",
339 &coalescing_count,
340 &coalescing_ticks) != 2) {
341 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
342 return -EINVAL;
343 }
344
345 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
346 coalescing_count, coalescing_ticks);
347
348 return strlen(buf);
349 }
350
351 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
352 struct device_attribute *attr, char *buf)
353 {
354 unsigned int rx_watermark;
355 unsigned long flags;
356 struct ata_host *host = dev_get_drvdata(dev);
357 struct sata_fsl_host_priv *host_priv = host->private_data;
358 void __iomem *csr_base = host_priv->csr_base;
359
360 spin_lock_irqsave(&host->lock, flags);
361 rx_watermark = ioread32(csr_base + TRANSCFG);
362 rx_watermark &= 0x1f;
363
364 spin_unlock_irqrestore(&host->lock, flags);
365 return sprintf(buf, "%d\n", rx_watermark);
366 }
367
368 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
369 struct device_attribute *attr,
370 const char *buf, size_t count)
371 {
372 unsigned int rx_watermark;
373 unsigned long flags;
374 struct ata_host *host = dev_get_drvdata(dev);
375 struct sata_fsl_host_priv *host_priv = host->private_data;
376 void __iomem *csr_base = host_priv->csr_base;
377 u32 temp;
378
379 if (sscanf(buf, "%d", &rx_watermark) != 1) {
380 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
381 return -EINVAL;
382 }
383
384 spin_lock_irqsave(&host->lock, flags);
385 temp = ioread32(csr_base + TRANSCFG);
386 temp &= 0xffffffe0;
387 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
388
389 spin_unlock_irqrestore(&host->lock, flags);
390 return strlen(buf);
391 }
392
393 static inline unsigned int sata_fsl_tag(unsigned int tag,
394 void __iomem *hcr_base)
395 {
396 /* We let libATA core do actual (queue) tag allocation */
397
398 /* all non NCQ/queued commands should have tag#0 */
399 if (ata_tag_internal(tag)) {
400 DPRINTK("mapping internal cmds to tag#0\n");
401 return 0;
402 }
403
404 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
405 DPRINTK("tag %d invalid : out of range\n", tag);
406 return 0;
407 }
408
409 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
410 DPRINTK("tag %d invalid : in use!!\n", tag);
411 return 0;
412 }
413
414 return tag;
415 }
416
417 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
418 unsigned int tag, u32 desc_info,
419 u32 data_xfer_len, u8 num_prde,
420 u8 fis_len)
421 {
422 dma_addr_t cmd_descriptor_address;
423
424 cmd_descriptor_address = pp->cmdentry_paddr +
425 tag * SATA_FSL_CMD_DESC_SIZE;
426
427 /* NOTE: both data_xfer_len & fis_len are Dword counts */
428
429 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
430 pp->cmdslot[tag].prde_fis_len =
431 cpu_to_le32((num_prde << 16) | (fis_len << 2));
432 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
433 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
434
435 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
436 pp->cmdslot[tag].cda,
437 pp->cmdslot[tag].prde_fis_len,
438 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
439
440 }
441
442 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
443 u32 *ttl, dma_addr_t cmd_desc_paddr,
444 int data_snoop)
445 {
446 struct scatterlist *sg;
447 unsigned int num_prde = 0;
448 u32 ttl_dwords = 0;
449
450 /*
451 * NOTE : direct & indirect prdt's are contiguously allocated
452 */
453 struct prde *prd = (struct prde *)&((struct command_desc *)
454 cmd_desc)->prdt;
455
456 struct prde *prd_ptr_to_indirect_ext = NULL;
457 unsigned indirect_ext_segment_sz = 0;
458 dma_addr_t indirect_ext_segment_paddr;
459 unsigned int si;
460
461 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
462
463 indirect_ext_segment_paddr = cmd_desc_paddr +
464 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
465
466 for_each_sg(qc->sg, sg, qc->n_elem, si) {
467 dma_addr_t sg_addr = sg_dma_address(sg);
468 u32 sg_len = sg_dma_len(sg);
469
470 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
471 (unsigned long long)sg_addr, sg_len);
472
473 /* warn if each s/g element is not dword aligned */
474 if (unlikely(sg_addr & 0x03))
475 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
476 (unsigned long long)sg_addr);
477 if (unlikely(sg_len & 0x03))
478 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
479 sg_len);
480
481 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
482 sg_next(sg) != NULL) {
483 VPRINTK("setting indirect prde\n");
484 prd_ptr_to_indirect_ext = prd;
485 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
486 indirect_ext_segment_sz = 0;
487 ++prd;
488 ++num_prde;
489 }
490
491 ttl_dwords += sg_len;
492 prd->dba = cpu_to_le32(sg_addr);
493 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
494
495 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
496 ttl_dwords, prd->dba, prd->ddc_and_ext);
497
498 ++num_prde;
499 ++prd;
500 if (prd_ptr_to_indirect_ext)
501 indirect_ext_segment_sz += sg_len;
502 }
503
504 if (prd_ptr_to_indirect_ext) {
505 /* set indirect extension flag along with indirect ext. size */
506 prd_ptr_to_indirect_ext->ddc_and_ext =
507 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
508 data_snoop |
509 (indirect_ext_segment_sz & ~0x03)));
510 }
511
512 *ttl = ttl_dwords;
513 return num_prde;
514 }
515
516 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
517 {
518 struct ata_port *ap = qc->ap;
519 struct sata_fsl_port_priv *pp = ap->private_data;
520 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
521 void __iomem *hcr_base = host_priv->hcr_base;
522 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
523 struct command_desc *cd;
524 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
525 u32 num_prde = 0;
526 u32 ttl_dwords = 0;
527 dma_addr_t cd_paddr;
528
529 cd = (struct command_desc *)pp->cmdentry + tag;
530 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
531
532 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
533
534 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
535 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
536
537 if (qc->tf.protocol == ATA_PROT_NCQ) {
538 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
539 cd->cfis[3], cd->cfis[11]);
540 }
541
542 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
543 if (ata_is_atapi(qc->tf.protocol)) {
544 desc_info |= ATAPI_CMD;
545 memset((void *)&cd->acmd, 0, 32);
546 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
547 }
548
549 if (qc->flags & ATA_QCFLAG_DMAMAP)
550 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
551 &ttl_dwords, cd_paddr,
552 host_priv->data_snoop);
553
554 if (qc->tf.protocol == ATA_PROT_NCQ)
555 desc_info |= FPDMA_QUEUED_CMD;
556
557 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
558 num_prde, 5);
559
560 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
561 desc_info, ttl_dwords, num_prde);
562 }
563
564 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
565 {
566 struct ata_port *ap = qc->ap;
567 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
568 void __iomem *hcr_base = host_priv->hcr_base;
569 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
570
571 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
572 ioread32(CQ + hcr_base),
573 ioread32(CA + hcr_base),
574 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
575
576 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
577
578 /* Simply queue command to the controller/device */
579 iowrite32(1 << tag, CQ + hcr_base);
580
581 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
582 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
583
584 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
585 ioread32(CE + hcr_base),
586 ioread32(DE + hcr_base),
587 ioread32(CC + hcr_base),
588 ioread32(COMMANDSTAT + host_priv->csr_base));
589
590 return 0;
591 }
592
593 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
594 {
595 struct sata_fsl_port_priv *pp = qc->ap->private_data;
596 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
597 void __iomem *hcr_base = host_priv->hcr_base;
598 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
599 struct command_desc *cd;
600
601 cd = pp->cmdentry + tag;
602
603 ata_tf_from_fis(cd->sfis, &qc->result_tf);
604 return true;
605 }
606
607 static int sata_fsl_scr_write(struct ata_link *link,
608 unsigned int sc_reg_in, u32 val)
609 {
610 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
611 void __iomem *ssr_base = host_priv->ssr_base;
612 unsigned int sc_reg;
613
614 switch (sc_reg_in) {
615 case SCR_STATUS:
616 case SCR_ERROR:
617 case SCR_CONTROL:
618 case SCR_ACTIVE:
619 sc_reg = sc_reg_in;
620 break;
621 default:
622 return -EINVAL;
623 }
624
625 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
626
627 iowrite32(val, ssr_base + (sc_reg * 4));
628 return 0;
629 }
630
631 static int sata_fsl_scr_read(struct ata_link *link,
632 unsigned int sc_reg_in, u32 *val)
633 {
634 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
635 void __iomem *ssr_base = host_priv->ssr_base;
636 unsigned int sc_reg;
637
638 switch (sc_reg_in) {
639 case SCR_STATUS:
640 case SCR_ERROR:
641 case SCR_CONTROL:
642 case SCR_ACTIVE:
643 sc_reg = sc_reg_in;
644 break;
645 default:
646 return -EINVAL;
647 }
648
649 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
650
651 *val = ioread32(ssr_base + (sc_reg * 4));
652 return 0;
653 }
654
655 static void sata_fsl_freeze(struct ata_port *ap)
656 {
657 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
658 void __iomem *hcr_base = host_priv->hcr_base;
659 u32 temp;
660
661 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
662 ioread32(CQ + hcr_base),
663 ioread32(CA + hcr_base),
664 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
665 VPRINTK("CmdStat = 0x%x\n",
666 ioread32(host_priv->csr_base + COMMANDSTAT));
667
668 /* disable interrupts on the controller/port */
669 temp = ioread32(hcr_base + HCONTROL);
670 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
671
672 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
673 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
674 }
675
676 static void sata_fsl_thaw(struct ata_port *ap)
677 {
678 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
679 void __iomem *hcr_base = host_priv->hcr_base;
680 u32 temp;
681
682 /* ack. any pending IRQs for this controller/port */
683 temp = ioread32(hcr_base + HSTATUS);
684
685 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
686
687 if (temp & 0x3F)
688 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
689
690 /* enable interrupts on the controller/port */
691 temp = ioread32(hcr_base + HCONTROL);
692 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
693
694 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
695 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
696 }
697
698 static void sata_fsl_pmp_attach(struct ata_port *ap)
699 {
700 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
701 void __iomem *hcr_base = host_priv->hcr_base;
702 u32 temp;
703
704 temp = ioread32(hcr_base + HCONTROL);
705 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
706 }
707
708 static void sata_fsl_pmp_detach(struct ata_port *ap)
709 {
710 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
711 void __iomem *hcr_base = host_priv->hcr_base;
712 u32 temp;
713
714 temp = ioread32(hcr_base + HCONTROL);
715 temp &= ~HCONTROL_PMP_ATTACHED;
716 iowrite32(temp, hcr_base + HCONTROL);
717
718 /* enable interrupts on the controller/port */
719 temp = ioread32(hcr_base + HCONTROL);
720 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
721
722 }
723
724 static int sata_fsl_port_start(struct ata_port *ap)
725 {
726 struct device *dev = ap->host->dev;
727 struct sata_fsl_port_priv *pp;
728 void *mem;
729 dma_addr_t mem_dma;
730 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
731 void __iomem *hcr_base = host_priv->hcr_base;
732 u32 temp;
733
734 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
735 if (!pp)
736 return -ENOMEM;
737
738 mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
739 GFP_KERNEL);
740 if (!mem) {
741 kfree(pp);
742 return -ENOMEM;
743 }
744
745 pp->cmdslot = mem;
746 pp->cmdslot_paddr = mem_dma;
747
748 mem += SATA_FSL_CMD_SLOT_SIZE;
749 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
750
751 pp->cmdentry = mem;
752 pp->cmdentry_paddr = mem_dma;
753
754 ap->private_data = pp;
755
756 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
757 pp->cmdslot_paddr, pp->cmdentry_paddr);
758
759 /* Now, update the CHBA register in host controller cmd register set */
760 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
761
762 /*
763 * Now, we can bring the controller on-line & also initiate
764 * the COMINIT sequence, we simply return here and the boot-probing
765 * & device discovery process is re-initiated by libATA using a
766 * Softreset EH (dummy) session. Hence, boot probing and device
767 * discovey will be part of sata_fsl_softreset() callback.
768 */
769
770 temp = ioread32(hcr_base + HCONTROL);
771 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
772
773 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
774 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
775 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
776
777 return 0;
778 }
779
780 static void sata_fsl_port_stop(struct ata_port *ap)
781 {
782 struct device *dev = ap->host->dev;
783 struct sata_fsl_port_priv *pp = ap->private_data;
784 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
785 void __iomem *hcr_base = host_priv->hcr_base;
786 u32 temp;
787
788 /*
789 * Force host controller to go off-line, aborting current operations
790 */
791 temp = ioread32(hcr_base + HCONTROL);
792 temp &= ~HCONTROL_ONLINE_PHY_RST;
793 temp |= HCONTROL_FORCE_OFFLINE;
794 iowrite32(temp, hcr_base + HCONTROL);
795
796 /* Poll for controller to go offline - should happen immediately */
797 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
798
799 ap->private_data = NULL;
800 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
801 pp->cmdslot, pp->cmdslot_paddr);
802
803 kfree(pp);
804 }
805
806 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
807 {
808 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
809 void __iomem *hcr_base = host_priv->hcr_base;
810 struct ata_taskfile tf;
811 u32 temp;
812
813 temp = ioread32(hcr_base + SIGNATURE);
814
815 VPRINTK("raw sig = 0x%x\n", temp);
816 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
817 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
818
819 tf.lbah = (temp >> 24) & 0xff;
820 tf.lbam = (temp >> 16) & 0xff;
821 tf.lbal = (temp >> 8) & 0xff;
822 tf.nsect = temp & 0xff;
823
824 return ata_dev_classify(&tf);
825 }
826
827 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
828 unsigned long deadline)
829 {
830 struct ata_port *ap = link->ap;
831 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
832 void __iomem *hcr_base = host_priv->hcr_base;
833 u32 temp;
834 int i = 0;
835 unsigned long start_jiffies;
836
837 DPRINTK("in xx_hardreset\n");
838
839 try_offline_again:
840 /*
841 * Force host controller to go off-line, aborting current operations
842 */
843 temp = ioread32(hcr_base + HCONTROL);
844 temp &= ~HCONTROL_ONLINE_PHY_RST;
845 iowrite32(temp, hcr_base + HCONTROL);
846
847 /* Poll for controller to go offline */
848 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
849 1, 500);
850
851 if (temp & ONLINE) {
852 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
853
854 /*
855 * Try to offline controller atleast twice
856 */
857 i++;
858 if (i == 2)
859 goto err;
860 else
861 goto try_offline_again;
862 }
863
864 DPRINTK("hardreset, controller off-lined\n");
865 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
866 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
867
868 /*
869 * PHY reset should remain asserted for atleast 1ms
870 */
871 ata_msleep(ap, 1);
872
873 sata_set_spd(link);
874
875 /*
876 * Now, bring the host controller online again, this can take time
877 * as PHY reset and communication establishment, 1st D2H FIS and
878 * device signature update is done, on safe side assume 500ms
879 * NOTE : Host online status may be indicated immediately!!
880 */
881
882 temp = ioread32(hcr_base + HCONTROL);
883 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
884 temp |= HCONTROL_PMP_ATTACHED;
885 iowrite32(temp, hcr_base + HCONTROL);
886
887 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
888
889 if (!(temp & ONLINE)) {
890 ata_port_err(ap, "Hardreset failed, not on-lined\n");
891 goto err;
892 }
893
894 DPRINTK("hardreset, controller off-lined & on-lined\n");
895 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
896 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
897
898 /*
899 * First, wait for the PHYRDY change to occur before waiting for
900 * the signature, and also verify if SStatus indicates device
901 * presence
902 */
903
904 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
905 if ((!(temp & 0x10)) || ata_link_offline(link)) {
906 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
907 ioread32(hcr_base + HSTATUS));
908 *class = ATA_DEV_NONE;
909 return 0;
910 }
911
912 /*
913 * Wait for the first D2H from device,i.e,signature update notification
914 */
915 start_jiffies = jiffies;
916 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
917 500, jiffies_to_msecs(deadline - start_jiffies));
918
919 if ((temp & 0xFF) != 0x18) {
920 ata_port_warn(ap, "No Signature Update\n");
921 *class = ATA_DEV_NONE;
922 goto do_followup_srst;
923 } else {
924 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
925 jiffies_to_msecs(jiffies - start_jiffies));
926 *class = sata_fsl_dev_classify(ap);
927 return 0;
928 }
929
930 do_followup_srst:
931 /*
932 * request libATA to perform follow-up softreset
933 */
934 return -EAGAIN;
935
936 err:
937 return -EIO;
938 }
939
940 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
941 unsigned long deadline)
942 {
943 struct ata_port *ap = link->ap;
944 struct sata_fsl_port_priv *pp = ap->private_data;
945 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
946 void __iomem *hcr_base = host_priv->hcr_base;
947 int pmp = sata_srst_pmp(link);
948 u32 temp;
949 struct ata_taskfile tf;
950 u8 *cfis;
951 u32 Serror;
952
953 DPRINTK("in xx_softreset\n");
954
955 if (ata_link_offline(link)) {
956 DPRINTK("PHY reports no device\n");
957 *class = ATA_DEV_NONE;
958 return 0;
959 }
960
961 /*
962 * Send a device reset (SRST) explicitly on command slot #0
963 * Check : will the command queue (reg) be cleared during offlining ??
964 * Also we will be online only if Phy commn. has been established
965 * and device presence has been detected, therefore if we have
966 * reached here, we can send a command to the target device
967 */
968
969 DPRINTK("Sending SRST/device reset\n");
970
971 ata_tf_init(link->device, &tf);
972 cfis = (u8 *) &pp->cmdentry->cfis;
973
974 /* device reset/SRST is a control register update FIS, uses tag0 */
975 sata_fsl_setup_cmd_hdr_entry(pp, 0,
976 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
977
978 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
979 ata_tf_to_fis(&tf, pmp, 0, cfis);
980
981 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
982 cfis[0], cfis[1], cfis[2], cfis[3]);
983
984 /*
985 * Queue SRST command to the controller/device, ensure that no
986 * other commands are active on the controller/device
987 */
988
989 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
990 ioread32(CQ + hcr_base),
991 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
992
993 iowrite32(0xFFFF, CC + hcr_base);
994 if (pmp != SATA_PMP_CTRL_PORT)
995 iowrite32(pmp, CQPMP + hcr_base);
996 iowrite32(1, CQ + hcr_base);
997
998 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
999 if (temp & 0x1) {
1000 ata_port_warn(ap, "ATA_SRST issue failed\n");
1001
1002 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1003 ioread32(CQ + hcr_base),
1004 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1005
1006 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1007
1008 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1009 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1010 DPRINTK("Serror = 0x%x\n", Serror);
1011 goto err;
1012 }
1013
1014 ata_msleep(ap, 1);
1015
1016 /*
1017 * SATA device enters reset state after receiving a Control register
1018 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1019 * FIS with SRST bit cleared, then the device does internal diags &
1020 * initialization, followed by indicating it's initialization status
1021 * using ATA signature D2H register FIS to the host controller.
1022 */
1023
1024 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1025 0, 0, 5);
1026
1027 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1028 ata_tf_to_fis(&tf, pmp, 0, cfis);
1029
1030 if (pmp != SATA_PMP_CTRL_PORT)
1031 iowrite32(pmp, CQPMP + hcr_base);
1032 iowrite32(1, CQ + hcr_base);
1033 ata_msleep(ap, 150); /* ?? */
1034
1035 /*
1036 * The above command would have signalled an interrupt on command
1037 * complete, which needs special handling, by clearing the Nth
1038 * command bit of the CCreg
1039 */
1040 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1041
1042 DPRINTK("SATA FSL : Now checking device signature\n");
1043
1044 *class = ATA_DEV_NONE;
1045
1046 /* Verify if SStatus indicates device presence */
1047 if (ata_link_online(link)) {
1048 /*
1049 * if we are here, device presence has been detected,
1050 * 1st D2H FIS would have been received, but sfis in
1051 * command desc. is not updated, but signature register
1052 * would have been updated
1053 */
1054
1055 *class = sata_fsl_dev_classify(ap);
1056
1057 DPRINTK("class = %d\n", *class);
1058 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1059 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1060 }
1061
1062 return 0;
1063
1064 err:
1065 return -EIO;
1066 }
1067
1068 static void sata_fsl_error_handler(struct ata_port *ap)
1069 {
1070
1071 DPRINTK("in xx_error_handler\n");
1072 sata_pmp_error_handler(ap);
1073
1074 }
1075
1076 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1077 {
1078 if (qc->flags & ATA_QCFLAG_FAILED)
1079 qc->err_mask |= AC_ERR_OTHER;
1080
1081 if (qc->err_mask) {
1082 /* make DMA engine forget about the failed command */
1083
1084 }
1085 }
1086
1087 static void sata_fsl_error_intr(struct ata_port *ap)
1088 {
1089 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1090 void __iomem *hcr_base = host_priv->hcr_base;
1091 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1092 unsigned int err_mask = 0, action = 0;
1093 int freeze = 0, abort=0;
1094 struct ata_link *link = NULL;
1095 struct ata_queued_cmd *qc = NULL;
1096 struct ata_eh_info *ehi;
1097
1098 hstatus = ioread32(hcr_base + HSTATUS);
1099 cereg = ioread32(hcr_base + CE);
1100
1101 /* first, analyze and record host port events */
1102 link = &ap->link;
1103 ehi = &link->eh_info;
1104 ata_ehi_clear_desc(ehi);
1105
1106 /*
1107 * Handle & Clear SError
1108 */
1109
1110 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1111 if (unlikely(SError & 0xFFFF0000))
1112 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1113
1114 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1115 hstatus, cereg, ioread32(hcr_base + DE), SError);
1116
1117 /* handle fatal errors */
1118 if (hstatus & FATAL_ERROR_DECODE) {
1119 ehi->err_mask |= AC_ERR_ATA_BUS;
1120 ehi->action |= ATA_EH_SOFTRESET;
1121
1122 freeze = 1;
1123 }
1124
1125 /* Handle SDB FIS receive & notify update */
1126 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1127 sata_async_notification(ap);
1128
1129 /* Handle PHYRDY change notification */
1130 if (hstatus & INT_ON_PHYRDY_CHG) {
1131 DPRINTK("SATA FSL: PHYRDY change indication\n");
1132
1133 /* Setup a soft-reset EH action */
1134 ata_ehi_hotplugged(ehi);
1135 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1136 freeze = 1;
1137 }
1138
1139 /* handle single device errors */
1140 if (cereg) {
1141 /*
1142 * clear the command error, also clears queue to the device
1143 * in error, and we can (re)issue commands to this device.
1144 * When a device is in error all commands queued into the
1145 * host controller and at the device are considered aborted
1146 * and the queue for that device is stopped. Now, after
1147 * clearing the device error, we can issue commands to the
1148 * device to interrogate it to find the source of the error.
1149 */
1150 abort = 1;
1151
1152 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1153 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1154
1155 /* find out the offending link and qc */
1156 if (ap->nr_pmp_links) {
1157 unsigned int dev_num;
1158
1159 dereg = ioread32(hcr_base + DE);
1160 iowrite32(dereg, hcr_base + DE);
1161 iowrite32(cereg, hcr_base + CE);
1162
1163 dev_num = ffs(dereg) - 1;
1164 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1165 link = &ap->pmp_link[dev_num];
1166 ehi = &link->eh_info;
1167 qc = ata_qc_from_tag(ap, link->active_tag);
1168 /*
1169 * We should consider this as non fatal error,
1170 * and TF must be updated as done below.
1171 */
1172
1173 err_mask |= AC_ERR_DEV;
1174
1175 } else {
1176 err_mask |= AC_ERR_HSM;
1177 action |= ATA_EH_HARDRESET;
1178 freeze = 1;
1179 }
1180 } else {
1181 dereg = ioread32(hcr_base + DE);
1182 iowrite32(dereg, hcr_base + DE);
1183 iowrite32(cereg, hcr_base + CE);
1184
1185 qc = ata_qc_from_tag(ap, link->active_tag);
1186 /*
1187 * We should consider this as non fatal error,
1188 * and TF must be updated as done below.
1189 */
1190 err_mask |= AC_ERR_DEV;
1191 }
1192 }
1193
1194 /* record error info */
1195 if (qc)
1196 qc->err_mask |= err_mask;
1197 else
1198 ehi->err_mask |= err_mask;
1199
1200 ehi->action |= action;
1201
1202 /* freeze or abort */
1203 if (freeze)
1204 ata_port_freeze(ap);
1205 else if (abort) {
1206 if (qc)
1207 ata_link_abort(qc->dev->link);
1208 else
1209 ata_port_abort(ap);
1210 }
1211 }
1212
1213 static void sata_fsl_host_intr(struct ata_port *ap)
1214 {
1215 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1216 void __iomem *hcr_base = host_priv->hcr_base;
1217 u32 hstatus, done_mask = 0;
1218 struct ata_queued_cmd *qc;
1219 u32 SError;
1220 u32 tag;
1221 u32 status_mask = INT_ON_ERROR;
1222
1223 hstatus = ioread32(hcr_base + HSTATUS);
1224
1225 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1226
1227 /* Read command completed register */
1228 done_mask = ioread32(hcr_base + CC);
1229
1230 /* Workaround for data length mismatch errata */
1231 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1232 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1233 qc = ata_qc_from_tag(ap, tag);
1234 if (qc && ata_is_atapi(qc->tf.protocol)) {
1235 u32 hcontrol;
1236 /* Set HControl[27] to clear error registers */
1237 hcontrol = ioread32(hcr_base + HCONTROL);
1238 iowrite32(hcontrol | CLEAR_ERROR,
1239 hcr_base + HCONTROL);
1240
1241 /* Clear HControl[27] */
1242 iowrite32(hcontrol & ~CLEAR_ERROR,
1243 hcr_base + HCONTROL);
1244
1245 /* Clear SError[E] bit */
1246 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1247 SError);
1248
1249 /* Ignore fatal error and device error */
1250 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1251 | INT_ON_FATAL_ERR);
1252 break;
1253 }
1254 }
1255 }
1256
1257 if (unlikely(SError & 0xFFFF0000)) {
1258 DPRINTK("serror @host_intr : 0x%x\n", SError);
1259 sata_fsl_error_intr(ap);
1260 }
1261
1262 if (unlikely(hstatus & status_mask)) {
1263 DPRINTK("error interrupt!!\n");
1264 sata_fsl_error_intr(ap);
1265 return;
1266 }
1267
1268 VPRINTK("Status of all queues :\n");
1269 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1270 done_mask,
1271 ioread32(hcr_base + CA),
1272 ioread32(hcr_base + CE),
1273 ioread32(hcr_base + CQ),
1274 ap->qc_active);
1275
1276 if (done_mask & ap->qc_active) {
1277 int i;
1278 /* clear CC bit, this will also complete the interrupt */
1279 iowrite32(done_mask, hcr_base + CC);
1280
1281 DPRINTK("Status of all queues :\n");
1282 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1283 done_mask, ioread32(hcr_base + CA),
1284 ioread32(hcr_base + CE));
1285
1286 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1287 if (done_mask & (1 << i))
1288 DPRINTK
1289 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1290 i, ioread32(hcr_base + CC),
1291 ioread32(hcr_base + CA));
1292 }
1293 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1294 return;
1295
1296 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1297 iowrite32(1, hcr_base + CC);
1298 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1299
1300 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1301 ioread32(hcr_base + CC));
1302
1303 if (qc) {
1304 ata_qc_complete(qc);
1305 }
1306 } else {
1307 /* Spurious Interrupt!! */
1308 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1309 ioread32(hcr_base + CC));
1310 iowrite32(done_mask, hcr_base + CC);
1311 return;
1312 }
1313 }
1314
1315 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1316 {
1317 struct ata_host *host = dev_instance;
1318 struct sata_fsl_host_priv *host_priv = host->private_data;
1319 void __iomem *hcr_base = host_priv->hcr_base;
1320 u32 interrupt_enables;
1321 unsigned handled = 0;
1322 struct ata_port *ap;
1323
1324 /* ack. any pending IRQs for this controller/port */
1325 interrupt_enables = ioread32(hcr_base + HSTATUS);
1326 interrupt_enables &= 0x3F;
1327
1328 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1329
1330 if (!interrupt_enables)
1331 return IRQ_NONE;
1332
1333 spin_lock(&host->lock);
1334
1335 /* Assuming one port per host controller */
1336
1337 ap = host->ports[0];
1338 if (ap) {
1339 sata_fsl_host_intr(ap);
1340 } else {
1341 dev_warn(host->dev, "interrupt on disabled port 0\n");
1342 }
1343
1344 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1345 handled = 1;
1346
1347 spin_unlock(&host->lock);
1348
1349 return IRQ_RETVAL(handled);
1350 }
1351
1352 /*
1353 * Multiple ports are represented by multiple SATA controllers with
1354 * one port per controller
1355 */
1356 static int sata_fsl_init_controller(struct ata_host *host)
1357 {
1358 struct sata_fsl_host_priv *host_priv = host->private_data;
1359 void __iomem *hcr_base = host_priv->hcr_base;
1360 u32 temp;
1361
1362 /*
1363 * NOTE : We cannot bring the controller online before setting
1364 * the CHBA, hence main controller initialization is done as
1365 * part of the port_start() callback
1366 */
1367
1368 /* sata controller to operate in enterprise mode */
1369 temp = ioread32(hcr_base + HCONTROL);
1370 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1371
1372 /* ack. any pending IRQs for this controller/port */
1373 temp = ioread32(hcr_base + HSTATUS);
1374 if (temp & 0x3F)
1375 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1376
1377 /* Keep interrupts disabled on the controller */
1378 temp = ioread32(hcr_base + HCONTROL);
1379 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1380
1381 /* Disable interrupt coalescing control(icc), for the moment */
1382 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1383 iowrite32(0x01000000, hcr_base + ICC);
1384
1385 /* clear error registers, SError is cleared by libATA */
1386 iowrite32(0x00000FFFF, hcr_base + CE);
1387 iowrite32(0x00000FFFF, hcr_base + DE);
1388
1389 /*
1390 * reset the number of command complete bits which will cause the
1391 * interrupt to be signaled
1392 */
1393 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1394 intr_coalescing_ticks);
1395
1396 /*
1397 * host controller will be brought on-line, during xx_port_start()
1398 * callback, that should also initiate the OOB, COMINIT sequence
1399 */
1400
1401 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1402 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1403
1404 return 0;
1405 }
1406
1407 /*
1408 * scsi mid-layer and libata interface structures
1409 */
1410 static struct scsi_host_template sata_fsl_sht = {
1411 ATA_NCQ_SHT("sata_fsl"),
1412 .can_queue = SATA_FSL_QUEUE_DEPTH,
1413 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1414 .dma_boundary = ATA_DMA_BOUNDARY,
1415 };
1416
1417 static struct ata_port_operations sata_fsl_ops = {
1418 .inherits = &sata_pmp_port_ops,
1419
1420 .qc_defer = ata_std_qc_defer,
1421 .qc_prep = sata_fsl_qc_prep,
1422 .qc_issue = sata_fsl_qc_issue,
1423 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1424
1425 .scr_read = sata_fsl_scr_read,
1426 .scr_write = sata_fsl_scr_write,
1427
1428 .freeze = sata_fsl_freeze,
1429 .thaw = sata_fsl_thaw,
1430 .softreset = sata_fsl_softreset,
1431 .hardreset = sata_fsl_hardreset,
1432 .pmp_softreset = sata_fsl_softreset,
1433 .error_handler = sata_fsl_error_handler,
1434 .post_internal_cmd = sata_fsl_post_internal_cmd,
1435
1436 .port_start = sata_fsl_port_start,
1437 .port_stop = sata_fsl_port_stop,
1438
1439 .pmp_attach = sata_fsl_pmp_attach,
1440 .pmp_detach = sata_fsl_pmp_detach,
1441 };
1442
1443 static const struct ata_port_info sata_fsl_port_info[] = {
1444 {
1445 .flags = SATA_FSL_HOST_FLAGS,
1446 .pio_mask = ATA_PIO4,
1447 .udma_mask = ATA_UDMA6,
1448 .port_ops = &sata_fsl_ops,
1449 },
1450 };
1451
1452 static int sata_fsl_probe(struct platform_device *ofdev)
1453 {
1454 int retval = -ENXIO;
1455 void __iomem *hcr_base = NULL;
1456 void __iomem *ssr_base = NULL;
1457 void __iomem *csr_base = NULL;
1458 struct sata_fsl_host_priv *host_priv = NULL;
1459 int irq;
1460 struct ata_host *host = NULL;
1461 u32 temp;
1462
1463 struct ata_port_info pi = sata_fsl_port_info[0];
1464 const struct ata_port_info *ppi[] = { &pi, NULL };
1465
1466 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1467
1468 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1469 if (!hcr_base)
1470 goto error_exit_with_cleanup;
1471
1472 ssr_base = hcr_base + 0x100;
1473 csr_base = hcr_base + 0x140;
1474
1475 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1476 temp = ioread32(csr_base + TRANSCFG);
1477 temp = temp & 0xffffffe0;
1478 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1479 }
1480
1481 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1482 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1483 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1484
1485 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1486 if (!host_priv)
1487 goto error_exit_with_cleanup;
1488
1489 host_priv->hcr_base = hcr_base;
1490 host_priv->ssr_base = ssr_base;
1491 host_priv->csr_base = csr_base;
1492
1493 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1494 if (!irq) {
1495 dev_err(&ofdev->dev, "invalid irq from platform\n");
1496 goto error_exit_with_cleanup;
1497 }
1498 host_priv->irq = irq;
1499
1500 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1501 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1502 else
1503 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1504
1505 /* allocate host structure */
1506 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1507 if (!host) {
1508 retval = -ENOMEM;
1509 goto error_exit_with_cleanup;
1510 }
1511
1512 /* host->iomap is not used currently */
1513 host->private_data = host_priv;
1514
1515 /* initialize host controller */
1516 sata_fsl_init_controller(host);
1517
1518 /*
1519 * Now, register with libATA core, this will also initiate the
1520 * device discovery process, invoking our port_start() handler &
1521 * error_handler() to execute a dummy Softreset EH session
1522 */
1523 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1524 &sata_fsl_sht);
1525
1526 platform_set_drvdata(ofdev, host);
1527
1528 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1529 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1530 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1531 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1532 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1533 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1534 if (retval)
1535 goto error_exit_with_cleanup;
1536
1537 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1538 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1539 sysfs_attr_init(&host_priv->rx_watermark.attr);
1540 host_priv->rx_watermark.attr.name = "rx_watermark";
1541 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1542 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1543 if (retval) {
1544 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1545 goto error_exit_with_cleanup;
1546 }
1547
1548 return 0;
1549
1550 error_exit_with_cleanup:
1551
1552 if (host)
1553 ata_host_detach(host);
1554
1555 if (hcr_base)
1556 iounmap(hcr_base);
1557 kfree(host_priv);
1558
1559 return retval;
1560 }
1561
1562 static int sata_fsl_remove(struct platform_device *ofdev)
1563 {
1564 struct ata_host *host = platform_get_drvdata(ofdev);
1565 struct sata_fsl_host_priv *host_priv = host->private_data;
1566
1567 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1568 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1569
1570 ata_host_detach(host);
1571
1572 irq_dispose_mapping(host_priv->irq);
1573 iounmap(host_priv->hcr_base);
1574 kfree(host_priv);
1575
1576 return 0;
1577 }
1578
1579 #ifdef CONFIG_PM_SLEEP
1580 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1581 {
1582 struct ata_host *host = platform_get_drvdata(op);
1583 return ata_host_suspend(host, state);
1584 }
1585
1586 static int sata_fsl_resume(struct platform_device *op)
1587 {
1588 struct ata_host *host = platform_get_drvdata(op);
1589 struct sata_fsl_host_priv *host_priv = host->private_data;
1590 int ret;
1591 void __iomem *hcr_base = host_priv->hcr_base;
1592 struct ata_port *ap = host->ports[0];
1593 struct sata_fsl_port_priv *pp = ap->private_data;
1594
1595 ret = sata_fsl_init_controller(host);
1596 if (ret) {
1597 dev_err(&op->dev, "Error initializing hardware\n");
1598 return ret;
1599 }
1600
1601 /* Recovery the CHBA register in host controller cmd register set */
1602 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1603
1604 iowrite32((ioread32(hcr_base + HCONTROL)
1605 | HCONTROL_ONLINE_PHY_RST
1606 | HCONTROL_SNOOP_ENABLE
1607 | HCONTROL_PMP_ATTACHED),
1608 hcr_base + HCONTROL);
1609
1610 ata_host_resume(host);
1611 return 0;
1612 }
1613 #endif
1614
1615 static struct of_device_id fsl_sata_match[] = {
1616 {
1617 .compatible = "fsl,pq-sata",
1618 },
1619 {
1620 .compatible = "fsl,pq-sata-v2",
1621 },
1622 {},
1623 };
1624
1625 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1626
1627 static struct platform_driver fsl_sata_driver = {
1628 .driver = {
1629 .name = "fsl-sata",
1630 .of_match_table = fsl_sata_match,
1631 },
1632 .probe = sata_fsl_probe,
1633 .remove = sata_fsl_remove,
1634 #ifdef CONFIG_PM_SLEEP
1635 .suspend = sata_fsl_suspend,
1636 .resume = sata_fsl_resume,
1637 #endif
1638 };
1639
1640 module_platform_driver(fsl_sata_driver);
1641
1642 MODULE_LICENSE("GPL");
1643 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1644 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1645 MODULE_VERSION("1.10");
Linux with added FPC-III support