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USB: EHCI: fix compiler warning introduced by commit 2a40f324541e
[linux/fpc-iii.git] / drivers / pinctrl / sirf / pinctrl-atlas7.c
blobbeb024c31a5d8b5ffb115fa94283dc7909219f7c
1 /*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/io.h>
13 #include <linux/bitops.h>
14 #include <linux/irq.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/gpio.h>
30
31 /* Definition of Pad&Mux Properties */
32 #define N 0
33
34 /* The Bank contains input-disable regisgers */
35 #define BANK_DS 0
36
37 /* Clear Register offset */
38 #define CLR_REG(r) ((r) + 0x04)
39
40 /* Definition of multiple function select register */
41 #define FUNC_CLEAR_MASK 0x7
42 #define FUNC_GPIO 0
43 #define FUNC_ANALOGUE 0x8
44 #define ANA_CLEAR_MASK 0x1
45
46 /* The Atlas7's Pad Type List */
47 enum altas7_pad_type {
48 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
49 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
50 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
51 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
52 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
53 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
54 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
55 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
56 };
57
58 /* Raw value of Driver-Strength Bits */
59 #define DS3 BIT(3)
60 #define DS2 BIT(2)
61 #define DS1 BIT(1)
62 #define DS0 BIT(0)
63 #define DSZ 0
64
65 /* Drive-Strength Intermediate Values */
66 #define DS_NULL -1
67 #define DS_1BIT_IM_VAL DS0
68 #define DS_1BIT_MASK 0x1
69 #define DS_2BIT_IM_VAL (DS1 | DS0)
70 #define DS_2BIT_MASK 0x3
71 #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
72 #define DS_4BIT_MASK 0xf
73
74 /* The Drive-Strength of 4WE Pad DS1 0 CO */
75 #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
76 #define DS_4WE_2 (DS1) /* 1 0 2 */
77 #define DS_4WE_1 (DS0) /* 0 1 1 */
78 #define DS_4WE_0 (DSZ) /* 0 0 0 */
79
80 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
81 #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
82 #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
83 #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
84 #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
85 #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
86 #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
87 #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
88 #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
89 #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
90 #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
91 #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
92 #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
93 #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
94 #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
95 #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
96 #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
97
98 /* The Drive-Strength of M31 Pad DS0 CO */
99 #define DS_M31_0 (DSZ) /* 0 0 */
100 #define DS_M31_1 (DS0) /* 1 1 */
101
102 /* Raw values of Pull Option Bits */
103 #define PUN BIT(1)
104 #define PD BIT(0)
105 #define PE BIT(0)
106 #define PZ 0
107
108 /* Definition of Pull Types */
109 #define PULL_UP 0
110 #define HIGH_HYSTERESIS 1
111 #define HIGH_Z 2
112 #define PULL_DOWN 3
113 #define PULL_DISABLE 4
114 #define PULL_ENABLE 5
115 #define PULL_UNKNOWN -1
116
117 /* Pull Options for 4WE Pad PUN PD CO */
118 #define P4WE_PULL_MASK 0x3
119 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
120 #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
121 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122 #define P4WE_PULL_UP (PZ) /* 0 0 0 */
123
124 /* Pull Options for 16ST Pad PUN PD CO */
125 #define P16ST_PULL_MASK 0x3
126 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
127 #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
128 #define P16ST_PULL_UP (PZ) /* 0 0 0 */
129
130 /* Pull Options for M31 Pad PE */
131 #define PM31_PULL_MASK 0x1
132 #define PM31_PULL_ENABLED (PE) /* 1 */
133 #define PM31_PULL_DISABLED (PZ) /* 0 */
134
135 /* Pull Options for A/D Pad PUN PD CO */
136 #define PANGD_PULL_MASK 0x3
137 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
138 #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
139 #define PANGD_PULL_UP (PZ) /* 0 0 0 */
140
141 /* Definition of Input Disable */
142 #define DI_MASK 0x1
143 #define DI_DISABLE 0x1
144 #define DI_ENABLE 0x0
145
146 /* Definition of Input Disable Value */
147 #define DIV_MASK 0x1
148 #define DIV_DISABLE 0x1
149 #define DIV_ENABLE 0x0
150
151 /* Number of Function input disable registers */
152 #define NUM_OF_IN_DISABLE_REG 0x2
153
154 /* Offset of Function input disable registers */
155 #define IN_DISABLE_0_REG_SET 0x0A00
156 #define IN_DISABLE_0_REG_CLR 0x0A04
157 #define IN_DISABLE_1_REG_SET 0x0A08
158 #define IN_DISABLE_1_REG_CLR 0x0A0C
159 #define IN_DISABLE_VAL_0_REG_SET 0x0A80
160 #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
161 #define IN_DISABLE_VAL_1_REG_SET 0x0A88
162 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
163
164 /* Offset of the SDIO9SEL*/
165 #define SYS2PCI_SDIO9SEL 0x14
166
167 struct dt_params {
168 const char *property;
169 int value;
170 };
171
172 /**
173 * struct atlas7_pad_conf - Atlas7 Pad Configuration
174 * @id The ID of this Pad.
175 * @type: The type of this Pad.
176 * @mux_reg: The mux register offset.
177 * This register contains the mux.
178 * @pupd_reg: The pull-up/down register offset.
179 * @drvstr_reg: The drive-strength register offset.
180 * @ad_ctrl_reg: The Analogue/Digital Control register.
181 *
182 * @mux_bit: The start bit of mux register.
183 * @pupd_bit: The start bit of pull-up/down register.
184 * @drvstr_bit: The start bit of drive-strength register.
185 * @ad_ctrl_bit: The start bit of analogue/digital register.
186 */
187 struct atlas7_pad_config {
188 const u32 id;
189 u32 type;
190 u32 mux_reg;
191 u32 pupd_reg;
192 u32 drvstr_reg;
193 u32 ad_ctrl_reg;
194 /* bits in register */
195 u8 mux_bit;
196 u8 pupd_bit;
197 u8 drvstr_bit;
198 u8 ad_ctrl_bit;
199 };
200
201 #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
202 { \
203 .id = pad, \
204 .type = t, \
205 .mux_reg = mr, \
206 .pupd_reg = pr, \
207 .drvstr_reg = dsr, \
208 .ad_ctrl_reg = adr, \
209 .mux_bit = mb, \
210 .pupd_bit = pb, \
211 .drvstr_bit = dsb, \
212 .ad_ctrl_bit = adb, \
213 }
214
215 /**
216 * struct atlas7_pad_status - Atlas7 Pad status
217 */
218 struct atlas7_pad_status {
219 u8 func;
220 u8 pull;
221 u8 dstr;
222 u8 reserved;
223 };
224
225 /**
226 * struct atlas7_pad_mux - Atlas7 mux
227 * @bank: The bank of this pad's registers on.
228 * @pin : The ID of this Pad.
229 * @func: The mux func on this Pad.
230 * @dinput_reg: The Input-Disable register offset.
231 * @dinput_bit: The start bit of Input-Disable register.
232 * @dinput_val_reg: The Input-Disable-value register offset.
233 * This register is used to set the value of this pad
234 * if this pad was disabled.
235 * @dinput_val_bit: The start bit of Input-Disable Value register.
236 */
237 struct atlas7_pad_mux {
238 u32 bank;
239 u32 pin;
240 u32 func;
241 u32 dinput_reg;
242 u32 dinput_bit;
243 u32 dinput_val_reg;
244 u32 dinput_val_bit;
245 };
246
247 #define MUX(b, pad, f, dr, db, dvr, dvb) \
248 { \
249 .bank = b, \
250 .pin = pad, \
251 .func = f, \
252 .dinput_reg = dr, \
253 .dinput_bit = db, \
254 .dinput_val_reg = dvr, \
255 .dinput_val_bit = dvb, \
256 }
257
258 struct atlas7_grp_mux {
259 unsigned int group;
260 unsigned int pad_mux_count;
261 const struct atlas7_pad_mux *pad_mux_list;
262 };
263
264 /**
265 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
266 * @name: the name of this specific pin group
267 * @pins: an array of discrete physical pins used in this group, taken
268 * from the driver-local pin enumeration space
269 * @num_pins: the number of pins in this group array, i.e. the number of
270 * elements in .pins so we can iterate over that array
271 */
272 struct atlas7_pin_group {
273 const char *name;
274 const unsigned int *pins;
275 const unsigned num_pins;
276 };
277
278 #define GROUP(n, p) \
279 { \
280 .name = n, \
281 .pins = p, \
282 .num_pins = ARRAY_SIZE(p), \
283 }
284
285 struct atlas7_pmx_func {
286 const char *name;
287 const char * const *groups;
288 const unsigned num_groups;
289 const struct atlas7_grp_mux *grpmux;
290 };
291
292 #define FUNCTION(n, g, m) \
293 { \
294 .name = n, \
295 .groups = g, \
296 .num_groups = ARRAY_SIZE(g), \
297 .grpmux = m, \
298 }
299
300 struct atlas7_pinctrl_data {
301 struct pinctrl_pin_desc *pads;
302 int pads_cnt;
303 struct atlas7_pin_group *grps;
304 int grps_cnt;
305 struct atlas7_pmx_func *funcs;
306 int funcs_cnt;
307 struct atlas7_pad_config *confs;
308 int confs_cnt;
309 };
310
311 /* Platform info of atlas7 pinctrl */
312 #define ATLAS7_PINCTRL_REG_BANKS 2
313 #define ATLAS7_PINCTRL_BANK_0_PINS 18
314 #define ATLAS7_PINCTRL_BANK_1_PINS 141
315 #define ATLAS7_PINCTRL_TOTAL_PINS \
316 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
317
318 /**
319 * Atlas7 GPIO Chip
320 */
321
322 #define NGPIO_OF_BANK 32
323 #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
324
325 /* Registers of GPIO Controllers */
326 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
327 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
328 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
329
330 /* Definition bits of GPIO Control Registers */
331 #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
332 #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
333 #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
334 #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
335 #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
336 #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
337 #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
338 #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
339
340 struct atlas7_gpio_bank {
341 struct pinctrl_dev *pctldev;
342 int id;
343 int irq;
344 void __iomem *base;
345 unsigned int gpio_offset;
346 unsigned int ngpio;
347 const unsigned int *gpio_pins;
348 u32 sleep_data[NGPIO_OF_BANK];
349 };
350
351 struct atlas7_gpio_chip {
352 const char *name;
353 void __iomem *reg;
354 struct clk *clk;
355 int nbank;
356 spinlock_t lock;
357 struct gpio_chip chip;
358 struct atlas7_gpio_bank banks[0];
359 };
360
361 /**
362 * @dev: a pointer back to containing device
363 * @virtbase: the offset to the controller in virtual memory
364 */
365 struct atlas7_pmx {
366 struct device *dev;
367 struct pinctrl_dev *pctl;
368 struct pinctrl_desc pctl_desc;
369 struct atlas7_pinctrl_data *pctl_data;
370 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
371 void __iomem *sys2pci_base;
372 u32 status_ds[NUM_OF_IN_DISABLE_REG];
373 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
374 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
375 };
376
377 /*
378 * Pad list for the pinmux subsystem
379 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
380 */
381
382 /*Pads in IOC RTC & TOP */
383 static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
384 /* RTC PADs */
385 PINCTRL_PIN(0, "rtc_gpio_0"),
386 PINCTRL_PIN(1, "rtc_gpio_1"),
387 PINCTRL_PIN(2, "rtc_gpio_2"),
388 PINCTRL_PIN(3, "rtc_gpio_3"),
389 PINCTRL_PIN(4, "low_bat_ind_b"),
390 PINCTRL_PIN(5, "on_key_b"),
391 PINCTRL_PIN(6, "ext_on"),
392 PINCTRL_PIN(7, "mem_on"),
393 PINCTRL_PIN(8, "core_on"),
394 PINCTRL_PIN(9, "io_on"),
395 PINCTRL_PIN(10, "can0_tx"),
396 PINCTRL_PIN(11, "can0_rx"),
397 PINCTRL_PIN(12, "spi0_clk"),
398 PINCTRL_PIN(13, "spi0_cs_b"),
399 PINCTRL_PIN(14, "spi0_io_0"),
400 PINCTRL_PIN(15, "spi0_io_1"),
401 PINCTRL_PIN(16, "spi0_io_2"),
402 PINCTRL_PIN(17, "spi0_io_3"),
403
404 /* TOP PADs */
405 PINCTRL_PIN(18, "spi1_en"),
406 PINCTRL_PIN(19, "spi1_clk"),
407 PINCTRL_PIN(20, "spi1_din"),
408 PINCTRL_PIN(21, "spi1_dout"),
409 PINCTRL_PIN(22, "trg_spi_clk"),
410 PINCTRL_PIN(23, "trg_spi_di"),
411 PINCTRL_PIN(24, "trg_spi_do"),
412 PINCTRL_PIN(25, "trg_spi_cs_b"),
413 PINCTRL_PIN(26, "trg_acq_d1"),
414 PINCTRL_PIN(27, "trg_irq_b"),
415 PINCTRL_PIN(28, "trg_acq_d0"),
416 PINCTRL_PIN(29, "trg_acq_clk"),
417 PINCTRL_PIN(30, "trg_shutdown_b_out"),
418 PINCTRL_PIN(31, "sdio2_clk"),
419 PINCTRL_PIN(32, "sdio2_cmd"),
420 PINCTRL_PIN(33, "sdio2_dat_0"),
421 PINCTRL_PIN(34, "sdio2_dat_1"),
422 PINCTRL_PIN(35, "sdio2_dat_2"),
423 PINCTRL_PIN(36, "sdio2_dat_3"),
424 PINCTRL_PIN(37, "df_ad_7"),
425 PINCTRL_PIN(38, "df_ad_6"),
426 PINCTRL_PIN(39, "df_ad_5"),
427 PINCTRL_PIN(40, "df_ad_4"),
428 PINCTRL_PIN(41, "df_ad_3"),
429 PINCTRL_PIN(42, "df_ad_2"),
430 PINCTRL_PIN(43, "df_ad_1"),
431 PINCTRL_PIN(44, "df_ad_0"),
432 PINCTRL_PIN(45, "df_dqs"),
433 PINCTRL_PIN(46, "df_cle"),
434 PINCTRL_PIN(47, "df_ale"),
435 PINCTRL_PIN(48, "df_we_b"),
436 PINCTRL_PIN(49, "df_re_b"),
437 PINCTRL_PIN(50, "df_ry_by"),
438 PINCTRL_PIN(51, "df_cs_b_1"),
439 PINCTRL_PIN(52, "df_cs_b_0"),
440 PINCTRL_PIN(53, "l_pclk"),
441 PINCTRL_PIN(54, "l_lck"),
442 PINCTRL_PIN(55, "l_fck"),
443 PINCTRL_PIN(56, "l_de"),
444 PINCTRL_PIN(57, "ldd_0"),
445 PINCTRL_PIN(58, "ldd_1"),
446 PINCTRL_PIN(59, "ldd_2"),
447 PINCTRL_PIN(60, "ldd_3"),
448 PINCTRL_PIN(61, "ldd_4"),
449 PINCTRL_PIN(62, "ldd_5"),
450 PINCTRL_PIN(63, "ldd_6"),
451 PINCTRL_PIN(64, "ldd_7"),
452 PINCTRL_PIN(65, "ldd_8"),
453 PINCTRL_PIN(66, "ldd_9"),
454 PINCTRL_PIN(67, "ldd_10"),
455 PINCTRL_PIN(68, "ldd_11"),
456 PINCTRL_PIN(69, "ldd_12"),
457 PINCTRL_PIN(70, "ldd_13"),
458 PINCTRL_PIN(71, "ldd_14"),
459 PINCTRL_PIN(72, "ldd_15"),
460 PINCTRL_PIN(73, "lcd_gpio_20"),
461 PINCTRL_PIN(74, "vip_0"),
462 PINCTRL_PIN(75, "vip_1"),
463 PINCTRL_PIN(76, "vip_2"),
464 PINCTRL_PIN(77, "vip_3"),
465 PINCTRL_PIN(78, "vip_4"),
466 PINCTRL_PIN(79, "vip_5"),
467 PINCTRL_PIN(80, "vip_6"),
468 PINCTRL_PIN(81, "vip_7"),
469 PINCTRL_PIN(82, "vip_pxclk"),
470 PINCTRL_PIN(83, "vip_hsync"),
471 PINCTRL_PIN(84, "vip_vsync"),
472 PINCTRL_PIN(85, "sdio3_clk"),
473 PINCTRL_PIN(86, "sdio3_cmd"),
474 PINCTRL_PIN(87, "sdio3_dat_0"),
475 PINCTRL_PIN(88, "sdio3_dat_1"),
476 PINCTRL_PIN(89, "sdio3_dat_2"),
477 PINCTRL_PIN(90, "sdio3_dat_3"),
478 PINCTRL_PIN(91, "sdio5_clk"),
479 PINCTRL_PIN(92, "sdio5_cmd"),
480 PINCTRL_PIN(93, "sdio5_dat_0"),
481 PINCTRL_PIN(94, "sdio5_dat_1"),
482 PINCTRL_PIN(95, "sdio5_dat_2"),
483 PINCTRL_PIN(96, "sdio5_dat_3"),
484 PINCTRL_PIN(97, "rgmii_txd_0"),
485 PINCTRL_PIN(98, "rgmii_txd_1"),
486 PINCTRL_PIN(99, "rgmii_txd_2"),
487 PINCTRL_PIN(100, "rgmii_txd_3"),
488 PINCTRL_PIN(101, "rgmii_txclk"),
489 PINCTRL_PIN(102, "rgmii_tx_ctl"),
490 PINCTRL_PIN(103, "rgmii_rxd_0"),
491 PINCTRL_PIN(104, "rgmii_rxd_1"),
492 PINCTRL_PIN(105, "rgmii_rxd_2"),
493 PINCTRL_PIN(106, "rgmii_rxd_3"),
494 PINCTRL_PIN(107, "rgmii_rx_clk"),
495 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
496 PINCTRL_PIN(109, "rgmii_mdio"),
497 PINCTRL_PIN(110, "rgmii_mdc"),
498 PINCTRL_PIN(111, "rgmii_intr_n"),
499 PINCTRL_PIN(112, "i2s_mclk"),
500 PINCTRL_PIN(113, "i2s_bclk"),
501 PINCTRL_PIN(114, "i2s_ws"),
502 PINCTRL_PIN(115, "i2s_dout0"),
503 PINCTRL_PIN(116, "i2s_dout1"),
504 PINCTRL_PIN(117, "i2s_dout2"),
505 PINCTRL_PIN(118, "i2s_din"),
506 PINCTRL_PIN(119, "gpio_0"),
507 PINCTRL_PIN(120, "gpio_1"),
508 PINCTRL_PIN(121, "gpio_2"),
509 PINCTRL_PIN(122, "gpio_3"),
510 PINCTRL_PIN(123, "gpio_4"),
511 PINCTRL_PIN(124, "gpio_5"),
512 PINCTRL_PIN(125, "gpio_6"),
513 PINCTRL_PIN(126, "gpio_7"),
514 PINCTRL_PIN(127, "sda_0"),
515 PINCTRL_PIN(128, "scl_0"),
516 PINCTRL_PIN(129, "coex_pio_0"),
517 PINCTRL_PIN(130, "coex_pio_1"),
518 PINCTRL_PIN(131, "coex_pio_2"),
519 PINCTRL_PIN(132, "coex_pio_3"),
520 PINCTRL_PIN(133, "uart0_tx"),
521 PINCTRL_PIN(134, "uart0_rx"),
522 PINCTRL_PIN(135, "uart1_tx"),
523 PINCTRL_PIN(136, "uart1_rx"),
524 PINCTRL_PIN(137, "uart3_tx"),
525 PINCTRL_PIN(138, "uart3_rx"),
526 PINCTRL_PIN(139, "uart4_tx"),
527 PINCTRL_PIN(140, "uart4_rx"),
528 PINCTRL_PIN(141, "usp0_clk"),
529 PINCTRL_PIN(142, "usp0_tx"),
530 PINCTRL_PIN(143, "usp0_rx"),
531 PINCTRL_PIN(144, "usp0_fs"),
532 PINCTRL_PIN(145, "usp1_clk"),
533 PINCTRL_PIN(146, "usp1_tx"),
534 PINCTRL_PIN(147, "usp1_rx"),
535 PINCTRL_PIN(148, "usp1_fs"),
536 PINCTRL_PIN(149, "lvds_tx0d4p"),
537 PINCTRL_PIN(150, "lvds_tx0d4n"),
538 PINCTRL_PIN(151, "lvds_tx0d3p"),
539 PINCTRL_PIN(152, "lvds_tx0d3n"),
540 PINCTRL_PIN(153, "lvds_tx0d2p"),
541 PINCTRL_PIN(154, "lvds_tx0d2n"),
542 PINCTRL_PIN(155, "lvds_tx0d1p"),
543 PINCTRL_PIN(156, "lvds_tx0d1n"),
544 PINCTRL_PIN(157, "lvds_tx0d0p"),
545 PINCTRL_PIN(158, "lvds_tx0d0n"),
546 PINCTRL_PIN(159, "jtag_tdo"),
547 PINCTRL_PIN(160, "jtag_tms"),
548 PINCTRL_PIN(161, "jtag_tck"),
549 PINCTRL_PIN(162, "jtag_tdi"),
550 PINCTRL_PIN(163, "jtag_trstn"),
551 };
552
553 struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
554 /* The Configuration of IOC_RTC Pads */
555 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
556 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
557 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
558 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
559 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
560 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
561 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
562 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
563 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
564 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
565 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
566 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
567 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
568 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
569 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
570 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
571 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
572 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
573 /* The Configuration of IOC_TOP Pads */
574 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
575 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
576 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
577 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
578 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
579 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
580 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
581 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
582 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
583 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
584 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
585 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
586 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
587 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
588 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
589 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
590 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
591 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
592 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
593 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
594 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
595 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
596 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
597 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
598 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
599 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
600 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
601 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
602 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
603 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
604 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
605 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
606 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
607 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
608 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
609 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
610 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
611 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
612 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
613 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
614 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
615 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
616 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
617 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
618 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
619 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
620 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
621 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
622 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
623 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
624 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
625 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
626 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
627 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
628 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
629 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
630 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
631 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
632 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
633 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
634 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
635 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
636 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
637 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
638 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
639 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
640 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
641 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
642 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
643 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
644 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
645 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
646 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
647 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
648 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
649 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
650 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
651 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
652 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
653 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
654 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
655 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
656 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
657 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
658 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
659 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
660 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
661 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
662 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
663 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
664 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
665 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
666 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
667 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
668 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
669 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
670 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
671 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
672 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
673 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
674 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
675 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
676 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
677 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
678 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
679 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
680 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
681 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
682 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
683 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
684 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
685 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
686 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
687 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
688 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
689 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
690 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
691 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
692 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
693 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
694 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
695 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
696 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
697 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
698 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
699 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
700 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
701 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
702 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
703 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
704 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
705 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
706 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
707 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
708 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
709 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
710 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
711 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
712 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
713 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
714 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
715 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
716 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
717 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
718 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
719 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
720 };
721
722 /* pin list of each pin group */
723 static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
724 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
725 static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
726 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
727 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
728 static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
729 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
730 95, 96, 112, 113, 114, 115, 116, 117, 118, };
731 static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
732 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
733 141, 142, 143, 144, 145, 146, 147, 148, };
734 static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
735 151, 152, 149, 150, };
736 static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
737 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
738 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
739 static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
740 14, 15, 16, 17, 9, };
741 static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
742 static const unsigned int audio_digmic_pins0[] = { 51, };
743 static const unsigned int audio_digmic_pins1[] = { 122, };
744 static const unsigned int audio_digmic_pins2[] = { 161, };
745 static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
746 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
747 115, 49, 50, 142, 143, 80, };
748 static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
749 114, };
750 static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
751 static const unsigned int audio_i2s_extclk_pins[] = { 112, };
752 static const unsigned int audio_spdif_out_pins0[] = { 112, };
753 static const unsigned int audio_spdif_out_pins1[] = { 116, };
754 static const unsigned int audio_spdif_out_pins2[] = { 142, };
755 static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
756 static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
757 static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
758 static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
759 static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
760 static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
761 static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
762 static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
763 static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
764 static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
765 static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
766 static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
767 static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
768 static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
769 static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
770 static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
771 static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
772 static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
773 static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
774 static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
775 static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
776 static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
777 static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
778 static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
779 static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
780 static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
781 static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
782 static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
783 static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
784 static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
785 static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
786 static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
787 static const unsigned int c1_can_rxd_pins0[] = { 138, };
788 static const unsigned int c1_can_rxd_pins1[] = { 147, };
789 static const unsigned int c1_can_rxd_pins2[] = { 2, };
790 static const unsigned int c1_can_rxd_pins3[] = { 162, };
791 static const unsigned int c1_can_txd_pins0[] = { 137, };
792 static const unsigned int c1_can_txd_pins1[] = { 146, };
793 static const unsigned int c1_can_txd_pins2[] = { 3, };
794 static const unsigned int c1_can_txd_pins3[] = { 161, };
795 static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
796 69, 70, 71, };
797 static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
798 static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
799 static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
800 static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
801 static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
802 49, 50, 54, 55, 56, };
803 static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
804 static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
805 static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
806 76, 77, };
807 static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
808 static const unsigned int clkc_pins0[] = { 30, 47, };
809 static const unsigned int clkc_pins1[] = { 78, 54, };
810 static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
811 static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
812 static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
813 static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
814 static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
815 static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
816 79, 80, 81, 83, 84, 73, 55, 56, };
817 static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
818 static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
819 static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
820 static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
821 static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
822 static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
823 static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
824 static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
825 static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
826 static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
827 static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
828 static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
829 static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
830 static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
831 static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
832 static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
833 static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
834 120, };
835 static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
836 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
837 static const unsigned int gn_gnss_eclk_pins[] = { 113, };
838 static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
839 static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
840 static const unsigned int gn_gnss_tm_pins[] = { 115, };
841 static const unsigned int gn_gnss_tsync_pins[] = { 114, };
842 static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
843 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
844 static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
845 static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
846 static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
847 static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
848 static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
849 static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
850 static const unsigned int i2c0_pins[] = { 128, 127, };
851 static const unsigned int i2c1_pins[] = { 126, 125, };
852 static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
853 static const unsigned int i2s1_basic_pins[] = { 95, 96, };
854 static const unsigned int i2s1_rxd0_pins0[] = { 61, };
855 static const unsigned int i2s1_rxd0_pins1[] = { 131, };
856 static const unsigned int i2s1_rxd0_pins2[] = { 129, };
857 static const unsigned int i2s1_rxd0_pins3[] = { 117, };
858 static const unsigned int i2s1_rxd0_pins4[] = { 83, };
859 static const unsigned int i2s1_rxd1_pins0[] = { 72, };
860 static const unsigned int i2s1_rxd1_pins1[] = { 132, };
861 static const unsigned int i2s1_rxd1_pins2[] = { 130, };
862 static const unsigned int i2s1_rxd1_pins3[] = { 118, };
863 static const unsigned int i2s1_rxd1_pins4[] = { 84, };
864 static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
865 static const unsigned int jtag_ntrst_pins0[] = { 4, };
866 static const unsigned int jtag_ntrst_pins1[] = { 163, };
867 static const unsigned int jtag_swdiotms_pins0[] = { 2, };
868 static const unsigned int jtag_swdiotms_pins1[] = { 160, };
869 static const unsigned int jtag_tck_pins0[] = { 0, };
870 static const unsigned int jtag_tck_pins1[] = { 161, };
871 static const unsigned int jtag_tdi_pins0[] = { 1, };
872 static const unsigned int jtag_tdi_pins1[] = { 162, };
873 static const unsigned int jtag_tdo_pins0[] = { 3, };
874 static const unsigned int jtag_tdo_pins1[] = { 159, };
875 static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
876 static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
877 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
878 81, 56, 53, };
879 static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
880 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
881 static const unsigned int ld_ldd_fck_pins[] = { 55, };
882 static const unsigned int ld_ldd_lck_pins[] = { 54, };
883 static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
884 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
885 static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
886 155, 156, 157, 158, };
887 static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
888 37, 47, 46, 52, 45, 49, 50, 48, };
889 static const unsigned int nd_df_wp_pins[] = { 124, };
890 static const unsigned int nd_df_cs_pins[] = { 51, };
891 static const unsigned int ps_pins[] = { 120, 119, 121, };
892 static const unsigned int ps_no_dir_pins[] = { 119, };
893 static const unsigned int pwc_core_on_pins[] = { 8, };
894 static const unsigned int pwc_ext_on_pins[] = { 6, };
895 static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
896 static const unsigned int pwc_io_on_pins[] = { 9, };
897 static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
898 static const unsigned int pwc_mem_on_pins[] = { 7, };
899 static const unsigned int pwc_on_key_b_pins0[] = { 5, };
900 static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
901 static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
902 static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
903 static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
904 static const unsigned int pw_cko0_pins0[] = { 123, };
905 static const unsigned int pw_cko0_pins1[] = { 101, };
906 static const unsigned int pw_cko0_pins2[] = { 82, };
907 static const unsigned int pw_cko0_pins3[] = { 162, };
908 static const unsigned int pw_cko1_pins0[] = { 124, };
909 static const unsigned int pw_cko1_pins1[] = { 110, };
910 static const unsigned int pw_cko1_pins2[] = { 163, };
911 static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
912 static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
913 static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
914 static const unsigned int pw_pwm0_pins0[] = { 119, };
915 static const unsigned int pw_pwm0_pins1[] = { 159, };
916 static const unsigned int pw_pwm1_pins0[] = { 120, };
917 static const unsigned int pw_pwm1_pins1[] = { 160, };
918 static const unsigned int pw_pwm1_pins2[] = { 131, };
919 static const unsigned int pw_pwm2_pins0[] = { 121, };
920 static const unsigned int pw_pwm2_pins1[] = { 98, };
921 static const unsigned int pw_pwm2_pins2[] = { 161, };
922 static const unsigned int pw_pwm3_pins0[] = { 122, };
923 static const unsigned int pw_pwm3_pins1[] = { 73, };
924 static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
925 static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
926 static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
927 static const unsigned int pw_backlight_pins0[] = { 122, };
928 static const unsigned int pw_backlight_pins1[] = { 73, };
929 static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
930 102, 97, 98, 99, 100, 101, };
931 static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
932 static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
933 static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
934 static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
935 static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
936 37, };
937 static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
938 static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
939 37, };
940 static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
941 static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
942 static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
943 static const unsigned int sd2_cdb_pins0[] = { 124, };
944 static const unsigned int sd2_cdb_pins1[] = { 161, };
945 static const unsigned int sd2_wpb_pins0[] = { 123, };
946 static const unsigned int sd2_wpb_pins1[] = { 163, };
947 static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
948 static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
949 static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
950 static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
951 static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
952 static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
953 static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
954 static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
955 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
956 static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
957 static const unsigned int uart0_nopause_pins[] = { 134, 133, };
958 static const unsigned int uart1_pins[] = { 136, 135, };
959 static const unsigned int uart2_cts_pins0[] = { 132, };
960 static const unsigned int uart2_cts_pins1[] = { 162, };
961 static const unsigned int uart2_rts_pins0[] = { 131, };
962 static const unsigned int uart2_rts_pins1[] = { 161, };
963 static const unsigned int uart2_rxd_pins0[] = { 11, };
964 static const unsigned int uart2_rxd_pins1[] = { 160, };
965 static const unsigned int uart2_rxd_pins2[] = { 130, };
966 static const unsigned int uart2_txd_pins0[] = { 10, };
967 static const unsigned int uart2_txd_pins1[] = { 159, };
968 static const unsigned int uart2_txd_pins2[] = { 129, };
969 static const unsigned int uart3_cts_pins0[] = { 125, };
970 static const unsigned int uart3_cts_pins1[] = { 111, };
971 static const unsigned int uart3_cts_pins2[] = { 140, };
972 static const unsigned int uart3_rts_pins0[] = { 126, };
973 static const unsigned int uart3_rts_pins1[] = { 109, };
974 static const unsigned int uart3_rts_pins2[] = { 139, };
975 static const unsigned int uart3_rxd_pins0[] = { 138, };
976 static const unsigned int uart3_rxd_pins1[] = { 84, };
977 static const unsigned int uart3_rxd_pins2[] = { 162, };
978 static const unsigned int uart3_txd_pins0[] = { 137, };
979 static const unsigned int uart3_txd_pins1[] = { 83, };
980 static const unsigned int uart3_txd_pins2[] = { 161, };
981 static const unsigned int uart4_basic_pins[] = { 140, 139, };
982 static const unsigned int uart4_cts_pins0[] = { 122, };
983 static const unsigned int uart4_cts_pins1[] = { 100, };
984 static const unsigned int uart4_cts_pins2[] = { 117, };
985 static const unsigned int uart4_rts_pins0[] = { 123, };
986 static const unsigned int uart4_rts_pins1[] = { 99, };
987 static const unsigned int uart4_rts_pins2[] = { 116, };
988 static const unsigned int usb0_drvvbus_pins0[] = { 51, };
989 static const unsigned int usb0_drvvbus_pins1[] = { 162, };
990 static const unsigned int usb1_drvvbus_pins0[] = { 134, };
991 static const unsigned int usb1_drvvbus_pins1[] = { 163, };
992 static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
993 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
994 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
995 static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
996 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
997 static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
998 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
999 99, 100, };
1000 static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
1001 80, 81, 82, 83, 84, };
1002 static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
1003 105, 106, 107, 102, 97, 98, };
1004
1005 /* definition of pin group table */
1006 struct atlas7_pin_group altas7_pin_groups[] = {
1007 GROUP("gnss_gpio_grp", gnss_gpio_pins),
1008 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1009 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1010 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1011 GROUP("lvds_gpio_grp", lvds_gpio_pins),
1012 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1013 GROUP("rtc_gpio_grp", rtc_gpio_pins),
1014 GROUP("audio_ac97_grp", audio_ac97_pins),
1015 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1016 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1017 GROUP("audio_digmic_grp2", audio_digmic_pins2),
1018 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1019 GROUP("audio_i2s_grp", audio_i2s_pins),
1020 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1021 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1022 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1023 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1024 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1025 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1026 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1027 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1028 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1029 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1030 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1031 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1032 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1033 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1034 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1035 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1036 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1037 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1038 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1039 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1040 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1041 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1042 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1043 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1044 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1045 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1046 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1047 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1048 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1049 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1050 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1051 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1052 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1053 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1054 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1055 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1056 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1057 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1058 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1059 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1060 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1061 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1062 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1063 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1064 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1065 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1066 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1067 GROUP("ca_coex_grp", ca_coex_pins),
1068 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1069 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1070 GROUP("ca_pio_grp", ca_pio_pins),
1071 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1072 GROUP("ca_spi_grp", ca_spi_pins),
1073 GROUP("ca_trb_grp", ca_trb_pins),
1074 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1075 GROUP("clkc_grp0", clkc_pins0),
1076 GROUP("clkc_grp1", clkc_pins1),
1077 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1078 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1079 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1080 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1081 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1082 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1083 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1084 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1085 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1086 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1087 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1088 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1089 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1090 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1091 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1092 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1093 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1094 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1095 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1096 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1097 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1098 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1099 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1100 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1101 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1102 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1103 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1104 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1105 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1106 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1107 GROUP("gn_trg_grp0", gn_trg_pins0),
1108 GROUP("gn_trg_grp1", gn_trg_pins1),
1109 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1110 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1111 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1112 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1113 GROUP("i2c0_grp", i2c0_pins),
1114 GROUP("i2c1_grp", i2c1_pins),
1115 GROUP("i2s0_grp", i2s0_pins),
1116 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1117 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1118 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1119 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1120 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1121 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1122 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1123 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1124 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1125 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1126 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1127 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1128 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1129 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1130 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1131 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1132 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1133 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1134 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1135 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1136 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1137 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1138 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1139 GROUP("ld_ldd_grp", ld_ldd_pins),
1140 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1141 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1142 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1143 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1144 GROUP("lvds_analog_grp", lvds_analog_pins),
1145 GROUP("nd_df_basic_grp", nd_df_basic_pins),
1146 GROUP("nd_df_wp_grp", nd_df_wp_pins),
1147 GROUP("nd_df_cs_grp", nd_df_cs_pins),
1148 GROUP("ps_grp", ps_pins),
1149 GROUP("ps_no_dir_grp", ps_no_dir_pins),
1150 GROUP("pwc_core_on_grp", pwc_core_on_pins),
1151 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1152 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1153 GROUP("pwc_io_on_grp", pwc_io_on_pins),
1154 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1155 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1156 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1157 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1158 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1159 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1160 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1161 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1162 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1163 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1164 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1165 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1166 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1167 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1168 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1169 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1170 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1171 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1172 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1173 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1174 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1175 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1176 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1177 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1178 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1179 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1180 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1181 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1182 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1183 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1184 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1185 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1186 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1187 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1188 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1189 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1190 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1191 GROUP("sd0_grp", sd0_pins),
1192 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1193 GROUP("sd1_grp", sd1_pins),
1194 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1195 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1196 GROUP("sd2_basic_grp", sd2_basic_pins),
1197 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1198 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1199 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1200 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1201 GROUP("sd3_9_grp", sd3_9_pins),
1202 GROUP("sd5_grp", sd5_pins),
1203 GROUP("sd6_grp0", sd6_pins0),
1204 GROUP("sd6_grp1", sd6_pins1),
1205 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1206 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1207 GROUP("sp1_spi_grp", sp1_spi_pins),
1208 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1209 GROUP("uart0_grp", uart0_pins),
1210 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1211 GROUP("uart1_grp", uart1_pins),
1212 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1213 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1214 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1215 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1216 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1217 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1218 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1219 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1220 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1221 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1222 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1223 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1224 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1225 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1226 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1227 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1228 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1229 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1230 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1231 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1232 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1233 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1234 GROUP("uart4_basic_grp", uart4_basic_pins),
1235 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1236 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1237 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1238 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1239 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1240 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1241 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1242 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1243 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1244 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1245 GROUP("visbus_dout_grp", visbus_dout_pins),
1246 GROUP("vi_vip1_grp", vi_vip1_pins),
1247 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1248 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1249 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1250 };
1251
1252 /* How many groups that a function can use */
1253 static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1254 static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1255 static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1256 static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1257 static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1258 static const char * const jtag_uart_nand_gpio_grp[] = {
1259 "jtag_uart_nand_gpio_grp", };
1260 static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1261 static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1262 static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1263 static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1264 static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1265 static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1266 static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1267 static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1268 static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1269 static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1270 static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1271 static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1272 static const char * const audio_uart0_basic_grp[] = {
1273 "audio_uart0_basic_grp", };
1274 static const char * const audio_uart0_urfs_grp0[] = {
1275 "audio_uart0_urfs_grp0", };
1276 static const char * const audio_uart0_urfs_grp1[] = {
1277 "audio_uart0_urfs_grp1", };
1278 static const char * const audio_uart0_urfs_grp2[] = {
1279 "audio_uart0_urfs_grp2", };
1280 static const char * const audio_uart0_urfs_grp3[] = {
1281 "audio_uart0_urfs_grp3", };
1282 static const char * const audio_uart1_basic_grp[] = {
1283 "audio_uart1_basic_grp", };
1284 static const char * const audio_uart1_urfs_grp0[] = {
1285 "audio_uart1_urfs_grp0", };
1286 static const char * const audio_uart1_urfs_grp1[] = {
1287 "audio_uart1_urfs_grp1", };
1288 static const char * const audio_uart1_urfs_grp2[] = {
1289 "audio_uart1_urfs_grp2", };
1290 static const char * const audio_uart2_urfs_grp0[] = {
1291 "audio_uart2_urfs_grp0", };
1292 static const char * const audio_uart2_urfs_grp1[] = {
1293 "audio_uart2_urfs_grp1", };
1294 static const char * const audio_uart2_urfs_grp2[] = {
1295 "audio_uart2_urfs_grp2", };
1296 static const char * const audio_uart2_urxd_grp0[] = {
1297 "audio_uart2_urxd_grp0", };
1298 static const char * const audio_uart2_urxd_grp1[] = {
1299 "audio_uart2_urxd_grp1", };
1300 static const char * const audio_uart2_urxd_grp2[] = {
1301 "audio_uart2_urxd_grp2", };
1302 static const char * const audio_uart2_usclk_grp0[] = {
1303 "audio_uart2_usclk_grp0", };
1304 static const char * const audio_uart2_usclk_grp1[] = {
1305 "audio_uart2_usclk_grp1", };
1306 static const char * const audio_uart2_usclk_grp2[] = {
1307 "audio_uart2_usclk_grp2", };
1308 static const char * const audio_uart2_utfs_grp0[] = {
1309 "audio_uart2_utfs_grp0", };
1310 static const char * const audio_uart2_utfs_grp1[] = {
1311 "audio_uart2_utfs_grp1", };
1312 static const char * const audio_uart2_utfs_grp2[] = {
1313 "audio_uart2_utfs_grp2", };
1314 static const char * const audio_uart2_utxd_grp0[] = {
1315 "audio_uart2_utxd_grp0", };
1316 static const char * const audio_uart2_utxd_grp1[] = {
1317 "audio_uart2_utxd_grp1", };
1318 static const char * const audio_uart2_utxd_grp2[] = {
1319 "audio_uart2_utxd_grp2", };
1320 static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1321 static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1322 static const char * const c_can_trnsvr_intr_grp[] = {
1323 "c_can_trnsvr_intr_grp", };
1324 static const char * const c_can_trnsvr_stb_n_grp[] = {
1325 "c_can_trnsvr_stb_n_grp", };
1326 static const char * const c0_can_rxd_trnsv0_grp[] = {
1327 "c0_can_rxd_trnsv0_grp", };
1328 static const char * const c0_can_rxd_trnsv1_grp[] = {
1329 "c0_can_rxd_trnsv1_grp", };
1330 static const char * const c0_can_txd_trnsv0_grp[] = {
1331 "c0_can_txd_trnsv0_grp", };
1332 static const char * const c0_can_txd_trnsv1_grp[] = {
1333 "c0_can_txd_trnsv1_grp", };
1334 static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1335 static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1336 static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1337 static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1338 static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1339 static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1340 static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1341 static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1342 static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1343 static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1344 static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1345 static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1346 static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1347 static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1348 static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1349 static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1350 static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1351 static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1352 static const char * const clkc_grp0[] = { "clkc_grp0", };
1353 static const char * const clkc_grp1[] = { "clkc_grp1", };
1354 static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1355 static const char * const gn_gnss_uart_nopause_grp[] = {
1356 "gn_gnss_uart_nopause_grp", };
1357 static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1358 static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1359 static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1360 static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1361 static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1362 static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1363 static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1364 static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1365 static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1366 static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1367 static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1368 static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1369 static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1370 static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1371 static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1372 static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1373 static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1374 static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1375 static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1376 static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1377 static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1378 static const char * const gn_gnss_sw_status_grp[] = {
1379 "gn_gnss_sw_status_grp", };
1380 static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1381 static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1382 static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1383 static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1384 static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1385 static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1386 "gn_io_gnsssys_sw_cfg_grp", };
1387 static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1388 static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1389 static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1390 static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1391 static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1392 static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1393 static const char * const i2c0_grp[] = { "i2c0_grp", };
1394 static const char * const i2c1_grp[] = { "i2c1_grp", };
1395 static const char * const i2s0_grp[] = { "i2s0_grp", };
1396 static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1397 static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1398 static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1399 static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1400 static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1401 static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1402 static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1403 static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1404 static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1405 static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1406 static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1407 static const char * const jtag_jt_dbg_nsrst_grp[] = {
1408 "jtag_jt_dbg_nsrst_grp", };
1409 static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1410 static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1411 static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1412 static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1413 static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1414 static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1415 static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1416 static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1417 static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1418 static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1419 static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1420 static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1421 static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1422 static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1423 static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1424 static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1425 static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1426 static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
1427 static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
1428 static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
1429 static const char * const ps_grp[] = { "ps_grp", };
1430 static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
1431 static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1432 static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1433 static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1434 static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1435 static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1436 static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1437 static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1438 static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1439 static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1440 static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1441 static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1442 static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1443 static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1444 static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1445 static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1446 static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1447 static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1448 static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1449 static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1450 static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1451 static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1452 static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1453 static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1454 static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1455 static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1456 static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1457 static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1458 static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1459 static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1460 static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1461 static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1462 static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1463 static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1464 static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1465 static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1466 static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1467 static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1468 static const char * const rg_gmac_phy_intr_n_grp[] = {
1469 "rg_gmac_phy_intr_n_grp", };
1470 static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1471 static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1472 "rg_rgmii_phy_ref_clk_grp0", };
1473 static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1474 "rg_rgmii_phy_ref_clk_grp1", };
1475 static const char * const sd0_grp[] = { "sd0_grp", };
1476 static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1477 static const char * const sd1_grp[] = { "sd1_grp", };
1478 static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1479 static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1480 static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1481 static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1482 static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1483 static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1484 static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1485 static const char * const sd3_9_grp[] = { "sd3_9_grp", };
1486 static const char * const sd5_grp[] = { "sd5_grp", };
1487 static const char * const sd6_grp0[] = { "sd6_grp0", };
1488 static const char * const sd6_grp1[] = { "sd6_grp1", };
1489 static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1490 static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1491 static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1492 static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1493 static const char * const uart0_grp[] = { "uart0_grp", };
1494 static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1495 static const char * const uart1_grp[] = { "uart1_grp", };
1496 static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1497 static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1498 static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1499 static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1500 static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1501 static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1502 static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1503 static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1504 static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1505 static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1506 static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1507 static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1508 static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1509 static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1510 static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1511 static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1512 static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1513 static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1514 static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1515 static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1516 static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1517 static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1518 static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1519 static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1520 static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1521 static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1522 static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1523 static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1524 static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1525 static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1526 static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1527 static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1528 static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1529 static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1530 static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1531 static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1532 static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1533 static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1534
1535 static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1536 MUX(1, 119, 0, N, N, N, N),
1537 MUX(1, 120, 0, N, N, N, N),
1538 MUX(1, 121, 0, N, N, N, N),
1539 MUX(1, 122, 0, N, N, N, N),
1540 MUX(1, 123, 0, N, N, N, N),
1541 MUX(1, 124, 0, N, N, N, N),
1542 MUX(1, 125, 0, N, N, N, N),
1543 MUX(1, 126, 0, N, N, N, N),
1544 MUX(1, 127, 0, N, N, N, N),
1545 MUX(1, 128, 0, N, N, N, N),
1546 MUX(1, 22, 0, N, N, N, N),
1547 MUX(1, 23, 0, N, N, N, N),
1548 MUX(1, 24, 0, N, N, N, N),
1549 MUX(1, 25, 0, N, N, N, N),
1550 MUX(1, 26, 0, N, N, N, N),
1551 MUX(1, 27, 0, N, N, N, N),
1552 MUX(1, 28, 0, N, N, N, N),
1553 MUX(1, 29, 0, N, N, N, N),
1554 MUX(1, 30, 0, N, N, N, N),
1555 };
1556
1557 static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1558 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1559 .pad_mux_list = gnss_gpio_grp_pad_mux,
1560 };
1561
1562 static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1563 MUX(1, 74, 0, N, N, N, N),
1564 MUX(1, 75, 0, N, N, N, N),
1565 MUX(1, 76, 0, N, N, N, N),
1566 MUX(1, 77, 0, N, N, N, N),
1567 MUX(1, 78, 0, N, N, N, N),
1568 MUX(1, 79, 0, N, N, N, N),
1569 MUX(1, 80, 0, N, N, N, N),
1570 MUX(1, 81, 0, N, N, N, N),
1571 MUX(1, 82, 0, N, N, N, N),
1572 MUX(1, 83, 0, N, N, N, N),
1573 MUX(1, 84, 0, N, N, N, N),
1574 MUX(1, 53, 0, N, N, N, N),
1575 MUX(1, 54, 0, N, N, N, N),
1576 MUX(1, 55, 0, N, N, N, N),
1577 MUX(1, 56, 0, N, N, N, N),
1578 MUX(1, 57, 0, N, N, N, N),
1579 MUX(1, 58, 0, N, N, N, N),
1580 MUX(1, 59, 0, N, N, N, N),
1581 MUX(1, 60, 0, N, N, N, N),
1582 MUX(1, 61, 0, N, N, N, N),
1583 MUX(1, 62, 0, N, N, N, N),
1584 MUX(1, 63, 0, N, N, N, N),
1585 MUX(1, 64, 0, N, N, N, N),
1586 MUX(1, 65, 0, N, N, N, N),
1587 MUX(1, 66, 0, N, N, N, N),
1588 MUX(1, 67, 0, N, N, N, N),
1589 MUX(1, 68, 0, N, N, N, N),
1590 MUX(1, 69, 0, N, N, N, N),
1591 MUX(1, 70, 0, N, N, N, N),
1592 MUX(1, 71, 0, N, N, N, N),
1593 MUX(1, 72, 0, N, N, N, N),
1594 MUX(1, 73, 0, N, N, N, N),
1595 };
1596
1597 static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1598 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1599 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1600 };
1601
1602 static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1603 MUX(1, 31, 0, N, N, N, N),
1604 MUX(1, 32, 0, N, N, N, N),
1605 MUX(1, 33, 0, N, N, N, N),
1606 MUX(1, 34, 0, N, N, N, N),
1607 MUX(1, 35, 0, N, N, N, N),
1608 MUX(1, 36, 0, N, N, N, N),
1609 MUX(1, 85, 0, N, N, N, N),
1610 MUX(1, 86, 0, N, N, N, N),
1611 MUX(1, 87, 0, N, N, N, N),
1612 MUX(1, 88, 0, N, N, N, N),
1613 MUX(1, 89, 0, N, N, N, N),
1614 MUX(1, 90, 0, N, N, N, N),
1615 MUX(1, 129, 0, N, N, N, N),
1616 MUX(1, 130, 0, N, N, N, N),
1617 MUX(1, 131, 0, N, N, N, N),
1618 MUX(1, 132, 0, N, N, N, N),
1619 MUX(1, 91, 0, N, N, N, N),
1620 MUX(1, 92, 0, N, N, N, N),
1621 MUX(1, 93, 0, N, N, N, N),
1622 MUX(1, 94, 0, N, N, N, N),
1623 MUX(1, 95, 0, N, N, N, N),
1624 MUX(1, 96, 0, N, N, N, N),
1625 MUX(1, 112, 0, N, N, N, N),
1626 MUX(1, 113, 0, N, N, N, N),
1627 MUX(1, 114, 0, N, N, N, N),
1628 MUX(1, 115, 0, N, N, N, N),
1629 MUX(1, 116, 0, N, N, N, N),
1630 MUX(1, 117, 0, N, N, N, N),
1631 MUX(1, 118, 0, N, N, N, N),
1632 };
1633
1634 static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1635 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1636 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1637 };
1638
1639 static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1640 MUX(1, 97, 0, N, N, N, N),
1641 MUX(1, 98, 0, N, N, N, N),
1642 MUX(1, 99, 0, N, N, N, N),
1643 MUX(1, 100, 0, N, N, N, N),
1644 MUX(1, 101, 0, N, N, N, N),
1645 MUX(1, 102, 0, N, N, N, N),
1646 MUX(1, 103, 0, N, N, N, N),
1647 MUX(1, 104, 0, N, N, N, N),
1648 MUX(1, 105, 0, N, N, N, N),
1649 MUX(1, 106, 0, N, N, N, N),
1650 MUX(1, 107, 0, N, N, N, N),
1651 MUX(1, 108, 0, N, N, N, N),
1652 MUX(1, 109, 0, N, N, N, N),
1653 MUX(1, 110, 0, N, N, N, N),
1654 MUX(1, 111, 0, N, N, N, N),
1655 MUX(1, 18, 0, N, N, N, N),
1656 MUX(1, 19, 0, N, N, N, N),
1657 MUX(1, 20, 0, N, N, N, N),
1658 MUX(1, 21, 0, N, N, N, N),
1659 MUX(1, 141, 0, N, N, N, N),
1660 MUX(1, 142, 0, N, N, N, N),
1661 MUX(1, 143, 0, N, N, N, N),
1662 MUX(1, 144, 0, N, N, N, N),
1663 MUX(1, 145, 0, N, N, N, N),
1664 MUX(1, 146, 0, N, N, N, N),
1665 MUX(1, 147, 0, N, N, N, N),
1666 MUX(1, 148, 0, N, N, N, N),
1667 };
1668
1669 static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1670 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1671 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1672 };
1673
1674 static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1675 MUX(1, 157, 0, N, N, N, N),
1676 MUX(1, 158, 0, N, N, N, N),
1677 MUX(1, 155, 0, N, N, N, N),
1678 MUX(1, 156, 0, N, N, N, N),
1679 MUX(1, 153, 0, N, N, N, N),
1680 MUX(1, 154, 0, N, N, N, N),
1681 MUX(1, 151, 0, N, N, N, N),
1682 MUX(1, 152, 0, N, N, N, N),
1683 MUX(1, 149, 0, N, N, N, N),
1684 MUX(1, 150, 0, N, N, N, N),
1685 };
1686
1687 static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1688 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1689 .pad_mux_list = lvds_gpio_grp_pad_mux,
1690 };
1691
1692 static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1693 MUX(1, 44, 0, N, N, N, N),
1694 MUX(1, 43, 0, N, N, N, N),
1695 MUX(1, 42, 0, N, N, N, N),
1696 MUX(1, 41, 0, N, N, N, N),
1697 MUX(1, 40, 0, N, N, N, N),
1698 MUX(1, 39, 0, N, N, N, N),
1699 MUX(1, 38, 0, N, N, N, N),
1700 MUX(1, 37, 0, N, N, N, N),
1701 MUX(1, 46, 0, N, N, N, N),
1702 MUX(1, 47, 0, N, N, N, N),
1703 MUX(1, 48, 0, N, N, N, N),
1704 MUX(1, 49, 0, N, N, N, N),
1705 MUX(1, 50, 0, N, N, N, N),
1706 MUX(1, 52, 0, N, N, N, N),
1707 MUX(1, 51, 0, N, N, N, N),
1708 MUX(1, 45, 0, N, N, N, N),
1709 MUX(1, 133, 0, N, N, N, N),
1710 MUX(1, 134, 0, N, N, N, N),
1711 MUX(1, 135, 0, N, N, N, N),
1712 MUX(1, 136, 0, N, N, N, N),
1713 MUX(1, 137, 0, N, N, N, N),
1714 MUX(1, 138, 0, N, N, N, N),
1715 MUX(1, 139, 0, N, N, N, N),
1716 MUX(1, 140, 0, N, N, N, N),
1717 MUX(1, 159, 0, N, N, N, N),
1718 MUX(1, 160, 0, N, N, N, N),
1719 MUX(1, 161, 0, N, N, N, N),
1720 MUX(1, 162, 0, N, N, N, N),
1721 MUX(1, 163, 0, N, N, N, N),
1722 };
1723
1724 static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1725 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1726 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1727 };
1728
1729 static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1730 MUX(0, 0, 0, N, N, N, N),
1731 MUX(0, 1, 0, N, N, N, N),
1732 MUX(0, 2, 0, N, N, N, N),
1733 MUX(0, 3, 0, N, N, N, N),
1734 MUX(0, 4, 0, N, N, N, N),
1735 MUX(0, 10, 0, N, N, N, N),
1736 MUX(0, 11, 0, N, N, N, N),
1737 MUX(0, 12, 0, N, N, N, N),
1738 MUX(0, 13, 0, N, N, N, N),
1739 MUX(0, 14, 0, N, N, N, N),
1740 MUX(0, 15, 0, N, N, N, N),
1741 MUX(0, 16, 0, N, N, N, N),
1742 MUX(0, 17, 0, N, N, N, N),
1743 MUX(0, 9, 0, N, N, N, N),
1744 };
1745
1746 static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1747 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1748 .pad_mux_list = rtc_gpio_grp_pad_mux,
1749 };
1750
1751 static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1752 MUX(1, 113, 2, N, N, N, N),
1753 MUX(1, 118, 2, N, N, N, N),
1754 MUX(1, 115, 2, N, N, N, N),
1755 MUX(1, 114, 2, N, N, N, N),
1756 };
1757
1758 static struct atlas7_grp_mux audio_ac97_grp_mux = {
1759 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1760 .pad_mux_list = audio_ac97_grp_pad_mux,
1761 };
1762
1763 static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1764 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1765 };
1766
1767 static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1768 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1769 .pad_mux_list = audio_digmic_grp0_pad_mux,
1770 };
1771
1772 static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1773 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1774 };
1775
1776 static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1777 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1778 .pad_mux_list = audio_digmic_grp1_pad_mux,
1779 };
1780
1781 static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1782 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1783 };
1784
1785 static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1786 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1787 .pad_mux_list = audio_digmic_grp2_pad_mux,
1788 };
1789
1790 static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1791 MUX(1, 141, 4, N, N, N, N),
1792 MUX(1, 144, 4, N, N, N, N),
1793 MUX(1, 44, 6, N, N, N, N),
1794 MUX(1, 43, 6, N, N, N, N),
1795 MUX(1, 42, 6, N, N, N, N),
1796 MUX(1, 41, 6, N, N, N, N),
1797 MUX(1, 40, 6, N, N, N, N),
1798 MUX(1, 39, 6, N, N, N, N),
1799 MUX(1, 38, 6, N, N, N, N),
1800 MUX(1, 37, 6, N, N, N, N),
1801 MUX(1, 74, 6, N, N, N, N),
1802 MUX(1, 75, 6, N, N, N, N),
1803 MUX(1, 76, 6, N, N, N, N),
1804 MUX(1, 77, 6, N, N, N, N),
1805 MUX(1, 78, 6, N, N, N, N),
1806 MUX(1, 79, 6, N, N, N, N),
1807 MUX(1, 81, 6, N, N, N, N),
1808 MUX(1, 113, 6, N, N, N, N),
1809 MUX(1, 114, 6, N, N, N, N),
1810 MUX(1, 118, 6, N, N, N, N),
1811 MUX(1, 115, 6, N, N, N, N),
1812 MUX(1, 49, 6, N, N, N, N),
1813 MUX(1, 50, 6, N, N, N, N),
1814 MUX(1, 142, 4, N, N, N, N),
1815 MUX(1, 143, 4, N, N, N, N),
1816 MUX(1, 80, 6, N, N, N, N),
1817 };
1818
1819 static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1820 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1821 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1822 };
1823
1824 static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1825 MUX(1, 118, 1, N, N, N, N),
1826 MUX(1, 115, 1, N, N, N, N),
1827 MUX(1, 116, 1, N, N, N, N),
1828 MUX(1, 117, 1, N, N, N, N),
1829 MUX(1, 112, 1, N, N, N, N),
1830 MUX(1, 113, 1, N, N, N, N),
1831 MUX(1, 114, 1, N, N, N, N),
1832 };
1833
1834 static struct atlas7_grp_mux audio_i2s_grp_mux = {
1835 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1836 .pad_mux_list = audio_i2s_grp_pad_mux,
1837 };
1838
1839 static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1840 MUX(1, 118, 1, N, N, N, N),
1841 MUX(1, 115, 1, N, N, N, N),
1842 MUX(1, 112, 1, N, N, N, N),
1843 MUX(1, 113, 1, N, N, N, N),
1844 MUX(1, 114, 1, N, N, N, N),
1845 };
1846
1847 static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1848 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1849 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1850 };
1851
1852 static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1853 MUX(1, 112, 2, N, N, N, N),
1854 };
1855
1856 static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1857 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1858 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1859 };
1860
1861 static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1862 MUX(1, 112, 3, N, N, N, N),
1863 };
1864
1865 static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1866 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1867 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1868 };
1869
1870 static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1871 MUX(1, 116, 3, N, N, N, N),
1872 };
1873
1874 static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1875 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1876 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1877 };
1878
1879 static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1880 MUX(1, 142, 3, N, N, N, N),
1881 };
1882
1883 static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1884 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1885 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1886 };
1887
1888 static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1889 MUX(1, 143, 1, N, N, N, N),
1890 MUX(1, 142, 1, N, N, N, N),
1891 MUX(1, 141, 1, N, N, N, N),
1892 MUX(1, 144, 1, N, N, N, N),
1893 };
1894
1895 static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1896 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1897 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1898 };
1899
1900 static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1901 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1902 };
1903
1904 static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1905 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1906 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1907 };
1908
1909 static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1910 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1911 };
1912
1913 static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1914 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1915 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1916 };
1917
1918 static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1919 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1920 };
1921
1922 static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1923 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1924 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1925 };
1926
1927 static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1928 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1929 };
1930
1931 static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1932 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1933 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1934 };
1935
1936 static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1937 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1938 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1939 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1940 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1941 };
1942
1943 static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1944 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1945 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1946 };
1947
1948 static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1949 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1950 };
1951
1952 static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1953 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1954 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1955 };
1956
1957 static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1958 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1959 };
1960
1961 static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1962 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1963 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1964 };
1965
1966 static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1967 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1968 };
1969
1970 static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1971 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1972 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1973 };
1974
1975 static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1976 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1977 };
1978
1979 static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1980 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1981 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1982 };
1983
1984 static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1985 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1986 };
1987
1988 static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1989 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1990 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1991 };
1992
1993 static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1994 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1995 };
1996
1997 static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1998 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1999 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
2000 };
2001
2002 static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
2003 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
2004 };
2005
2006 static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2007 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2008 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2009 };
2010
2011 static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2012 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2013 };
2014
2015 static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2016 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2017 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2018 };
2019
2020 static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2021 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2022 };
2023
2024 static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2025 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2026 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2027 };
2028
2029 static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2030 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2031 };
2032
2033 static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2034 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2035 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2036 };
2037
2038 static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2039 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2040 };
2041
2042 static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2043 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2044 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2045 };
2046
2047 static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2048 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2049 };
2050
2051 static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2052 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2053 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2054 };
2055
2056 static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2057 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2058 };
2059
2060 static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2061 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2062 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2063 };
2064
2065 static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2066 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2067 };
2068
2069 static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2070 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2071 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2072 };
2073
2074 static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2075 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2076 };
2077
2078 static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2079 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2080 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2081 };
2082
2083 static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2084 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2085 };
2086
2087 static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2088 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2089 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2090 };
2091
2092 static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2093 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2094 };
2095
2096 static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2097 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2098 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2099 };
2100
2101 static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2102 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2103 };
2104
2105 static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2106 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2107 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2108 };
2109
2110 static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2111 MUX(0, 2, 6, N, N, N, N),
2112 };
2113
2114 static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2115 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2116 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2117 };
2118
2119 static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2120 MUX(0, 0, 2, N, N, N, N),
2121 };
2122
2123 static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2124 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2125 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2126 };
2127
2128 static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2129 MUX(0, 1, 2, N, N, N, N),
2130 };
2131
2132 static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2133 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2134 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2135 };
2136
2137 static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2138 MUX(0, 3, 6, N, N, N, N),
2139 };
2140
2141 static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2142 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2143 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2144 };
2145
2146 static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2147 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2148 };
2149
2150 static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2151 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2152 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2153 };
2154
2155 static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2156 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2157 };
2158
2159 static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2160 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2161 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2162 };
2163
2164 static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2165 MUX(0, 10, 1, N, N, N, N),
2166 };
2167
2168 static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2169 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2170 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2171 };
2172
2173 static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2174 MUX(0, 3, 5, N, N, N, N),
2175 };
2176
2177 static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2178 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2179 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2180 };
2181
2182 static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2183 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2184 };
2185
2186 static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2187 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2188 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2189 };
2190
2191 static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2192 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2193 };
2194
2195 static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2196 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2197 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2198 };
2199
2200 static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2201 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2202 };
2203
2204 static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2205 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2206 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2207 };
2208
2209 static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2210 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2211 };
2212
2213 static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2214 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2215 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2216 };
2217
2218 static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2219 MUX(1, 137, 2, N, N, N, N),
2220 };
2221
2222 static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2223 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2224 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2225 };
2226
2227 static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2228 MUX(1, 146, 2, N, N, N, N),
2229 };
2230
2231 static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2232 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2233 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2234 };
2235
2236 static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2237 MUX(0, 3, 2, N, N, N, N),
2238 };
2239
2240 static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2241 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2242 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2243 };
2244
2245 static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2246 MUX(1, 161, 4, N, N, N, N),
2247 };
2248
2249 static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2250 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2251 .pad_mux_list = c1_can_txd_grp3_pad_mux,
2252 };
2253
2254 static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2255 MUX(1, 62, 4, N, N, N, N),
2256 MUX(1, 63, 4, N, N, N, N),
2257 MUX(1, 64, 4, N, N, N, N),
2258 MUX(1, 65, 4, N, N, N, N),
2259 MUX(1, 66, 4, N, N, N, N),
2260 MUX(1, 67, 4, N, N, N, N),
2261 MUX(1, 68, 4, N, N, N, N),
2262 MUX(1, 69, 4, N, N, N, N),
2263 MUX(1, 70, 4, N, N, N, N),
2264 MUX(1, 71, 4, N, N, N, N),
2265 };
2266
2267 static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2268 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2269 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2270 };
2271
2272 static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2273 MUX(1, 85, 5, N, N, N, N),
2274 MUX(1, 86, 5, N, N, N, N),
2275 MUX(1, 87, 5, N, N, N, N),
2276 MUX(1, 88, 5, N, N, N, N),
2277 MUX(1, 89, 5, N, N, N, N),
2278 MUX(1, 90, 5, N, N, N, N),
2279 };
2280
2281 static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2282 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2283 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2284 };
2285
2286 static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2287 MUX(1, 129, 1, N, N, N, N),
2288 MUX(1, 130, 1, N, N, N, N),
2289 MUX(1, 131, 1, N, N, N, N),
2290 MUX(1, 132, 1, N, N, N, N),
2291 };
2292
2293 static struct atlas7_grp_mux ca_coex_grp_mux = {
2294 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2295 .pad_mux_list = ca_coex_grp_pad_mux,
2296 };
2297
2298 static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2299 MUX(1, 57, 4, N, N, N, N),
2300 MUX(1, 58, 4, N, N, N, N),
2301 MUX(1, 59, 4, N, N, N, N),
2302 MUX(1, 60, 4, N, N, N, N),
2303 };
2304
2305 static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2306 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2307 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2308 };
2309
2310 static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2311 MUX(1, 91, 5, N, N, N, N),
2312 MUX(1, 93, 5, N, N, N, N),
2313 MUX(1, 94, 5, N, N, N, N),
2314 MUX(1, 92, 5, N, N, N, N),
2315 };
2316
2317 static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2318 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2319 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2320 };
2321
2322 static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2323 MUX(1, 121, 2, N, N, N, N),
2324 MUX(1, 122, 2, N, N, N, N),
2325 MUX(1, 125, 6, N, N, N, N),
2326 MUX(1, 126, 6, N, N, N, N),
2327 MUX(1, 38, 5, N, N, N, N),
2328 MUX(1, 37, 5, N, N, N, N),
2329 MUX(1, 47, 5, N, N, N, N),
2330 MUX(1, 49, 5, N, N, N, N),
2331 MUX(1, 50, 5, N, N, N, N),
2332 MUX(1, 54, 4, N, N, N, N),
2333 MUX(1, 55, 4, N, N, N, N),
2334 MUX(1, 56, 4, N, N, N, N),
2335 };
2336
2337 static struct atlas7_grp_mux ca_pio_grp_mux = {
2338 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2339 .pad_mux_list = ca_pio_grp_pad_mux,
2340 };
2341
2342 static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2343 MUX(1, 40, 5, N, N, N, N),
2344 MUX(1, 39, 5, N, N, N, N),
2345 MUX(1, 44, 5, N, N, N, N),
2346 MUX(1, 43, 5, N, N, N, N),
2347 MUX(1, 42, 5, N, N, N, N),
2348 MUX(1, 41, 5, N, N, N, N),
2349 };
2350
2351 static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2352 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2353 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2354 };
2355
2356 static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2357 MUX(1, 82, 5, N, N, N, N),
2358 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2359 MUX(1, 80, 5, N, N, N, N),
2360 MUX(1, 81, 5, N, N, N, N),
2361 };
2362
2363 static struct atlas7_grp_mux ca_spi_grp_mux = {
2364 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2365 .pad_mux_list = ca_spi_grp_pad_mux,
2366 };
2367
2368 static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2369 MUX(1, 91, 4, N, N, N, N),
2370 MUX(1, 93, 4, N, N, N, N),
2371 MUX(1, 94, 4, N, N, N, N),
2372 MUX(1, 95, 4, N, N, N, N),
2373 MUX(1, 96, 4, N, N, N, N),
2374 MUX(1, 78, 5, N, N, N, N),
2375 MUX(1, 74, 5, N, N, N, N),
2376 MUX(1, 75, 5, N, N, N, N),
2377 MUX(1, 76, 5, N, N, N, N),
2378 MUX(1, 77, 5, N, N, N, N),
2379 };
2380
2381 static struct atlas7_grp_mux ca_trb_grp_mux = {
2382 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2383 .pad_mux_list = ca_trb_grp_pad_mux,
2384 };
2385
2386 static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2387 MUX(1, 136, 3, N, N, N, N),
2388 MUX(1, 135, 3, N, N, N, N),
2389 MUX(1, 134, 3, N, N, N, N),
2390 MUX(1, 133, 3, N, N, N, N),
2391 };
2392
2393 static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2394 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2395 .pad_mux_list = ca_uart_debug_grp_pad_mux,
2396 };
2397
2398 static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2399 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2400 MUX(1, 47, 6, N, N, N, N),
2401 };
2402
2403 static struct atlas7_grp_mux clkc_grp0_mux = {
2404 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2405 .pad_mux_list = clkc_grp0_pad_mux,
2406 };
2407
2408 static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2409 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2410 MUX(1, 54, 5, N, N, N, N),
2411 };
2412
2413 static struct atlas7_grp_mux clkc_grp1_mux = {
2414 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2415 .pad_mux_list = clkc_grp1_pad_mux,
2416 };
2417
2418 static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2419 MUX(1, 128, 2, N, N, N, N),
2420 MUX(1, 127, 2, N, N, N, N),
2421 };
2422
2423 static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2424 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2425 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2426 };
2427
2428 static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2429 MUX(1, 134, 4, N, N, N, N),
2430 MUX(1, 133, 4, N, N, N, N),
2431 };
2432
2433 static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2434 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2435 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2436 };
2437
2438 static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2439 MUX(1, 134, 4, N, N, N, N),
2440 MUX(1, 133, 4, N, N, N, N),
2441 MUX(1, 136, 4, N, N, N, N),
2442 MUX(1, 135, 4, N, N, N, N),
2443 };
2444
2445 static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2446 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2447 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2448 };
2449
2450 static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2451 MUX(1, 22, 1, N, N, N, N),
2452 MUX(1, 25, 1, N, N, N, N),
2453 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2454 MUX(1, 24, 1, N, N, N, N),
2455 };
2456
2457 static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2458 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2459 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2460 };
2461
2462 static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2463 MUX(1, 82, 3, N, N, N, N),
2464 MUX(1, 79, 3, N, N, N, N),
2465 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2466 MUX(1, 81, 3, N, N, N, N),
2467 };
2468
2469 static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2470 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2471 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2472 };
2473
2474 static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2475 MUX(1, 54, 3, N, N, N, N),
2476 MUX(1, 53, 3, N, N, N, N),
2477 MUX(1, 82, 7, N, N, N, N),
2478 MUX(1, 74, 7, N, N, N, N),
2479 MUX(1, 75, 7, N, N, N, N),
2480 MUX(1, 76, 7, N, N, N, N),
2481 MUX(1, 77, 7, N, N, N, N),
2482 MUX(1, 78, 7, N, N, N, N),
2483 MUX(1, 79, 7, N, N, N, N),
2484 MUX(1, 80, 7, N, N, N, N),
2485 MUX(1, 81, 7, N, N, N, N),
2486 MUX(1, 83, 7, N, N, N, N),
2487 MUX(1, 84, 7, N, N, N, N),
2488 MUX(1, 73, 3, N, N, N, N),
2489 MUX(1, 55, 3, N, N, N, N),
2490 MUX(1, 56, 3, N, N, N, N),
2491 };
2492
2493 static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2494 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2495 .pad_mux_list = cvbs_dbg_grp_pad_mux,
2496 };
2497
2498 static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2499 MUX(1, 57, 3, N, N, N, N),
2500 };
2501
2502 static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2503 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2504 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2505 };
2506
2507 static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2508 MUX(1, 58, 3, N, N, N, N),
2509 };
2510
2511 static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2512 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2513 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2514 };
2515
2516 static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2517 MUX(1, 59, 3, N, N, N, N),
2518 };
2519
2520 static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2521 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2522 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2523 };
2524
2525 static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2526 MUX(1, 60, 3, N, N, N, N),
2527 };
2528
2529 static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2530 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2531 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2532 };
2533
2534 static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2535 MUX(1, 61, 3, N, N, N, N),
2536 };
2537
2538 static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2539 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2540 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2541 };
2542
2543 static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2544 MUX(1, 62, 3, N, N, N, N),
2545 };
2546
2547 static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2548 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2549 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2550 };
2551
2552 static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2553 MUX(1, 63, 3, N, N, N, N),
2554 };
2555
2556 static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2557 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2558 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2559 };
2560
2561 static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2562 MUX(1, 64, 3, N, N, N, N),
2563 };
2564
2565 static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2566 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2567 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2568 };
2569
2570 static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2571 MUX(1, 65, 3, N, N, N, N),
2572 };
2573
2574 static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2575 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2576 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2577 };
2578
2579 static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2580 MUX(1, 66, 3, N, N, N, N),
2581 };
2582
2583 static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2584 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2585 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2586 };
2587
2588 static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2589 MUX(1, 67, 3, N, N, N, N),
2590 };
2591
2592 static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2593 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2594 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2595 };
2596
2597 static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2598 MUX(1, 68, 3, N, N, N, N),
2599 };
2600
2601 static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2602 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2603 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2604 };
2605
2606 static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2607 MUX(1, 69, 3, N, N, N, N),
2608 };
2609
2610 static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2611 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2612 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2613 };
2614
2615 static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2616 MUX(1, 70, 3, N, N, N, N),
2617 };
2618
2619 static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2620 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2621 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2622 };
2623
2624 static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2625 MUX(1, 71, 3, N, N, N, N),
2626 };
2627
2628 static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2629 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2630 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2631 };
2632
2633 static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2634 MUX(1, 72, 3, N, N, N, N),
2635 };
2636
2637 static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2638 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2639 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2640 };
2641
2642 static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2643 MUX(1, 123, 7, N, N, N, N),
2644 MUX(1, 124, 7, N, N, N, N),
2645 MUX(1, 121, 7, N, N, N, N),
2646 MUX(1, 122, 7, N, N, N, N),
2647 MUX(1, 125, 7, N, N, N, N),
2648 MUX(1, 120, 7, N, N, N, N),
2649 };
2650
2651 static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2652 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2653 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2654 };
2655
2656 static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2657 MUX(1, 57, 7, N, N, N, N),
2658 MUX(1, 58, 7, N, N, N, N),
2659 MUX(1, 59, 7, N, N, N, N),
2660 MUX(1, 60, 7, N, N, N, N),
2661 MUX(1, 61, 7, N, N, N, N),
2662 MUX(1, 62, 7, N, N, N, N),
2663 MUX(1, 63, 7, N, N, N, N),
2664 MUX(1, 64, 7, N, N, N, N),
2665 MUX(1, 65, 7, N, N, N, N),
2666 MUX(1, 66, 7, N, N, N, N),
2667 MUX(1, 67, 7, N, N, N, N),
2668 MUX(1, 68, 7, N, N, N, N),
2669 MUX(1, 69, 7, N, N, N, N),
2670 MUX(1, 70, 7, N, N, N, N),
2671 MUX(1, 71, 7, N, N, N, N),
2672 MUX(1, 72, 7, N, N, N, N),
2673 MUX(1, 53, 7, N, N, N, N),
2674 MUX(1, 55, 7, N, N, N, N),
2675 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2676 MUX(1, 54, 7, N, N, N, N),
2677 };
2678
2679 static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2680 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2681 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2682 };
2683
2684 static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2685 MUX(1, 113, 4, N, N, N, N),
2686 };
2687
2688 static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2689 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2690 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2691 };
2692
2693 static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2694 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2695 };
2696
2697 static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2698 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2699 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2700 };
2701
2702 static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2703 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2704 };
2705
2706 static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2707 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2708 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2709 };
2710
2711 static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2712 MUX(1, 115, 4, N, N, N, N),
2713 };
2714
2715 static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2716 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2717 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2718 };
2719
2720 static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2721 MUX(1, 114, 4, N, N, N, N),
2722 };
2723
2724 static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2725 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2726 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2727 };
2728
2729 static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2730 MUX(1, 44, 7, N, N, N, N),
2731 MUX(1, 43, 7, N, N, N, N),
2732 MUX(1, 42, 7, N, N, N, N),
2733 MUX(1, 41, 7, N, N, N, N),
2734 MUX(1, 40, 7, N, N, N, N),
2735 MUX(1, 39, 7, N, N, N, N),
2736 MUX(1, 38, 7, N, N, N, N),
2737 MUX(1, 37, 7, N, N, N, N),
2738 MUX(1, 49, 7, N, N, N, N),
2739 MUX(1, 50, 7, N, N, N, N),
2740 MUX(1, 91, 7, N, N, N, N),
2741 MUX(1, 92, 7, N, N, N, N),
2742 MUX(1, 93, 7, N, N, N, N),
2743 MUX(1, 94, 7, N, N, N, N),
2744 MUX(1, 95, 7, N, N, N, N),
2745 MUX(1, 96, 7, N, N, N, N),
2746 };
2747
2748 static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2749 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2750 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2751 };
2752
2753 static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2754 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2755 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2756 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2757 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2758 };
2759
2760 static struct atlas7_grp_mux gn_trg_grp0_mux = {
2761 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2762 .pad_mux_list = gn_trg_grp0_pad_mux,
2763 };
2764
2765 static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2766 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2767 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2768 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2769 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2770 };
2771
2772 static struct atlas7_grp_mux gn_trg_grp1_mux = {
2773 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2774 .pad_mux_list = gn_trg_grp1_pad_mux,
2775 };
2776
2777 static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2778 MUX(1, 30, 1, N, N, N, N),
2779 };
2780
2781 static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2782 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2783 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2784 };
2785
2786 static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2787 MUX(1, 83, 3, N, N, N, N),
2788 };
2789
2790 static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2791 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2792 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2793 };
2794
2795 static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2796 MUX(1, 117, 4, N, N, N, N),
2797 };
2798
2799 static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2800 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2801 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2802 };
2803
2804 static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2805 MUX(1, 123, 5, N, N, N, N),
2806 };
2807
2808 static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2809 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2810 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2811 };
2812
2813 static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2814 MUX(1, 128, 1, N, N, N, N),
2815 MUX(1, 127, 1, N, N, N, N),
2816 };
2817
2818 static struct atlas7_grp_mux i2c0_grp_mux = {
2819 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2820 .pad_mux_list = i2c0_grp_pad_mux,
2821 };
2822
2823 static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2824 MUX(1, 126, 4, N, N, N, N),
2825 MUX(1, 125, 4, N, N, N, N),
2826 };
2827
2828 static struct atlas7_grp_mux i2c1_grp_mux = {
2829 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2830 .pad_mux_list = i2c1_grp_pad_mux,
2831 };
2832
2833 static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2834 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2835 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2836 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2837 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2838 };
2839
2840 static struct atlas7_grp_mux i2s0_grp_mux = {
2841 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2842 .pad_mux_list = i2s0_grp_pad_mux,
2843 };
2844
2845 static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2846 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2847 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2848 };
2849
2850 static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2851 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2852 .pad_mux_list = i2s1_basic_grp_pad_mux,
2853 };
2854
2855 static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2856 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2857 };
2858
2859 static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2860 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2861 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2862 };
2863
2864 static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2865 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2866 };
2867
2868 static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2869 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2870 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2871 };
2872
2873 static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2874 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2875 };
2876
2877 static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2878 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2879 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2880 };
2881
2882 static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2883 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2884 };
2885
2886 static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2887 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2888 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2889 };
2890
2891 static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2892 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2893 };
2894
2895 static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2896 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2897 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2898 };
2899
2900 static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2901 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2902 };
2903
2904 static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2905 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2906 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2907 };
2908
2909 static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2910 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2911 };
2912
2913 static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2914 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2915 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2916 };
2917
2918 static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2919 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2920 };
2921
2922 static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2923 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2924 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2925 };
2926
2927 static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2928 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2929 };
2930
2931 static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2932 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2933 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2934 };
2935
2936 static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2937 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2938 };
2939
2940 static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2941 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2942 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2943 };
2944
2945 static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2946 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2947 };
2948
2949 static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2950 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2951 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2952 };
2953
2954 static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2955 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2956 };
2957
2958 static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2959 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2960 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2961 };
2962
2963 static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2964 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2965 };
2966
2967 static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2968 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2969 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2970 };
2971
2972 static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2973 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2974 };
2975
2976 static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2977 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2978 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2979 };
2980
2981 static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2982 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2983 };
2984
2985 static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2986 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2987 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2988 };
2989
2990 static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2991 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2992 };
2993
2994 static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2995 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2996 .pad_mux_list = jtag_tck_grp0_pad_mux,
2997 };
2998
2999 static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
3000 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
3001 };
3002
3003 static struct atlas7_grp_mux jtag_tck_grp1_mux = {
3004 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
3005 .pad_mux_list = jtag_tck_grp1_pad_mux,
3006 };
3007
3008 static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3009 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3010 };
3011
3012 static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3013 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3014 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3015 };
3016
3017 static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3018 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3019 };
3020
3021 static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3022 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3023 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3024 };
3025
3026 static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3027 MUX(0, 3, 3, N, N, N, N),
3028 };
3029
3030 static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3031 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3032 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3033 };
3034
3035 static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3036 MUX(1, 159, 1, N, N, N, N),
3037 };
3038
3039 static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3040 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3041 .pad_mux_list = jtag_tdo_grp1_pad_mux,
3042 };
3043
3044 static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3045 MUX(1, 141, 2, N, N, N, N),
3046 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3047 MUX(1, 143, 2, N, N, N, N),
3048 MUX(1, 142, 2, N, N, N, N),
3049 };
3050
3051 static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3052 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3053 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3054 };
3055
3056 static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3057 MUX(1, 57, 1, N, N, N, N),
3058 MUX(1, 58, 1, N, N, N, N),
3059 MUX(1, 59, 1, N, N, N, N),
3060 MUX(1, 60, 1, N, N, N, N),
3061 MUX(1, 61, 1, N, N, N, N),
3062 MUX(1, 62, 1, N, N, N, N),
3063 MUX(1, 63, 1, N, N, N, N),
3064 MUX(1, 64, 1, N, N, N, N),
3065 MUX(1, 65, 1, N, N, N, N),
3066 MUX(1, 66, 1, N, N, N, N),
3067 MUX(1, 67, 1, N, N, N, N),
3068 MUX(1, 68, 1, N, N, N, N),
3069 MUX(1, 69, 1, N, N, N, N),
3070 MUX(1, 70, 1, N, N, N, N),
3071 MUX(1, 71, 1, N, N, N, N),
3072 MUX(1, 72, 1, N, N, N, N),
3073 MUX(1, 74, 2, N, N, N, N),
3074 MUX(1, 75, 2, N, N, N, N),
3075 MUX(1, 76, 2, N, N, N, N),
3076 MUX(1, 77, 2, N, N, N, N),
3077 MUX(1, 78, 2, N, N, N, N),
3078 MUX(1, 79, 2, N, N, N, N),
3079 MUX(1, 80, 2, N, N, N, N),
3080 MUX(1, 81, 2, N, N, N, N),
3081 MUX(1, 56, 1, N, N, N, N),
3082 MUX(1, 53, 1, N, N, N, N),
3083 };
3084
3085 static struct atlas7_grp_mux ld_ldd_grp_mux = {
3086 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3087 .pad_mux_list = ld_ldd_grp_pad_mux,
3088 };
3089
3090 static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3091 MUX(1, 57, 1, N, N, N, N),
3092 MUX(1, 58, 1, N, N, N, N),
3093 MUX(1, 59, 1, N, N, N, N),
3094 MUX(1, 60, 1, N, N, N, N),
3095 MUX(1, 61, 1, N, N, N, N),
3096 MUX(1, 62, 1, N, N, N, N),
3097 MUX(1, 63, 1, N, N, N, N),
3098 MUX(1, 64, 1, N, N, N, N),
3099 MUX(1, 65, 1, N, N, N, N),
3100 MUX(1, 66, 1, N, N, N, N),
3101 MUX(1, 67, 1, N, N, N, N),
3102 MUX(1, 68, 1, N, N, N, N),
3103 MUX(1, 69, 1, N, N, N, N),
3104 MUX(1, 70, 1, N, N, N, N),
3105 MUX(1, 71, 1, N, N, N, N),
3106 MUX(1, 72, 1, N, N, N, N),
3107 MUX(1, 56, 1, N, N, N, N),
3108 MUX(1, 53, 1, N, N, N, N),
3109 };
3110
3111 static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3112 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3113 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3114 };
3115
3116 static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3117 MUX(1, 55, 1, N, N, N, N),
3118 };
3119
3120 static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3121 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3122 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3123 };
3124
3125 static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3126 MUX(1, 54, 1, N, N, N, N),
3127 };
3128
3129 static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3130 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3131 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3132 };
3133
3134 static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3135 MUX(1, 73, 2, N, N, N, N),
3136 MUX(1, 54, 2, N, N, N, N),
3137 MUX(1, 57, 2, N, N, N, N),
3138 MUX(1, 58, 2, N, N, N, N),
3139 MUX(1, 59, 2, N, N, N, N),
3140 MUX(1, 60, 2, N, N, N, N),
3141 MUX(1, 61, 2, N, N, N, N),
3142 MUX(1, 62, 2, N, N, N, N),
3143 MUX(1, 63, 2, N, N, N, N),
3144 MUX(1, 64, 2, N, N, N, N),
3145 MUX(1, 65, 2, N, N, N, N),
3146 MUX(1, 66, 2, N, N, N, N),
3147 MUX(1, 67, 2, N, N, N, N),
3148 MUX(1, 68, 2, N, N, N, N),
3149 MUX(1, 69, 2, N, N, N, N),
3150 MUX(1, 70, 2, N, N, N, N),
3151 MUX(1, 71, 2, N, N, N, N),
3152 MUX(1, 72, 2, N, N, N, N),
3153 MUX(1, 56, 2, N, N, N, N),
3154 MUX(1, 53, 2, N, N, N, N),
3155 MUX(1, 55, 2, N, N, N, N),
3156 };
3157
3158 static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3159 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3160 .pad_mux_list = lr_lcdrom_grp_pad_mux,
3161 };
3162
3163 static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3164 MUX(1, 149, 8, N, N, N, N),
3165 MUX(1, 150, 8, N, N, N, N),
3166 MUX(1, 151, 8, N, N, N, N),
3167 MUX(1, 152, 8, N, N, N, N),
3168 MUX(1, 153, 8, N, N, N, N),
3169 MUX(1, 154, 8, N, N, N, N),
3170 MUX(1, 155, 8, N, N, N, N),
3171 MUX(1, 156, 8, N, N, N, N),
3172 MUX(1, 157, 8, N, N, N, N),
3173 MUX(1, 158, 8, N, N, N, N),
3174 };
3175
3176 static struct atlas7_grp_mux lvds_analog_grp_mux = {
3177 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3178 .pad_mux_list = lvds_analog_grp_pad_mux,
3179 };
3180
3181 static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
3182 MUX(1, 44, 1, N, N, N, N),
3183 MUX(1, 43, 1, N, N, N, N),
3184 MUX(1, 42, 1, N, N, N, N),
3185 MUX(1, 41, 1, N, N, N, N),
3186 MUX(1, 40, 1, N, N, N, N),
3187 MUX(1, 39, 1, N, N, N, N),
3188 MUX(1, 38, 1, N, N, N, N),
3189 MUX(1, 37, 1, N, N, N, N),
3190 MUX(1, 47, 1, N, N, N, N),
3191 MUX(1, 46, 1, N, N, N, N),
3192 MUX(1, 52, 1, N, N, N, N),
3193 MUX(1, 45, 1, N, N, N, N),
3194 MUX(1, 49, 1, N, N, N, N),
3195 MUX(1, 50, 1, N, N, N, N),
3196 MUX(1, 48, 1, N, N, N, N),
3197 };
3198
3199 static struct atlas7_grp_mux nd_df_basic_grp_mux = {
3200 .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
3201 .pad_mux_list = nd_df_basic_grp_pad_mux,
3202 };
3203
3204 static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
3205 MUX(1, 124, 4, N, N, N, N),
3206 };
3207
3208 static struct atlas7_grp_mux nd_df_wp_grp_mux = {
3209 .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
3210 .pad_mux_list = nd_df_wp_grp_pad_mux,
3211 };
3212
3213 static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
3214 MUX(1, 51, 1, N, N, N, N),
3215 };
3216
3217 static struct atlas7_grp_mux nd_df_cs_grp_mux = {
3218 .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
3219 .pad_mux_list = nd_df_cs_grp_pad_mux,
3220 };
3221
3222 static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3223 MUX(1, 120, 2, N, N, N, N),
3224 MUX(1, 119, 2, N, N, N, N),
3225 MUX(1, 121, 5, N, N, N, N),
3226 };
3227
3228 static struct atlas7_grp_mux ps_grp_mux = {
3229 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3230 .pad_mux_list = ps_grp_pad_mux,
3231 };
3232
3233 static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
3234 MUX(1, 119, 2, N, N, N, N),
3235 };
3236
3237 static struct atlas7_grp_mux ps_no_dir_grp_mux = {
3238 .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
3239 .pad_mux_list = ps_no_dir_grp_pad_mux,
3240 };
3241
3242 static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3243 MUX(0, 8, 1, N, N, N, N),
3244 };
3245
3246 static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3247 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3248 .pad_mux_list = pwc_core_on_grp_pad_mux,
3249 };
3250
3251 static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3252 MUX(0, 6, 1, N, N, N, N),
3253 };
3254
3255 static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3256 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3257 .pad_mux_list = pwc_ext_on_grp_pad_mux,
3258 };
3259
3260 static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3261 MUX(0, 3, 4, N, N, N, N),
3262 };
3263
3264 static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3265 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3266 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3267 };
3268
3269 static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3270 MUX(0, 9, 1, N, N, N, N),
3271 };
3272
3273 static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3274 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3275 .pad_mux_list = pwc_io_on_grp_pad_mux,
3276 };
3277
3278 static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3279 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3280 };
3281
3282 static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3283 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3284 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3285 };
3286
3287 static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3288 MUX(0, 7, 1, N, N, N, N),
3289 };
3290
3291 static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3292 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3293 .pad_mux_list = pwc_mem_on_grp_pad_mux,
3294 };
3295
3296 static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3297 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3298 };
3299
3300 static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3301 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3302 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3303 };
3304
3305 static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3306 MUX(0, 0, 1, N, N, N, N),
3307 };
3308
3309 static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3310 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3311 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3312 };
3313
3314 static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3315 MUX(0, 1, 1, N, N, N, N),
3316 };
3317
3318 static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3319 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3320 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3321 };
3322
3323 static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3324 MUX(0, 2, 1, N, N, N, N),
3325 };
3326
3327 static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3328 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3329 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3330 };
3331
3332 static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3333 MUX(0, 3, 1, N, N, N, N),
3334 };
3335
3336 static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3337 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3338 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3339 };
3340
3341 static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3342 MUX(1, 123, 3, N, N, N, N),
3343 };
3344
3345 static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3346 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3347 .pad_mux_list = pw_cko0_grp0_pad_mux,
3348 };
3349
3350 static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3351 MUX(1, 101, 4, N, N, N, N),
3352 };
3353
3354 static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3355 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3356 .pad_mux_list = pw_cko0_grp1_pad_mux,
3357 };
3358
3359 static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3360 MUX(1, 82, 2, N, N, N, N),
3361 };
3362
3363 static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3364 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3365 .pad_mux_list = pw_cko0_grp2_pad_mux,
3366 };
3367
3368 static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3369 MUX(1, 162, 5, N, N, N, N),
3370 };
3371
3372 static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3373 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3374 .pad_mux_list = pw_cko0_grp3_pad_mux,
3375 };
3376
3377 static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3378 MUX(1, 124, 3, N, N, N, N),
3379 };
3380
3381 static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3382 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3383 .pad_mux_list = pw_cko1_grp0_pad_mux,
3384 };
3385
3386 static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3387 MUX(1, 110, 4, N, N, N, N),
3388 };
3389
3390 static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3391 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3392 .pad_mux_list = pw_cko1_grp1_pad_mux,
3393 };
3394
3395 static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3396 MUX(1, 163, 5, N, N, N, N),
3397 };
3398
3399 static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3400 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3401 .pad_mux_list = pw_cko1_grp2_pad_mux,
3402 };
3403
3404 static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3405 MUX(1, 125, 3, N, N, N, N),
3406 };
3407
3408 static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3409 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3410 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3411 };
3412
3413 static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3414 MUX(1, 117, 3, N, N, N, N),
3415 };
3416
3417 static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3418 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3419 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3420 };
3421
3422 static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3423 MUX(1, 132, 2, N, N, N, N),
3424 };
3425
3426 static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3427 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3428 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3429 };
3430
3431 static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3432 MUX(1, 119, 3, N, N, N, N),
3433 };
3434
3435 static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3436 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3437 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3438 };
3439
3440 static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3441 MUX(1, 159, 5, N, N, N, N),
3442 };
3443
3444 static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3445 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3446 .pad_mux_list = pw_pwm0_grp1_pad_mux,
3447 };
3448
3449 static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3450 MUX(1, 120, 3, N, N, N, N),
3451 };
3452
3453 static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3454 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3455 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3456 };
3457
3458 static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3459 MUX(1, 160, 5, N, N, N, N),
3460 };
3461
3462 static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3463 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3464 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3465 };
3466
3467 static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3468 MUX(1, 131, 2, N, N, N, N),
3469 };
3470
3471 static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3472 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3473 .pad_mux_list = pw_pwm1_grp2_pad_mux,
3474 };
3475
3476 static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3477 MUX(1, 121, 3, N, N, N, N),
3478 };
3479
3480 static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3481 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3482 .pad_mux_list = pw_pwm2_grp0_pad_mux,
3483 };
3484
3485 static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3486 MUX(1, 98, 3, N, N, N, N),
3487 };
3488
3489 static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3490 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3491 .pad_mux_list = pw_pwm2_grp1_pad_mux,
3492 };
3493
3494 static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3495 MUX(1, 161, 5, N, N, N, N),
3496 };
3497
3498 static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3499 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3500 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3501 };
3502
3503 static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3504 MUX(1, 122, 3, N, N, N, N),
3505 };
3506
3507 static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3508 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3509 .pad_mux_list = pw_pwm3_grp0_pad_mux,
3510 };
3511
3512 static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3513 MUX(1, 73, 4, N, N, N, N),
3514 };
3515
3516 static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3517 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3518 .pad_mux_list = pw_pwm3_grp1_pad_mux,
3519 };
3520
3521 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3522 MUX(1, 121, 3, N, N, N, N),
3523 };
3524
3525 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3526 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3527 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3528 };
3529
3530 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3531 MUX(1, 98, 3, N, N, N, N),
3532 };
3533
3534 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3535 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3536 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3537 };
3538
3539 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3540 MUX(1, 161, 5, N, N, N, N),
3541 };
3542
3543 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3544 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3545 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3546 };
3547
3548 static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3549 MUX(1, 122, 3, N, N, N, N),
3550 };
3551
3552 static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3553 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3554 .pad_mux_list = pw_backlight_grp0_pad_mux,
3555 };
3556
3557 static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3558 MUX(1, 73, 4, N, N, N, N),
3559 };
3560
3561 static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3562 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3563 .pad_mux_list = pw_backlight_grp1_pad_mux,
3564 };
3565
3566 static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3567 MUX(1, 108, 1, N, N, N, N),
3568 MUX(1, 103, 1, N, N, N, N),
3569 MUX(1, 104, 1, N, N, N, N),
3570 MUX(1, 105, 1, N, N, N, N),
3571 MUX(1, 106, 1, N, N, N, N),
3572 MUX(1, 107, 1, N, N, N, N),
3573 MUX(1, 102, 1, N, N, N, N),
3574 MUX(1, 97, 1, N, N, N, N),
3575 MUX(1, 98, 1, N, N, N, N),
3576 MUX(1, 99, 1, N, N, N, N),
3577 MUX(1, 100, 1, N, N, N, N),
3578 MUX(1, 101, 1, N, N, N, N),
3579 };
3580
3581 static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3582 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3583 .pad_mux_list = rg_eth_mac_grp_pad_mux,
3584 };
3585
3586 static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3587 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3588 };
3589
3590 static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3591 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3592 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3593 };
3594
3595 static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3596 MUX(1, 109, 1, N, N, N, N),
3597 MUX(1, 110, 1, N, N, N, N),
3598 };
3599
3600 static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3601 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3602 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3603 };
3604
3605 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3606 MUX(1, 111, 5, N, N, N, N),
3607 };
3608
3609 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3610 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3611 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3612 };
3613
3614 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3615 MUX(1, 53, 4, N, N, N, N),
3616 };
3617
3618 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3619 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3620 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3621 };
3622
3623 static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3624 MUX(1, 46, 2, N, N, N, N),
3625 MUX(1, 47, 2, N, N, N, N),
3626 MUX(1, 44, 2, N, N, N, N),
3627 MUX(1, 43, 2, N, N, N, N),
3628 MUX(1, 42, 2, N, N, N, N),
3629 MUX(1, 41, 2, N, N, N, N),
3630 MUX(1, 40, 2, N, N, N, N),
3631 MUX(1, 39, 2, N, N, N, N),
3632 MUX(1, 38, 2, N, N, N, N),
3633 MUX(1, 37, 2, N, N, N, N),
3634 };
3635
3636 static struct atlas7_grp_mux sd0_grp_mux = {
3637 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3638 .pad_mux_list = sd0_grp_pad_mux,
3639 };
3640
3641 static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3642 MUX(1, 46, 2, N, N, N, N),
3643 MUX(1, 47, 2, N, N, N, N),
3644 MUX(1, 44, 2, N, N, N, N),
3645 MUX(1, 43, 2, N, N, N, N),
3646 MUX(1, 42, 2, N, N, N, N),
3647 MUX(1, 41, 2, N, N, N, N),
3648 };
3649
3650 static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3651 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3652 .pad_mux_list = sd0_4bit_grp_pad_mux,
3653 };
3654
3655 static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3656 MUX(1, 48, 3, N, N, N, N),
3657 MUX(1, 49, 3, N, N, N, N),
3658 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3659 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3660 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3661 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3662 MUX(1, 40, 3, N, N, N, N),
3663 MUX(1, 39, 3, N, N, N, N),
3664 MUX(1, 38, 3, N, N, N, N),
3665 MUX(1, 37, 3, N, N, N, N),
3666 };
3667
3668 static struct atlas7_grp_mux sd1_grp_mux = {
3669 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3670 .pad_mux_list = sd1_grp_pad_mux,
3671 };
3672
3673 static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3674 MUX(1, 48, 3, N, N, N, N),
3675 MUX(1, 49, 3, N, N, N, N),
3676 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3677 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3678 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3679 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3680 };
3681
3682 static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3683 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3684 .pad_mux_list = sd1_4bit_grp0_pad_mux,
3685 };
3686
3687 static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3688 MUX(1, 48, 3, N, N, N, N),
3689 MUX(1, 49, 3, N, N, N, N),
3690 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3691 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3692 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3693 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3694 };
3695
3696 static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3697 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3698 .pad_mux_list = sd1_4bit_grp1_pad_mux,
3699 };
3700
3701 static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3702 MUX(1, 31, 1, N, N, N, N),
3703 MUX(1, 32, 1, N, N, N, N),
3704 MUX(1, 33, 1, N, N, N, N),
3705 MUX(1, 34, 1, N, N, N, N),
3706 MUX(1, 35, 1, N, N, N, N),
3707 MUX(1, 36, 1, N, N, N, N),
3708 };
3709
3710 static struct atlas7_grp_mux sd2_basic_grp_mux = {
3711 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3712 .pad_mux_list = sd2_basic_grp_pad_mux,
3713 };
3714
3715 static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3716 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3717 };
3718
3719 static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3720 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3721 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3722 };
3723
3724 static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3725 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3726 };
3727
3728 static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3729 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3730 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3731 };
3732
3733 static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3734 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3735 };
3736
3737 static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3738 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3739 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3740 };
3741
3742 static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3743 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3744 };
3745
3746 static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3747 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3748 .pad_mux_list = sd2_wpb_grp1_pad_mux,
3749 };
3750
3751 static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
3752 MUX(1, 85, 1, N, N, N, N),
3753 MUX(1, 86, 1, N, N, N, N),
3754 MUX(1, 87, 1, N, N, N, N),
3755 MUX(1, 88, 1, N, N, N, N),
3756 MUX(1, 89, 1, N, N, N, N),
3757 MUX(1, 90, 1, N, N, N, N),
3758 };
3759
3760 static struct atlas7_grp_mux sd3_9_grp_mux = {
3761 .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
3762 .pad_mux_list = sd3_9_grp_pad_mux,
3763 };
3764
3765 static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3766 MUX(1, 91, 1, N, N, N, N),
3767 MUX(1, 92, 1, N, N, N, N),
3768 MUX(1, 93, 1, N, N, N, N),
3769 MUX(1, 94, 1, N, N, N, N),
3770 MUX(1, 95, 1, N, N, N, N),
3771 MUX(1, 96, 1, N, N, N, N),
3772 };
3773
3774 static struct atlas7_grp_mux sd5_grp_mux = {
3775 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3776 .pad_mux_list = sd5_grp_pad_mux,
3777 };
3778
3779 static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3780 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3781 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3782 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3783 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3784 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3785 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3786 };
3787
3788 static struct atlas7_grp_mux sd6_grp0_mux = {
3789 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3790 .pad_mux_list = sd6_grp0_pad_mux,
3791 };
3792
3793 static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3794 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3795 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3796 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3797 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3798 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3799 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3800 };
3801
3802 static struct atlas7_grp_mux sd6_grp1_mux = {
3803 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3804 .pad_mux_list = sd6_grp1_pad_mux,
3805 };
3806
3807 static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3808 MUX(0, 4, 2, N, N, N, N),
3809 };
3810
3811 static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3812 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3813 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3814 };
3815
3816 static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3817 MUX(0, 12, 1, N, N, N, N),
3818 MUX(0, 13, 1, N, N, N, N),
3819 MUX(0, 14, 1, N, N, N, N),
3820 MUX(0, 15, 1, N, N, N, N),
3821 MUX(0, 16, 1, N, N, N, N),
3822 MUX(0, 17, 1, N, N, N, N),
3823 };
3824
3825 static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3826 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3827 .pad_mux_list = sp0_qspi_grp_pad_mux,
3828 };
3829
3830 static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3831 MUX(1, 19, 1, N, N, N, N),
3832 MUX(1, 20, 1, N, N, N, N),
3833 MUX(1, 21, 1, N, N, N, N),
3834 MUX(1, 18, 1, N, N, N, N),
3835 };
3836
3837 static struct atlas7_grp_mux sp1_spi_grp_mux = {
3838 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3839 .pad_mux_list = sp1_spi_grp_pad_mux,
3840 };
3841
3842 static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3843 MUX(1, 53, 5, N, N, N, N),
3844 MUX(1, 56, 5, N, N, N, N),
3845 MUX(1, 57, 5, N, N, N, N),
3846 MUX(1, 58, 5, N, N, N, N),
3847 MUX(1, 59, 5, N, N, N, N),
3848 MUX(1, 60, 5, N, N, N, N),
3849 MUX(1, 61, 5, N, N, N, N),
3850 MUX(1, 62, 5, N, N, N, N),
3851 MUX(1, 63, 5, N, N, N, N),
3852 MUX(1, 64, 5, N, N, N, N),
3853 MUX(1, 65, 5, N, N, N, N),
3854 MUX(1, 66, 5, N, N, N, N),
3855 MUX(1, 67, 5, N, N, N, N),
3856 MUX(1, 68, 5, N, N, N, N),
3857 MUX(1, 69, 5, N, N, N, N),
3858 MUX(1, 70, 5, N, N, N, N),
3859 MUX(1, 71, 5, N, N, N, N),
3860 MUX(1, 72, 5, N, N, N, N),
3861 };
3862
3863 static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3864 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3865 .pad_mux_list = tpiu_trace_grp_pad_mux,
3866 };
3867
3868 static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3869 MUX(1, 121, 4, N, N, N, N),
3870 MUX(1, 120, 4, N, N, N, N),
3871 MUX(1, 134, 1, N, N, N, N),
3872 MUX(1, 133, 1, N, N, N, N),
3873 };
3874
3875 static struct atlas7_grp_mux uart0_grp_mux = {
3876 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3877 .pad_mux_list = uart0_grp_pad_mux,
3878 };
3879
3880 static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3881 MUX(1, 134, 1, N, N, N, N),
3882 MUX(1, 133, 1, N, N, N, N),
3883 };
3884
3885 static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3886 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3887 .pad_mux_list = uart0_nopause_grp_pad_mux,
3888 };
3889
3890 static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3891 MUX(1, 136, 1, N, N, N, N),
3892 MUX(1, 135, 1, N, N, N, N),
3893 };
3894
3895 static struct atlas7_grp_mux uart1_grp_mux = {
3896 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3897 .pad_mux_list = uart1_grp_pad_mux,
3898 };
3899
3900 static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3901 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3902 };
3903
3904 static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3905 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3906 .pad_mux_list = uart2_cts_grp0_pad_mux,
3907 };
3908
3909 static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3910 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3911 };
3912
3913 static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3914 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3915 .pad_mux_list = uart2_cts_grp1_pad_mux,
3916 };
3917
3918 static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3919 MUX(1, 131, 3, N, N, N, N),
3920 };
3921
3922 static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3923 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3924 .pad_mux_list = uart2_rts_grp0_pad_mux,
3925 };
3926
3927 static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3928 MUX(1, 161, 2, N, N, N, N),
3929 };
3930
3931 static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3932 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3933 .pad_mux_list = uart2_rts_grp1_pad_mux,
3934 };
3935
3936 static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3937 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3938 };
3939
3940 static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3941 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3942 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3943 };
3944
3945 static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3946 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3947 };
3948
3949 static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3950 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3951 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3952 };
3953
3954 static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3955 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3956 };
3957
3958 static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3959 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3960 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3961 };
3962
3963 static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3964 MUX(0, 10, 2, N, N, N, N),
3965 };
3966
3967 static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3968 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3969 .pad_mux_list = uart2_txd_grp0_pad_mux,
3970 };
3971
3972 static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3973 MUX(1, 159, 2, N, N, N, N),
3974 };
3975
3976 static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3977 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3978 .pad_mux_list = uart2_txd_grp1_pad_mux,
3979 };
3980
3981 static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3982 MUX(1, 129, 3, N, N, N, N),
3983 };
3984
3985 static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3986 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3987 .pad_mux_list = uart2_txd_grp2_pad_mux,
3988 };
3989
3990 static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3991 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3992 };
3993
3994 static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3995 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3996 .pad_mux_list = uart3_cts_grp0_pad_mux,
3997 };
3998
3999 static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
4000 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
4001 };
4002
4003 static struct atlas7_grp_mux uart3_cts_grp1_mux = {
4004 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
4005 .pad_mux_list = uart3_cts_grp1_pad_mux,
4006 };
4007
4008 static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4009 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4010 };
4011
4012 static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4013 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4014 .pad_mux_list = uart3_cts_grp2_pad_mux,
4015 };
4016
4017 static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4018 MUX(1, 126, 2, N, N, N, N),
4019 };
4020
4021 static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4022 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4023 .pad_mux_list = uart3_rts_grp0_pad_mux,
4024 };
4025
4026 static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4027 MUX(1, 109, 4, N, N, N, N),
4028 };
4029
4030 static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4031 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4032 .pad_mux_list = uart3_rts_grp1_pad_mux,
4033 };
4034
4035 static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4036 MUX(1, 139, 2, N, N, N, N),
4037 };
4038
4039 static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4040 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4041 .pad_mux_list = uart3_rts_grp2_pad_mux,
4042 };
4043
4044 static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4045 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4046 };
4047
4048 static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4049 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4050 .pad_mux_list = uart3_rxd_grp0_pad_mux,
4051 };
4052
4053 static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4054 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4055 };
4056
4057 static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4058 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4059 .pad_mux_list = uart3_rxd_grp1_pad_mux,
4060 };
4061
4062 static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4063 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4064 };
4065
4066 static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4067 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4068 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4069 };
4070
4071 static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4072 MUX(1, 137, 1, N, N, N, N),
4073 };
4074
4075 static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4076 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4077 .pad_mux_list = uart3_txd_grp0_pad_mux,
4078 };
4079
4080 static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4081 MUX(1, 83, 2, N, N, N, N),
4082 };
4083
4084 static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4085 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4086 .pad_mux_list = uart3_txd_grp1_pad_mux,
4087 };
4088
4089 static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4090 MUX(1, 161, 3, N, N, N, N),
4091 };
4092
4093 static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4094 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4095 .pad_mux_list = uart3_txd_grp2_pad_mux,
4096 };
4097
4098 static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4099 MUX(1, 140, 1, N, N, N, N),
4100 MUX(1, 139, 1, N, N, N, N),
4101 };
4102
4103 static struct atlas7_grp_mux uart4_basic_grp_mux = {
4104 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4105 .pad_mux_list = uart4_basic_grp_pad_mux,
4106 };
4107
4108 static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4109 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4110 };
4111
4112 static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4113 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4114 .pad_mux_list = uart4_cts_grp0_pad_mux,
4115 };
4116
4117 static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4118 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4119 };
4120
4121 static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4122 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4123 .pad_mux_list = uart4_cts_grp1_pad_mux,
4124 };
4125
4126 static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4127 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4128 };
4129
4130 static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4131 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4132 .pad_mux_list = uart4_cts_grp2_pad_mux,
4133 };
4134
4135 static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4136 MUX(1, 123, 4, N, N, N, N),
4137 };
4138
4139 static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4140 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4141 .pad_mux_list = uart4_rts_grp0_pad_mux,
4142 };
4143
4144 static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4145 MUX(1, 99, 4, N, N, N, N),
4146 };
4147
4148 static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4149 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4150 .pad_mux_list = uart4_rts_grp1_pad_mux,
4151 };
4152
4153 static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4154 MUX(1, 116, 2, N, N, N, N),
4155 };
4156
4157 static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4158 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4159 .pad_mux_list = uart4_rts_grp2_pad_mux,
4160 };
4161
4162 static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4163 MUX(1, 51, 2, N, N, N, N),
4164 };
4165
4166 static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4167 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4168 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4169 };
4170
4171 static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4172 MUX(1, 162, 7, N, N, N, N),
4173 };
4174
4175 static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4176 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4177 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4178 };
4179
4180 static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4181 MUX(1, 134, 2, N, N, N, N),
4182 };
4183
4184 static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4185 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4186 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4187 };
4188
4189 static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4190 MUX(1, 163, 2, N, N, N, N),
4191 };
4192
4193 static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4194 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4195 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4196 };
4197
4198 static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4199 MUX(1, 57, 6, N, N, N, N),
4200 MUX(1, 58, 6, N, N, N, N),
4201 MUX(1, 59, 6, N, N, N, N),
4202 MUX(1, 60, 6, N, N, N, N),
4203 MUX(1, 61, 6, N, N, N, N),
4204 MUX(1, 62, 6, N, N, N, N),
4205 MUX(1, 63, 6, N, N, N, N),
4206 MUX(1, 64, 6, N, N, N, N),
4207 MUX(1, 65, 6, N, N, N, N),
4208 MUX(1, 66, 6, N, N, N, N),
4209 MUX(1, 67, 6, N, N, N, N),
4210 MUX(1, 68, 6, N, N, N, N),
4211 MUX(1, 69, 6, N, N, N, N),
4212 MUX(1, 70, 6, N, N, N, N),
4213 MUX(1, 71, 6, N, N, N, N),
4214 MUX(1, 72, 6, N, N, N, N),
4215 MUX(1, 53, 6, N, N, N, N),
4216 MUX(1, 54, 6, N, N, N, N),
4217 MUX(1, 55, 6, N, N, N, N),
4218 MUX(1, 56, 6, N, N, N, N),
4219 MUX(1, 85, 6, N, N, N, N),
4220 MUX(1, 86, 6, N, N, N, N),
4221 MUX(1, 87, 6, N, N, N, N),
4222 MUX(1, 88, 6, N, N, N, N),
4223 MUX(1, 89, 6, N, N, N, N),
4224 MUX(1, 90, 6, N, N, N, N),
4225 MUX(1, 91, 6, N, N, N, N),
4226 MUX(1, 92, 6, N, N, N, N),
4227 MUX(1, 93, 6, N, N, N, N),
4228 MUX(1, 94, 6, N, N, N, N),
4229 MUX(1, 95, 6, N, N, N, N),
4230 MUX(1, 96, 6, N, N, N, N),
4231 };
4232
4233 static struct atlas7_grp_mux visbus_dout_grp_mux = {
4234 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4235 .pad_mux_list = visbus_dout_grp_pad_mux,
4236 };
4237
4238 static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4239 MUX(1, 74, 1, N, N, N, N),
4240 MUX(1, 75, 1, N, N, N, N),
4241 MUX(1, 76, 1, N, N, N, N),
4242 MUX(1, 77, 1, N, N, N, N),
4243 MUX(1, 78, 1, N, N, N, N),
4244 MUX(1, 79, 1, N, N, N, N),
4245 MUX(1, 80, 1, N, N, N, N),
4246 MUX(1, 81, 1, N, N, N, N),
4247 MUX(1, 82, 1, N, N, N, N),
4248 MUX(1, 83, 1, N, N, N, N),
4249 MUX(1, 84, 1, N, N, N, N),
4250 MUX(1, 103, 2, N, N, N, N),
4251 MUX(1, 104, 2, N, N, N, N),
4252 MUX(1, 105, 2, N, N, N, N),
4253 MUX(1, 106, 2, N, N, N, N),
4254 MUX(1, 107, 2, N, N, N, N),
4255 MUX(1, 102, 2, N, N, N, N),
4256 MUX(1, 97, 2, N, N, N, N),
4257 MUX(1, 98, 2, N, N, N, N),
4258 };
4259
4260 static struct atlas7_grp_mux vi_vip1_grp_mux = {
4261 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4262 .pad_mux_list = vi_vip1_grp_pad_mux,
4263 };
4264
4265 static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4266 MUX(1, 74, 1, N, N, N, N),
4267 MUX(1, 75, 1, N, N, N, N),
4268 MUX(1, 76, 1, N, N, N, N),
4269 MUX(1, 77, 1, N, N, N, N),
4270 MUX(1, 78, 1, N, N, N, N),
4271 MUX(1, 79, 1, N, N, N, N),
4272 MUX(1, 80, 1, N, N, N, N),
4273 MUX(1, 81, 1, N, N, N, N),
4274 MUX(1, 82, 1, N, N, N, N),
4275 MUX(1, 83, 1, N, N, N, N),
4276 MUX(1, 84, 1, N, N, N, N),
4277 MUX(1, 108, 2, N, N, N, N),
4278 MUX(1, 103, 2, N, N, N, N),
4279 MUX(1, 104, 2, N, N, N, N),
4280 MUX(1, 105, 2, N, N, N, N),
4281 MUX(1, 106, 2, N, N, N, N),
4282 MUX(1, 107, 2, N, N, N, N),
4283 MUX(1, 102, 2, N, N, N, N),
4284 MUX(1, 97, 2, N, N, N, N),
4285 MUX(1, 98, 2, N, N, N, N),
4286 MUX(1, 99, 2, N, N, N, N),
4287 MUX(1, 100, 2, N, N, N, N),
4288 };
4289
4290 static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4291 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4292 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4293 };
4294
4295 static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4296 MUX(1, 74, 1, N, N, N, N),
4297 MUX(1, 75, 1, N, N, N, N),
4298 MUX(1, 76, 1, N, N, N, N),
4299 MUX(1, 77, 1, N, N, N, N),
4300 MUX(1, 78, 1, N, N, N, N),
4301 MUX(1, 79, 1, N, N, N, N),
4302 MUX(1, 80, 1, N, N, N, N),
4303 MUX(1, 81, 1, N, N, N, N),
4304 MUX(1, 82, 1, N, N, N, N),
4305 MUX(1, 83, 1, N, N, N, N),
4306 MUX(1, 84, 1, N, N, N, N),
4307 };
4308
4309 static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4310 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4311 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4312 };
4313
4314 static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4315 MUX(1, 82, 1, N, N, N, N),
4316 MUX(1, 83, 1, N, N, N, N),
4317 MUX(1, 84, 1, N, N, N, N),
4318 MUX(1, 103, 2, N, N, N, N),
4319 MUX(1, 104, 2, N, N, N, N),
4320 MUX(1, 105, 2, N, N, N, N),
4321 MUX(1, 106, 2, N, N, N, N),
4322 MUX(1, 107, 2, N, N, N, N),
4323 MUX(1, 102, 2, N, N, N, N),
4324 MUX(1, 97, 2, N, N, N, N),
4325 MUX(1, 98, 2, N, N, N, N),
4326 };
4327
4328 static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4329 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4330 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4331 };
4332
4333 static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4334 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4335 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4336 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4337 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4338 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4339 FUNCTION("jtag_uart_nand_gpio",
4340 jtag_uart_nand_gpio_grp,
4341 &jtag_uart_nand_gpio_grp_mux),
4342 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4343 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4344 FUNCTION("audio_digmic_m0",
4345 audio_digmic_grp0,
4346 &audio_digmic_grp0_mux),
4347 FUNCTION("audio_digmic_m1",
4348 audio_digmic_grp1,
4349 &audio_digmic_grp1_mux),
4350 FUNCTION("audio_digmic_m2",
4351 audio_digmic_grp2,
4352 &audio_digmic_grp2_mux),
4353 FUNCTION("audio_func_dbg",
4354 audio_func_dbg_grp,
4355 &audio_func_dbg_grp_mux),
4356 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4357 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4358 FUNCTION("audio_i2s_extclk",
4359 audio_i2s_extclk_grp,
4360 &audio_i2s_extclk_grp_mux),
4361 FUNCTION("audio_spdif_out_m0",
4362 audio_spdif_out_grp0,
4363 &audio_spdif_out_grp0_mux),
4364 FUNCTION("audio_spdif_out_m1",
4365 audio_spdif_out_grp1,
4366 &audio_spdif_out_grp1_mux),
4367 FUNCTION("audio_spdif_out_m2",
4368 audio_spdif_out_grp2,
4369 &audio_spdif_out_grp2_mux),
4370 FUNCTION("audio_uart0_basic",
4371 audio_uart0_basic_grp,
4372 &audio_uart0_basic_grp_mux),
4373 FUNCTION("audio_uart0_urfs_m0",
4374 audio_uart0_urfs_grp0,
4375 &audio_uart0_urfs_grp0_mux),
4376 FUNCTION("audio_uart0_urfs_m1",
4377 audio_uart0_urfs_grp1,
4378 &audio_uart0_urfs_grp1_mux),
4379 FUNCTION("audio_uart0_urfs_m2",
4380 audio_uart0_urfs_grp2,
4381 &audio_uart0_urfs_grp2_mux),
4382 FUNCTION("audio_uart0_urfs_m3",
4383 audio_uart0_urfs_grp3,
4384 &audio_uart0_urfs_grp3_mux),
4385 FUNCTION("audio_uart1_basic",
4386 audio_uart1_basic_grp,
4387 &audio_uart1_basic_grp_mux),
4388 FUNCTION("audio_uart1_urfs_m0",
4389 audio_uart1_urfs_grp0,
4390 &audio_uart1_urfs_grp0_mux),
4391 FUNCTION("audio_uart1_urfs_m1",
4392 audio_uart1_urfs_grp1,
4393 &audio_uart1_urfs_grp1_mux),
4394 FUNCTION("audio_uart1_urfs_m2",
4395 audio_uart1_urfs_grp2,
4396 &audio_uart1_urfs_grp2_mux),
4397 FUNCTION("audio_uart2_urfs_m0",
4398 audio_uart2_urfs_grp0,
4399 &audio_uart2_urfs_grp0_mux),
4400 FUNCTION("audio_uart2_urfs_m1",
4401 audio_uart2_urfs_grp1,
4402 &audio_uart2_urfs_grp1_mux),
4403 FUNCTION("audio_uart2_urfs_m2",
4404 audio_uart2_urfs_grp2,
4405 &audio_uart2_urfs_grp2_mux),
4406 FUNCTION("audio_uart2_urxd_m0",
4407 audio_uart2_urxd_grp0,
4408 &audio_uart2_urxd_grp0_mux),
4409 FUNCTION("audio_uart2_urxd_m1",
4410 audio_uart2_urxd_grp1,
4411 &audio_uart2_urxd_grp1_mux),
4412 FUNCTION("audio_uart2_urxd_m2",
4413 audio_uart2_urxd_grp2,
4414 &audio_uart2_urxd_grp2_mux),
4415 FUNCTION("audio_uart2_usclk_m0",
4416 audio_uart2_usclk_grp0,
4417 &audio_uart2_usclk_grp0_mux),
4418 FUNCTION("audio_uart2_usclk_m1",
4419 audio_uart2_usclk_grp1,
4420 &audio_uart2_usclk_grp1_mux),
4421 FUNCTION("audio_uart2_usclk_m2",
4422 audio_uart2_usclk_grp2,
4423 &audio_uart2_usclk_grp2_mux),
4424 FUNCTION("audio_uart2_utfs_m0",
4425 audio_uart2_utfs_grp0,
4426 &audio_uart2_utfs_grp0_mux),
4427 FUNCTION("audio_uart2_utfs_m1",
4428 audio_uart2_utfs_grp1,
4429 &audio_uart2_utfs_grp1_mux),
4430 FUNCTION("audio_uart2_utfs_m2",
4431 audio_uart2_utfs_grp2,
4432 &audio_uart2_utfs_grp2_mux),
4433 FUNCTION("audio_uart2_utxd_m0",
4434 audio_uart2_utxd_grp0,
4435 &audio_uart2_utxd_grp0_mux),
4436 FUNCTION("audio_uart2_utxd_m1",
4437 audio_uart2_utxd_grp1,
4438 &audio_uart2_utxd_grp1_mux),
4439 FUNCTION("audio_uart2_utxd_m2",
4440 audio_uart2_utxd_grp2,
4441 &audio_uart2_utxd_grp2_mux),
4442 FUNCTION("c_can_trnsvr_en_m0",
4443 c_can_trnsvr_en_grp0,
4444 &c_can_trnsvr_en_grp0_mux),
4445 FUNCTION("c_can_trnsvr_en_m1",
4446 c_can_trnsvr_en_grp1,
4447 &c_can_trnsvr_en_grp1_mux),
4448 FUNCTION("c_can_trnsvr_intr",
4449 c_can_trnsvr_intr_grp,
4450 &c_can_trnsvr_intr_grp_mux),
4451 FUNCTION("c_can_trnsvr_stb_n",
4452 c_can_trnsvr_stb_n_grp,
4453 &c_can_trnsvr_stb_n_grp_mux),
4454 FUNCTION("c0_can_rxd_trnsv0",
4455 c0_can_rxd_trnsv0_grp,
4456 &c0_can_rxd_trnsv0_grp_mux),
4457 FUNCTION("c0_can_rxd_trnsv1",
4458 c0_can_rxd_trnsv1_grp,
4459 &c0_can_rxd_trnsv1_grp_mux),
4460 FUNCTION("c0_can_txd_trnsv0",
4461 c0_can_txd_trnsv0_grp,
4462 &c0_can_txd_trnsv0_grp_mux),
4463 FUNCTION("c0_can_txd_trnsv1",
4464 c0_can_txd_trnsv1_grp,
4465 &c0_can_txd_trnsv1_grp_mux),
4466 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4467 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4468 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4469 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4470 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4471 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4472 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4473 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4474 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4475 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4476 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4477 FUNCTION("ca_curator_lpc",
4478 ca_curator_lpc_grp,
4479 &ca_curator_lpc_grp_mux),
4480 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4481 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4482 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4483 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4484 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4485 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4486 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4487 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4488 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4489 FUNCTION("gn_gnss_uart_nopause",
4490 gn_gnss_uart_nopause_grp,
4491 &gn_gnss_uart_nopause_grp_mux),
4492 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4493 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4494 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4495 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4496 FUNCTION("cvbs_dbg_test_m0",
4497 cvbs_dbg_test_grp0,
4498 &cvbs_dbg_test_grp0_mux),
4499 FUNCTION("cvbs_dbg_test_m1",
4500 cvbs_dbg_test_grp1,
4501 &cvbs_dbg_test_grp1_mux),
4502 FUNCTION("cvbs_dbg_test_m2",
4503 cvbs_dbg_test_grp2,
4504 &cvbs_dbg_test_grp2_mux),
4505 FUNCTION("cvbs_dbg_test_m3",
4506 cvbs_dbg_test_grp3,
4507 &cvbs_dbg_test_grp3_mux),
4508 FUNCTION("cvbs_dbg_test_m4",
4509 cvbs_dbg_test_grp4,
4510 &cvbs_dbg_test_grp4_mux),
4511 FUNCTION("cvbs_dbg_test_m5",
4512 cvbs_dbg_test_grp5,
4513 &cvbs_dbg_test_grp5_mux),
4514 FUNCTION("cvbs_dbg_test_m6",
4515 cvbs_dbg_test_grp6,
4516 &cvbs_dbg_test_grp6_mux),
4517 FUNCTION("cvbs_dbg_test_m7",
4518 cvbs_dbg_test_grp7,
4519 &cvbs_dbg_test_grp7_mux),
4520 FUNCTION("cvbs_dbg_test_m8",
4521 cvbs_dbg_test_grp8,
4522 &cvbs_dbg_test_grp8_mux),
4523 FUNCTION("cvbs_dbg_test_m9",
4524 cvbs_dbg_test_grp9,
4525 &cvbs_dbg_test_grp9_mux),
4526 FUNCTION("cvbs_dbg_test_m10",
4527 cvbs_dbg_test_grp10,
4528 &cvbs_dbg_test_grp10_mux),
4529 FUNCTION("cvbs_dbg_test_m11",
4530 cvbs_dbg_test_grp11,
4531 &cvbs_dbg_test_grp11_mux),
4532 FUNCTION("cvbs_dbg_test_m12",
4533 cvbs_dbg_test_grp12,
4534 &cvbs_dbg_test_grp12_mux),
4535 FUNCTION("cvbs_dbg_test_m13",
4536 cvbs_dbg_test_grp13,
4537 &cvbs_dbg_test_grp13_mux),
4538 FUNCTION("cvbs_dbg_test_m14",
4539 cvbs_dbg_test_grp14,
4540 &cvbs_dbg_test_grp14_mux),
4541 FUNCTION("cvbs_dbg_test_m15",
4542 cvbs_dbg_test_grp15,
4543 &cvbs_dbg_test_grp15_mux),
4544 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4545 FUNCTION("gn_gnss_sw_status",
4546 gn_gnss_sw_status_grp,
4547 &gn_gnss_sw_status_grp_mux),
4548 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4549 FUNCTION("gn_gnss_irq1_m0",
4550 gn_gnss_irq1_grp0,
4551 &gn_gnss_irq1_grp0_mux),
4552 FUNCTION("gn_gnss_irq2_m0",
4553 gn_gnss_irq2_grp0,
4554 &gn_gnss_irq2_grp0_mux),
4555 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4556 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4557 FUNCTION("gn_io_gnsssys_sw_cfg",
4558 gn_io_gnsssys_sw_cfg_grp,
4559 &gn_io_gnsssys_sw_cfg_grp_mux),
4560 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4561 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4562 FUNCTION("gn_trg_shutdown_m0",
4563 gn_trg_shutdown_grp0,
4564 &gn_trg_shutdown_grp0_mux),
4565 FUNCTION("gn_trg_shutdown_m1",
4566 gn_trg_shutdown_grp1,
4567 &gn_trg_shutdown_grp1_mux),
4568 FUNCTION("gn_trg_shutdown_m2",
4569 gn_trg_shutdown_grp2,
4570 &gn_trg_shutdown_grp2_mux),
4571 FUNCTION("gn_trg_shutdown_m3",
4572 gn_trg_shutdown_grp3,
4573 &gn_trg_shutdown_grp3_mux),
4574 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4575 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4576 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4577 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4578 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4579 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4580 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4581 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4582 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4583 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4584 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4585 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4586 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4587 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4588 FUNCTION("jtag_jt_dbg_nsrst",
4589 jtag_jt_dbg_nsrst_grp,
4590 &jtag_jt_dbg_nsrst_grp_mux),
4591 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4592 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4593 FUNCTION("jtag_swdiotms_m0",
4594 jtag_swdiotms_grp0,
4595 &jtag_swdiotms_grp0_mux),
4596 FUNCTION("jtag_swdiotms_m1",
4597 jtag_swdiotms_grp1,
4598 &jtag_swdiotms_grp1_mux),
4599 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4600 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4601 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4602 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4603 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4604 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4605 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4606 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4607 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4608 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4609 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4610 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4611 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4612 FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
4613 FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
4614 FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
4615 FUNCTION("ps", ps_grp, &ps_grp_mux),
4616 FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
4617 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4618 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4619 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4620 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4621 FUNCTION("pwc_lowbatt_b_m0",
4622 pwc_lowbatt_b_grp0,
4623 &pwc_lowbatt_b_grp0_mux),
4624 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4625 FUNCTION("pwc_on_key_b_m0",
4626 pwc_on_key_b_grp0,
4627 &pwc_on_key_b_grp0_mux),
4628 FUNCTION("pwc_wakeup_src0",
4629 pwc_wakeup_src0_grp,
4630 &pwc_wakeup_src0_grp_mux),
4631 FUNCTION("pwc_wakeup_src1",
4632 pwc_wakeup_src1_grp,
4633 &pwc_wakeup_src1_grp_mux),
4634 FUNCTION("pwc_wakeup_src2",
4635 pwc_wakeup_src2_grp,
4636 &pwc_wakeup_src2_grp_mux),
4637 FUNCTION("pwc_wakeup_src3",
4638 pwc_wakeup_src3_grp,
4639 &pwc_wakeup_src3_grp_mux),
4640 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4641 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4642 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4643 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4644 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4645 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4646 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4647 FUNCTION("pw_i2s01_clk_m0",
4648 pw_i2s01_clk_grp0,
4649 &pw_i2s01_clk_grp0_mux),
4650 FUNCTION("pw_i2s01_clk_m1",
4651 pw_i2s01_clk_grp1,
4652 &pw_i2s01_clk_grp1_mux),
4653 FUNCTION("pw_i2s01_clk_m2",
4654 pw_i2s01_clk_grp2,
4655 &pw_i2s01_clk_grp2_mux),
4656 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4657 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4658 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4659 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4660 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4661 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4662 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4663 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4664 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4665 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4666 FUNCTION("pw_pwm_cpu_vol_m0",
4667 pw_pwm_cpu_vol_grp0,
4668 &pw_pwm_cpu_vol_grp0_mux),
4669 FUNCTION("pw_pwm_cpu_vol_m1",
4670 pw_pwm_cpu_vol_grp1,
4671 &pw_pwm_cpu_vol_grp1_mux),
4672 FUNCTION("pw_pwm_cpu_vol_m2",
4673 pw_pwm_cpu_vol_grp2,
4674 &pw_pwm_cpu_vol_grp2_mux),
4675 FUNCTION("pw_backlight_m0",
4676 pw_backlight_grp0,
4677 &pw_backlight_grp0_mux),
4678 FUNCTION("pw_backlight_m1",
4679 pw_backlight_grp1,
4680 &pw_backlight_grp1_mux),
4681 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4682 FUNCTION("rg_gmac_phy_intr_n",
4683 rg_gmac_phy_intr_n_grp,
4684 &rg_gmac_phy_intr_n_grp_mux),
4685 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4686 FUNCTION("rg_rgmii_phy_ref_clk_m0",
4687 rg_rgmii_phy_ref_clk_grp0,
4688 &rg_rgmii_phy_ref_clk_grp0_mux),
4689 FUNCTION("rg_rgmii_phy_ref_clk_m1",
4690 rg_rgmii_phy_ref_clk_grp1,
4691 &rg_rgmii_phy_ref_clk_grp1_mux),
4692 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4693 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4694 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4695 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4696 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4697 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4698 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4699 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4700 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4701 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4702 FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
4703 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4704 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4705 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4706 FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
4707 FUNCTION("sp0_ext_ldo_on",
4708 sp0_ext_ldo_on_grp,
4709 &sp0_ext_ldo_on_grp_mux),
4710 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4711 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4712 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4713 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4714 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4715 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4716 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4717 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4718 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4719 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4720 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4721 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4722 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4723 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4724 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4725 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4726 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4727 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4728 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4729 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4730 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4731 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4732 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4733 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4734 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4735 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4736 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4737 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4738 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4739 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4740 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4741 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4742 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4743 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4744 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4745 FUNCTION("usb0_drvvbus_m0",
4746 usb0_drvvbus_grp0,
4747 &usb0_drvvbus_grp0_mux),
4748 FUNCTION("usb0_drvvbus_m1",
4749 usb0_drvvbus_grp1,
4750 &usb0_drvvbus_grp1_mux),
4751 FUNCTION("usb1_drvvbus_m0",
4752 usb1_drvvbus_grp0,
4753 &usb1_drvvbus_grp0_mux),
4754 FUNCTION("usb1_drvvbus_m1",
4755 usb1_drvvbus_grp1,
4756 &usb1_drvvbus_grp1_mux),
4757 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4758 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4759 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4760 FUNCTION("vi_vip1_low8bit",
4761 vi_vip1_low8bit_grp,
4762 &vi_vip1_low8bit_grp_mux),
4763 FUNCTION("vi_vip1_high8bit",
4764 vi_vip1_high8bit_grp,
4765 &vi_vip1_high8bit_grp_mux),
4766 };
4767
4768 struct atlas7_pinctrl_data atlas7_ioc_data = {
4769 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4770 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4771 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4772 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4773 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4774 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4775 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4776 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4777 };
4778
4779 /* Simple map data structure */
4780 struct map_data {
4781 u8 idx;
4782 u8 data;
4783 };
4784
4785 /**
4786 * struct atlas7_pull_info - Atlas7 Pad pull info
4787 * @type:The type of this Pad.
4788 * @mask:The mas value of this pin's pull bits.
4789 * @v2s: The map of pull register value to pull status.
4790 * @s2v: The map of pull status to pull register value.
4791 */
4792 struct atlas7_pull_info {
4793 u8 pad_type;
4794 u8 mask;
4795 const struct map_data *v2s;
4796 const struct map_data *s2v;
4797 };
4798
4799 /* Pull Register value map to status */
4800 static const struct map_data p4we_pull_v2s[] = {
4801 { P4WE_PULL_UP, PULL_UP },
4802 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4803 { P4WE_HIGH_Z, HIGH_Z },
4804 { P4WE_PULL_DOWN, PULL_DOWN },
4805 };
4806
4807 static const struct map_data p16st_pull_v2s[] = {
4808 { P16ST_PULL_UP, PULL_UP },
4809 { PD, PULL_UNKNOWN },
4810 { P16ST_HIGH_Z, HIGH_Z },
4811 { P16ST_PULL_DOWN, PULL_DOWN },
4812 };
4813
4814 static const struct map_data pm31_pull_v2s[] = {
4815 { PM31_PULL_DISABLED, PULL_DOWN },
4816 { PM31_PULL_ENABLED, PULL_UP },
4817 };
4818
4819 static const struct map_data pangd_pull_v2s[] = {
4820 { PANGD_PULL_UP, PULL_UP },
4821 { PD, PULL_UNKNOWN },
4822 { PANGD_HIGH_Z, HIGH_Z },
4823 { PANGD_PULL_DOWN, PULL_DOWN },
4824 };
4825
4826 /* Pull status map to register value */
4827 static const struct map_data p4we_pull_s2v[] = {
4828 { PULL_UP, P4WE_PULL_UP },
4829 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4830 { HIGH_Z, P4WE_HIGH_Z },
4831 { PULL_DOWN, P4WE_PULL_DOWN },
4832 { PULL_DISABLE, -1 },
4833 { PULL_ENABLE, -1 },
4834 };
4835
4836 static const struct map_data p16st_pull_s2v[] = {
4837 { PULL_UP, P16ST_PULL_UP },
4838 { HIGH_HYSTERESIS, -1 },
4839 { HIGH_Z, P16ST_HIGH_Z },
4840 { PULL_DOWN, P16ST_PULL_DOWN },
4841 { PULL_DISABLE, -1 },
4842 { PULL_ENABLE, -1 },
4843 };
4844
4845 static const struct map_data pm31_pull_s2v[] = {
4846 { PULL_UP, PM31_PULL_ENABLED },
4847 { HIGH_HYSTERESIS, -1 },
4848 { HIGH_Z, -1 },
4849 { PULL_DOWN, PM31_PULL_DISABLED },
4850 { PULL_DISABLE, -1 },
4851 { PULL_ENABLE, -1 },
4852 };
4853
4854 static const struct map_data pangd_pull_s2v[] = {
4855 { PULL_UP, PANGD_PULL_UP },
4856 { HIGH_HYSTERESIS, -1 },
4857 { HIGH_Z, PANGD_HIGH_Z },
4858 { PULL_DOWN, PANGD_PULL_DOWN },
4859 { PULL_DISABLE, -1 },
4860 { PULL_ENABLE, -1 },
4861 };
4862
4863 static const struct atlas7_pull_info atlas7_pull_map[] = {
4864 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4865 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4866 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4867 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4868 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4869 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4870 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4871 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4872 };
4873
4874 /**
4875 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4876 * @ma: The Drive Strength in current value .
4877 * @ds_16st: The correspond raw value of 16st pad.
4878 * @ds_4we: The correspond raw value of 4we pad.
4879 * @ds_0204m31: The correspond raw value of 0204m31 pad.
4880 * @ds_0610m31: The correspond raw value of 0610m31 pad.
4881 */
4882 struct atlas7_ds_ma_info {
4883 u32 ma;
4884 u32 ds_16st;
4885 u32 ds_4we;
4886 u32 ds_0204m31;
4887 u32 ds_0610m31;
4888 };
4889
4890 static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4891 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4892 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4893 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4894 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4895 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4896 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4897 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4898 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4899 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4900 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4901 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4902 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4903 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4904 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4905 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4906 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4907 };
4908
4909 /**
4910 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4911 * @type: The type of this Pad.
4912 * @mask: The mask value of this pin's pull bits.
4913 * @imval: The immediate value of drives trength register.
4914 */
4915 struct atlas7_ds_info {
4916 u8 type;
4917 u8 mask;
4918 u8 imval;
4919 u8 reserved;
4920 };
4921
4922 static const struct atlas7_ds_info atlas7_ds_map[] = {
4923 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4924 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4925 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4926 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4927 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4928 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4929 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4930 { PAD_T_AD, DS_NULL, DS_NULL },
4931 };
4932
4933 static inline u32 atlas7_pin_to_bank(u32 pin)
4934 {
4935 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4936 }
4937
4938 static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4939 {
4940 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4941
4942 return pmx->pctl_data->funcs_cnt;
4943 }
4944
4945 static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
4946 u32 selector)
4947 {
4948 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4949
4950 return pmx->pctl_data->funcs[selector].name;
4951 }
4952
4953 static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4954 u32 selector, const char * const **groups,
4955 u32 * const num_groups)
4956 {
4957 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4958
4959 *groups = pmx->pctl_data->funcs[selector].groups;
4960 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4961
4962 return 0;
4963 }
4964
4965 static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4966 const struct atlas7_pad_mux *mux)
4967 {
4968 /* Set Input Disable to avoid input glitches
4969 *
4970 * All Input-Disable Control registers are located on IOCRTC.
4971 * So the regs bank is always 0.
4972 *
4973 */
4974 if (mux->dinput_reg && mux->dinput_val_reg) {
4975 writel(DI_MASK << mux->dinput_bit,
4976 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4977 writel(DI_DISABLE << mux->dinput_bit,
4978 pmx->regs[BANK_DS] + mux->dinput_reg);
4979
4980
4981 writel(DIV_MASK << mux->dinput_val_bit,
4982 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4983 writel(DIV_DISABLE << mux->dinput_val_bit,
4984 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4985 }
4986 }
4987
4988 static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4989 const struct atlas7_pad_mux *mux)
4990 {
4991 /* Clear Input Disable to avoid input glitches */
4992 if (mux->dinput_reg && mux->dinput_val_reg) {
4993 writel(DI_MASK << mux->dinput_bit,
4994 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4995 writel(DI_ENABLE << mux->dinput_bit,
4996 pmx->regs[BANK_DS] + mux->dinput_reg);
4997
4998 writel(DIV_MASK << mux->dinput_val_bit,
4999 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
5000 writel(DIV_ENABLE << mux->dinput_val_bit,
5001 pmx->regs[BANK_DS] + mux->dinput_val_reg);
5002 }
5003 }
5004
5005 static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
5006 struct atlas7_pad_config *conf,
5007 u32 bank, u32 ad_sel)
5008 {
5009 unsigned long regv;
5010
5011 /* Write to clear register to clear A/D selector */
5012 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
5013 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
5014
5015 /* Set target pad A/D selector */
5016 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5017 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
5018 writel(regv | (ad_sel << conf->ad_ctrl_bit),
5019 pmx->regs[bank] + conf->ad_ctrl_reg);
5020
5021 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5022 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5023 bank, conf->ad_ctrl_reg, regv);
5024 return 0;
5025 }
5026
5027 static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
5028 struct atlas7_pad_config *conf, u32 bank)
5029 {
5030 /* Only PAD_T_AD pins can change between Analogue&Digital */
5031 if (conf->type != PAD_T_AD)
5032 return -EINVAL;
5033
5034 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
5035 }
5036
5037 static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
5038 struct atlas7_pad_config *conf, u32 bank)
5039 {
5040 /* Other type pads are always digital */
5041 if (conf->type != PAD_T_AD)
5042 return 0;
5043
5044 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
5045 }
5046
5047 static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
5048 u32 pin, u32 func)
5049 {
5050 struct atlas7_pad_config *conf;
5051 u32 bank;
5052 int ret;
5053 unsigned long regv;
5054
5055 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
5056 pin, func);
5057
5058 /* Get this Pad's descriptor from PINCTRL */
5059 conf = &pmx->pctl_data->confs[pin];
5060 bank = atlas7_pin_to_bank(pin);
5061
5062 /* Just enable the analog function of this pad */
5063 if (FUNC_ANALOGUE == func) {
5064 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
5065 if (ret)
5066 dev_err(pmx->dev,
5067 "Convert pad#%d to analog failed, ret=%d\n",
5068 pin, ret);
5069 return ret;
5070 }
5071
5072 /* Set Pads from analog to digital */
5073 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
5074 if (ret) {
5075 dev_err(pmx->dev,
5076 "Convert pad#%d to digital failed, ret=%d\n",
5077 pin, ret);
5078 return ret;
5079 }
5080
5081 /* Write to clear register to clear current function */
5082 writel(FUNC_CLEAR_MASK << conf->mux_bit,
5083 pmx->regs[bank] + CLR_REG(conf->mux_reg));
5084
5085 /* Set target pad mux function */
5086 regv = readl(pmx->regs[bank] + conf->mux_reg);
5087 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
5088 writel(regv | (func << conf->mux_bit),
5089 pmx->regs[bank] + conf->mux_reg);
5090
5091 regv = readl(pmx->regs[bank] + conf->mux_reg);
5092 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5093 bank, conf->mux_reg, regv);
5094
5095 return 0;
5096 }
5097
5098 static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
5099 u32 func_selector, u32 group_selector)
5100 {
5101 int idx, ret;
5102 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5103 struct atlas7_pmx_func *pmx_func;
5104 struct atlas7_pin_group *pin_grp;
5105 const struct atlas7_grp_mux *grp_mux;
5106 const struct atlas7_pad_mux *mux;
5107
5108 pmx_func = &pmx->pctl_data->funcs[func_selector];
5109 pin_grp = &pmx->pctl_data->grps[group_selector];
5110
5111 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
5112 pmx_func->name, pin_grp->name);
5113
5114 /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
5115 if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
5116 if (!strcmp(pmx_func->name, "sd9"))
5117 writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5118 else
5119 writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5120 }
5121
5122 grp_mux = pmx_func->grpmux;
5123
5124 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
5125 mux = &grp_mux->pad_mux_list[idx];
5126 __atlas7_pmx_pin_input_disable_set(pmx, mux);
5127 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
5128 if (ret) {
5129 dev_err(pmx->dev,
5130 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
5131 pmx_func->name, pin_grp->name,
5132 mux->pin, mux->func, ret);
5133 BUG_ON(1);
5134 }
5135 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
5136 }
5137 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
5138 pmx_func->name, pin_grp->name);
5139
5140 return 0;
5141 }
5142
5143 static u32 convert_current_to_drive_strength(u32 type, u32 ma)
5144 {
5145 int idx;
5146
5147 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
5148 if (atlas7_ma2ds_map[idx].ma != ma)
5149 continue;
5150
5151 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
5152 return atlas7_ma2ds_map[idx].ds_4we;
5153 else if (type == PAD_T_16ST)
5154 return atlas7_ma2ds_map[idx].ds_16st;
5155 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
5156 return atlas7_ma2ds_map[idx].ds_0204m31;
5157 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
5158 return atlas7_ma2ds_map[idx].ds_0610m31;
5159 }
5160
5161 return DS_NULL;
5162 }
5163
5164 static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
5165 u32 pin, u32 sel)
5166 {
5167 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5168 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5169 const struct atlas7_pull_info *pull_info;
5170 u32 bank;
5171 unsigned long regv;
5172 void __iomem *pull_sel_reg;
5173
5174 bank = atlas7_pin_to_bank(pin);
5175 pull_info = &atlas7_pull_map[conf->type];
5176 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
5177
5178 /* Retrieve correspond register value from table by sel */
5179 regv = pull_info->s2v[sel].data & pull_info->mask;
5180
5181 /* Clear & Set new value to pull register */
5182 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
5183 writel(regv << conf->pupd_bit, pull_sel_reg);
5184
5185 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
5186 pin, sel);
5187 return 0;
5188 }
5189
5190 static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5191 u32 pin, u32 sel)
5192 {
5193 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5194 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5195 const struct atlas7_ds_info *ds_info;
5196 u32 bank;
5197 void __iomem *ds_sel_reg;
5198
5199 ds_info = &atlas7_ds_map[conf->type];
5200 if (sel & (~(ds_info->mask)))
5201 goto unsupport;
5202
5203 bank = atlas7_pin_to_bank(pin);
5204 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
5205
5206 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
5207 writel(sel << conf->drvstr_bit, ds_sel_reg);
5208
5209 return 0;
5210
5211 unsupport:
5212 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
5213 pin, conf->type, sel);
5214 return -ENOTSUPP;
5215 }
5216
5217 static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5218 u32 pin, u32 ma)
5219 {
5220 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5221 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5222 u32 type = conf->type;
5223 u32 sel;
5224 int ret;
5225
5226 sel = convert_current_to_drive_strength(conf->type, ma);
5227 if (DS_NULL == sel) {
5228 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
5229 pin, type, ma);
5230 return -ENOTSUPP;
5231 }
5232
5233 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
5234 pin, sel);
5235 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
5236 pin, sel, ma, ret?"FAILED":"OK");
5237 return ret;
5238 }
5239
5240 static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
5241 struct pinctrl_gpio_range *range, u32 pin)
5242 {
5243 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5244 u32 idx;
5245
5246 dev_dbg(pmx->dev,
5247 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
5248 for (idx = 0; idx < range->npins; idx++) {
5249 if (pin == range->pins[idx])
5250 break;
5251 }
5252
5253 if (idx >= range->npins) {
5254 dev_err(pmx->dev,
5255 "The pin#%d could not be requested as GPIO!!\n",
5256 pin);
5257 return -EPERM;
5258 }
5259
5260 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
5261
5262 return 0;
5263 }
5264
5265 static struct pinmux_ops atlas7_pinmux_ops = {
5266 .get_functions_count = atlas7_pmx_get_funcs_count,
5267 .get_function_name = atlas7_pmx_get_func_name,
5268 .get_function_groups = atlas7_pmx_get_func_groups,
5269 .set_mux = atlas7_pmx_set_mux,
5270 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
5271 };
5272
5273 static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
5274 {
5275 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5276
5277 return pmx->pctl_data->grps_cnt;
5278 }
5279
5280 static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
5281 u32 group)
5282 {
5283 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5284
5285 return pmx->pctl_data->grps[group].name;
5286 }
5287
5288 static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
5289 u32 group, const u32 **pins, u32 *num_pins)
5290 {
5291 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5292
5293 *num_pins = pmx->pctl_data->grps[group].num_pins;
5294 *pins = pmx->pctl_data->grps[group].pins;
5295
5296 return 0;
5297 }
5298
5299 static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
5300 struct device_node *np_config,
5301 struct pinctrl_map **map,
5302 u32 *num_maps)
5303 {
5304 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
5305 num_maps, PIN_MAP_TYPE_INVALID);
5306 }
5307
5308 static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
5309 struct pinctrl_map *map, u32 num_maps)
5310 {
5311 kfree(map);
5312 }
5313
5314 static const struct pinctrl_ops atlas7_pinctrl_ops = {
5315 .get_groups_count = atlas7_pinctrl_get_groups_count,
5316 .get_group_name = atlas7_pinctrl_get_group_name,
5317 .get_group_pins = atlas7_pinctrl_get_group_pins,
5318 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
5319 .dt_free_map = atlas7_pinctrl_dt_free_map,
5320 };
5321
5322 static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
5323 unsigned pin, unsigned long *configs,
5324 unsigned num_configs)
5325 {
5326 u16 param, arg;
5327 int idx, err;
5328
5329 for (idx = 0; idx < num_configs; idx++) {
5330 param = pinconf_to_config_param(configs[idx]);
5331 arg = pinconf_to_config_argument(configs[idx]);
5332
5333 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
5334 pin, atlas7_ioc_pads[pin].name, param, arg);
5335 switch (param) {
5336 case PIN_CONFIG_BIAS_PULL_UP:
5337 err = altas7_pinctrl_set_pull_sel(pctldev,
5338 pin, PULL_UP);
5339 if (err)
5340 return err;
5341 break;
5342
5343 case PIN_CONFIG_BIAS_PULL_DOWN:
5344 err = altas7_pinctrl_set_pull_sel(pctldev,
5345 pin, PULL_DOWN);
5346 if (err)
5347 return err;
5348 break;
5349
5350 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
5351 err = altas7_pinctrl_set_pull_sel(pctldev,
5352 pin, HIGH_HYSTERESIS);
5353 if (err)
5354 return err;
5355 break;
5356 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
5357 err = altas7_pinctrl_set_pull_sel(pctldev,
5358 pin, HIGH_Z);
5359 if (err)
5360 return err;
5361 break;
5362
5363 case PIN_CONFIG_DRIVE_STRENGTH:
5364 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
5365 pin, arg);
5366 if (err)
5367 return err;
5368 break;
5369 default:
5370 return -ENOTSUPP;
5371 }
5372 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
5373 pin, atlas7_ioc_pads[pin].name, param, arg);
5374 }
5375
5376 return 0;
5377 }
5378
5379 static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
5380 unsigned group, unsigned long *configs,
5381 unsigned num_configs)
5382 {
5383 const unsigned *pins;
5384 unsigned npins;
5385 int i, ret;
5386
5387 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
5388 if (ret)
5389 return ret;
5390 for (i = 0; i < npins; i++) {
5391 if (atlas7_pin_config_set(pctldev, pins[i],
5392 configs, num_configs))
5393 return -ENOTSUPP;
5394 }
5395 return 0;
5396 }
5397
5398 static const struct pinconf_ops atlas7_pinconf_ops = {
5399 .pin_config_set = atlas7_pin_config_set,
5400 .pin_config_group_set = atlas7_pin_config_group_set,
5401 .is_generic = true,
5402 };
5403
5404 static int atlas7_pinmux_probe(struct platform_device *pdev)
5405 {
5406 int ret, idx;
5407 struct atlas7_pmx *pmx;
5408 struct device_node *np = pdev->dev.of_node;
5409 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
5410 struct device_node *sys2pci_np;
5411 struct resource res;
5412
5413 /* Create state holders etc for this driver */
5414 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
5415 if (!pmx)
5416 return -ENOMEM;
5417
5418 /* The sd3 and sd9 shared all pins, and the function select by
5419 * SYS2PCI_SDIO9SEL register
5420 */
5421 sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
5422 if (!sys2pci_np)
5423 return -EINVAL;
5424 ret = of_address_to_resource(sys2pci_np, 0, &res);
5425 if (ret)
5426 return ret;
5427 pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
5428 if (IS_ERR(pmx->sys2pci_base))
5429 return -ENOMEM;
5430
5431 pmx->dev = &pdev->dev;
5432
5433 pmx->pctl_data = &atlas7_ioc_data;
5434 pmx->pctl_desc.name = "pinctrl-atlas7";
5435 pmx->pctl_desc.pins = pmx->pctl_data->pads;
5436 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
5437 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
5438 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
5439 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
5440
5441 for (idx = 0; idx < banks; idx++) {
5442 pmx->regs[idx] = of_iomap(np, idx);
5443 if (!pmx->regs[idx]) {
5444 dev_err(&pdev->dev,
5445 "can't map ioc bank#%d registers\n", idx);
5446 ret = -ENOMEM;
5447 goto unmap_io;
5448 }
5449 }
5450
5451 /* Now register the pin controller and all pins it handles */
5452 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
5453 if (IS_ERR(pmx->pctl)) {
5454 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
5455 ret = PTR_ERR(pmx->pctl);
5456 goto unmap_io;
5457 }
5458
5459 platform_set_drvdata(pdev, pmx);
5460
5461 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
5462
5463 return 0;
5464
5465 unmap_io:
5466 for (idx = 0; idx < banks; idx++) {
5467 if (!pmx->regs[idx])
5468 break;
5469 iounmap(pmx->regs[idx]);
5470 }
5471
5472 return ret;
5473 }
5474
5475 #ifdef CONFIG_PM_SLEEP
5476 static int atlas7_pinmux_suspend_noirq(struct device *dev)
5477 {
5478 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5479 struct atlas7_pad_status *status;
5480 struct atlas7_pad_config *conf;
5481 const struct atlas7_ds_info *ds_info;
5482 const struct atlas7_pull_info *pull_info;
5483 int idx;
5484 u32 bank;
5485 unsigned long regv;
5486
5487 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5488 /* Get this Pad's descriptor from PINCTRL */
5489 conf = &pmx->pctl_data->confs[idx];
5490 bank = atlas7_pin_to_bank(idx);
5491 status = &pmx->sleep_data[idx];
5492
5493 /* Save Function selector */
5494 regv = readl(pmx->regs[bank] + conf->mux_reg);
5495 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
5496
5497 /* Check if Pad is in Analogue selector */
5498 if (conf->ad_ctrl_reg == -1)
5499 goto save_ds_sel;
5500
5501 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5502 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
5503 status->func = FUNC_ANALOGUE;
5504
5505 save_ds_sel:
5506 if (conf->drvstr_reg == -1)
5507 goto save_pull_sel;
5508
5509 /* Save Drive Strength selector */
5510 ds_info = &atlas7_ds_map[conf->type];
5511 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
5512 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
5513
5514 save_pull_sel:
5515 /* Save Pull selector */
5516 pull_info = &atlas7_pull_map[conf->type];
5517 regv = readl(pmx->regs[bank] + conf->pupd_reg);
5518 regv = (regv >> conf->pupd_bit) & pull_info->mask;
5519 status->pull = pull_info->v2s[regv].data;
5520 }
5521
5522 /*
5523 * Save disable input selector, this selector is not for Pin,
5524 * but for Mux function.
5525 */
5526 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5527 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
5528 IN_DISABLE_0_REG_SET + 0x8 * idx);
5529 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
5530 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5531 }
5532
5533 return 0;
5534 }
5535
5536 static int atlas7_pinmux_resume_noirq(struct device *dev)
5537 {
5538 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5539 struct atlas7_pad_status *status;
5540 struct atlas7_pad_config *conf;
5541 int idx;
5542 u32 bank;
5543
5544 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5545 /* Get this Pad's descriptor from PINCTRL */
5546 conf = &pmx->pctl_data->confs[idx];
5547 bank = atlas7_pin_to_bank(idx);
5548 status = &pmx->sleep_data[idx];
5549
5550 /* Restore Function selector */
5551 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
5552
5553 if (FUNC_ANALOGUE == status->func)
5554 goto restore_pull_sel;
5555
5556 /* Restore Drive Strength selector */
5557 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
5558 (u32)status->dstr & 0xff);
5559
5560 restore_pull_sel:
5561 /* Restore Pull selector */
5562 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
5563 (u32)status->pull & 0xff);
5564 }
5565
5566 /*
5567 * Restore disable input selector, this selector is not for Pin,
5568 * but for Mux function
5569 */
5570 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5571 writel(~0, pmx->regs[BANK_DS] +
5572 IN_DISABLE_0_REG_CLR + 0x8 * idx);
5573 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
5574 IN_DISABLE_0_REG_SET + 0x8 * idx);
5575 writel(~0, pmx->regs[BANK_DS] +
5576 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
5577 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
5578 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5579 }
5580
5581 return 0;
5582 }
5583
5584 static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
5585 .suspend_noirq = atlas7_pinmux_suspend_noirq,
5586 .resume_noirq = atlas7_pinmux_resume_noirq,
5587 .freeze_noirq = atlas7_pinmux_suspend_noirq,
5588 .restore_noirq = atlas7_pinmux_resume_noirq,
5589 };
5590 #endif
5591
5592 static const struct of_device_id atlas7_pinmux_ids[] = {
5593 { .compatible = "sirf,atlas7-ioc",},
5594 {},
5595 };
5596
5597 static struct platform_driver atlas7_pinmux_driver = {
5598 .driver = {
5599 .name = "atlas7-ioc",
5600 .of_match_table = atlas7_pinmux_ids,
5601 #ifdef CONFIG_PM_SLEEP
5602 .pm = &atlas7_pinmux_pm_ops,
5603 #endif
5604 },
5605 .probe = atlas7_pinmux_probe,
5606 };
5607
5608 static int __init atlas7_pinmux_init(void)
5609 {
5610 return platform_driver_register(&atlas7_pinmux_driver);
5611 }
5612 arch_initcall(atlas7_pinmux_init);
5613
5614
5615 /**
5616 * The Following is GPIO Code
5617 */
5618 static inline struct
5619 atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
5620 {
5621 return &a7gc->banks[GPIO_TO_BANK(gpio)];
5622 }
5623
5624 static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
5625 {
5626 struct atlas7_gpio_bank *bank;
5627 u32 ofs;
5628
5629 bank = atlas7_gpio_to_bank(a7gc, gpio);
5630 ofs = gpio - bank->gpio_offset;
5631 if (ofs >= bank->ngpio)
5632 return -ENODEV;
5633
5634 return bank->gpio_pins[ofs];
5635 }
5636
5637 static void atlas7_gpio_irq_ack(struct irq_data *d)
5638 {
5639 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5640 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5641 struct atlas7_gpio_bank *bank;
5642 void __iomem *ctrl_reg;
5643 u32 val, pin_in_bank;
5644 unsigned long flags;
5645
5646 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5647 pin_in_bank = d->hwirq - bank->gpio_offset;
5648 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5649
5650 spin_lock_irqsave(&a7gc->lock, flags);
5651
5652 val = readl(ctrl_reg);
5653 /* clear interrupt status */
5654 writel(val, ctrl_reg);
5655
5656 spin_unlock_irqrestore(&a7gc->lock, flags);
5657 }
5658
5659 static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
5660 {
5661 struct atlas7_gpio_bank *bank;
5662 void __iomem *ctrl_reg;
5663 u32 val, pin_in_bank;
5664
5665 bank = atlas7_gpio_to_bank(a7gc, idx);
5666 pin_in_bank = idx - bank->gpio_offset;
5667 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5668
5669 val = readl(ctrl_reg);
5670 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
5671 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
5672 writel(val, ctrl_reg);
5673 }
5674
5675 static void atlas7_gpio_irq_mask(struct irq_data *d)
5676 {
5677 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5678 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5679 unsigned long flags;
5680
5681 spin_lock_irqsave(&a7gc->lock, flags);
5682
5683 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
5684
5685 spin_unlock_irqrestore(&a7gc->lock, flags);
5686 }
5687
5688 static void atlas7_gpio_irq_unmask(struct irq_data *d)
5689 {
5690 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5691 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5692 struct atlas7_gpio_bank *bank;
5693 void __iomem *ctrl_reg;
5694 u32 val, pin_in_bank;
5695 unsigned long flags;
5696
5697 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5698 pin_in_bank = d->hwirq - bank->gpio_offset;
5699 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5700
5701 spin_lock_irqsave(&a7gc->lock, flags);
5702
5703 val = readl(ctrl_reg);
5704 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
5705 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
5706 writel(val, ctrl_reg);
5707
5708 spin_unlock_irqrestore(&a7gc->lock, flags);
5709 }
5710
5711 static int atlas7_gpio_irq_type(struct irq_data *d,
5712 unsigned int type)
5713 {
5714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5715 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5716 struct atlas7_gpio_bank *bank;
5717 void __iomem *ctrl_reg;
5718 u32 val, pin_in_bank;
5719 unsigned long flags;
5720
5721 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5722 pin_in_bank = d->hwirq - bank->gpio_offset;
5723 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5724
5725 spin_lock_irqsave(&a7gc->lock, flags);
5726
5727 val = readl(ctrl_reg);
5728 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
5729 ATLAS7_GPIO_CTL_INTR_EN_MASK);
5730
5731 switch (type) {
5732 case IRQ_TYPE_NONE:
5733 break;
5734
5735 case IRQ_TYPE_EDGE_RISING:
5736 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5737 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5738 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5739 break;
5740
5741 case IRQ_TYPE_EDGE_FALLING:
5742 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5743 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5744 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5745 break;
5746
5747 case IRQ_TYPE_EDGE_BOTH:
5748 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5749 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5750 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5751 break;
5752
5753 case IRQ_TYPE_LEVEL_LOW:
5754 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5755 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5756 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5757 break;
5758
5759 case IRQ_TYPE_LEVEL_HIGH:
5760 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5761 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5762 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5763 break;
5764 }
5765
5766 writel(val, ctrl_reg);
5767
5768 spin_unlock_irqrestore(&a7gc->lock, flags);
5769
5770 return 0;
5771 }
5772
5773 static struct irq_chip atlas7_gpio_irq_chip = {
5774 .name = "atlas7-gpio-irq",
5775 .irq_ack = atlas7_gpio_irq_ack,
5776 .irq_mask = atlas7_gpio_irq_mask,
5777 .irq_unmask = atlas7_gpio_irq_unmask,
5778 .irq_set_type = atlas7_gpio_irq_type,
5779 };
5780
5781 static void atlas7_gpio_handle_irq(struct irq_desc *desc)
5782 {
5783 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5784 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5785 struct atlas7_gpio_bank *bank = NULL;
5786 u32 status, ctrl;
5787 int pin_in_bank = 0, idx;
5788 struct irq_chip *chip = irq_desc_get_chip(desc);
5789 unsigned int irq = irq_desc_get_irq(desc);
5790
5791 for (idx = 0; idx < a7gc->nbank; idx++) {
5792 bank = &a7gc->banks[idx];
5793 if (bank->irq == irq)
5794 break;
5795 }
5796 BUG_ON(idx == a7gc->nbank);
5797
5798 chained_irq_enter(chip, desc);
5799
5800 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
5801 if (!status) {
5802 pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n",
5803 __func__, gc->label, status);
5804 handle_bad_irq(desc);
5805 return;
5806 }
5807
5808 while (status) {
5809 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5810
5811 /*
5812 * Here we must check whether the corresponding GPIO's
5813 * interrupt has been enabled, otherwise just skip it
5814 */
5815 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
5816 pr_debug("%s: chip[%s] gpio:%d happens\n",
5817 __func__, gc->label,
5818 bank->gpio_offset + pin_in_bank);
5819 generic_handle_irq(
5820 irq_find_mapping(gc->irqdomain,
5821 bank->gpio_offset + pin_in_bank));
5822 }
5823
5824 if (++pin_in_bank >= bank->ngpio)
5825 break;
5826
5827 status = status >> 1;
5828 }
5829
5830 chained_irq_exit(chip, desc);
5831 }
5832
5833 static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
5834 unsigned int gpio)
5835 {
5836 struct atlas7_gpio_bank *bank;
5837 void __iomem *ctrl_reg;
5838 u32 val, pin_in_bank;
5839
5840 bank = atlas7_gpio_to_bank(a7gc, gpio);
5841 pin_in_bank = gpio - bank->gpio_offset;
5842 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5843
5844 val = readl(ctrl_reg);
5845 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
5846 writel(val, ctrl_reg);
5847 }
5848
5849 static int atlas7_gpio_request(struct gpio_chip *chip,
5850 unsigned int gpio)
5851 {
5852 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5853 int ret;
5854 unsigned long flags;
5855
5856 ret = __atlas7_gpio_to_pin(a7gc, gpio);
5857 if (ret < 0)
5858 return ret;
5859
5860 if (pinctrl_request_gpio(chip->base + gpio))
5861 return -ENODEV;
5862
5863 spin_lock_irqsave(&a7gc->lock, flags);
5864
5865 /*
5866 * default status:
5867 * set direction as input and mask irq
5868 */
5869 __atlas7_gpio_set_input(a7gc, gpio);
5870 __atlas7_gpio_irq_mask(a7gc, gpio);
5871
5872 spin_unlock_irqrestore(&a7gc->lock, flags);
5873
5874 return 0;
5875 }
5876
5877 static void atlas7_gpio_free(struct gpio_chip *chip,
5878 unsigned int gpio)
5879 {
5880 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5881 unsigned long flags;
5882
5883 spin_lock_irqsave(&a7gc->lock, flags);
5884
5885 __atlas7_gpio_irq_mask(a7gc, gpio);
5886 __atlas7_gpio_set_input(a7gc, gpio);
5887
5888 spin_unlock_irqrestore(&a7gc->lock, flags);
5889
5890 pinctrl_free_gpio(chip->base + gpio);
5891 }
5892
5893 static int atlas7_gpio_direction_input(struct gpio_chip *chip,
5894 unsigned int gpio)
5895 {
5896 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5897 unsigned long flags;
5898
5899 spin_lock_irqsave(&a7gc->lock, flags);
5900
5901 __atlas7_gpio_set_input(a7gc, gpio);
5902
5903 spin_unlock_irqrestore(&a7gc->lock, flags);
5904
5905 return 0;
5906 }
5907
5908 static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
5909 unsigned int gpio, int value)
5910 {
5911 struct atlas7_gpio_bank *bank;
5912 void __iomem *ctrl_reg;
5913 u32 out_ctrl, pin_in_bank;
5914
5915 bank = atlas7_gpio_to_bank(a7gc, gpio);
5916 pin_in_bank = gpio - bank->gpio_offset;
5917 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5918
5919 out_ctrl = readl(ctrl_reg);
5920 if (value)
5921 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5922 else
5923 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5924
5925 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
5926 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
5927 writel(out_ctrl, ctrl_reg);
5928 }
5929
5930 static int atlas7_gpio_direction_output(struct gpio_chip *chip,
5931 unsigned int gpio, int value)
5932 {
5933 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5934 unsigned long flags;
5935
5936 spin_lock_irqsave(&a7gc->lock, flags);
5937
5938 __atlas7_gpio_set_output(a7gc, gpio, value);
5939
5940 spin_unlock_irqrestore(&a7gc->lock, flags);
5941
5942 return 0;
5943 }
5944
5945 static int atlas7_gpio_get_value(struct gpio_chip *chip,
5946 unsigned int gpio)
5947 {
5948 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5949 struct atlas7_gpio_bank *bank;
5950 u32 val, pin_in_bank;
5951 unsigned long flags;
5952
5953 bank = atlas7_gpio_to_bank(a7gc, gpio);
5954 pin_in_bank = gpio - bank->gpio_offset;
5955
5956 spin_lock_irqsave(&a7gc->lock, flags);
5957
5958 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5959
5960 spin_unlock_irqrestore(&a7gc->lock, flags);
5961
5962 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
5963 }
5964
5965 static void atlas7_gpio_set_value(struct gpio_chip *chip,
5966 unsigned int gpio, int value)
5967 {
5968 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5969 struct atlas7_gpio_bank *bank;
5970 void __iomem *ctrl_reg;
5971 u32 ctrl, pin_in_bank;
5972 unsigned long flags;
5973
5974 bank = atlas7_gpio_to_bank(a7gc, gpio);
5975 pin_in_bank = gpio - bank->gpio_offset;
5976 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5977
5978 spin_lock_irqsave(&a7gc->lock, flags);
5979
5980 ctrl = readl(ctrl_reg);
5981 if (value)
5982 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5983 else
5984 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5985 writel(ctrl, ctrl_reg);
5986
5987 spin_unlock_irqrestore(&a7gc->lock, flags);
5988 }
5989
5990 static const struct of_device_id atlas7_gpio_ids[] = {
5991 { .compatible = "sirf,atlas7-gpio", },
5992 {},
5993 };
5994
5995 static int atlas7_gpio_probe(struct platform_device *pdev)
5996 {
5997 struct device_node *np = pdev->dev.of_node;
5998 struct atlas7_gpio_chip *a7gc;
5999 struct gpio_chip *chip;
6000 u32 nbank;
6001 int ret, idx;
6002
6003 ret = of_property_read_u32(np, "gpio-banks", &nbank);
6004 if (ret) {
6005 dev_err(&pdev->dev,
6006 "Could not find GPIO bank info,ret=%d!\n",
6007 ret);
6008 return ret;
6009 }
6010
6011 /* retrieve gpio descriptor data */
6012 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
6013 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
6014 if (!a7gc)
6015 return -ENOMEM;
6016
6017 /* Get Gpio clk */
6018 a7gc->clk = of_clk_get(np, 0);
6019 if (!IS_ERR(a7gc->clk)) {
6020 ret = clk_prepare_enable(a7gc->clk);
6021 if (ret) {
6022 dev_err(&pdev->dev,
6023 "Could not enable clock!\n");
6024 return ret;
6025 }
6026 }
6027
6028 /* Get Gpio Registers */
6029 a7gc->reg = of_iomap(np, 0);
6030 if (!a7gc->reg) {
6031 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
6032 return -ENOMEM;
6033 }
6034
6035 a7gc->nbank = nbank;
6036 spin_lock_init(&a7gc->lock);
6037
6038 /* Setup GPIO Chip */
6039 chip = &a7gc->chip;
6040 chip->request = atlas7_gpio_request;
6041 chip->free = atlas7_gpio_free;
6042 chip->direction_input = atlas7_gpio_direction_input;
6043 chip->get = atlas7_gpio_get_value;
6044 chip->direction_output = atlas7_gpio_direction_output;
6045 chip->set = atlas7_gpio_set_value;
6046 chip->base = -1;
6047 /* Each chip can support 32 pins at one bank */
6048 chip->ngpio = NGPIO_OF_BANK * nbank;
6049 chip->label = kstrdup(np->name, GFP_KERNEL);
6050 chip->of_node = np;
6051 chip->of_gpio_n_cells = 2;
6052 chip->parent = &pdev->dev;
6053
6054 /* Add gpio chip to system */
6055 ret = gpiochip_add_data(chip, a7gc);
6056 if (ret) {
6057 dev_err(&pdev->dev,
6058 "%s: error in probe function with status %d\n",
6059 np->name, ret);
6060 goto failed;
6061 }
6062
6063 /* Add gpio chip to irq subsystem */
6064 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6065 0, handle_level_irq, IRQ_TYPE_NONE);
6066 if (ret) {
6067 dev_err(&pdev->dev,
6068 "could not connect irqchip to gpiochip\n");
6069 goto failed;
6070 }
6071
6072 for (idx = 0; idx < nbank; idx++) {
6073 struct gpio_pin_range *pin_range;
6074 struct atlas7_gpio_bank *bank;
6075
6076 bank = &a7gc->banks[idx];
6077 /* Set ctrl registers' base of this bank */
6078 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6079
6080 /* Get interrupt number from DTS */
6081 ret = of_irq_get(np, idx);
6082 if (ret == -EPROBE_DEFER) {
6083 dev_err(&pdev->dev,
6084 "Unable to find IRQ number. ret=%d\n", ret);
6085 goto failed;
6086 }
6087 bank->irq = ret;
6088
6089 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6090 bank->irq, atlas7_gpio_handle_irq);
6091
6092 /* Records gpio_pin_range to a7gc */
6093 list_for_each_entry(pin_range, &chip->pin_ranges, node) {
6094 struct pinctrl_gpio_range *range;
6095
6096 range = &pin_range->range;
6097 if (range->id == NGPIO_OF_BANK * idx) {
6098 bank->gpio_offset = range->id;
6099 bank->ngpio = range->npins;
6100 bank->gpio_pins = range->pins;
6101 bank->pctldev = pin_range->pctldev;
6102 break;
6103 }
6104 }
6105
6106 BUG_ON(!bank->pctldev);
6107 }
6108
6109 platform_set_drvdata(pdev, a7gc);
6110 dev_info(&pdev->dev, "add to system.\n");
6111 return 0;
6112 failed:
6113 return ret;
6114 }
6115
6116 #ifdef CONFIG_PM_SLEEP
6117 static int atlas7_gpio_suspend_noirq(struct device *dev)
6118 {
6119 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6120 struct atlas7_gpio_bank *bank;
6121 void __iomem *ctrl_reg;
6122 u32 idx, pin;
6123
6124 for (idx = 0; idx < a7gc->nbank; idx++) {
6125 bank = &a7gc->banks[idx];
6126 for (pin = 0; pin < bank->ngpio; pin++) {
6127 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6128 bank->sleep_data[pin] = readl(ctrl_reg);
6129 }
6130 }
6131
6132 return 0;
6133 }
6134
6135 static int atlas7_gpio_resume_noirq(struct device *dev)
6136 {
6137 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6138 struct atlas7_gpio_bank *bank;
6139 void __iomem *ctrl_reg;
6140 u32 idx, pin;
6141
6142 for (idx = 0; idx < a7gc->nbank; idx++) {
6143 bank = &a7gc->banks[idx];
6144 for (pin = 0; pin < bank->ngpio; pin++) {
6145 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6146 writel(bank->sleep_data[pin], ctrl_reg);
6147 }
6148 }
6149
6150 return 0;
6151 }
6152
6153 static const struct dev_pm_ops atlas7_gpio_pm_ops = {
6154 .suspend_noirq = atlas7_gpio_suspend_noirq,
6155 .resume_noirq = atlas7_gpio_resume_noirq,
6156 .freeze_noirq = atlas7_gpio_suspend_noirq,
6157 .restore_noirq = atlas7_gpio_resume_noirq,
6158 };
6159 #endif
6160
6161 static struct platform_driver atlas7_gpio_driver = {
6162 .driver = {
6163 .name = "atlas7-gpio",
6164 .of_match_table = atlas7_gpio_ids,
6165 #ifdef CONFIG_PM_SLEEP
6166 .pm = &atlas7_gpio_pm_ops,
6167 #endif
6168 },
6169 .probe = atlas7_gpio_probe,
6170 };
6171
6172 static int __init atlas7_gpio_init(void)
6173 {
6174 return platform_driver_register(&atlas7_gpio_driver);
6175 }
6176 subsys_initcall(atlas7_gpio_init);
6177
6178 MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver");
6179 MODULE_LICENSE("GPL");
Linux with added FPC-III support