drivers/net/wireless/rsi/rsi_hal.h

   1 /**
   2  * Copyright (c) 2017 Redpine Signals Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __RSI_HAL_H__
  18 #define __RSI_HAL_H__
  19
  20 /* Device Operating modes */
  21 #define DEV_OPMODE_WIFI_ALONE           1
  22 #define DEV_OPMODE_BT_ALONE             4
  23 #define DEV_OPMODE_BT_LE_ALONE          8
  24 #define DEV_OPMODE_BT_DUAL              12
  25 #define DEV_OPMODE_STA_BT               5
  26 #define DEV_OPMODE_STA_BT_LE            9
  27 #define DEV_OPMODE_STA_BT_DUAL          13
  28 #define DEV_OPMODE_AP_BT                6
  29 #define DEV_OPMODE_AP_BT_DUAL           14
  30
  31 #define FLASH_WRITE_CHUNK_SIZE          (4 * 1024)
  32 #define FLASH_SECTOR_SIZE               (4 * 1024)
  33
  34 #define FLASH_SIZE_ADDR                 0x04000016
  35 #define PING_BUFFER_ADDRESS             0x19000
  36 #define PONG_BUFFER_ADDRESS             0x1a000
  37 #define SWBL_REGIN                      0x41050034
  38 #define SWBL_REGOUT                     0x4105003c
  39 #define PING_WRITE                      0x1
  40 #define PONG_WRITE                      0x2
  41
  42 #define BL_CMD_TIMEOUT                  2000
  43 #define BL_BURN_TIMEOUT                 (50 * 1000)
  44
  45 #define REGIN_VALID                     0xA
  46 #define REGIN_INPUT                     0xA0
  47 #define REGOUT_VALID                    0xAB
  48 #define REGOUT_INVALID                  (~0xAB)
  49 #define CMD_PASS                        0xAA
  50 #define CMD_FAIL                        0xCC
  51
  52 #define LOAD_HOSTED_FW                  'A'
  53 #define BURN_HOSTED_FW                  'B'
  54 #define PING_VALID                      'I'
  55 #define PONG_VALID                      'O'
  56 #define PING_AVAIL                      'I'
  57 #define PONG_AVAIL                      'O'
  58 #define EOF_REACHED                     'E'
  59 #define CHECK_CRC                       'K'
  60 #define POLLING_MODE                    'P'
  61 #define CONFIG_AUTO_READ_MODE           'R'
  62 #define JUMP_TO_ZERO_PC                 'J'
  63 #define FW_LOADING_SUCCESSFUL           'S'
  64 #define LOADING_INITIATED               '1'
  65
  66 #define RSI_ULP_RESET_REG               0x161
  67 #define RSI_WATCH_DOG_TIMER_1           0x16c
  68 #define RSI_WATCH_DOG_TIMER_2           0x16d
  69 #define RSI_WATCH_DOG_DELAY_TIMER_1             0x16e
  70 #define RSI_WATCH_DOG_DELAY_TIMER_2             0x16f
  71 #define RSI_WATCH_DOG_TIMER_ENABLE              0x170
  72
  73 #define RSI_ULP_WRITE_0                 00
  74 #define RSI_ULP_WRITE_2                 02
  75 #define RSI_ULP_WRITE_50                50
  76
  77 #define RSI_RESTART_WDT                 BIT(11)
  78 #define RSI_BYPASS_ULP_ON_WDT           BIT(1)
  79
  80 #define RSI_ULP_TIMER_ENABLE            ((0xaa000) | RSI_RESTART_WDT |  \
  81                                          RSI_BYPASS_ULP_ON_WDT)
  82 #define RSI_RF_SPI_PROG_REG_BASE_ADDR   0x40080000
  83
  84 #define RSI_GSPI_CTRL_REG0              (RSI_RF_SPI_PROG_REG_BASE_ADDR)
  85 #define RSI_GSPI_CTRL_REG1              (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
  86 #define RSI_GSPI_DATA_REG0              (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
  87 #define RSI_GSPI_DATA_REG1              (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
  88 #define RSI_GSPI_DATA_REG2              (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
  89
  90 #define RSI_GSPI_CTRL_REG0_VALUE                0x340
  91
  92 #define RSI_GSPI_DMA_MODE                       BIT(13)
  93
  94 #define RSI_GSPI_2_ULP                  BIT(12)
  95 #define RSI_GSPI_TRIG                   BIT(7)
  96 #define RSI_GSPI_READ                   BIT(6)
  97 #define RSI_GSPI_RF_SPI_ACTIVE          BIT(8)
  98
  99 /* Boot loader commands */
 100 #define SEND_RPS_FILE                   '2'
 101
 102 #define FW_IMAGE_MIN_ADDRESS            (68 * 1024)
 103 #define MAX_FLASH_FILE_SIZE             (400 * 1024) //400K
 104 #define FLASH_START_ADDRESS             16
 105
 106 #define COMMON_HAL_CARD_READY_IND       0x0
 107
 108 #define COMMAN_HAL_WAIT_FOR_CARD_READY  1
 109
 110 #define RSI_DEV_OPMODE_WIFI_ALONE       1
 111 #define RSI_DEV_COEX_MODE_WIFI_ALONE    1
 112
 113 #define BBP_INFO_40MHZ 0x6
 114
 115 #define FW_FLASH_OFFSET                 0x820
 116 #define LMAC_VER_OFFSET                 (FW_FLASH_OFFSET + 0x200)
 117 #define MAX_DWORD_ALIGN_BYTES           64
 118 #define RSI_COMMON_REG_SIZE             2
 119
 120 struct bl_header {
 121         __le32 flags;
 122         __le32 image_no;
 123         __le32 check_sum;
 124         __le32 flash_start_address;
 125         __le32 flash_len;
 126 } __packed;
 127
 128 struct ta_metadata {
 129         char *name;
 130         unsigned int address;
 131 };
 132
 133 struct rsi_mgmt_desc {
 134         __le16 len_qno;
 135         u8 frame_type;
 136         u8 misc_flags;
 137         u8 xtend_desc_size;
 138         u8 header_len;
 139         __le16 frame_info;
 140         __le16 rate_info;
 141         __le16 bbp_info;
 142         __le16 seq_ctrl;
 143         u8 reserved2;
 144         u8 sta_id;
 145 } __packed;
 146
 147 struct rsi_data_desc {
 148         __le16 len_qno;
 149         u8 cfm_frame_type;
 150         u8 misc_flags;
 151         u8 xtend_desc_size;
 152         u8 header_len;
 153         __le16 frame_info;
 154         __le16 rate_info;
 155         __le16 bbp_info;
 156         __le16 mac_flags;
 157         u8 qid_tid;
 158         u8 sta_id;
 159 } __packed;
 160
 161 struct rsi_bt_desc {
 162         __le16 len_qno;
 163         __le16 reserved1;
 164         __le32 reserved2;
 165         __le32 reserved3;
 166         __le16 reserved4;
 167         __le16 bt_pkt_type;
 168 } __packed;
 169
 170 int rsi_hal_device_init(struct rsi_hw *adapter);
 171 int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
 172 int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
 173 int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
 174 int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
 175 int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
 176
 177 #endif