| blob | f868fb822a303ac6f62eed632ae066865d5b7b8f |
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/delay.h>
38 #include <linux/netdevice.h>
39 #include <linux/interrupt.h>
40 #include <linux/tcp.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/mii.h>
46 #include <linux/ethtool.h>
47 #include <linux/if_vlan.h>
48 #include <linux/cpu.h>
49 #include <linux/smp.h>
50 #include <linux/pm_qos.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/aer.h>
53 #include <linux/prefetch.h>
77 };
80 u32 ofs;
82 };
98 /* General Registers */
103 /* Interrupt Registers */
106 /* Rx Registers */
122 /* Tx Registers */
139 /* List Terminator */
141 };
143 /*
144 * e1000_regdump - register printout routine
145 */
147 {
169 }
173 }
175 /*
176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
177 */
179 {
186 __le64 a;
187 __le64 b;
194 __le64 a;
195 __le64 b;
196 __le64 c;
197 __le64 d;
199 u32 staterr;
205 /* Print netdevice Info */
212 }
214 /* Print Registers */
220 }
222 /* Print Tx Ring Summary */
236 /* Print Tx Ring */
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
283 else
288 i,
300 }
302 /* Print Rx Ring Summary */
303 rx_ring_summary:
309 /* Print Rx Ring */
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
348 staterr =
355 else
359 /* Descriptor Done */
382 }
383 }
387 /* Extended Receive Descriptor (Read) Format
388 *
389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
394 */
395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
423 else
427 /* Descriptor Done */
445 phys_to_virt
449 }
450 }
451 }
452 }
454 /**
455 * e1000_desc_unused - calculate if we have unused descriptors
456 **/
458 {
463 }
465 /**
466 * e1000_receive_skb - helper function to handle Rx indications
467 * @adapter: board private structure
468 * @status: descriptor status field as written by hardware
469 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
470 * @skb: pointer to sk_buff to be indicated to stack
471 **/
475 {
483 }
485 /**
486 * e1000_rx_checksum - Receive Checksum Offload
487 * @adapter: board private structure
488 * @status_err: receive descriptor status and error fields
489 * @csum: receive descriptor csum field
490 * @sk_buff: socket buffer with received data
491 **/
494 {
500 /* Rx checksum disabled */
504 /* Ignore Checksum bit is set */
508 /* TCP/UDP checksum error bit is set */
510 /* let the stack verify checksum errors */
513 }
515 /* TCP/UDP Checksum has not been calculated */
519 /* It must be a TCP or UDP packet with a valid checksum */
521 /* TCP checksum is good */
524 /*
525 * IP fragment with UDP payload
526 * Hardware complements the payload checksum, so we undo it
527 * and then put the value in host order for further stack use.
528 */
532 }
534 }
536 /**
537 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
538 * @hw: pointer to the HW structure
539 * @tail: address of tail descriptor register
540 * @i: value to write to tail descriptor register
541 *
542 * When updating the tail register, the ME could be accessing Host CSR
543 * registers at the same time. Normally, this is handled in h/w by an
544 * arbiter but on some parts there is a bug that acknowledges Host accesses
545 * later than it should which could result in the descriptor register to
546 * have an incorrect value. Workaround this by checking the FWSM register
547 * which has bit 24 set while ME is accessing Host CSR registers, wait
548 * if it is set and try again a number of times.
549 **/
552 {
565 }
568 {
577 }
578 }
581 {
590 }
591 }
593 /**
594 * e1000_alloc_rx_buffers - Replace used receive buffers
595 * @rx_ring: Rx descriptor ring
596 **/
599 {
617 }
621 /* Better luck next round */
624 }
627 map_skb:
630 DMA_FROM_DEVICE);
635 }
641 /*
642 * Force memory writes to complete before letting h/w
643 * know there are new descriptors to fetch. (Only
644 * applicable for weak-ordered memory model archs,
645 * such as IA-64).
646 */
650 else
652 }
653 i++;
657 }
660 }
662 /**
663 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
664 * @rx_ring: Rx descriptor ring
665 **/
668 {
687 /* all unused desc entries get hw null ptr */
691 }
697 }
701 DMA_FROM_DEVICE);
708 }
709 }
710 /*
711 * Refresh the desc even if buffer_addrs
712 * didn't change because each write-back
713 * erases this info.
714 */
717 }
721 gfp);
726 }
731 DMA_FROM_DEVICE);
735 /* cleanup skb */
739 }
744 /*
745 * Force memory writes to complete before letting h/w
746 * know there are new descriptors to fetch. (Only
747 * applicable for weak-ordered memory model archs,
748 * such as IA-64).
749 */
753 else
755 }
757 i++;
761 }
763 no_buffers:
765 }
767 /**
768 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
769 * @rx_ring: Rx descriptor ring
770 * @cleaned_count: number of buffers to allocate this pass
771 **/
775 {
793 }
797 /* Better luck next round */
800 }
803 check_page:
804 /* allocate a new page if necessary */
810 }
811 }
816 PAGE_SIZE,
817 DMA_FROM_DEVICE);
825 }
832 /* Force memory writes to complete before letting h/w
833 * know there are new descriptors to fetch. (Only
834 * applicable for weak-ordered memory model archs,
835 * such as IA-64). */
839 else
841 }
842 }
846 {
849 }
851 /**
852 * e1000_clean_rx_irq - Send received data up the network stack
853 * @rx_ring: Rx descriptor ring
854 *
855 * the return value indicates whether actual cleaning was done, there
856 * is no guarantee that everything was cleaned
857 **/
860 {
891 i++;
900 cleaned_count++;
904 DMA_FROM_DEVICE);
909 /*
910 * !EOP means multiple descriptors were used to store a single
911 * packet, if that's the case we need to toss it. In fact, we
912 * need to toss every packet with the EOP bit clear and the
913 * next frame that _does_ have the EOP bit set, as it is by
914 * definition only a frame fragment
915 */
920 /* All receives must fit into a single buffer */
922 /* recycle */
927 }
930 /* recycle */
933 }
935 /* adjust length to remove Ethernet CRC */
940 total_rx_packets++;
942 /*
943 * code added for copybreak, this should improve
944 * performance for small packets with large amounts
945 * of reassembly being done in the stack
946 */
954 NET_IP_ALIGN),
956 NET_IP_ALIGN));
957 /* save the skb in buffer_info as good */
960 }
961 /* else just continue with the old one */
962 }
963 /* end copybreak code */
966 /* Receive Checksum Offload */
975 next_desc:
978 /* return some buffers to hardware, one at a time is too slow */
981 GFP_ATOMIC);
983 }
985 /* use prefetched values */
990 }
1000 }
1004 {
1011 else
1015 }
1019 }
1021 }
1024 {
1027 print_hang_task);
1035 u16 pci_status;
1042 /* May be block on write-back, flush and detect again
1043 * flush pending descriptor writebacks to memory
1044 */
1046 /* execute the writes immediately */
1050 }
1051 /* Real hang detected */
1061 /* detected Hardware unit hang */
1082 eop,
1083 jiffies,
1086 phy_status,
1087 phy_1000t_status,
1088 phy_ext_status,
1089 pci_status);
1090 }
1092 /**
1093 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1094 * @tx_ring: Tx descriptor ring
1095 *
1096 * the return value indicates whether actual cleaning was done, there
1097 * is no guarantee that everything was cleaned
1098 **/
1100 {
1129 pkts_compl++;
1130 }
1131 }
1136 i++;
1139 }
1145 }
1151 #define TX_WAKE_THRESHOLD 32
1154 /* Make sure that anybody stopping the queue after this
1155 * sees the new next_to_clean.
1156 */
1163 }
1164 }
1167 /*
1168 * Detect a transmit hang in hardware, this serializes the
1169 * check with the clearing of time_stamp and movement of i
1170 */
1177 else
1179 }
1183 }
1185 /**
1186 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1187 * @rx_ring: Rx descriptor ring
1188 *
1189 * the return value indicates whether actual cleaning was done, there
1190 * is no guarantee that everything was cleaned
1191 **/
1194 {
1221 /* in the packet split case this is header only */
1224 i++;
1233 cleaned_count++;
1238 /* see !EOP comment in other Rx routine */
1248 }
1253 }
1261 }
1263 /* Good Receive */
1266 {
1267 /*
1268 * this looks ugly, but it seems compiler issues make
1269 * it more efficient than reusing j
1270 */
1273 /*
1274 * page alloc/put takes too long and effects small
1275 * packet throughput, so unsplit small packets and
1276 * save the alloc/put only valid in softirq (napi)
1277 * context to call kmap_*
1278 */
1285 /*
1286 * there is no documentation about how to call
1287 * kmap_atomic, so we can't hold the mapping
1288 * very long
1289 */
1292 PAGE_SIZE,
1293 DMA_FROM_DEVICE);
1295 KM_SKB_DATA_SOFTIRQ);
1300 PAGE_SIZE,
1301 DMA_FROM_DEVICE);
1303 /* remove the CRC */
1310 }
1319 DMA_FROM_DEVICE);
1326 }
1328 /* strip the ethernet crc, problem is we're using pages now so
1329 * this whole operation can get a little cpu intensive
1330 */
1334 copydone:
1336 total_rx_packets++;
1350 next_desc:
1354 /* return some buffers to hardware, one at a time is too slow */
1357 GFP_ATOMIC);
1359 }
1361 /* use prefetched values */
1366 }
1376 }
1378 /**
1379 * e1000_consume_page - helper function
1380 **/
1382 u16 length)
1383 {
1388 }
1390 /**
1391 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1392 * @adapter: board private structure
1393 *
1394 * the return value indicates whether actual cleaning was done, there
1395 * is no guarantee that everything was cleaned
1396 **/
1399 {
1436 cleaned_count++;
1438 DMA_FROM_DEVICE);
1443 /* errors is only valid for DD + EOP descriptors */
1446 /* recycle both page and skb */
1448 /* an error means any chain goes out the window too */
1453 }
1455 #define rxtop (rx_ring->rx_skb_top)
1457 /* this descriptor is only the beginning (or middle) */
1459 /* this is the beginning of a chain */
1464 /* this is the middle of a chain */
1468 /* re-use the skb, only consumed the page */
1470 }
1475 /* end of the chain */
1479 /* re-use the current skb, we only consumed the
1480 * page */
1486 /* no chain, got EOP, this buf is the packet
1487 * copybreak to save the put_page/alloc_page */
1492 KM_SKB_DATA_SOFTIRQ);
1494 length);
1496 KM_SKB_DATA_SOFTIRQ);
1497 /* re-use the page, so don't erase
1498 * buffer_info->page */
1503 length);
1505 length);
1506 }
1507 }
1508 }
1510 /* Receive Checksum Offload XXX recompute due to CRC strip? */
1516 /* probably a little skewed due to removing CRC */
1518 total_rx_packets++;
1520 /* eth type trans needs skb->data to point to something */
1525 }
1530 next_desc:
1533 /* return some buffers to hardware, one at a time is too slow */
1536 GFP_ATOMIC);
1538 }
1540 /* use prefetched values */
1545 }
1555 }
1557 /**
1558 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1559 * @rx_ring: Rx descriptor ring
1560 **/
1562 {
1569 /* Free all the Rx ring sk_buffs */
1576 DMA_FROM_DEVICE);
1579 PAGE_SIZE,
1580 DMA_FROM_DEVICE);
1584 DMA_FROM_DEVICE);
1586 }
1591 }
1596 }
1603 DMA_FROM_DEVICE);
1607 }
1608 }
1610 /* there also may be some cached data from a chained receive */
1614 }
1616 /* Zero out the descriptor ring */
1625 }
1628 {
1636 }
1638 /**
1639 * e1000_intr_msi - Interrupt Handler
1640 * @irq: interrupt number
1641 * @data: pointer to a network interface device structure
1642 **/
1644 {
1650 /*
1651 * read ICR disables interrupts using IAM
1652 */
1656 /*
1657 * ICH8 workaround-- Call gig speed drop workaround on cable
1658 * disconnect (LSC) before accessing any PHY registers
1659 */
1664 /*
1665 * 80003ES2LAN workaround-- For packet buffer work-around on
1666 * link down event; disable receives here in the ISR and reset
1667 * adapter in watchdog
1668 */
1671 /* disable receives */
1675 }
1676 /* guard against interrupt when we're going down */
1679 }
1687 }
1690 }
1692 /**
1693 * e1000_intr - Interrupt Handler
1694 * @irq: interrupt number
1695 * @data: pointer to a network interface device structure
1696 **/
1698 {
1707 /*
1708 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1709 * not set, then the adapter didn't send an interrupt
1710 */
1714 /*
1715 * Interrupt Auto-Mask...upon reading ICR,
1716 * interrupts are masked. No need for the
1717 * IMC write
1718 */
1722 /*
1723 * ICH8 workaround-- Call gig speed drop workaround on cable
1724 * disconnect (LSC) before accessing any PHY registers
1725 */
1730 /*
1731 * 80003ES2LAN workaround--
1732 * For packet buffer work-around on link down event;
1733 * disable receives here in the ISR and
1734 * reset adapter in watchdog
1735 */
1738 /* disable receives */
1742 }
1743 /* guard against interrupt when we're going down */
1746 }
1754 }
1757 }
1760 {
1770 }
1779 /* guard against interrupt when we're going down */
1782 }
1784 no_link_interrupt:
1789 }
1793 {
1804 /* Ring was not completely cleaned, so fire another interrupt */
1808 }
1811 {
1816 /* Write the ITR value calculated at the end of the
1817 * previous interrupt.
1818 */
1823 }
1829 }
1831 }
1833 /**
1834 * e1000_configure_msix - Configure MSI-X hardware
1835 *
1836 * e1000_configure_msix sets up the hardware to properly
1837 * generate MSI-X interrupts.
1838 **/
1840 {
1849 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1854 }
1856 #define E1000_IVAR_INT_ALLOC_VALID 0x8
1857 /* Configure Rx vector */
1863 else
1867 /* Configure Tx vector */
1869 vector++;
1873 else
1878 /* set vector for Other Causes, e.g. link changes */
1879 vector++;
1884 else
1887 /* Cause Tx interrupts on every write back */
1892 /* enable MSI-X PBA support */
1896 /* Auto-Mask Other interrupts upon ICR read */
1897 #define E1000_EIAC_MASK_82574 0x01F00000
1902 }
1905 {
1913 }
1914 }
1916 /**
1917 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1918 *
1919 * Attempt to configure interrupts using the best available
1920 * capabilities of the hardware and kernel.
1921 **/
1923 {
1933 GFP_KERNEL);
1943 }
1944 /* MSI-X failed, so fall through and try MSI */
1947 }
1949 /* Fall through */
1956 }
1957 /* Fall through */
1959 /* Don't do anything; this is the system default */
1961 }
1963 /* store the number of vectors being used */
1965 }
1967 /**
1968 * e1000_request_msix - Initialize MSI-X interrupts
1969 *
1970 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1971 * kernel.
1972 **/
1974 {
1982 else
1986 netdev);
1992 vector++;
1998 else
2002 netdev);
2008 vector++;
2017 out:
2019 }
2021 /**
2022 * e1000_request_irq - initialize interrupts
2023 *
2024 * Attempts to configure interrupts using the best available
2025 * capabilities of the hardware and kernel.
2026 **/
2028 {
2036 /* fall back to MSI */
2040 }
2047 /* fall back to legacy interrupt */
2050 }
2058 }
2061 {
2068 vector++;
2071 vector++;
2073 /* Other Causes interrupt vector */
2076 }
2079 }
2081 /**
2082 * e1000_irq_disable - Mask off interrupt generation on the NIC
2083 **/
2085 {
2099 }
2100 }
2102 /**
2103 * e1000_irq_enable - Enable default interrupt generation settings
2104 **/
2106 {
2114 }
2116 }
2118 /**
2119 * e1000e_get_hw_control - get control of the h/w from f/w
2120 * @adapter: address of board private structure
2121 *
2122 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2123 * For ASF and Pass Through versions of f/w this means that
2124 * the driver is loaded. For AMT version (only with 82573)
2125 * of the f/w this means that the network i/f is open.
2126 **/
2128 {
2130 u32 ctrl_ext;
2131 u32 swsm;
2133 /* Let firmware know the driver has taken over */
2140 }
2141 }
2143 /**
2144 * e1000e_release_hw_control - release control of the h/w to f/w
2145 * @adapter: address of board private structure
2146 *
2147 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2148 * For ASF and Pass Through versions of f/w this means that the
2149 * driver is no longer loaded. For AMT version (only with 82573) i
2150 * of the f/w this means that the network i/f is closed.
2151 *
2152 **/
2154 {
2156 u32 ctrl_ext;
2157 u32 swsm;
2159 /* Let firmware taken over control of h/w */
2166 }
2167 }
2169 /**
2170 * @e1000_alloc_ring - allocate memory for a ring structure
2171 **/
2174 {
2178 GFP_KERNEL);
2183 }
2185 /**
2186 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2187 * @tx_ring: Tx descriptor ring
2188 *
2189 * Return 0 on success, negative on failure
2190 **/
2192 {
2201 /* round up to nearest 4K */
2213 err:
2217 }
2219 /**
2220 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2221 * @rx_ring: Rx descriptor ring
2222 *
2223 * Returns 0 on success, negative on failure
2224 **/
2226 {
2240 GFP_KERNEL);
2243 }
2247 /* Round up to nearest 4K */
2261 err_pages:
2265 }
2266 err:
2270 }
2272 /**
2273 * e1000_clean_tx_ring - Free Tx Buffers
2274 * @tx_ring: Tx descriptor ring
2275 **/
2277 {
2286 }
2299 }
2301 /**
2302 * e1000e_free_tx_resources - Free Tx Resources per Queue
2303 * @tx_ring: Tx descriptor ring
2304 *
2305 * Free all transmit software resources
2306 **/
2308 {
2320 }
2322 /**
2323 * e1000e_free_rx_resources - Free Rx Resources
2324 * @rx_ring: Rx descriptor ring
2325 *
2326 * Free all receive software resources
2327 **/
2329 {
2345 }
2347 /**
2348 * e1000_update_itr - update the dynamic ITR value based on statistics
2349 * @adapter: pointer to adapter
2350 * @itr_setting: current adapter->itr
2351 * @packets: the number of packets during this measurement interval
2352 * @bytes: the number of bytes during this measurement interval
2353 *
2354 * Stores a new ITR value based on packets and byte
2355 * counts during the last interrupt. The advantage of per interrupt
2356 * computation is faster updates and more accurate ITR for the current
2357 * traffic pattern. Constants in this function were computed
2358 * based on theoretical maximum wire speed and thresholds were set based
2359 * on testing data as well as attempting to minimize response time
2360 * while increasing bulk throughput. This functionality is controlled
2361 * by the InterruptThrottleRate module parameter.
2362 **/
2366 {
2374 /* handle TSO and jumbo frames */
2382 /* this if handles the TSO accounting */
2393 }
2401 }
2403 }
2405 update_itr_done:
2407 }
2410 {
2412 u16 current_itr;
2415 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2420 }
2425 }
2431 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2439 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2446 /* counts and packets in update_itr are dependent on these numbers */
2458 }
2460 set_itr_now:
2462 /*
2463 * this attempts to bias the interrupt rate towards Bulk
2464 * by adding intermediate steps when interrupt rate is
2465 * increasing
2466 */
2469 new_itr;
2474 else
2477 else
2479 }
2480 }
2482 /**
2483 * e1000_alloc_queues - Allocate memory for all rings
2484 * @adapter: board private structure to initialize
2485 **/
2487 {
2503 err:
2508 }
2510 /**
2511 * e1000_clean - NAPI Rx polling callback
2512 * @napi: struct associated with this polling callback
2513 * @budget: amount of packets driver is allowed to process this poll
2514 **/
2516 {
2530 clean_rx:
2536 /* If budget not fully consumed, exit the polling mode */
2544 else
2546 }
2547 }
2550 }
2553 {
2558 /* don't update vlan cookie if already programmed */
2560 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2564 /* add VID to filter table */
2570 }
2575 }
2578 {
2584 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2586 /* release control to f/w */
2589 }
2591 /* remove VID from filter table */
2597 }
2602 }
2604 /**
2605 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2606 * @adapter: board private structure to initialize
2607 **/
2609 {
2612 u32 rctl;
2615 /* disable VLAN receive filtering */
2623 }
2624 }
2625 }
2627 /**
2628 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2629 * @adapter: board private structure to initialize
2630 **/
2632 {
2634 u32 rctl;
2637 /* enable VLAN receive filtering */
2642 }
2643 }
2645 /**
2646 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2647 * @adapter: board private structure to initialize
2648 **/
2650 {
2652 u32 ctrl;
2654 /* disable VLAN tag insert/strip */
2658 }
2660 /**
2661 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2662 * @adapter: board private structure to initialize
2663 **/
2665 {
2667 u32 ctrl;
2669 /* enable VLAN tag insert/strip */
2673 }
2676 {
2682 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2685 }
2689 }
2692 {
2693 u16 vid;
2699 }
2702 {
2711 /*
2712 * enable receiving management packets to the host. this will probably
2713 * generate destination unreachable messages from the host OS, but
2714 * the packets will be handled on SMBUS
2715 */
2725 /*
2726 * Check if IPMI pass-through decision filter already exists;
2727 * if so, enable it.
2728 */
2732 /* Ignore filters with anything other than IPMI ports */
2736 /* Enable this decision filter in MANC2H */
2741 }
2746 /* Create new decision filter in an empty filter */
2750 E1000_MDEF_PORT_664));
2752 j++;
2754 }
2759 }
2763 }
2765 /**
2766 * e1000_configure_tx - Configure Transmit Unit after Reset
2767 * @adapter: board private structure
2768 *
2769 * Configure the Tx unit of the MAC after a reset.
2770 **/
2772 {
2775 u64 tdba;
2778 /* Setup the HW Tx Head and Tail descriptor pointers */
2789 /* Set the Tx Interrupt Delay register */
2791 /* Tx irq moderation */
2797 E1000_TXDCTL_WTHRESH);
2798 /*
2799 * set up some performance related parameters to encourage the
2800 * hardware to use the bus more efficiently in bursts, depends
2801 * on the tx_int_delay to be enabled,
2802 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2803 * hthresh = 1 ==> prefetch when one or more available
2804 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2805 * BEWARE: this seems to work but should be considered first if
2806 * there are Tx hangs or other Tx related bugs
2807 */
2810 }
2811 /* erratum work around: set txdctl the same for both queues */
2816 /*
2817 * set the speed mode bit, we'll clear it if we're not at
2818 * gigabit link later
2819 */
2820 #define SPEED_MODE_BIT (1 << 21)
2823 }
2825 /* errata: program both queues to unweighted RR */
2833 }
2835 /* Setup Transmit Descriptor Settings for eop descriptor */
2838 /* only set IDE if we are delaying interrupts using the timers */
2842 /* enable Report Status bit */
2846 }
2848 /**
2849 * e1000_setup_rctl - configure the receive control registers
2850 * @adapter: Board private structure
2851 **/
2852 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2853 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2855 {
2860 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2862 s32 ret_val;
2866 else
2871 }
2873 /* Program MC offset vector base */
2880 /* Do not Store bad packets */
2883 /* Enable Long Packet receive */
2886 else
2889 /* Some systems expect that the CRC is included in SMBUS traffic. The
2890 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2891 * host memory when this is enabled
2892 */
2896 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2898 u16 phy_data;
2911 }
2913 /* Setup buffer sizes */
2931 }
2933 /* Enable Extended Status in all Receive Descriptors */
2937 /*
2938 * 82571 and greater support packet-split where the protocol
2939 * header is placed in skb->data and the packet data is
2940 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2941 * In the case of a non-split, skb->data is linearly filled,
2942 * followed by the page buffers. Therefore, skb->data is
2943 * sized to hold the largest protocol header.
2944 *
2945 * allocations using alloc_page take too long for regular MTU
2946 * so only enable packet split for jumbo frames
2947 *
2948 * Using pages when the page size is greater than 16k wastes
2949 * a lot of memory, since we allocate 3 pages at all times
2950 * per packet.
2951 */
2955 else
2961 /*
2962 * disable packet split support for IPv6 extension headers,
2963 * because some malformed IPv6 headers can hang the Rx
2964 */
2966 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2968 /* Enable Packet split descriptors */
2972 E1000_PSRCTL_BSIZE0_SHIFT;
2977 E1000_PSRCTL_BSIZE3_SHIFT;
2980 E1000_PSRCTL_BSIZE2_SHIFT;
2983 E1000_PSRCTL_BSIZE1_SHIFT;
2985 }
2988 }
2992 /* just started the receive unit, no need to restart */
2994 }
2996 /**
2997 * e1000_configure_rx - Configure Receive Unit after Reset
2998 * @adapter: board private structure
2999 *
3000 * Configure the Rx unit of the MAC after a reset.
3001 **/
3003 {
3006 u64 rdba;
3010 /* this is a 32 byte descriptor */
3023 }
3025 /* disable receives while setting up the descriptors */
3033 /*
3034 * set the writeback threshold (only takes effect if the RDTR
3035 * is set). set GRAN=1 and write back up to 0x4 worth, and
3036 * enable prefetching of 0x20 Rx descriptors
3037 * granularity = 01
3038 * wthresh = 04,
3039 * hthresh = 04,
3040 * pthresh = 0x20
3041 */
3045 /*
3046 * override the delay timers for enabling bursting, only if
3047 * the value was not set by the user via module options
3048 */
3053 }
3055 /* set the Receive Delay Timer Register */
3058 /* irq moderation */
3064 /* Auto-Mask interrupts upon ICR access */
3070 /*
3071 * Setup the HW Rx Head and Tail Descriptor Pointers and
3072 * the Base and Length of the Rx Descriptor Ring
3073 */
3083 /* Enable Receive Checksum Offload for TCP and UDP */
3088 /*
3089 * IPv4 payload checksum for UDP fragments must be
3090 * used in conjunction with packet-split.
3091 */
3096 /* no need to clear IPPCSE as it defaults to 0 */
3097 }
3101 /*
3102 * With jumbo frames, excessive C-state transition
3103 * latencies result in dropped transactions.
3104 */
3111 PM_QOS_DEFAULT_VALUE);
3112 }
3113 }
3115 /* Enable Receives */
3117 }
3119 /**
3120 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3121 * @netdev: network interface device structure
3122 *
3123 * Writes multicast address list to the MTA hash table.
3124 * Returns: -ENOMEM on failure
3125 * 0 on no addresses written
3126 * X on writing X addresses to MTA
3127 */
3129 {
3137 /* nothing to program, so clear mc list */
3140 }
3146 /* update_mc_addr_list expects a packed array of only addresses. */
3155 }
3157 /**
3158 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3159 * @netdev: network interface device structure
3160 *
3161 * Writes unicast address list to the RAR table.
3162 * Returns: -ENOMEM on failure/insufficient address space
3163 * 0 on no addresses written
3164 * X on writing X addresses to the RAR table
3165 **/
3167 {
3173 /* save a rar entry for our hardware address */
3174 rar_entries--;
3176 /* save a rar entry for the LAA workaround */
3178 rar_entries--;
3180 /* return ENOMEM indicating insufficient memory for addresses */
3187 /*
3188 * write the addresses in reverse order to avoid write
3189 * combining
3190 */
3195 count++;
3196 }
3197 }
3199 /* zero out the remaining RAR entries not used above */
3203 }
3207 }
3209 /**
3210 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3211 * @netdev: network interface device structure
3212 *
3213 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3214 * address list or the network interface flags are updated. This routine is
3215 * responsible for configuring the hardware for proper unicast, multicast,
3216 * promiscuous mode, and all-multi behavior.
3217 **/
3219 {
3222 u32 rctl;
3224 /* Check for Promiscuous and All Multicast modes */
3227 /* clear the affected bits */
3232 /* Do not hardware filter VLANs in promisc mode */
3239 /*
3240 * Write addresses to the MTA, if the attempt fails
3241 * then we should just turn on promiscuous mode so
3242 * that we can at least receive multicast traffic
3243 */
3247 }
3249 /*
3250 * Write addresses to available RAR registers, if there is not
3251 * sufficient space to store all the addresses then enable
3252 * unicast promiscuous mode
3253 */
3257 }
3263 else
3265 }
3268 {
3275 };
3277 /* Fill out hash function seed */
3281 /* Direct all traffic to queue 0 */
3285 /*
3286 * Disable raw packet checksumming so that RSS hash is placed in
3287 * descriptor on writeback.
3288 */
3295 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3296 E1000_MRQC_RSS_FIELD_IPV6 |
3297 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3298 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3301 }
3303 /**
3304 * e1000_configure - configure the hardware for Rx and Tx
3305 * @adapter: private board structure
3306 **/
3308 {
3323 }
3325 /**
3326 * e1000e_power_up_phy - restore link in case the phy was powered down
3327 * @adapter: address of board private structure
3328 *
3329 * The phy may be powered down to save power and turn off link when the
3330 * driver is unloaded and wake on lan is not enabled (among others)
3331 * *** this routine MUST be followed by a call to e1000e_reset ***
3332 **/
3334 {
3339 }
3341 /**
3342 * e1000_power_down_phy - Power down the PHY
3343 *
3344 * Power down the PHY so no link is implied when interface is down.
3345 * The PHY cannot be powered down if management or WoL is active.
3346 */
3348 {
3349 /* WoL is enabled */
3355 }
3357 /**
3358 * e1000e_reset - bring the hardware into a known good state
3359 *
3360 * This function boots the hardware and enables some settings that
3361 * require a configuration cycle of the hardware - those cannot be
3362 * set/changed during runtime. After reset the device needs to be
3363 * properly configured for Rx, Tx etc.
3364 */
3366 {
3372 u16 hwm;
3374 /* reset Packet Buffer Allocation to default */
3378 /*
3379 * To maintain wire speed transmits, the Tx FIFO should be
3380 * large enough to accommodate two full transmit packets,
3381 * rounded up to the next 1KB and expressed in KB. Likewise,
3382 * the Rx FIFO should be large enough to accommodate at least
3383 * one full receive packet and is similarly rounded up and
3384 * expressed in KB.
3385 */
3387 /* upper 16 bits has Tx packet buffer allocation size in KB */
3389 /* lower 16 bits has Rx packet buffer allocation size in KB */
3391 /*
3392 * the Tx fifo also stores 16 bytes of information about the Tx
3393 * but don't include ethernet FCS because hardware appends it
3394 */
3400 /* software strips receive CRC, so leave room for it */
3405 /*
3406 * If current Tx allocation is less than the min Tx FIFO size,
3407 * and the min Tx FIFO size is less than the current Rx FIFO
3408 * allocation, take space away from current Rx allocation
3409 */
3414 /*
3415 * if short on Rx space, Rx wins and must trump Tx
3416 * adjustment or use Early Receive if available
3417 */
3420 }
3423 }
3425 /*
3426 * flow control settings
3427 *
3428 * The high water mark must be low enough to fit one full frame
3429 * (or the size used for early receive) above it in the Rx FIFO.
3430 * Set it to the lower of:
3431 * - 90% of the Rx FIFO size, and
3432 * - the full Rx FIFO size minus one full frame
3433 */
3436 else
3450 }
3451 /* fall-through */
3460 /*
3461 * Workaround PCH LOM adapter hangs with certain network
3462 * loads. If hangs persist, try disabling Tx flow control.
3463 */
3470 }
3481 }
3483 }
3485 /*
3486 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3487 * fit in receive buffer.
3488 */
3496 }
3503 }
3504 }
3506 /* Allow time for pending master requests to run */
3509 /*
3510 * For parts with AMT enabled, let the firmware know
3511 * that the network interface is in control
3512 */
3523 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3532 }
3539 /*
3540 * speed up time to link by disabling smart power down, ignore
3541 * the return value of this function because there is nothing
3542 * different we would do if it failed
3543 */
3547 }
3548 }
3551 {
3554 /* hardware has been reset, we need to reload some things */
3565 /* fire a link change interrupt to start the watchdog */
3568 else
3572 }
3575 {
3581 /* flush pending descriptor writebacks to memory */
3585 /* execute the writes immediately */
3587 }
3592 {
3597 /*
3598 * signal that we're down so the interrupt handler does not
3599 * reschedule our watchdog timer
3600 */
3603 /* disable receives in the hardware */
3607 /* flush and sleep below */
3611 /* disable transmits in the hardware */
3616 /* flush both disables and wait for them to finish */
3641 /*
3642 * TODO: for power management, we could drop the link and
3643 * pci_disable_device here.
3644 */
3645 }
3648 {
3655 }
3657 /**
3658 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3659 * @adapter: board private structure to initialize
3660 *
3661 * e1000_sw_init initializes the Adapter private data structure.
3662 * Fields are initialized based on PCI device information and
3663 * OS network device settings (MTU size).
3664 **/
3666 {
3683 /* Explicitly disable IRQ since the NIC can be in any state. */
3688 }
3690 /**
3691 * e1000_intr_msi_test - Interrupt Handler
3692 * @irq: interrupt number
3693 * @data: pointer to a network interface device structure
3694 **/
3696 {
3706 }
3709 }
3711 /**
3712 * e1000_test_msi_interrupt - Returns 0 for successful test
3713 * @adapter: board private struct
3714 *
3715 * code flow taken from tg3.c
3716 **/
3718 {
3723 /* poll_enable hasn't been called yet, so don't need disable */
3724 /* clear any pending events */
3727 /* free the real vector and request a test handler */
3731 /* Assume that the test fails, if it succeeds then the test
3732 * MSI irq handler will unset this flag */
3744 }
3750 /* fire an unusual interrupt on the test handler */
3764 }
3769 msi_test_failed:
3772 }
3774 /**
3775 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3776 * @adapter: board private struct
3777 *
3778 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3779 **/
3781 {
3783 u16 pci_cmd;
3788 /* disable SERR in case the MSI write causes a master abort */
3796 /* re-enable SERR */
3801 }
3804 }
3806 /**
3807 * e1000_open - Called when a network interface is made active
3808 * @netdev: network interface device structure
3809 *
3810 * Returns 0 on success, negative value on failure
3811 *
3812 * The open entry point is called when a network interface is made
3813 * active by the system (IFF_UP). At this point all resources needed
3814 * for transmit and receive operations are allocated, the interrupt
3815 * handler is registered with the OS, the watchdog timer is started,
3816 * and the stack is notified that the interface is ready.
3817 **/
3819 {
3825 /* disallow open during test */
3833 /* allocate transmit descriptors */
3838 /* allocate receive descriptors */
3843 /*
3844 * If AMT is enabled, let the firmware know that the network
3845 * interface is now open and reset the part to a known state.
3846 */
3850 }
3856 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3859 /* DMA latency requirement to workaround jumbo issue */
3862 PM_QOS_CPU_DMA_LATENCY,
3863 PM_QOS_DEFAULT_VALUE);
3865 /*
3866 * before we allocate an interrupt, we must be ready to handle it.
3867 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3868 * as soon as we call pci_request_irq, so we have to setup our
3869 * clean_rx handler before we do so.
3870 */
3877 /*
3878 * Work around PCIe errata with MSI interrupts causing some chipsets to
3879 * ignore e1000e MSI messages, which means we need to test our MSI
3880 * interrupt now
3881 */
3887 }
3888 }
3890 /* From here on the code is the same as e1000e_up() */
3903 /* fire a link status change interrupt to start the watchdog */
3906 else
3911 err_req_irq:
3915 err_setup_rx:
3917 err_setup_tx:
3922 }
3924 /**
3925 * e1000_close - Disables a network interface
3926 * @netdev: network interface device structure
3927 *
3928 * Returns 0, this is not allowed to fail
3929 *
3930 * The close entry point is called when an interface is de-activated
3931 * by the OS. The hardware is still under the drivers control, but
3932 * needs to be disabled. A global MAC reset is issued to stop the
3933 * hardware, and all transmit and receive resources are freed.
3934 **/
3936 {
3949 }
3955 /*
3956 * kill manageability vlan ID if supported, but not if a vlan with
3957 * the same ID is registered on the host OS (let 8021q kill it)
3958 */
3960 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
3963 /*
3964 * If AMT is enabled, let the firmware know that the network
3965 * interface is now closed
3966 */
3977 }
3978 /**
3979 * e1000_set_mac - Change the Ethernet Address of the NIC
3980 * @netdev: network interface device structure
3981 * @p: pointer to an address structure
3982 *
3983 * Returns 0 on success, negative on failure
3984 **/
3986 {
3999 /* activate the work around */
4002 /*
4003 * Hold a copy of the LAA in RAR[14] This is done so that
4004 * between the time RAR[0] gets clobbered and the time it
4005 * gets fixed (in e1000_watchdog), the actual LAA is in one
4006 * of the RARs and no incoming packets directed to this port
4007 * are dropped. Eventually the LAA will be in RAR[0] and
4008 * RAR[14]
4009 */
4013 }
4016 }
4018 /**
4019 * e1000e_update_phy_task - work thread to update phy
4020 * @work: pointer to our work struct
4021 *
4022 * this worker thread exists because we must acquire a
4023 * semaphore to read the phy, which we could msleep while
4024 * waiting for it, and we can't msleep in a timer.
4025 **/
4027 {
4035 }
4037 /*
4038 * Need to wait a few seconds after link up to get diagnostic information from
4039 * the phy
4040 */
4042 {
4049 }
4051 /**
4052 * e1000e_update_phy_stats - Update the PHY statistics counters
4053 * @adapter: board private structure
4054 *
4055 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4056 **/
4058 {
4060 s32 ret_val;
4061 u16 phy_data;
4067 /*
4068 * A page set is expensive so check if already on desired page.
4069 * If not, set to the page with the PHY status registers.
4070 */
4081 }
4083 /* Single Collision Count */
4089 /* Excessive Collision Count */
4095 /* Multiple Collision Count */
4101 /* Late Collision Count */
4107 /* Collision Count - also used for adaptive IFS */
4113 /* Defer Count */
4119 /* Transmit with no CRS */
4125 release:
4127 }
4129 /**
4130 * e1000e_update_stats - Update the board statistics counters
4131 * @adapter: board private structure
4132 **/
4134 {
4139 /*
4140 * Prevent stats update while adapter is being reset, or if the pci
4141 * connection is down.
4142 */
4158 /* Half-duplex statistics */
4174 }
4176 }
4191 /* used for adaptive IFS */
4202 /* Fill out the OS statistics structure */
4206 /* Rx Errors */
4208 /*
4209 * RLEC on some newer hardware can be incorrect so build
4210 * our own version based on RUC and ROC
4211 */
4222 /* Tx Errors */
4229 /* Tx Dropped needs to be maintained elsewhere */
4231 /* Management Stats */
4235 }
4237 /**
4238 * e1000_phy_read_status - Update the PHY register status snapshot
4239 * @adapter: board private structure
4240 **/
4242 {
4261 /*
4262 * Do not read PHY registers if link is not up
4263 * Set values to typical power-on defaults
4264 */
4268 BMSR_ERCAP);
4276 }
4277 }
4280 {
4284 /* Link status message must follow this format for user tools */
4292 }
4295 {
4300 /*
4301 * get_link_status is set on LSC (link status) interrupt or
4302 * Rx sequence error interrupt. get_link_status will stay
4303 * false until the check_for_link establishes link
4304 * for copper adapters ONLY
4305 */
4313 }
4326 }
4330 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
4332 }
4335 }
4338 {
4339 /* make sure the receive unit is started */
4346 }
4347 }
4350 {
4353 /*
4354 * With 82574 controllers, PHY needs to be checked periodically
4355 * for hung state and reset, if two calls return true
4356 */
4359 else
4365 }
4366 }
4368 /**
4369 * e1000_watchdog - Timer Call-back
4370 * @data: pointer to adapter cast into an unsigned long
4371 **/
4373 {
4376 /* Do the rest outside of interrupt context */
4379 /* TODO: make this use queue_delayed_work() */
4380 }
4383 {
4398 /* Cancel scheduled suspend requests. */
4403 }
4413 /* Cancel scheduled suspend requests. */
4416 /* update snapshot of PHY registers on LSC */
4422 /*
4423 * On supported PHYs, check for duplex mismatch only
4424 * if link has autonegotiated at 10/100 half
4425 */
4432 u16 autoneg_exp;
4437 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
4438 }
4440 /* adjust timeout factor according to speed/duplex */
4451 }
4453 /*
4454 * workaround: re-program speed mode bit after
4455 * link-up event
4456 */
4459 u32 tarc0;
4463 }
4465 /*
4466 * disable TSO for pcie and 10/100 speeds, to avoid
4467 * some hardware issues
4468 */
4482 /* oops */
4484 }
4485 }
4487 /*
4488 * enable transmits in the hardware, need to do this
4489 * after setting TARC(0)
4490 */
4495 /*
4496 * Perform any post-link-up configuration before
4497 * reporting link up.
4498 */
4507 }
4512 /* Link status message must follow this format */
4522 else
4524 LINK_TIMEOUT);
4525 }
4526 }
4528 link_up:
4547 /*
4548 * We've lost link, so the controller stops DMA,
4549 * but we've got queued Tx work that's never going
4550 * to get done, so reset controller to flush Tx.
4551 * (Do the reset outside of interrupt context).
4552 */
4554 /* return immediately since reset is imminent */
4556 }
4558 /* Simple mode for Interrupt Throttle Rate (ITR) */
4560 /*
4561 * Symmetric Tx/Rx gets a reduced ITR=2000;
4562 * Total asymmetrical Tx or Rx gets ITR=8000;
4563 * everyone else is between 2000-8000.
4564 */
4572 }
4574 /* Cause software interrupt to ensure Rx ring is cleaned */
4577 else
4580 /* flush pending descriptors to memory before detecting Tx hang */
4583 /* Force detection of hung controller every watchdog period */
4586 /*
4587 * With 82571 controllers, LAA may be overwritten due to controller
4588 * reset from the other port. Set the appropriate LAA in RAR[0]
4589 */
4596 /* Reset the timer */
4600 }
4602 #define E1000_TX_FLAGS_CSUM 0x00000001
4603 #define E1000_TX_FLAGS_VLAN 0x00000002
4604 #define E1000_TX_FLAGS_TSO 0x00000004
4605 #define E1000_TX_FLAGS_IPV4 0x00000008
4606 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4607 #define E1000_TX_FLAGS_VLAN_SHIFT 16
4610 {
4626 }
4644 }
4671 i++;
4677 }
4680 {
4685 u8 css;
4687 __be16 protocol;
4694 else
4703 /* XXX not handling all IPV6 headers */
4712 }
4731 i++;
4737 }
4739 #define E1000_MAX_PER_TXD 8192
4740 #define E1000_MAX_TXD_PWR 12
4745 {
4771 count++;
4774 i++;
4777 }
4778 }
4788 i++;
4806 count++;
4807 }
4808 }
4811 /* multiply data chunks by size of headers */
4821 dma_error:
4825 count--;
4830 i--;
4833 }
4836 }
4839 {
4848 E1000_TXD_CMD_TSE;
4853 }
4858 }
4863 }
4875 i++;
4882 /*
4883 * Force memory writes to complete before letting h/w
4884 * know there are new descriptors to fetch. (Only
4885 * applicable for weak-ordered memory model archs,
4886 * such as IA-64).
4887 */
4894 else
4897 /*
4898 * we need this if more than one processor can write to our tail
4899 * at a time, it synchronizes IO on IA64/Altix systems
4900 */
4902 }
4904 #define MINIMUM_DHCP_PACKET_SIZE 282
4907 {
4914 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4916 }
4924 {
4938 }
4941 }
4944 {
4948 /*
4949 * Herbert's original patch had:
4950 * smp_mb__after_netif_stop_queue();
4951 * but since that doesn't exist yet, just open code it.
4952 */
4955 /*
4956 * We need to check again in a case another CPU has just
4957 * made room available.
4958 */
4962 /* A reprieve! */
4966 }
4969 {
4973 }
4975 #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
4978 {
4995 }
5000 }
5003 /*
5004 * The controller does a simple calculation to
5005 * make sure there is enough room in the FIFO before
5006 * initiating the DMA for each buffer. The calc is:
5007 * 4 = ceil(buffer len/mss). To make sure we don't
5008 * overrun the FIFO, adjust the max buffer len if mss
5009 * drops.
5010 */
5012 u8 hdr_len;
5016 /*
5017 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5018 * points to just header, pull a few bytes of payload from
5019 * frags into skb->data
5020 */
5022 /*
5023 * we do this workaround for ES2LAN, but it is un-necessary,
5024 * avoiding it could save a lot of cycles
5025 */
5034 }
5036 }
5037 }
5039 /* reserve a descriptor for the offload context */
5041 count++;
5042 count++;
5049 max_txd_pwr);
5054 /*
5055 * need: count + 2 desc gap to keep tail from touching
5056 * head, otherwise try next time
5057 */
5064 }
5072 }
5079 /*
5080 * Old method was to assume IPv4 packet by default if TSO was enabled.
5081 * 82571 hardware supports TSO capabilities for IPv6 as well...
5082 * no longer assume, we must.
5083 */
5087 /* if count is 0 then mapping error has occurred */
5092 /* Make sure there is space in the ring for the next send. */
5099 }
5102 }
5104 /**
5105 * e1000_tx_timeout - Respond to a Tx Hang
5106 * @netdev: network interface device structure
5107 **/
5109 {
5112 /* Do the reset outside of interrupt context */
5115 }
5118 {
5122 /* don't run the task if already down */
5130 }
5132 }
5134 /**
5135 * e1000_get_stats64 - Get System Network Statistics
5136 * @netdev: network interface device structure
5137 * @stats: rtnl_link_stats64 pointer
5138 *
5139 * Returns the address of the device statistics structure.
5140 **/
5143 {
5149 /* Fill out the OS statistics structure */
5157 /* Rx Errors */
5159 /*
5160 * RLEC on some newer hardware can be incorrect so build
5161 * our own version based on RUC and ROC
5162 */
5173 /* Tx Errors */
5180 /* Tx Dropped needs to be maintained elsewhere */
5184 }
5186 /**
5187 * e1000_change_mtu - Change the Maximum Transfer Unit
5188 * @netdev: network interface device structure
5189 * @new_mtu: new value for maximum frame size
5190 *
5191 * Returns 0 on success, negative on failure
5192 **/
5194 {
5198 /* Jumbo frame support */
5203 }
5205 /*
5206 * IP payload checksum (enabled with jumbos/packet-split when
5207 * Rx checksum is enabled) and generation of RSS hash is
5208 * mutually exclusive in the hardware.
5209 */
5212 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5214 }
5215 }
5217 /* Supported frame sizes */
5222 }
5224 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5230 }
5232 /* 82573 Errata 17 */
5238 }
5242 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
5249 /*
5250 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5251 * means we reserve 2 more, this pushes us to allocate from the next
5252 * larger slab size.
5253 * i.e. RXBUFFER_2048 --> size-4096 slab
5254 * However with the new *_jumbo_rx* routines, jumbo receives will use
5255 * fragmented skbs
5256 */
5260 else
5263 /* adjust allocation if LPE protects us, and we aren't using SBP */
5271 else
5277 }
5281 {
5328 }
5333 }
5335 }
5338 {
5346 }
5347 }
5350 {
5356 /* copy MAC RARs to PHY RARs */
5363 }
5365 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5370 /* copy MAC MTA to PHY MTA - only needed for pchlan */
5377 }
5379 /* configure PHY Rx Control register */
5399 /* enable PHY wakeup in MAC register */
5403 /* configure and enable PHY wakeup in PHY registers */
5407 /* activate PHY wakeup */
5412 out:
5416 }
5420 {
5425 /* Runtime suspend should only enable wakeup for link changes */
5435 }
5450 /* turn on all-multi mode if wake on multicast is enabled */
5455 }
5458 /* advertise wake from D3Cold */
5459 #define E1000_CTRL_ADVD3WUC 0x00100000
5460 /* phy power management enable */
5461 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5469 e1000_media_type_internal_serdes) {
5470 /* keep the laser running in D3 */
5474 }
5479 /* Allow time for pending master requests to run */
5483 /* enable wakeup by the PHY */
5488 /* enable wakeup by the MAC */
5491 }
5495 }
5499 /* make sure adapter isn't asleep if manageability is enabled */
5507 /*
5508 * Release control of h/w to f/w. If f/w is AMT enabled, this
5509 * would have already happened in close and is redundant.
5510 */
5516 }
5519 {
5523 }
5527 }
5531 {
5535 /*
5536 * The pci-e switch on some quad port adapters will report a
5537 * correctable error when the MAC transitions from D0 to D3. To
5538 * prevent this we need to mask off the correctable errors on the
5539 * downstream port of the pci-e switch.
5540 */
5544 u16 devctl;
5555 }
5556 }
5558 #ifdef CONFIG_PCIEASPM
5560 {
5562 }
5563 #else
5565 {
5567 u16 reg16;
5569 /*
5570 * Both device and parent should have the same ASPM setting.
5571 * Disable ASPM in downstream component first and then upstream.
5572 */
5585 }
5586 #endif
5588 {
5594 }
5596 #ifdef CONFIG_PM
5598 {
5600 }
5603 {
5608 u32 err;
5626 }
5633 /* report the system wakeup cause from S3/S4 */
5635 u16 phy_data;
5646 }
5658 }
5660 }
5671 /*
5672 * If the controller has AMT, do not set DRV_LOAD until the interface
5673 * is up. For all other cases, let the f/w know that the h/w is now
5674 * under the control of the driver.
5675 */
5680 }
5682 #ifdef CONFIG_PM_SLEEP
5684 {
5694 }
5697 {
5706 }
5709 #ifdef CONFIG_PM_RUNTIME
5711 {
5720 }
5723 }
5726 {
5738 }
5741 }
5744 {
5754 }
5759 {
5766 }
5768 #ifdef CONFIG_NET_POLL_CONTROLLER
5771 {
5784 vector++;
5790 vector++;
5795 }
5798 }
5800 /*
5801 * Polling 'interrupt' - used by things like netconsole to send skbs
5802 * without having to re-enable interrupts. It's not called while
5803 * the interrupt routine is executing.
5804 */
5806 {
5823 }
5824 }
5825 #endif
5827 /**
5828 * e1000_io_error_detected - called when PCI error is detected
5829 * @pdev: Pointer to PCI device
5830 * @state: The current pci connection state
5831 *
5832 * This function is called after a PCI bus error affecting
5833 * this device has been detected.
5834 */
5836 pci_channel_state_t state)
5837 {
5850 /* Request a slot slot reset. */
5852 }
5854 /**
5855 * e1000_io_slot_reset - called after the pci bus has been reset.
5856 * @pdev: Pointer to PCI device
5857 *
5858 * Restart the card from scratch, as if from a cold-boot. Implementation
5859 * resembles the first-half of the e1000_resume routine.
5860 */
5862 {
5868 pci_ers_result_t result;
5893 }
5898 }
5900 /**
5901 * e1000_io_resume - called when traffic can start flowing again.
5902 * @pdev: Pointer to PCI device
5903 *
5904 * This callback is called when the error recovery driver tells us that
5905 * its OK to resume normal operation. Implementation resembles the
5906 * second-half of the e1000_resume routine.
5907 */
5909 {
5920 }
5921 }
5925 /*
5926 * If the controller has AMT, do not set DRV_LOAD until the interface
5927 * is up. For all other cases, let the f/w know that the h/w is now
5928 * under the control of the driver.
5929 */
5933 }
5936 {
5939 u32 ret_val;
5942 /* print bus type/speed/width info */
5944 /* bus width */
5947 /* MAC address */
5952 E1000_PBANUM_LENGTH);
5957 }
5960 {
5971 /* Deep Smart Power Down (DSPD) */
5974 }
5975 }
5978 netdev_features_t features)
5979 {
5990 /*
5991 * IP payload checksum (enabled with jumbos/packet-split when Rx
5992 * checksum is enabled) and generation of RSS hash is mutually
5993 * exclusive in the hardware.
5994 */
5997 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
5999 }
6005 else
6009 }
6025 #ifdef CONFIG_NET_POLL_CONTROLLER
6027 #endif
6029 };
6031 /**
6032 * e1000_probe - Device Initialization Routine
6033 * @pdev: PCI device information struct
6034 * @ent: entry in e1000_pci_tbl
6035 *
6036 * Returns 0 on success, negative on failure
6037 *
6038 * e1000_probe initializes an adapter identified by a pci_dev structure.
6039 * The OS initialization, configuring of the adapter private structure,
6040 * and a hardware reset occur.
6041 **/
6044 {
6083 }
6084 }
6085 }
6089 e1000e_driver_name);
6093 /* AER (Advanced Error Reporting) hooks */
6097 /* PCI config space info */
6140 }
6142 /* construct the net_device struct */
6156 /* setup adapter struct */
6177 /* Copper options */
6182 }
6187 /* Set initial default active device features */
6189 NETIF_F_HW_VLAN_RX |
6190 NETIF_F_HW_VLAN_TX |
6191 NETIF_F_TSO |
6192 NETIF_F_TSO6 |
6193 NETIF_F_RXHASH |
6194 NETIF_F_RXCSUM |
6195 NETIF_F_HW_CSUM);
6197 /* Set user-changeable features (subset of all device features) */
6204 NETIF_F_TSO |
6205 NETIF_F_TSO6 |
6206 NETIF_F_HW_CSUM);
6213 }
6218 /*
6219 * before reading the NVM, reset the controller to
6220 * put the device in a known good starting state
6221 */
6224 /*
6225 * systems with ASPM and others may see the checksum fail on the first
6226 * attempt. Let's give it a few tries
6227 */
6235 }
6236 }
6240 /* copy the MAC address */
6251 }
6267 /* Initialize link parameters. User can change them with ethtool */
6274 /* ring size defaults */
6278 /*
6279 * Initial Wake on LAN setting - If APM wake is enabled in
6280 * the EEPROM, enable the ACPI Magic Packet filter
6281 */
6283 /* APME bit in EEPROM is mapped to WUC.APME */
6294 else
6297 }
6299 /* fetch WoL from EEPROM */
6303 /*
6304 * now that we have the eeprom settings, apply the special cases
6305 * where the eeprom may be wrong or the board simply won't support
6306 * wake on lan on a particular port
6307 */
6311 /* initialize the wol settings based on the eeprom settings */
6315 /* save off EEPROM version number */
6318 /* reset the hardware with the new settings */
6321 /*
6322 * If the controller has AMT, do not set DRV_LOAD until the interface
6323 * is up. For all other cases, let the f/w know that the h/w is now
6324 * under the control of the driver.
6325 */
6334 /* carrier off reporting is important to ethtool even BEFORE open */
6344 err_register:
6347 err_eeprom:
6350 err_hw_init:
6353 err_sw_init:
6357 err_flashmap:
6359 err_ioremap:
6361 err_alloc_etherdev:
6364 err_pci_reg:
6365 err_dma:
6368 }
6370 /**
6371 * e1000_remove - Device Removal Routine
6372 * @pdev: PCI device information struct
6373 *
6374 * e1000_remove is called by the PCI subsystem to alert the driver
6375 * that it should release a PCI device. The could be caused by a
6376 * Hot-Plug event, or because the driver is going to be removed from
6377 * memory.
6378 **/
6380 {
6385 /*
6386 * The timers may be rescheduled, so explicitly disable them
6387 * from being rescheduled.
6388 */
6403 /* Don't lie to e1000_close() down the road. */
6411 /*
6412 * Release control of h/w to f/w. If f/w is AMT enabled, this
6413 * would have already happened in close and is redundant.
6414 */
6429 /* AER disable */
6433 }
6435 /* PCI Error Recovery (ERS) */
6440 };
6467 board_80003es2lan },
6469 board_80003es2lan },
6471 board_80003es2lan },
6473 board_80003es2lan },
6511 };
6514 #ifdef CONFIG_PM
6519 };
6520 #endif
6522 /* PCI Device API Driver */
6528 #ifdef CONFIG_PM
6531 },
6532 #endif
6535 };
6537 /**
6538 * e1000_init_module - Driver Registration Routine
6539 *
6540 * e1000_init_module is the first routine called when the driver is
6541 * loaded. All it does is register with the PCI subsystem.
6542 **/
6544 {
6547 e1000e_driver_version);
6552 }
6555 /**
6556 * e1000_exit_module - Driver Exit Cleanup Routine
6557 *
6558 * e1000_exit_module is called just before the driver is removed
6559 * from memory.
6560 **/
6562 {
6564 }
6573 /* e1000_main.c */