2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 * Original release 01/11/99
16 * This code is released under the GNU General Public License (GPL)
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
55 # define BREAKPOINT() asm(" int $3");
57 # define BREAKPOINT() { }
60 #define MAX_ISA_DEVICES 10
61 #define MAX_PCI_DEVICES 10
62 #define MAX_TOTAL_DEVICES 20
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/signal.h>
67 #include <linux/sched.h>
68 #include <linux/timer.h>
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/tty.h>
72 #include <linux/tty_flip.h>
73 #include <linux/serial.h>
74 #include <linux/major.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
80 #include <linux/seq_file.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/vmalloc.h>
85 #include <linux/init.h>
86 #include <linux/ioctl.h>
87 #include <linux/synclink.h>
92 #include <linux/bitops.h>
93 #include <asm/types.h>
94 #include <linux/termios.h>
95 #include <linux/workqueue.h>
96 #include <linux/hdlc.h>
97 #include <linux/dma-mapping.h>
99 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100 #define SYNCLINK_GENERIC_HDLC 1
102 #define SYNCLINK_GENERIC_HDLC 0
105 #define GET_USER(error,value,addr) error = get_user(value,addr)
106 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107 #define PUT_USER(error,value,addr) error = put_user(value,addr)
108 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
110 #include <asm/uaccess.h>
112 #define RCLRVALUE 0xffff
114 static MGSL_PARAMS default_params
= {
115 MGSL_MODE_HDLC
, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE
/* unsigned char parity; */
130 #define SHARED_MEM_ADDRESS_SIZE 0x40000
131 #define BUFFERLISTSIZE 4096
132 #define DMABUFFERSIZE 4096
133 #define MAXRXFRAMES 7
135 typedef struct _DMABUFFERENTRY
137 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
138 volatile u16 count
; /* buffer size/data count */
139 volatile u16 status
; /* Control/status field */
140 volatile u16 rcc
; /* character count field */
141 u16 reserved
; /* padding required by 16C32 */
142 u32 link
; /* 32-bit flat link to next buffer entry */
143 char *virt_addr
; /* virtual address of data buffer */
144 u32 phys_entry
; /* physical address of this buffer entry */
146 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
148 /* The queue of BH actions to be performed */
151 #define BH_TRANSMIT 2
154 #define IO_PIN_SHUTDOWN_LIMIT 100
156 struct _input_signal_events
{
167 /* transmit holding buffer definitions*/
168 #define MAX_TX_HOLDING_BUFFERS 5
169 struct tx_holding_buffer
{
171 unsigned char * buffer
;
176 * Device instance data structure
181 struct tty_port port
;
185 struct mgsl_icount icount
;
188 int x_char
; /* xon/xoff character */
189 u16 read_status_mask
;
190 u16 ignore_status_mask
;
191 unsigned char *xmit_buf
;
196 wait_queue_head_t status_event_wait_q
;
197 wait_queue_head_t event_wait_q
;
198 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
199 struct mgsl_struct
*next_device
; /* device list link */
201 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
202 struct work_struct task
; /* task structure for scheduling bh */
204 u32 EventMask
; /* event trigger mask */
205 u32 RecordedEvents
; /* pending events */
207 u32 max_frame_size
; /* as set by device config */
211 bool bh_running
; /* Protection from multiple */
215 int dcd_chkcount
; /* check counts to prevent */
216 int cts_chkcount
; /* too many IRQs if a signal */
217 int dsr_chkcount
; /* is floating */
220 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
221 u32 buffer_list_phys
;
222 dma_addr_t buffer_list_dma_addr
;
224 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
226 unsigned int current_rx_buffer
;
228 int num_tx_dma_buffers
; /* number of tx dma frames required */
229 int tx_dma_buffers_used
;
230 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
232 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer
; /* next tx dma buffer to be loaded */
235 unsigned char *intermediate_rxbuffer
;
237 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
238 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index
; /* next tx holding buffer to store user request */
240 int tx_holding_count
; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
245 bool rx_rcc_underrun
;
254 char device_name
[25]; /* device instance name */
256 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus
; /* expansion bus number (zero based) */
258 unsigned char function
; /* PCI device number */
260 unsigned int io_base
; /* base I/O address of adapter */
261 unsigned int io_addr_size
; /* size of the I/O address range */
262 bool io_addr_requested
; /* true if I/O address requested */
264 unsigned int irq_level
; /* interrupt level */
265 unsigned long irq_flags
;
266 bool irq_requested
; /* true if IRQ requested */
268 unsigned int dma_level
; /* DMA channel */
269 bool dma_requested
; /* true if dma channel requested */
275 MGSL_PARAMS params
; /* communications parameters */
277 unsigned char serial_signals
; /* current serial signal states */
279 bool irq_occurred
; /* for diagnostics use */
280 unsigned int init_error
; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
284 unsigned char* memory_base
; /* shared memory address (PCI only) */
285 u32 phys_memory_base
;
286 bool shared_mem_requested
;
288 unsigned char* lcr_base
; /* local config registers (PCI only) */
291 bool lcr_mem_requested
;
295 bool drop_rts_on_tx_done
;
297 bool loopmode_insert_requested
;
298 bool loopmode_send_done_requested
;
300 struct _input_signal_events input_signal_events
;
302 /* generic HDLC device parts */
306 #if SYNCLINK_GENERIC_HDLC
307 struct net_device
*netdev
;
311 #define MGSL_MAGIC 0x5401
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
316 #ifndef SERIAL_XMIT_SIZE
317 #define SERIAL_XMIT_SIZE 4096
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
326 #define DCPIN 2 /* Bit 1 of I/O address */
327 #define SDPIN 4 /* Bit 2 of I/O address */
329 #define DCAR 0 /* DMA command/address register */
330 #define CCAR SDPIN /* channel command/address register */
331 #define DATAREG DCPIN + SDPIN /* serial data register */
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
340 #define CMR 0x02 /* Channel mode Register */
341 #define CCSR 0x04 /* Channel Command/status Register */
342 #define CCR 0x06 /* Channel Control Register */
343 #define PSR 0x08 /* Port status Register */
344 #define PCR 0x0a /* Port Control Register */
345 #define TMDR 0x0c /* Test mode Data Register */
346 #define TMCR 0x0e /* Test mode Control Register */
347 #define CMCR 0x10 /* Clock mode Control Register */
348 #define HCR 0x12 /* Hardware Configuration Register */
349 #define IVR 0x14 /* Interrupt Vector Register */
350 #define IOCR 0x16 /* Input/Output Control Register */
351 #define ICR 0x18 /* Interrupt Control Register */
352 #define DCCR 0x1a /* Daisy Chain Control Register */
353 #define MISR 0x1c /* Misc Interrupt status Register */
354 #define SICR 0x1e /* status Interrupt Control Register */
355 #define RDR 0x20 /* Receive Data Register */
356 #define RMR 0x22 /* Receive mode Register */
357 #define RCSR 0x24 /* Receive Command/status Register */
358 #define RICR 0x26 /* Receive Interrupt Control Register */
359 #define RSR 0x28 /* Receive Sync Register */
360 #define RCLR 0x2a /* Receive count Limit Register */
361 #define RCCR 0x2c /* Receive Character count Register */
362 #define TC0R 0x2e /* Time Constant 0 Register */
363 #define TDR 0x30 /* Transmit Data Register */
364 #define TMR 0x32 /* Transmit mode Register */
365 #define TCSR 0x34 /* Transmit Command/status Register */
366 #define TICR 0x36 /* Transmit Interrupt Control Register */
367 #define TSR 0x38 /* Transmit Sync Register */
368 #define TCLR 0x3a /* Transmit count Limit Register */
369 #define TCCR 0x3c /* Transmit Character count Register */
370 #define TC1R 0x3e /* Time Constant 1 Register */
374 * MACRO DEFINITIONS FOR DMA REGISTERS
377 #define DCR 0x06 /* DMA Control Register (shared) */
378 #define DACR 0x08 /* DMA Array count Register (shared) */
379 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
385 #define TDMR 0x02 /* Transmit DMA mode Register */
386 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387 #define TBCR 0x2a /* Transmit Byte count Register */
388 #define TARL 0x2c /* Transmit Address Register (low) */
389 #define TARU 0x2e /* Transmit Address Register (high) */
390 #define NTBCR 0x3a /* Next Transmit Byte count Register */
391 #define NTARL 0x3c /* Next Transmit Address Register (low) */
392 #define NTARU 0x3e /* Next Transmit Address Register (high) */
394 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396 #define RBCR 0xaa /* Receive Byte count Register */
397 #define RARL 0xac /* Receive Address Register (low) */
398 #define RARU 0xae /* Receive Address Register (high) */
399 #define NRBCR 0xba /* Next Receive Byte count Register */
400 #define NRARL 0xbc /* Next Receive Address Register (low) */
401 #define NRARU 0xbe /* Next Receive Address Register (high) */
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
408 #define MODEMSTATUS_DTR 0x80
409 #define MODEMSTATUS_DSR 0x40
410 #define MODEMSTATUS_RTS 0x20
411 #define MODEMSTATUS_CTS 0x10
412 #define MODEMSTATUS_RI 0x04
413 #define MODEMSTATUS_DCD 0x01
417 * Channel Command/Address Register (CCAR) Command Codes
420 #define RTCmd_Null 0x0000
421 #define RTCmd_ResetHighestIus 0x1000
422 #define RTCmd_TriggerChannelLoadDma 0x2000
423 #define RTCmd_TriggerRxDma 0x2800
424 #define RTCmd_TriggerTxDma 0x3000
425 #define RTCmd_TriggerRxAndTxDma 0x3800
426 #define RTCmd_PurgeRxFifo 0x4800
427 #define RTCmd_PurgeTxFifo 0x5000
428 #define RTCmd_PurgeRxAndTxFifo 0x5800
429 #define RTCmd_LoadRcc 0x6800
430 #define RTCmd_LoadTcc 0x7000
431 #define RTCmd_LoadRccAndTcc 0x7800
432 #define RTCmd_LoadTC0 0x8800
433 #define RTCmd_LoadTC1 0x9000
434 #define RTCmd_LoadTC0AndTC1 0x9800
435 #define RTCmd_SerialDataLSBFirst 0xa000
436 #define RTCmd_SerialDataMSBFirst 0xa800
437 #define RTCmd_SelectBigEndian 0xb000
438 #define RTCmd_SelectLittleEndian 0xb800
442 * DMA Command/Address Register (DCAR) Command Codes
445 #define DmaCmd_Null 0x0000
446 #define DmaCmd_ResetTxChannel 0x1000
447 #define DmaCmd_ResetRxChannel 0x1200
448 #define DmaCmd_StartTxChannel 0x2000
449 #define DmaCmd_StartRxChannel 0x2200
450 #define DmaCmd_ContinueTxChannel 0x3000
451 #define DmaCmd_ContinueRxChannel 0x3200
452 #define DmaCmd_PauseTxChannel 0x4000
453 #define DmaCmd_PauseRxChannel 0x4200
454 #define DmaCmd_AbortTxChannel 0x5000
455 #define DmaCmd_AbortRxChannel 0x5200
456 #define DmaCmd_InitTxChannel 0x7000
457 #define DmaCmd_InitRxChannel 0x7200
458 #define DmaCmd_ResetHighestDmaIus 0x8000
459 #define DmaCmd_ResetAllChannels 0x9000
460 #define DmaCmd_StartAllChannels 0xa000
461 #define DmaCmd_ContinueAllChannels 0xb000
462 #define DmaCmd_PauseAllChannels 0xc000
463 #define DmaCmd_AbortAllChannels 0xd000
464 #define DmaCmd_InitAllChannels 0xf000
466 #define TCmd_Null 0x0000
467 #define TCmd_ClearTxCRC 0x2000
468 #define TCmd_SelectTicrTtsaData 0x4000
469 #define TCmd_SelectTicrTxFifostatus 0x5000
470 #define TCmd_SelectTicrIntLevel 0x6000
471 #define TCmd_SelectTicrdma_level 0x7000
472 #define TCmd_SendFrame 0x8000
473 #define TCmd_SendAbort 0x9000
474 #define TCmd_EnableDleInsertion 0xc000
475 #define TCmd_DisableDleInsertion 0xd000
476 #define TCmd_ClearEofEom 0xe000
477 #define TCmd_SetEofEom 0xf000
479 #define RCmd_Null 0x0000
480 #define RCmd_ClearRxCRC 0x2000
481 #define RCmd_EnterHuntmode 0x3000
482 #define RCmd_SelectRicrRtsaData 0x4000
483 #define RCmd_SelectRicrRxFifostatus 0x5000
484 #define RCmd_SelectRicrIntLevel 0x6000
485 #define RCmd_SelectRicrdma_level 0x7000
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
491 #define RECEIVE_STATUS BIT5
492 #define RECEIVE_DATA BIT4
493 #define TRANSMIT_STATUS BIT3
494 #define TRANSMIT_DATA BIT2
500 * Receive status Bits in Receive Command/status Register RCSR
503 #define RXSTATUS_SHORT_FRAME BIT8
504 #define RXSTATUS_CODE_VIOLATION BIT8
505 #define RXSTATUS_EXITED_HUNT BIT7
506 #define RXSTATUS_IDLE_RECEIVED BIT6
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
509 #define RXSTATUS_RXBOUND BIT4
510 #define RXSTATUS_CRC_ERROR BIT3
511 #define RXSTATUS_FRAMING_ERROR BIT3
512 #define RXSTATUS_ABORT BIT2
513 #define RXSTATUS_PARITY_ERROR BIT2
514 #define RXSTATUS_OVERRUN BIT1
515 #define RXSTATUS_DATA_AVAILABLE BIT0
516 #define RXSTATUS_ALL 0x01f6
517 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
523 #define IDLEMODE_FLAGS 0x0000
524 #define IDLEMODE_ALT_ONE_ZERO 0x0100
525 #define IDLEMODE_ZERO 0x0200
526 #define IDLEMODE_ONE 0x0300
527 #define IDLEMODE_ALT_MARK_SPACE 0x0500
528 #define IDLEMODE_SPACE 0x0600
529 #define IDLEMODE_MARK 0x0700
530 #define IDLEMODE_MASK 0x0700
533 * IUSC revision identifiers
535 #define IUSC_SL1660 0x4d44
536 #define IUSC_PRE_SL1660 0x4553
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
542 #define TCSR_PRESERVE 0x0F00
544 #define TCSR_UNDERWAIT BIT11
545 #define TXSTATUS_PREAMBLE_SENT BIT7
546 #define TXSTATUS_IDLE_SENT BIT6
547 #define TXSTATUS_ABORT_SENT BIT5
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
550 #define TXSTATUS_CRC_SENT BIT3
551 #define TXSTATUS_ALL_SENT BIT2
552 #define TXSTATUS_UNDERRUN BIT1
553 #define TXSTATUS_FIFO_EMPTY BIT0
554 #define TXSTATUS_ALL 0x00fa
555 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
558 #define MISCSTATUS_RXC_LATCHED BIT15
559 #define MISCSTATUS_RXC BIT14
560 #define MISCSTATUS_TXC_LATCHED BIT13
561 #define MISCSTATUS_TXC BIT12
562 #define MISCSTATUS_RI_LATCHED BIT11
563 #define MISCSTATUS_RI BIT10
564 #define MISCSTATUS_DSR_LATCHED BIT9
565 #define MISCSTATUS_DSR BIT8
566 #define MISCSTATUS_DCD_LATCHED BIT7
567 #define MISCSTATUS_DCD BIT6
568 #define MISCSTATUS_CTS_LATCHED BIT5
569 #define MISCSTATUS_CTS BIT4
570 #define MISCSTATUS_RCC_UNDERRUN BIT3
571 #define MISCSTATUS_DPLL_NO_SYNC BIT2
572 #define MISCSTATUS_BRG1_ZERO BIT1
573 #define MISCSTATUS_BRG0_ZERO BIT0
575 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578 #define SICR_RXC_ACTIVE BIT15
579 #define SICR_RXC_INACTIVE BIT14
580 #define SICR_RXC (BIT15+BIT14)
581 #define SICR_TXC_ACTIVE BIT13
582 #define SICR_TXC_INACTIVE BIT12
583 #define SICR_TXC (BIT13+BIT12)
584 #define SICR_RI_ACTIVE BIT11
585 #define SICR_RI_INACTIVE BIT10
586 #define SICR_RI (BIT11+BIT10)
587 #define SICR_DSR_ACTIVE BIT9
588 #define SICR_DSR_INACTIVE BIT8
589 #define SICR_DSR (BIT9+BIT8)
590 #define SICR_DCD_ACTIVE BIT7
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7+BIT6)
593 #define SICR_CTS_ACTIVE BIT5
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5+BIT4)
596 #define SICR_RCC_UNDERFLOW BIT3
597 #define SICR_DPLL_NO_SYNC BIT2
598 #define SICR_BRG1_ZERO BIT1
599 #define SICR_BRG0_ZERO BIT0
601 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
602 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
603 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
604 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
605 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
607 #define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610 #define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613 #define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616 #define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
626 #define TXSTATUS_PREAMBLE_SENT BIT7
627 #define TXSTATUS_IDLE_SENT BIT6
628 #define TXSTATUS_ABORT_SENT BIT5
629 #define TXSTATUS_EOF BIT4
630 #define TXSTATUS_CRC_SENT BIT3
631 #define TXSTATUS_ALL_SENT BIT2
632 #define TXSTATUS_UNDERRUN BIT1
633 #define TXSTATUS_FIFO_EMPTY BIT0
635 #define DICR_MASTER BIT15
636 #define DICR_TRANSMIT BIT0
637 #define DICR_RECEIVE BIT1
639 #define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642 #define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645 #define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648 #define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651 /* Transmit status Bits in Transmit Control status Register (TCSR) */
652 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
655 #define DISABLE_UNCONDITIONAL 0
656 #define DISABLE_END_OF_FRAME 1
657 #define ENABLE_UNCONDITIONAL 2
658 #define ENABLE_AUTO_CTS 3
659 #define ENABLE_AUTO_DCD 3
660 #define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662 #define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
666 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
667 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
669 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
670 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
671 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
672 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
673 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
675 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
681 static void usc_start_receiver( struct mgsl_struct
*info
);
682 static void usc_stop_receiver( struct mgsl_struct
*info
);
684 static void usc_start_transmitter( struct mgsl_struct
*info
);
685 static void usc_stop_transmitter( struct mgsl_struct
*info
);
686 static void usc_set_txidle( struct mgsl_struct
*info
);
687 static void usc_load_txfifo( struct mgsl_struct
*info
);
689 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
690 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
692 static void usc_get_serial_signals( struct mgsl_struct
*info
);
693 static void usc_set_serial_signals( struct mgsl_struct
*info
);
695 static void usc_reset( struct mgsl_struct
*info
);
697 static void usc_set_sync_mode( struct mgsl_struct
*info
);
698 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
699 static void usc_set_async_mode( struct mgsl_struct
*info
);
700 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
702 static void usc_loopback_frame( struct mgsl_struct
*info
);
704 static void mgsl_tx_timeout(unsigned long context
);
707 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
708 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
709 static int usc_loopmode_active( struct mgsl_struct
* info
);
710 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
712 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
714 #if SYNCLINK_GENERIC_HDLC
715 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
716 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
717 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
718 static int hdlcdev_init(struct mgsl_struct
*info
);
719 static void hdlcdev_exit(struct mgsl_struct
*info
);
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
727 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
738 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
741 * Adapter diagnostic routines
743 static bool mgsl_register_test( struct mgsl_struct
*info
);
744 static bool mgsl_irq_test( struct mgsl_struct
*info
);
745 static bool mgsl_dma_test( struct mgsl_struct
*info
);
746 static bool mgsl_memory_test( struct mgsl_struct
*info
);
747 static int mgsl_adapter_test( struct mgsl_struct
*info
);
750 * device and resource management routines
752 static int mgsl_claim_resources(struct mgsl_struct
*info
);
753 static void mgsl_release_resources(struct mgsl_struct
*info
);
754 static void mgsl_add_device(struct mgsl_struct
*info
);
755 static struct mgsl_struct
* mgsl_allocate_device(void);
758 * DMA buffer manupulation functions.
760 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
761 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
762 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
763 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
764 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
765 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
766 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
767 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
770 * DMA and Shared Memory buffer allocation and formatting
772 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
773 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
774 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
775 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
776 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
777 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
778 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
779 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
780 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
781 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
782 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
783 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
786 * Bottom half interrupt handlers
788 static void mgsl_bh_handler(struct work_struct
*work
);
789 static void mgsl_bh_receive(struct mgsl_struct
*info
);
790 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
791 static void mgsl_bh_status(struct mgsl_struct
*info
);
794 * Interrupt handler routines and dispatch table.
796 static void mgsl_isr_null( struct mgsl_struct
*info
);
797 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
798 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
799 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
800 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
801 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
802 static void mgsl_isr_misc( struct mgsl_struct
*info
);
803 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
804 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
806 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
808 static isr_dispatch_func UscIsrTable
[7] =
813 mgsl_isr_transmit_data
,
814 mgsl_isr_transmit_status
,
815 mgsl_isr_receive_data
,
816 mgsl_isr_receive_status
820 * ioctl call handlers
822 static int tiocmget(struct tty_struct
*tty
);
823 static int tiocmset(struct tty_struct
*tty
,
824 unsigned int set
, unsigned int clear
);
825 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
826 __user
*user_icount
);
827 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
828 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
829 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
830 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
831 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
832 static int mgsl_txabort(struct mgsl_struct
* info
);
833 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
834 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
835 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
837 /* set non-zero on successful registration with PCI subsystem */
838 static bool pci_registered
;
841 * Global linked list of SyncLink devices
843 static struct mgsl_struct
*mgsl_device_list
;
844 static int mgsl_device_count
;
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
851 static bool break_on_load
;
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
860 * Array of user specified options for ISA adapters.
862 static int io
[MAX_ISA_DEVICES
];
863 static int irq
[MAX_ISA_DEVICES
];
864 static int dma
[MAX_ISA_DEVICES
];
865 static int debug_level
;
866 static int maxframe
[MAX_TOTAL_DEVICES
];
867 static int txdmabufs
[MAX_TOTAL_DEVICES
];
868 static int txholdbufs
[MAX_TOTAL_DEVICES
];
870 module_param(break_on_load
, bool, 0);
871 module_param(ttymajor
, int, 0);
872 module_param_array(io
, int, NULL
, 0);
873 module_param_array(irq
, int, NULL
, 0);
874 module_param_array(dma
, int, NULL
, 0);
875 module_param(debug_level
, int, 0);
876 module_param_array(maxframe
, int, NULL
, 0);
877 module_param_array(txdmabufs
, int, NULL
, 0);
878 module_param_array(txholdbufs
, int, NULL
, 0);
880 static char *driver_name
= "SyncLink serial driver";
881 static char *driver_version
= "$Revision: 4.38 $";
883 static int synclink_init_one (struct pci_dev
*dev
,
884 const struct pci_device_id
*ent
);
885 static void synclink_remove_one (struct pci_dev
*dev
);
887 static struct pci_device_id synclink_pci_tbl
[] = {
888 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
889 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
890 { 0, }, /* terminate list */
892 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
894 MODULE_LICENSE("GPL");
896 static struct pci_driver synclink_pci_driver
= {
898 .id_table
= synclink_pci_tbl
,
899 .probe
= synclink_init_one
,
900 .remove
= synclink_remove_one
,
903 static struct tty_driver
*serial_driver
;
905 /* number of characters left in xmit buffer before we ask for more */
906 #define WAKEUP_CHARS 256
909 static void mgsl_change_params(struct mgsl_struct
*info
);
910 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
918 static void* mgsl_get_text_ptr(void)
920 return mgsl_get_text_ptr
;
923 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
924 char *name
, const char *routine
)
926 #ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic
=
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo
=
930 "Warning: null mgsl_struct for (%s) in %s\n";
933 printk(badinfo
, name
, routine
);
936 if (info
->magic
!= MGSL_MAGIC
) {
937 printk(badmagic
, name
, routine
);
948 * line discipline callback wrappers
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
953 * ldisc_receive_buf - pass receive data to line discipline
956 static void ldisc_receive_buf(struct tty_struct
*tty
,
957 const __u8
*data
, char *flags
, int count
)
959 struct tty_ldisc
*ld
;
962 ld
= tty_ldisc_ref(tty
);
964 if (ld
->ops
->receive_buf
)
965 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
970 /* mgsl_stop() throttle (stop) transmitter
972 * Arguments: tty pointer to tty info structure
975 static void mgsl_stop(struct tty_struct
*tty
)
977 struct mgsl_struct
*info
= tty
->driver_data
;
980 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
983 if ( debug_level
>= DEBUG_LEVEL_INFO
)
984 printk("mgsl_stop(%s)\n",info
->device_name
);
986 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
987 if (info
->tx_enabled
)
988 usc_stop_transmitter(info
);
989 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
991 } /* end of mgsl_stop() */
993 /* mgsl_start() release (start) transmitter
995 * Arguments: tty pointer to tty info structure
998 static void mgsl_start(struct tty_struct
*tty
)
1000 struct mgsl_struct
*info
= tty
->driver_data
;
1001 unsigned long flags
;
1003 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1006 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1007 printk("mgsl_start(%s)\n",info
->device_name
);
1009 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1010 if (!info
->tx_enabled
)
1011 usc_start_transmitter(info
);
1012 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1014 } /* end of mgsl_start() */
1017 * Bottom half work queue access functions
1020 /* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1023 static int mgsl_bh_action(struct mgsl_struct
*info
)
1025 unsigned long flags
;
1028 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1030 if (info
->pending_bh
& BH_RECEIVE
) {
1031 info
->pending_bh
&= ~BH_RECEIVE
;
1033 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1034 info
->pending_bh
&= ~BH_TRANSMIT
;
1036 } else if (info
->pending_bh
& BH_STATUS
) {
1037 info
->pending_bh
&= ~BH_STATUS
;
1042 /* Mark BH routine as complete */
1043 info
->bh_running
= false;
1044 info
->bh_requested
= false;
1047 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1053 * Perform bottom half processing of work items queued by ISR.
1055 static void mgsl_bh_handler(struct work_struct
*work
)
1057 struct mgsl_struct
*info
=
1058 container_of(work
, struct mgsl_struct
, task
);
1061 if ( debug_level
>= DEBUG_LEVEL_BH
)
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__
,__LINE__
,info
->device_name
);
1065 info
->bh_running
= true;
1067 while((action
= mgsl_bh_action(info
)) != 0) {
1069 /* Process work item */
1070 if ( debug_level
>= DEBUG_LEVEL_BH
)
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__
,__LINE__
,action
);
1077 mgsl_bh_receive(info
);
1080 mgsl_bh_transmit(info
);
1083 mgsl_bh_status(info
);
1086 /* unknown work item ID */
1087 printk("Unknown work item ID=%08X!\n", action
);
1092 if ( debug_level
>= DEBUG_LEVEL_BH
)
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__
,__LINE__
,info
->device_name
);
1097 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1099 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1100 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1102 if ( debug_level
>= DEBUG_LEVEL_BH
)
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__
,__LINE__
,info
->device_name
);
1108 if (info
->rx_rcc_underrun
) {
1109 unsigned long flags
;
1110 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1111 usc_start_receiver(info
);
1112 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1115 } while(get_rx_frame(info
));
1118 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1120 struct tty_struct
*tty
= info
->port
.tty
;
1121 unsigned long flags
;
1123 if ( debug_level
>= DEBUG_LEVEL_BH
)
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__
,__LINE__
,info
->device_name
);
1130 /* if transmitter idle and loopmode_send_done_requested
1131 * then start echoing RxD to TxD
1133 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1134 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1135 usc_loopmode_send_done( info
);
1136 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1139 static void mgsl_bh_status(struct mgsl_struct
*info
)
1141 if ( debug_level
>= DEBUG_LEVEL_BH
)
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__
,__LINE__
,info
->device_name
);
1145 info
->ri_chkcount
= 0;
1146 info
->dsr_chkcount
= 0;
1147 info
->dcd_chkcount
= 0;
1148 info
->cts_chkcount
= 0;
1151 /* mgsl_isr_receive_status()
1153 * Service a receive status interrupt. The type of status
1154 * interrupt is indicated by the state of the RCSR.
1155 * This is only used for HDLC mode.
1157 * Arguments: info pointer to device instance data
1158 * Return Value: None
1160 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1162 u16 status
= usc_InReg( info
, RCSR
);
1164 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__
,__LINE__
,status
);
1168 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1169 info
->loopmode_insert_requested
&&
1170 usc_loopmode_active(info
) )
1172 ++info
->icount
.rxabort
;
1173 info
->loopmode_insert_requested
= false;
1175 /* clear CMR:13 to start echoing RxD to TxD */
1176 info
->cmr_value
&= ~BIT13
;
1177 usc_OutReg(info
, CMR
, info
->cmr_value
);
1179 /* disable received abort irq (no longer required) */
1180 usc_OutReg(info
, RICR
,
1181 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1184 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1185 if (status
& RXSTATUS_EXITED_HUNT
)
1186 info
->icount
.exithunt
++;
1187 if (status
& RXSTATUS_IDLE_RECEIVED
)
1188 info
->icount
.rxidle
++;
1189 wake_up_interruptible(&info
->event_wait_q
);
1192 if (status
& RXSTATUS_OVERRUN
){
1193 info
->icount
.rxover
++;
1194 usc_process_rxoverrun_sync( info
);
1197 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1198 usc_UnlatchRxstatusBits( info
, status
);
1200 } /* end of mgsl_isr_receive_status() */
1202 /* mgsl_isr_transmit_status()
1204 * Service a transmit status interrupt
1205 * HDLC mode :end of transmit frame
1206 * Async mode:all data is sent
1207 * transmit status is indicated by bits in the TCSR.
1209 * Arguments: info pointer to device instance data
1210 * Return Value: None
1212 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1214 u16 status
= usc_InReg( info
, TCSR
);
1216 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__
,__LINE__
,status
);
1220 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1221 usc_UnlatchTxstatusBits( info
, status
);
1223 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1225 /* finished sending HDLC abort. This may leave */
1226 /* the TxFifo with data from the aborted frame */
1227 /* so purge the TxFifo. Also shutdown the DMA */
1228 /* channel in case there is data remaining in */
1229 /* the DMA buffer */
1230 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1231 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1234 if ( status
& TXSTATUS_EOF_SENT
)
1235 info
->icount
.txok
++;
1236 else if ( status
& TXSTATUS_UNDERRUN
)
1237 info
->icount
.txunder
++;
1238 else if ( status
& TXSTATUS_ABORT_SENT
)
1239 info
->icount
.txabort
++;
1241 info
->icount
.txunder
++;
1243 info
->tx_active
= false;
1244 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1245 del_timer(&info
->tx_timer
);
1247 if ( info
->drop_rts_on_tx_done
) {
1248 usc_get_serial_signals( info
);
1249 if ( info
->serial_signals
& SerialSignal_RTS
) {
1250 info
->serial_signals
&= ~SerialSignal_RTS
;
1251 usc_set_serial_signals( info
);
1253 info
->drop_rts_on_tx_done
= false;
1256 #if SYNCLINK_GENERIC_HDLC
1258 hdlcdev_tx_done(info
);
1262 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1263 usc_stop_transmitter(info
);
1266 info
->pending_bh
|= BH_TRANSMIT
;
1269 } /* end of mgsl_isr_transmit_status() */
1271 /* mgsl_isr_io_pin()
1273 * Service an Input/Output pin interrupt. The type of
1274 * interrupt is indicated by bits in the MISR
1276 * Arguments: info pointer to device instance data
1277 * Return Value: None
1279 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1281 struct mgsl_icount
*icount
;
1282 u16 status
= usc_InReg( info
, MISR
);
1284 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__
,__LINE__
,status
);
1288 usc_ClearIrqPendingBits( info
, IO_PIN
);
1289 usc_UnlatchIostatusBits( info
, status
);
1291 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1292 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1293 icount
= &info
->icount
;
1294 /* update input line counters */
1295 if (status
& MISCSTATUS_RI_LATCHED
) {
1296 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1297 usc_DisablestatusIrqs(info
,SICR_RI
);
1299 if ( status
& MISCSTATUS_RI
)
1300 info
->input_signal_events
.ri_up
++;
1302 info
->input_signal_events
.ri_down
++;
1304 if (status
& MISCSTATUS_DSR_LATCHED
) {
1305 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1306 usc_DisablestatusIrqs(info
,SICR_DSR
);
1308 if ( status
& MISCSTATUS_DSR
)
1309 info
->input_signal_events
.dsr_up
++;
1311 info
->input_signal_events
.dsr_down
++;
1313 if (status
& MISCSTATUS_DCD_LATCHED
) {
1314 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1315 usc_DisablestatusIrqs(info
,SICR_DCD
);
1317 if (status
& MISCSTATUS_DCD
) {
1318 info
->input_signal_events
.dcd_up
++;
1320 info
->input_signal_events
.dcd_down
++;
1321 #if SYNCLINK_GENERIC_HDLC
1322 if (info
->netcount
) {
1323 if (status
& MISCSTATUS_DCD
)
1324 netif_carrier_on(info
->netdev
);
1326 netif_carrier_off(info
->netdev
);
1330 if (status
& MISCSTATUS_CTS_LATCHED
)
1332 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1333 usc_DisablestatusIrqs(info
,SICR_CTS
);
1335 if ( status
& MISCSTATUS_CTS
)
1336 info
->input_signal_events
.cts_up
++;
1338 info
->input_signal_events
.cts_down
++;
1340 wake_up_interruptible(&info
->status_event_wait_q
);
1341 wake_up_interruptible(&info
->event_wait_q
);
1343 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
1344 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1345 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1346 printk("%s CD now %s...", info
->device_name
,
1347 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1348 if (status
& MISCSTATUS_DCD
)
1349 wake_up_interruptible(&info
->port
.open_wait
);
1351 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1352 printk("doing serial hangup...");
1354 tty_hangup(info
->port
.tty
);
1358 if (tty_port_cts_enabled(&info
->port
) &&
1359 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1360 if (info
->port
.tty
->hw_stopped
) {
1361 if (status
& MISCSTATUS_CTS
) {
1362 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1363 printk("CTS tx start...");
1365 info
->port
.tty
->hw_stopped
= 0;
1366 usc_start_transmitter(info
);
1367 info
->pending_bh
|= BH_TRANSMIT
;
1371 if (!(status
& MISCSTATUS_CTS
)) {
1372 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1373 printk("CTS tx stop...");
1375 info
->port
.tty
->hw_stopped
= 1;
1376 usc_stop_transmitter(info
);
1382 info
->pending_bh
|= BH_STATUS
;
1384 /* for diagnostics set IRQ flag */
1385 if ( status
& MISCSTATUS_TXC_LATCHED
){
1386 usc_OutReg( info
, SICR
,
1387 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1388 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1389 info
->irq_occurred
= true;
1392 } /* end of mgsl_isr_io_pin() */
1394 /* mgsl_isr_transmit_data()
1396 * Service a transmit data interrupt (async mode only).
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1401 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1403 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__
,__LINE__
,info
->xmit_cnt
);
1407 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1409 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1410 usc_stop_transmitter(info
);
1414 if ( info
->xmit_cnt
)
1415 usc_load_txfifo( info
);
1417 info
->tx_active
= false;
1419 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1420 info
->pending_bh
|= BH_TRANSMIT
;
1422 } /* end of mgsl_isr_transmit_data() */
1424 /* mgsl_isr_receive_data()
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1433 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1438 unsigned char DataByte
;
1439 struct mgsl_icount
*icount
= &info
->icount
;
1441 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1445 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1454 /* flush the receive FIFO */
1456 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1459 /* read one byte from RxFIFO */
1460 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1461 info
->io_base
+ CCAR
);
1462 DataByte
= inb( info
->io_base
+ CCAR
);
1464 /* get the status of the received byte */
1465 status
= usc_InReg(info
, RCSR
);
1466 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1467 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1468 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1473 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1474 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1475 printk("rxerr=%04X\n",status
);
1476 /* update error statistics */
1477 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1478 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1480 } else if (status
& RXSTATUS_PARITY_ERROR
)
1482 else if (status
& RXSTATUS_FRAMING_ERROR
)
1484 else if (status
& RXSTATUS_OVERRUN
) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1491 /* discard char if tty control flags say so */
1492 if (status
& info
->ignore_status_mask
)
1495 status
&= info
->read_status_mask
;
1497 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1499 if (info
->port
.flags
& ASYNC_SAK
)
1500 do_SAK(info
->port
.tty
);
1501 } else if (status
& RXSTATUS_PARITY_ERROR
)
1503 else if (status
& RXSTATUS_FRAMING_ERROR
)
1505 } /* end of if (error) */
1506 tty_insert_flip_char(&info
->port
, DataByte
, flag
);
1507 if (status
& RXSTATUS_OVERRUN
) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1512 work
+= tty_insert_flip_char(&info
->port
, 0, TTY_OVERRUN
);
1516 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1519 icount
->parity
,icount
->frame
,icount
->overrun
);
1523 tty_flip_buffer_push(&info
->port
);
1528 * Service a miscellaneous interrupt source.
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1533 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1535 u16 status
= usc_InReg( info
, MISR
);
1537 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__
,__LINE__
,status
);
1541 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1542 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1546 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1547 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1548 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1549 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1551 /* schedule BH handler to restart receiver */
1552 info
->pending_bh
|= BH_RECEIVE
;
1553 info
->rx_rcc_underrun
= true;
1556 usc_ClearIrqPendingBits( info
, MISC
);
1557 usc_UnlatchMiscstatusBits( info
, status
);
1559 } /* end of mgsl_isr_misc() */
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1569 static void mgsl_isr_null( struct mgsl_struct
*info
)
1572 } /* end of mgsl_isr_null() */
1574 /* mgsl_isr_receive_dma()
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1593 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1598 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status
= usc_InDmaReg( info
, RDMR
);
1604 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__
,__LINE__
,info
->device_name
,status
);
1608 info
->pending_bh
|= BH_RECEIVE
;
1610 if ( status
& BIT3
) {
1611 info
->rx_overflow
= true;
1612 info
->icount
.buf_overrun
++;
1615 } /* end of mgsl_isr_receive_dma() */
1617 /* mgsl_isr_transmit_dma()
1619 * This function services a transmit DMA channel interrupt.
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1637 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1642 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1647 status
= usc_InDmaReg( info
, TDMR
);
1649 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__
,__LINE__
,info
->device_name
,status
);
1653 if ( status
& BIT2
) {
1654 --info
->tx_dma_buffers_used
;
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1659 if ( load_next_tx_holding_buffer(info
) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1663 info
->pending_bh
|= BH_TRANSMIT
;
1667 } /* end of mgsl_isr_transmit_dma() */
1671 * Interrupt service routine entry point.
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1678 * Return Value: None
1680 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1682 struct mgsl_struct
*info
= dev_id
;
1686 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1687 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__
, __LINE__
, info
->irq_level
);
1690 spin_lock(&info
->irq_spinlock
);
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector
= usc_InReg(info
, IVR
) >> 9;
1695 DmaVector
= usc_InDmaReg(info
, DIVR
);
1697 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1701 if ( !UscVector
&& !DmaVector
)
1704 /* Dispatch interrupt vector */
1706 (*UscIsrTable
[UscVector
])(info
);
1707 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1708 mgsl_isr_transmit_dma(info
);
1710 mgsl_isr_receive_dma(info
);
1712 if ( info
->isr_overflow
) {
1713 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1715 usc_DisableMasterIrqBit(info
);
1716 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1725 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1726 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__
,__LINE__
,info
->device_name
);
1729 schedule_work(&info
->task
);
1730 info
->bh_requested
= true;
1733 spin_unlock(&info
->irq_spinlock
);
1735 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1736 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__
, __LINE__
, info
->irq_level
);
1740 } /* end of mgsl_interrupt() */
1744 * Initialize and start device.
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1749 static int startup(struct mgsl_struct
* info
)
1753 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1756 if (info
->port
.flags
& ASYNC_INITIALIZED
)
1759 if (!info
->xmit_buf
) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1762 if (!info
->xmit_buf
) {
1763 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__
,__LINE__
,info
->device_name
);
1769 info
->pending_bh
= 0;
1771 memset(&info
->icount
, 0, sizeof(info
->icount
));
1773 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1775 /* Allocate and claim adapter resources */
1776 retval
= mgsl_claim_resources(info
);
1778 /* perform existence check and diagnostics */
1780 retval
= mgsl_adapter_test(info
);
1783 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1784 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1785 mgsl_release_resources(info
);
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info
);
1793 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1795 info
->port
.flags
|= ASYNC_INITIALIZED
;
1799 } /* end of startup() */
1803 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1805 * Arguments: info pointer to device instance data
1806 * Return Value: None
1808 static void shutdown(struct mgsl_struct
* info
)
1810 unsigned long flags
;
1812 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1815 if (debug_level
>= DEBUG_LEVEL_INFO
)
1816 printk("%s(%d):mgsl_shutdown(%s)\n",
1817 __FILE__
,__LINE__
, info
->device_name
);
1819 /* clear status wait queue because status changes */
1820 /* can't happen after shutting down the hardware */
1821 wake_up_interruptible(&info
->status_event_wait_q
);
1822 wake_up_interruptible(&info
->event_wait_q
);
1824 del_timer_sync(&info
->tx_timer
);
1826 if (info
->xmit_buf
) {
1827 free_page((unsigned long) info
->xmit_buf
);
1828 info
->xmit_buf
= NULL
;
1831 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1832 usc_DisableMasterIrqBit(info
);
1833 usc_stop_receiver(info
);
1834 usc_stop_transmitter(info
);
1835 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1836 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1837 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1839 /* Disable DMAEN (Port 7, Bit 14) */
1840 /* This disconnects the DMA request signal from the ISA bus */
1841 /* on the ISA adapter. This has no effect for the PCI adapter */
1842 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1844 /* Disable INTEN (Port 6, Bit12) */
1845 /* This disconnects the IRQ request signal to the ISA bus */
1846 /* on the ISA adapter. This has no effect for the PCI adapter */
1847 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1849 if (!info
->port
.tty
|| info
->port
.tty
->termios
.c_cflag
& HUPCL
) {
1850 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1851 usc_set_serial_signals(info
);
1854 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1856 mgsl_release_resources(info
);
1859 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1861 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
1863 } /* end of shutdown() */
1865 static void mgsl_program_hw(struct mgsl_struct
*info
)
1867 unsigned long flags
;
1869 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1871 usc_stop_receiver(info
);
1872 usc_stop_transmitter(info
);
1873 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1875 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1876 info
->params
.mode
== MGSL_MODE_RAW
||
1878 usc_set_sync_mode(info
);
1880 usc_set_async_mode(info
);
1882 usc_set_serial_signals(info
);
1884 info
->dcd_chkcount
= 0;
1885 info
->cts_chkcount
= 0;
1886 info
->ri_chkcount
= 0;
1887 info
->dsr_chkcount
= 0;
1889 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1890 usc_EnableInterrupts(info
, IO_PIN
);
1891 usc_get_serial_signals(info
);
1893 if (info
->netcount
|| info
->port
.tty
->termios
.c_cflag
& CREAD
)
1894 usc_start_receiver(info
);
1896 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1899 /* Reconfigure adapter based on new parameters
1901 static void mgsl_change_params(struct mgsl_struct
*info
)
1906 if (!info
->port
.tty
)
1909 if (debug_level
>= DEBUG_LEVEL_INFO
)
1910 printk("%s(%d):mgsl_change_params(%s)\n",
1911 __FILE__
,__LINE__
, info
->device_name
);
1913 cflag
= info
->port
.tty
->termios
.c_cflag
;
1915 /* if B0 rate (hangup) specified then negate RTS and DTR */
1916 /* otherwise assert RTS and DTR */
1918 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
1920 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1922 /* byte size and parity */
1924 switch (cflag
& CSIZE
) {
1925 case CS5
: info
->params
.data_bits
= 5; break;
1926 case CS6
: info
->params
.data_bits
= 6; break;
1927 case CS7
: info
->params
.data_bits
= 7; break;
1928 case CS8
: info
->params
.data_bits
= 8; break;
1929 /* Never happens, but GCC is too dumb to figure it out */
1930 default: info
->params
.data_bits
= 7; break;
1934 info
->params
.stop_bits
= 2;
1936 info
->params
.stop_bits
= 1;
1938 info
->params
.parity
= ASYNC_PARITY_NONE
;
1939 if (cflag
& PARENB
) {
1941 info
->params
.parity
= ASYNC_PARITY_ODD
;
1943 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1946 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1950 /* calculate number of jiffies to transmit a full
1951 * FIFO (32 bytes) at specified data rate
1953 bits_per_char
= info
->params
.data_bits
+
1954 info
->params
.stop_bits
+ 1;
1956 /* if port data rate is set to 460800 or less then
1957 * allow tty settings to override, otherwise keep the
1958 * current data rate.
1960 if (info
->params
.data_rate
<= 460800)
1961 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1963 if ( info
->params
.data_rate
) {
1964 info
->timeout
= (32*HZ
*bits_per_char
) /
1965 info
->params
.data_rate
;
1967 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1969 if (cflag
& CRTSCTS
)
1970 info
->port
.flags
|= ASYNC_CTS_FLOW
;
1972 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
1975 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
1977 info
->port
.flags
|= ASYNC_CHECK_CD
;
1979 /* process tty input control flags */
1981 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1982 if (I_INPCK(info
->port
.tty
))
1983 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1984 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1985 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1987 if (I_IGNPAR(info
->port
.tty
))
1988 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1989 if (I_IGNBRK(info
->port
.tty
)) {
1990 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1991 /* If ignoring parity and break indicators, ignore
1992 * overruns too. (For real raw support).
1994 if (I_IGNPAR(info
->port
.tty
))
1995 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
1998 mgsl_program_hw(info
);
2000 } /* end of mgsl_change_params() */
2004 * Add a character to the transmit buffer.
2006 * Arguments: tty pointer to tty information structure
2007 * ch character to add to transmit buffer
2009 * Return Value: None
2011 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2013 struct mgsl_struct
*info
= tty
->driver_data
;
2014 unsigned long flags
;
2017 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2018 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2019 __FILE__
, __LINE__
, ch
, info
->device_name
);
2022 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2025 if (!info
->xmit_buf
)
2028 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2030 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2031 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2032 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2033 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2038 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2041 } /* end of mgsl_put_char() */
2043 /* mgsl_flush_chars()
2045 * Enable transmitter so remaining characters in the
2046 * transmit buffer are sent.
2048 * Arguments: tty pointer to tty information structure
2049 * Return Value: None
2051 static void mgsl_flush_chars(struct tty_struct
*tty
)
2053 struct mgsl_struct
*info
= tty
->driver_data
;
2054 unsigned long flags
;
2056 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2057 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2058 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2060 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2063 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2067 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2068 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2069 __FILE__
,__LINE__
,info
->device_name
);
2071 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2073 if (!info
->tx_active
) {
2074 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2075 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2076 /* operating in synchronous (frame oriented) mode */
2077 /* copy data from circular xmit_buf to */
2078 /* transmit DMA buffer. */
2079 mgsl_load_tx_dma_buffer(info
,
2080 info
->xmit_buf
,info
->xmit_cnt
);
2082 usc_start_transmitter(info
);
2085 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2087 } /* end of mgsl_flush_chars() */
2091 * Send a block of data
2095 * tty pointer to tty information structure
2096 * buf pointer to buffer containing send data
2097 * count size of send data in bytes
2099 * Return Value: number of characters written
2101 static int mgsl_write(struct tty_struct
* tty
,
2102 const unsigned char *buf
, int count
)
2105 struct mgsl_struct
*info
= tty
->driver_data
;
2106 unsigned long flags
;
2108 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2109 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2110 __FILE__
,__LINE__
,info
->device_name
,count
);
2112 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2115 if (!info
->xmit_buf
)
2118 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2119 info
->params
.mode
== MGSL_MODE_RAW
) {
2120 /* operating in synchronous (frame oriented) mode */
2121 if (info
->tx_active
) {
2123 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2127 /* transmitter is actively sending data -
2128 * if we have multiple transmit dma and
2129 * holding buffers, attempt to queue this
2130 * frame for transmission at a later time.
2132 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2133 /* no tx holding buffers available */
2138 /* queue transmit frame request */
2140 save_tx_buffer_request(info
,buf
,count
);
2142 /* if we have sufficient tx dma buffers,
2143 * load the next buffered tx request
2145 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2146 load_next_tx_holding_buffer(info
);
2147 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2151 /* if operating in HDLC LoopMode and the adapter */
2152 /* has yet to be inserted into the loop, we can't */
2155 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2156 !usc_loopmode_active(info
) )
2162 if ( info
->xmit_cnt
) {
2163 /* Send accumulated from send_char() calls */
2164 /* as frame and wait before accepting more data. */
2167 /* copy data from circular xmit_buf to */
2168 /* transmit DMA buffer. */
2169 mgsl_load_tx_dma_buffer(info
,
2170 info
->xmit_buf
,info
->xmit_cnt
);
2171 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2172 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2173 __FILE__
,__LINE__
,info
->device_name
);
2175 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2176 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2177 __FILE__
,__LINE__
,info
->device_name
);
2179 info
->xmit_cnt
= count
;
2180 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2184 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2185 c
= min_t(int, count
,
2186 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2187 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2189 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2192 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2193 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2194 (SERIAL_XMIT_SIZE
-1));
2195 info
->xmit_cnt
+= c
;
2196 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2203 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2204 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2205 if (!info
->tx_active
)
2206 usc_start_transmitter(info
);
2207 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2210 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2211 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2212 __FILE__
,__LINE__
,info
->device_name
,ret
);
2216 } /* end of mgsl_write() */
2218 /* mgsl_write_room()
2220 * Return the count of free bytes in transmit buffer
2222 * Arguments: tty pointer to tty info structure
2223 * Return Value: None
2225 static int mgsl_write_room(struct tty_struct
*tty
)
2227 struct mgsl_struct
*info
= tty
->driver_data
;
2230 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2232 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2236 if (debug_level
>= DEBUG_LEVEL_INFO
)
2237 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2238 __FILE__
,__LINE__
, info
->device_name
,ret
);
2240 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2241 info
->params
.mode
== MGSL_MODE_RAW
) {
2242 /* operating in synchronous (frame oriented) mode */
2243 if ( info
->tx_active
)
2246 return HDLC_MAX_FRAME_SIZE
;
2251 } /* end of mgsl_write_room() */
2253 /* mgsl_chars_in_buffer()
2255 * Return the count of bytes in transmit buffer
2257 * Arguments: tty pointer to tty info structure
2258 * Return Value: None
2260 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2262 struct mgsl_struct
*info
= tty
->driver_data
;
2264 if (debug_level
>= DEBUG_LEVEL_INFO
)
2265 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2266 __FILE__
,__LINE__
, info
->device_name
);
2268 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2271 if (debug_level
>= DEBUG_LEVEL_INFO
)
2272 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2273 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2275 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2276 info
->params
.mode
== MGSL_MODE_RAW
) {
2277 /* operating in synchronous (frame oriented) mode */
2278 if ( info
->tx_active
)
2279 return info
->max_frame_size
;
2284 return info
->xmit_cnt
;
2285 } /* end of mgsl_chars_in_buffer() */
2287 /* mgsl_flush_buffer()
2289 * Discard all data in the send buffer
2291 * Arguments: tty pointer to tty info structure
2292 * Return Value: None
2294 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2296 struct mgsl_struct
*info
= tty
->driver_data
;
2297 unsigned long flags
;
2299 if (debug_level
>= DEBUG_LEVEL_INFO
)
2300 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2301 __FILE__
,__LINE__
, info
->device_name
);
2303 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2306 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2307 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2308 del_timer(&info
->tx_timer
);
2309 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2314 /* mgsl_send_xchar()
2316 * Send a high-priority XON/XOFF character
2318 * Arguments: tty pointer to tty info structure
2319 * ch character to send
2320 * Return Value: None
2322 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2324 struct mgsl_struct
*info
= tty
->driver_data
;
2325 unsigned long flags
;
2327 if (debug_level
>= DEBUG_LEVEL_INFO
)
2328 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2329 __FILE__
,__LINE__
, info
->device_name
, ch
);
2331 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2336 /* Make sure transmit interrupts are on */
2337 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2338 if (!info
->tx_enabled
)
2339 usc_start_transmitter(info
);
2340 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2342 } /* end of mgsl_send_xchar() */
2346 * Signal remote device to throttle send data (our receive data)
2348 * Arguments: tty pointer to tty info structure
2349 * Return Value: None
2351 static void mgsl_throttle(struct tty_struct
* tty
)
2353 struct mgsl_struct
*info
= tty
->driver_data
;
2354 unsigned long flags
;
2356 if (debug_level
>= DEBUG_LEVEL_INFO
)
2357 printk("%s(%d):mgsl_throttle(%s) entry\n",
2358 __FILE__
,__LINE__
, info
->device_name
);
2360 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2364 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2366 if (tty
->termios
.c_cflag
& CRTSCTS
) {
2367 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2368 info
->serial_signals
&= ~SerialSignal_RTS
;
2369 usc_set_serial_signals(info
);
2370 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2372 } /* end of mgsl_throttle() */
2374 /* mgsl_unthrottle()
2376 * Signal remote device to stop throttling send data (our receive data)
2378 * Arguments: tty pointer to tty info structure
2379 * Return Value: None
2381 static void mgsl_unthrottle(struct tty_struct
* tty
)
2383 struct mgsl_struct
*info
= tty
->driver_data
;
2384 unsigned long flags
;
2386 if (debug_level
>= DEBUG_LEVEL_INFO
)
2387 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2388 __FILE__
,__LINE__
, info
->device_name
);
2390 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2397 mgsl_send_xchar(tty
, START_CHAR(tty
));
2400 if (tty
->termios
.c_cflag
& CRTSCTS
) {
2401 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2402 info
->serial_signals
|= SerialSignal_RTS
;
2403 usc_set_serial_signals(info
);
2404 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2407 } /* end of mgsl_unthrottle() */
2411 * get the current serial parameters information
2413 * Arguments: info pointer to device instance data
2414 * user_icount pointer to buffer to hold returned stats
2416 * Return Value: 0 if success, otherwise error code
2418 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2422 if (debug_level
>= DEBUG_LEVEL_INFO
)
2423 printk("%s(%d):mgsl_get_params(%s)\n",
2424 __FILE__
,__LINE__
, info
->device_name
);
2427 memset(&info
->icount
, 0, sizeof(info
->icount
));
2429 mutex_lock(&info
->port
.mutex
);
2430 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2431 mutex_unlock(&info
->port
.mutex
);
2438 } /* end of mgsl_get_stats() */
2440 /* mgsl_get_params()
2442 * get the current serial parameters information
2444 * Arguments: info pointer to device instance data
2445 * user_params pointer to buffer to hold returned params
2447 * Return Value: 0 if success, otherwise error code
2449 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2452 if (debug_level
>= DEBUG_LEVEL_INFO
)
2453 printk("%s(%d):mgsl_get_params(%s)\n",
2454 __FILE__
,__LINE__
, info
->device_name
);
2456 mutex_lock(&info
->port
.mutex
);
2457 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2458 mutex_unlock(&info
->port
.mutex
);
2460 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2461 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2462 __FILE__
,__LINE__
,info
->device_name
);
2468 } /* end of mgsl_get_params() */
2470 /* mgsl_set_params()
2472 * set the serial parameters
2476 * info pointer to device instance data
2477 * new_params user buffer containing new serial params
2479 * Return Value: 0 if success, otherwise error code
2481 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2483 unsigned long flags
;
2484 MGSL_PARAMS tmp_params
;
2487 if (debug_level
>= DEBUG_LEVEL_INFO
)
2488 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2489 info
->device_name
);
2490 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2492 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2493 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2494 __FILE__
,__LINE__
,info
->device_name
);
2498 mutex_lock(&info
->port
.mutex
);
2499 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2500 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2501 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2503 mgsl_change_params(info
);
2504 mutex_unlock(&info
->port
.mutex
);
2508 } /* end of mgsl_set_params() */
2510 /* mgsl_get_txidle()
2512 * get the current transmit idle mode
2514 * Arguments: info pointer to device instance data
2515 * idle_mode pointer to buffer to hold returned idle mode
2517 * Return Value: 0 if success, otherwise error code
2519 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2523 if (debug_level
>= DEBUG_LEVEL_INFO
)
2524 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2525 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2527 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2529 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2530 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2531 __FILE__
,__LINE__
,info
->device_name
);
2537 } /* end of mgsl_get_txidle() */
2539 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2541 * Arguments: info pointer to device instance data
2542 * idle_mode new idle mode
2544 * Return Value: 0 if success, otherwise error code
2546 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2548 unsigned long flags
;
2550 if (debug_level
>= DEBUG_LEVEL_INFO
)
2551 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2552 info
->device_name
, idle_mode
);
2554 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2555 info
->idle_mode
= idle_mode
;
2556 usc_set_txidle( info
);
2557 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2560 } /* end of mgsl_set_txidle() */
2564 * enable or disable the transmitter
2568 * info pointer to device instance data
2569 * enable 1 = enable, 0 = disable
2571 * Return Value: 0 if success, otherwise error code
2573 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2575 unsigned long flags
;
2577 if (debug_level
>= DEBUG_LEVEL_INFO
)
2578 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2579 info
->device_name
, enable
);
2581 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2583 if ( !info
->tx_enabled
) {
2585 usc_start_transmitter(info
);
2586 /*--------------------------------------------------
2587 * if HDLC/SDLC Loop mode, attempt to insert the
2588 * station in the 'loop' by setting CMR:13. Upon
2589 * receipt of the next GoAhead (RxAbort) sequence,
2590 * the OnLoop indicator (CCSR:7) should go active
2591 * to indicate that we are on the loop
2592 *--------------------------------------------------*/
2593 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2594 usc_loopmode_insert_request( info
);
2597 if ( info
->tx_enabled
)
2598 usc_stop_transmitter(info
);
2600 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2603 } /* end of mgsl_txenable() */
2605 /* mgsl_txabort() abort send HDLC frame
2607 * Arguments: info pointer to device instance data
2608 * Return Value: 0 if success, otherwise error code
2610 static int mgsl_txabort(struct mgsl_struct
* info
)
2612 unsigned long flags
;
2614 if (debug_level
>= DEBUG_LEVEL_INFO
)
2615 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2618 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2619 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2621 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2622 usc_loopmode_cancel_transmit( info
);
2624 usc_TCmd(info
,TCmd_SendAbort
);
2626 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2629 } /* end of mgsl_txabort() */
2631 /* mgsl_rxenable() enable or disable the receiver
2633 * Arguments: info pointer to device instance data
2634 * enable 1 = enable, 0 = disable
2635 * Return Value: 0 if success, otherwise error code
2637 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2639 unsigned long flags
;
2641 if (debug_level
>= DEBUG_LEVEL_INFO
)
2642 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2643 info
->device_name
, enable
);
2645 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2647 if ( !info
->rx_enabled
)
2648 usc_start_receiver(info
);
2650 if ( info
->rx_enabled
)
2651 usc_stop_receiver(info
);
2653 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2656 } /* end of mgsl_rxenable() */
2658 /* mgsl_wait_event() wait for specified event to occur
2660 * Arguments: info pointer to device instance data
2661 * mask pointer to bitmask of events to wait for
2662 * Return Value: 0 if successful and bit mask updated with
2663 * of events triggerred,
2664 * otherwise error code
2666 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2668 unsigned long flags
;
2671 struct mgsl_icount cprev
, cnow
;
2674 struct _input_signal_events oldsigs
, newsigs
;
2675 DECLARE_WAITQUEUE(wait
, current
);
2677 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2682 if (debug_level
>= DEBUG_LEVEL_INFO
)
2683 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2684 info
->device_name
, mask
);
2686 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2688 /* return immediately if state matches requested events */
2689 usc_get_serial_signals(info
);
2690 s
= info
->serial_signals
;
2692 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2693 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2694 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2695 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2697 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2701 /* save current irq counts */
2702 cprev
= info
->icount
;
2703 oldsigs
= info
->input_signal_events
;
2705 /* enable hunt and idle irqs if needed */
2706 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2707 u16 oldreg
= usc_InReg(info
,RICR
);
2708 u16 newreg
= oldreg
+
2709 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2710 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2711 if (oldreg
!= newreg
)
2712 usc_OutReg(info
, RICR
, newreg
);
2715 set_current_state(TASK_INTERRUPTIBLE
);
2716 add_wait_queue(&info
->event_wait_q
, &wait
);
2718 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2723 if (signal_pending(current
)) {
2728 /* get current irq counts */
2729 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2730 cnow
= info
->icount
;
2731 newsigs
= info
->input_signal_events
;
2732 set_current_state(TASK_INTERRUPTIBLE
);
2733 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2735 /* if no change, wait aborted for some reason */
2736 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2737 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2738 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2739 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2740 newsigs
.cts_up
== oldsigs
.cts_up
&&
2741 newsigs
.cts_down
== oldsigs
.cts_down
&&
2742 newsigs
.ri_up
== oldsigs
.ri_up
&&
2743 newsigs
.ri_down
== oldsigs
.ri_down
&&
2744 cnow
.exithunt
== cprev
.exithunt
&&
2745 cnow
.rxidle
== cprev
.rxidle
) {
2751 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2752 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2753 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2754 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2755 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2756 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2757 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2758 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2759 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2760 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2768 remove_wait_queue(&info
->event_wait_q
, &wait
);
2769 set_current_state(TASK_RUNNING
);
2771 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2772 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2773 if (!waitqueue_active(&info
->event_wait_q
)) {
2774 /* disable enable exit hunt mode/idle rcvd IRQs */
2775 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2776 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2778 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2782 PUT_USER(rc
, events
, mask_ptr
);
2786 } /* end of mgsl_wait_event() */
2788 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2790 unsigned long flags
;
2792 struct mgsl_icount cprev
, cnow
;
2793 DECLARE_WAITQUEUE(wait
, current
);
2795 /* save current irq counts */
2796 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2797 cprev
= info
->icount
;
2798 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2799 set_current_state(TASK_INTERRUPTIBLE
);
2800 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2804 if (signal_pending(current
)) {
2809 /* get new irq counts */
2810 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2811 cnow
= info
->icount
;
2812 set_current_state(TASK_INTERRUPTIBLE
);
2813 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2815 /* if no change, wait aborted for some reason */
2816 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2817 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2822 /* check for change in caller specified modem input */
2823 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2824 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2825 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2826 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2833 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2834 set_current_state(TASK_RUNNING
);
2838 /* return the state of the serial control and status signals
2840 static int tiocmget(struct tty_struct
*tty
)
2842 struct mgsl_struct
*info
= tty
->driver_data
;
2843 unsigned int result
;
2844 unsigned long flags
;
2846 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2847 usc_get_serial_signals(info
);
2848 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2850 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2851 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2852 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2853 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2854 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2855 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2857 if (debug_level
>= DEBUG_LEVEL_INFO
)
2858 printk("%s(%d):%s tiocmget() value=%08X\n",
2859 __FILE__
,__LINE__
, info
->device_name
, result
);
2863 /* set modem control signals (DTR/RTS)
2865 static int tiocmset(struct tty_struct
*tty
,
2866 unsigned int set
, unsigned int clear
)
2868 struct mgsl_struct
*info
= tty
->driver_data
;
2869 unsigned long flags
;
2871 if (debug_level
>= DEBUG_LEVEL_INFO
)
2872 printk("%s(%d):%s tiocmset(%x,%x)\n",
2873 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2875 if (set
& TIOCM_RTS
)
2876 info
->serial_signals
|= SerialSignal_RTS
;
2877 if (set
& TIOCM_DTR
)
2878 info
->serial_signals
|= SerialSignal_DTR
;
2879 if (clear
& TIOCM_RTS
)
2880 info
->serial_signals
&= ~SerialSignal_RTS
;
2881 if (clear
& TIOCM_DTR
)
2882 info
->serial_signals
&= ~SerialSignal_DTR
;
2884 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2885 usc_set_serial_signals(info
);
2886 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2891 /* mgsl_break() Set or clear transmit break condition
2893 * Arguments: tty pointer to tty instance data
2894 * break_state -1=set break condition, 0=clear
2895 * Return Value: error code
2897 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2899 struct mgsl_struct
* info
= tty
->driver_data
;
2900 unsigned long flags
;
2902 if (debug_level
>= DEBUG_LEVEL_INFO
)
2903 printk("%s(%d):mgsl_break(%s,%d)\n",
2904 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2906 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2909 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2910 if (break_state
== -1)
2911 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2913 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2914 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2917 } /* end of mgsl_break() */
2920 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2921 * Return: write counters to the user passed counter struct
2922 * NB: both 1->0 and 0->1 transitions are counted except for
2923 * RI where only 0->1 is counted.
2925 static int msgl_get_icount(struct tty_struct
*tty
,
2926 struct serial_icounter_struct
*icount
)
2929 struct mgsl_struct
* info
= tty
->driver_data
;
2930 struct mgsl_icount cnow
; /* kernel counter temps */
2931 unsigned long flags
;
2933 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2934 cnow
= info
->icount
;
2935 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2937 icount
->cts
= cnow
.cts
;
2938 icount
->dsr
= cnow
.dsr
;
2939 icount
->rng
= cnow
.rng
;
2940 icount
->dcd
= cnow
.dcd
;
2941 icount
->rx
= cnow
.rx
;
2942 icount
->tx
= cnow
.tx
;
2943 icount
->frame
= cnow
.frame
;
2944 icount
->overrun
= cnow
.overrun
;
2945 icount
->parity
= cnow
.parity
;
2946 icount
->brk
= cnow
.brk
;
2947 icount
->buf_overrun
= cnow
.buf_overrun
;
2951 /* mgsl_ioctl() Service an IOCTL request
2955 * tty pointer to tty instance data
2956 * cmd IOCTL command code
2957 * arg command argument/context
2959 * Return Value: 0 if success, otherwise error code
2961 static int mgsl_ioctl(struct tty_struct
*tty
,
2962 unsigned int cmd
, unsigned long arg
)
2964 struct mgsl_struct
* info
= tty
->driver_data
;
2966 if (debug_level
>= DEBUG_LEVEL_INFO
)
2967 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2968 info
->device_name
, cmd
);
2970 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2973 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2974 (cmd
!= TIOCMIWAIT
)) {
2975 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2979 return mgsl_ioctl_common(info
, cmd
, arg
);
2982 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2984 void __user
*argp
= (void __user
*)arg
;
2987 case MGSL_IOCGPARAMS
:
2988 return mgsl_get_params(info
, argp
);
2989 case MGSL_IOCSPARAMS
:
2990 return mgsl_set_params(info
, argp
);
2991 case MGSL_IOCGTXIDLE
:
2992 return mgsl_get_txidle(info
, argp
);
2993 case MGSL_IOCSTXIDLE
:
2994 return mgsl_set_txidle(info
,(int)arg
);
2995 case MGSL_IOCTXENABLE
:
2996 return mgsl_txenable(info
,(int)arg
);
2997 case MGSL_IOCRXENABLE
:
2998 return mgsl_rxenable(info
,(int)arg
);
2999 case MGSL_IOCTXABORT
:
3000 return mgsl_txabort(info
);
3001 case MGSL_IOCGSTATS
:
3002 return mgsl_get_stats(info
, argp
);
3003 case MGSL_IOCWAITEVENT
:
3004 return mgsl_wait_event(info
, argp
);
3005 case MGSL_IOCLOOPTXDONE
:
3006 return mgsl_loopmode_send_done(info
);
3007 /* Wait for modem input (DCD,RI,DSR,CTS) change
3008 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3011 return modem_input_wait(info
,(int)arg
);
3014 return -ENOIOCTLCMD
;
3019 /* mgsl_set_termios()
3021 * Set new termios settings
3025 * tty pointer to tty structure
3026 * termios pointer to buffer to hold returned old termios
3028 * Return Value: None
3030 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3032 struct mgsl_struct
*info
= tty
->driver_data
;
3033 unsigned long flags
;
3035 if (debug_level
>= DEBUG_LEVEL_INFO
)
3036 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3037 tty
->driver
->name
);
3039 mgsl_change_params(info
);
3041 /* Handle transition to B0 status */
3042 if (old_termios
->c_cflag
& CBAUD
&&
3043 !(tty
->termios
.c_cflag
& CBAUD
)) {
3044 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3045 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3046 usc_set_serial_signals(info
);
3047 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3050 /* Handle transition away from B0 status */
3051 if (!(old_termios
->c_cflag
& CBAUD
) &&
3052 tty
->termios
.c_cflag
& CBAUD
) {
3053 info
->serial_signals
|= SerialSignal_DTR
;
3054 if (!(tty
->termios
.c_cflag
& CRTSCTS
) ||
3055 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3056 info
->serial_signals
|= SerialSignal_RTS
;
3058 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3059 usc_set_serial_signals(info
);
3060 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3063 /* Handle turning off CRTSCTS */
3064 if (old_termios
->c_cflag
& CRTSCTS
&&
3065 !(tty
->termios
.c_cflag
& CRTSCTS
)) {
3066 tty
->hw_stopped
= 0;
3070 } /* end of mgsl_set_termios() */
3074 * Called when port is closed. Wait for remaining data to be
3075 * sent. Disable port and free resources.
3079 * tty pointer to open tty structure
3080 * filp pointer to open file object
3082 * Return Value: None
3084 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3086 struct mgsl_struct
* info
= tty
->driver_data
;
3088 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3091 if (debug_level
>= DEBUG_LEVEL_INFO
)
3092 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3093 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3095 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
3098 mutex_lock(&info
->port
.mutex
);
3099 if (info
->port
.flags
& ASYNC_INITIALIZED
)
3100 mgsl_wait_until_sent(tty
, info
->timeout
);
3101 mgsl_flush_buffer(tty
);
3102 tty_ldisc_flush(tty
);
3104 mutex_unlock(&info
->port
.mutex
);
3106 tty_port_close_end(&info
->port
, tty
);
3107 info
->port
.tty
= NULL
;
3109 if (debug_level
>= DEBUG_LEVEL_INFO
)
3110 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3111 tty
->driver
->name
, info
->port
.count
);
3113 } /* end of mgsl_close() */
3115 /* mgsl_wait_until_sent()
3117 * Wait until the transmitter is empty.
3121 * tty pointer to tty info structure
3122 * timeout time to wait for send completion
3124 * Return Value: None
3126 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3128 struct mgsl_struct
* info
= tty
->driver_data
;
3129 unsigned long orig_jiffies
, char_time
;
3134 if (debug_level
>= DEBUG_LEVEL_INFO
)
3135 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3136 __FILE__
,__LINE__
, info
->device_name
);
3138 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3141 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
3144 orig_jiffies
= jiffies
;
3146 /* Set check interval to 1/5 of estimated time to
3147 * send a character, and make it at least 1. The check
3148 * interval should also be less than the timeout.
3149 * Note: use tight timings here to satisfy the NIST-PCTS.
3152 if ( info
->params
.data_rate
) {
3153 char_time
= info
->timeout
/(32 * 5);
3160 char_time
= min_t(unsigned long, char_time
, timeout
);
3162 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3163 info
->params
.mode
== MGSL_MODE_RAW
) {
3164 while (info
->tx_active
) {
3165 msleep_interruptible(jiffies_to_msecs(char_time
));
3166 if (signal_pending(current
))
3168 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3172 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3174 msleep_interruptible(jiffies_to_msecs(char_time
));
3175 if (signal_pending(current
))
3177 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3183 if (debug_level
>= DEBUG_LEVEL_INFO
)
3184 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3185 __FILE__
,__LINE__
, info
->device_name
);
3187 } /* end of mgsl_wait_until_sent() */
3191 * Called by tty_hangup() when a hangup is signaled.
3192 * This is the same as to closing all open files for the port.
3194 * Arguments: tty pointer to associated tty object
3195 * Return Value: None
3197 static void mgsl_hangup(struct tty_struct
*tty
)
3199 struct mgsl_struct
* info
= tty
->driver_data
;
3201 if (debug_level
>= DEBUG_LEVEL_INFO
)
3202 printk("%s(%d):mgsl_hangup(%s)\n",
3203 __FILE__
,__LINE__
, info
->device_name
);
3205 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3208 mgsl_flush_buffer(tty
);
3211 info
->port
.count
= 0;
3212 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
3213 info
->port
.tty
= NULL
;
3215 wake_up_interruptible(&info
->port
.open_wait
);
3217 } /* end of mgsl_hangup() */
3222 * Return true if carrier is raised
3225 static int carrier_raised(struct tty_port
*port
)
3227 unsigned long flags
;
3228 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3230 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3231 usc_get_serial_signals(info
);
3232 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3233 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3236 static void dtr_rts(struct tty_port
*port
, int on
)
3238 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3239 unsigned long flags
;
3241 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3243 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
3245 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3246 usc_set_serial_signals(info
);
3247 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3251 /* block_til_ready()
3253 * Block the current process until the specified port
3254 * is ready to be opened.
3258 * tty pointer to tty info structure
3259 * filp pointer to open file object
3260 * info pointer to device instance data
3262 * Return Value: 0 if success, otherwise error code
3264 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3265 struct mgsl_struct
*info
)
3267 DECLARE_WAITQUEUE(wait
, current
);
3269 bool do_clocal
= false;
3270 bool extra_count
= false;
3271 unsigned long flags
;
3273 struct tty_port
*port
= &info
->port
;
3275 if (debug_level
>= DEBUG_LEVEL_INFO
)
3276 printk("%s(%d):block_til_ready on %s\n",
3277 __FILE__
,__LINE__
, tty
->driver
->name
);
3279 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3280 /* nonblock mode is set or port is not enabled */
3281 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3285 if (tty
->termios
.c_cflag
& CLOCAL
)
3288 /* Wait for carrier detect and the line to become
3289 * free (i.e., not in use by the callout). While we are in
3290 * this loop, port->count is dropped by one, so that
3291 * mgsl_close() knows when to free things. We restore it upon
3292 * exit, either normal or abnormal.
3296 add_wait_queue(&port
->open_wait
, &wait
);
3298 if (debug_level
>= DEBUG_LEVEL_INFO
)
3299 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3300 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3302 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3303 if (!tty_hung_up_p(filp
)) {
3307 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3308 port
->blocked_open
++;
3311 if (C_BAUD(tty
) && test_bit(ASYNCB_INITIALIZED
, &port
->flags
))
3312 tty_port_raise_dtr_rts(port
);
3314 set_current_state(TASK_INTERRUPTIBLE
);
3316 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3317 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3318 -EAGAIN
: -ERESTARTSYS
;
3322 dcd
= tty_port_carrier_raised(&info
->port
);
3324 if (!(port
->flags
& ASYNC_CLOSING
) && (do_clocal
|| dcd
))
3327 if (signal_pending(current
)) {
3328 retval
= -ERESTARTSYS
;
3332 if (debug_level
>= DEBUG_LEVEL_INFO
)
3333 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3334 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3341 set_current_state(TASK_RUNNING
);
3342 remove_wait_queue(&port
->open_wait
, &wait
);
3344 /* FIXME: Racy on hangup during close wait */
3347 port
->blocked_open
--;
3349 if (debug_level
>= DEBUG_LEVEL_INFO
)
3350 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3351 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3354 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3358 } /* end of block_til_ready() */
3360 static int mgsl_install(struct tty_driver
*driver
, struct tty_struct
*tty
)
3362 struct mgsl_struct
*info
;
3363 int line
= tty
->index
;
3365 /* verify range of specified line number */
3366 if (line
>= mgsl_device_count
) {
3367 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3368 __FILE__
, __LINE__
, line
);
3372 /* find the info structure for the specified line */
3373 info
= mgsl_device_list
;
3374 while (info
&& info
->line
!= line
)
3375 info
= info
->next_device
;
3376 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3378 tty
->driver_data
= info
;
3380 return tty_port_install(&info
->port
, driver
, tty
);
3385 * Called when a port is opened. Init and enable port.
3386 * Perform serial-specific initialization for the tty structure.
3388 * Arguments: tty pointer to tty info structure
3389 * filp associated file pointer
3391 * Return Value: 0 if success, otherwise error code
3393 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3395 struct mgsl_struct
*info
= tty
->driver_data
;
3396 unsigned long flags
;
3399 info
->port
.tty
= tty
;
3401 if (debug_level
>= DEBUG_LEVEL_INFO
)
3402 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3403 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3405 /* If port is closing, signal caller to try again */
3406 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
3407 if (info
->port
.flags
& ASYNC_CLOSING
)
3408 interruptible_sleep_on(&info
->port
.close_wait
);
3409 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
3410 -EAGAIN
: -ERESTARTSYS
);
3414 info
->port
.low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3416 spin_lock_irqsave(&info
->netlock
, flags
);
3417 if (info
->netcount
) {
3419 spin_unlock_irqrestore(&info
->netlock
, flags
);
3423 spin_unlock_irqrestore(&info
->netlock
, flags
);
3425 if (info
->port
.count
== 1) {
3426 /* 1st open on this device, init hardware */
3427 retval
= startup(info
);
3432 retval
= block_til_ready(tty
, filp
, info
);
3434 if (debug_level
>= DEBUG_LEVEL_INFO
)
3435 printk("%s(%d):block_til_ready(%s) returned %d\n",
3436 __FILE__
,__LINE__
, info
->device_name
, retval
);
3440 if (debug_level
>= DEBUG_LEVEL_INFO
)
3441 printk("%s(%d):mgsl_open(%s) success\n",
3442 __FILE__
,__LINE__
, info
->device_name
);
3447 if (tty
->count
== 1)
3448 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3449 if(info
->port
.count
)
3455 } /* end of mgsl_open() */
3458 * /proc fs routines....
3461 static inline void line_info(struct seq_file
*m
, struct mgsl_struct
*info
)
3464 unsigned long flags
;
3466 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3467 seq_printf(m
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3468 info
->device_name
, info
->io_base
, info
->irq_level
,
3469 info
->phys_memory_base
, info
->phys_lcr_base
);
3471 seq_printf(m
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3472 info
->device_name
, info
->io_base
,
3473 info
->irq_level
, info
->dma_level
);
3476 /* output current serial signal states */
3477 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3478 usc_get_serial_signals(info
);
3479 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3483 if (info
->serial_signals
& SerialSignal_RTS
)
3484 strcat(stat_buf
, "|RTS");
3485 if (info
->serial_signals
& SerialSignal_CTS
)
3486 strcat(stat_buf
, "|CTS");
3487 if (info
->serial_signals
& SerialSignal_DTR
)
3488 strcat(stat_buf
, "|DTR");
3489 if (info
->serial_signals
& SerialSignal_DSR
)
3490 strcat(stat_buf
, "|DSR");
3491 if (info
->serial_signals
& SerialSignal_DCD
)
3492 strcat(stat_buf
, "|CD");
3493 if (info
->serial_signals
& SerialSignal_RI
)
3494 strcat(stat_buf
, "|RI");
3496 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3497 info
->params
.mode
== MGSL_MODE_RAW
) {
3498 seq_printf(m
, " HDLC txok:%d rxok:%d",
3499 info
->icount
.txok
, info
->icount
.rxok
);
3500 if (info
->icount
.txunder
)
3501 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
3502 if (info
->icount
.txabort
)
3503 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
3504 if (info
->icount
.rxshort
)
3505 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
3506 if (info
->icount
.rxlong
)
3507 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
3508 if (info
->icount
.rxover
)
3509 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
3510 if (info
->icount
.rxcrc
)
3511 seq_printf(m
, " rxcrc:%d", info
->icount
.rxcrc
);
3513 seq_printf(m
, " ASYNC tx:%d rx:%d",
3514 info
->icount
.tx
, info
->icount
.rx
);
3515 if (info
->icount
.frame
)
3516 seq_printf(m
, " fe:%d", info
->icount
.frame
);
3517 if (info
->icount
.parity
)
3518 seq_printf(m
, " pe:%d", info
->icount
.parity
);
3519 if (info
->icount
.brk
)
3520 seq_printf(m
, " brk:%d", info
->icount
.brk
);
3521 if (info
->icount
.overrun
)
3522 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
3525 /* Append serial signal status to end */
3526 seq_printf(m
, " %s\n", stat_buf
+1);
3528 seq_printf(m
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3529 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3532 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3534 u16 Tcsr
= usc_InReg( info
, TCSR
);
3535 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3536 u16 Ticr
= usc_InReg( info
, TICR
);
3537 u16 Rscr
= usc_InReg( info
, RCSR
);
3538 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3539 u16 Ricr
= usc_InReg( info
, RICR
);
3540 u16 Icr
= usc_InReg( info
, ICR
);
3541 u16 Dccr
= usc_InReg( info
, DCCR
);
3542 u16 Tmr
= usc_InReg( info
, TMR
);
3543 u16 Tccr
= usc_InReg( info
, TCCR
);
3544 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3545 seq_printf(m
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3546 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3547 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3549 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3552 /* Called to print information about devices */
3553 static int mgsl_proc_show(struct seq_file
*m
, void *v
)
3555 struct mgsl_struct
*info
;
3557 seq_printf(m
, "synclink driver:%s\n", driver_version
);
3559 info
= mgsl_device_list
;
3562 info
= info
->next_device
;
3567 static int mgsl_proc_open(struct inode
*inode
, struct file
*file
)
3569 return single_open(file
, mgsl_proc_show
, NULL
);
3572 static const struct file_operations mgsl_proc_fops
= {
3573 .owner
= THIS_MODULE
,
3574 .open
= mgsl_proc_open
,
3576 .llseek
= seq_lseek
,
3577 .release
= single_release
,
3580 /* mgsl_allocate_dma_buffers()
3582 * Allocate and format DMA buffers (ISA adapter)
3583 * or format shared memory buffers (PCI adapter).
3585 * Arguments: info pointer to device instance data
3586 * Return Value: 0 if success, otherwise error
3588 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3590 unsigned short BuffersPerFrame
;
3592 info
->last_mem_alloc
= 0;
3594 /* Calculate the number of DMA buffers necessary to hold the */
3595 /* largest allowable frame size. Note: If the max frame size is */
3596 /* not an even multiple of the DMA buffer size then we need to */
3597 /* round the buffer count per frame up one. */
3599 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3600 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3603 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3605 * The PCI adapter has 256KBytes of shared memory to use.
3606 * This is 64 PAGE_SIZE buffers.
3608 * The first page is used for padding at this time so the
3609 * buffer list does not begin at offset 0 of the PCI
3610 * adapter's shared memory.
3612 * The 2nd page is used for the buffer list. A 4K buffer
3613 * list can hold 128 DMA_BUFFER structures at 32 bytes
3616 * This leaves 62 4K pages.
3618 * The next N pages are used for transmit frame(s). We
3619 * reserve enough 4K page blocks to hold the required
3620 * number of transmit dma buffers (num_tx_dma_buffers),
3621 * each of MaxFrameSize size.
3623 * Of the remaining pages (62-N), determine how many can
3624 * be used to receive full MaxFrameSize inbound frames
3626 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3627 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3629 /* Calculate the number of PAGE_SIZE buffers needed for */
3630 /* receive and transmit DMA buffers. */
3633 /* Calculate the number of DMA buffers necessary to */
3634 /* hold 7 max size receive frames and one max size transmit frame. */
3635 /* The receive buffer count is bumped by one so we avoid an */
3636 /* End of List condition if all receive buffers are used when */
3637 /* using linked list DMA buffers. */
3639 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3640 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3643 * limit total TxBuffers & RxBuffers to 62 4K total
3644 * (ala PCI Allocation)
3647 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3648 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3652 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3653 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3654 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3656 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3657 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3658 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3659 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3660 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3661 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3665 mgsl_reset_rx_dma_buffers( info
);
3666 mgsl_reset_tx_dma_buffers( info
);
3670 } /* end of mgsl_allocate_dma_buffers() */
3673 * mgsl_alloc_buffer_list_memory()
3675 * Allocate a common DMA buffer for use as the
3676 * receive and transmit buffer lists.
3678 * A buffer list is a set of buffer entries where each entry contains
3679 * a pointer to an actual buffer and a pointer to the next buffer entry
3680 * (plus some other info about the buffer).
3682 * The buffer entries for a list are built to form a circular list so
3683 * that when the entire list has been traversed you start back at the
3686 * This function allocates memory for just the buffer entries.
3687 * The links (pointer to next entry) are filled in with the physical
3688 * address of the next entry so the adapter can navigate the list
3689 * using bus master DMA. The pointers to the actual buffers are filled
3690 * out later when the actual buffers are allocated.
3692 * Arguments: info pointer to device instance data
3693 * Return Value: 0 if success, otherwise error
3695 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3699 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3700 /* PCI adapter uses shared memory. */
3701 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3702 info
->buffer_list_phys
= info
->last_mem_alloc
;
3703 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3705 /* ISA adapter uses system memory. */
3706 /* The buffer lists are allocated as a common buffer that both */
3707 /* the processor and adapter can access. This allows the driver to */
3708 /* inspect portions of the buffer while other portions are being */
3709 /* updated by the adapter using Bus Master DMA. */
3711 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3712 if (info
->buffer_list
== NULL
)
3714 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3717 /* We got the memory for the buffer entry lists. */
3718 /* Initialize the memory block to all zeros. */
3719 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3721 /* Save virtual address pointers to the receive and */
3722 /* transmit buffer lists. (Receive 1st). These pointers will */
3723 /* be used by the processor to access the lists. */
3724 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3725 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3726 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3729 * Build the links for the buffer entry lists such that
3730 * two circular lists are built. (Transmit and Receive).
3732 * Note: the links are physical addresses
3733 * which are read by the adapter to determine the next
3734 * buffer entry to use.
3737 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3738 /* calculate and store physical address of this buffer entry */
3739 info
->rx_buffer_list
[i
].phys_entry
=
3740 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3742 /* calculate and store physical address of */
3743 /* next entry in cirular list of entries */
3745 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3747 if ( i
< info
->rx_buffer_count
- 1 )
3748 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3751 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3752 /* calculate and store physical address of this buffer entry */
3753 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3754 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3756 /* calculate and store physical address of */
3757 /* next entry in cirular list of entries */
3759 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3760 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3762 if ( i
< info
->tx_buffer_count
- 1 )
3763 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3768 } /* end of mgsl_alloc_buffer_list_memory() */
3770 /* Free DMA buffers allocated for use as the
3771 * receive and transmit buffer lists.
3774 * The data transfer buffers associated with the buffer list
3775 * MUST be freed before freeing the buffer list itself because
3776 * the buffer list contains the information necessary to free
3777 * the individual buffers!
3779 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3781 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3782 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3784 info
->buffer_list
= NULL
;
3785 info
->rx_buffer_list
= NULL
;
3786 info
->tx_buffer_list
= NULL
;
3788 } /* end of mgsl_free_buffer_list_memory() */
3791 * mgsl_alloc_frame_memory()
3793 * Allocate the frame DMA buffers used by the specified buffer list.
3794 * Each DMA buffer will be one memory page in size. This is necessary
3795 * because memory can fragment enough that it may be impossible
3800 * info pointer to device instance data
3801 * BufferList pointer to list of buffer entries
3802 * Buffercount count of buffer entries in buffer list
3804 * Return Value: 0 if success, otherwise -ENOMEM
3806 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3811 /* Allocate page sized buffers for the receive buffer list */
3813 for ( i
= 0; i
< Buffercount
; i
++ ) {
3814 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3815 /* PCI adapter uses shared memory buffers. */
3816 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3817 phys_addr
= info
->last_mem_alloc
;
3818 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3820 /* ISA adapter uses system memory. */
3821 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3822 if (BufferList
[i
].virt_addr
== NULL
)
3824 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3826 BufferList
[i
].phys_addr
= phys_addr
;
3831 } /* end of mgsl_alloc_frame_memory() */
3834 * mgsl_free_frame_memory()
3836 * Free the buffers associated with
3837 * each buffer entry of a buffer list.
3841 * info pointer to device instance data
3842 * BufferList pointer to list of buffer entries
3843 * Buffercount count of buffer entries in buffer list
3845 * Return Value: None
3847 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3852 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3853 if ( BufferList
[i
].virt_addr
) {
3854 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3855 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3856 BufferList
[i
].virt_addr
= NULL
;
3861 } /* end of mgsl_free_frame_memory() */
3863 /* mgsl_free_dma_buffers()
3867 * Arguments: info pointer to device instance data
3868 * Return Value: None
3870 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3872 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3873 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3874 mgsl_free_buffer_list_memory( info
);
3876 } /* end of mgsl_free_dma_buffers() */
3880 * mgsl_alloc_intermediate_rxbuffer_memory()
3882 * Allocate a buffer large enough to hold max_frame_size. This buffer
3883 * is used to pass an assembled frame to the line discipline.
3887 * info pointer to device instance data
3889 * Return Value: 0 if success, otherwise -ENOMEM
3891 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3893 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3894 if ( info
->intermediate_rxbuffer
== NULL
)
3896 /* unused flag buffer to satisfy receive_buf calling interface */
3897 info
->flag_buf
= kzalloc(info
->max_frame_size
, GFP_KERNEL
);
3898 if (!info
->flag_buf
) {
3899 kfree(info
->intermediate_rxbuffer
);
3900 info
->intermediate_rxbuffer
= NULL
;
3905 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3908 * mgsl_free_intermediate_rxbuffer_memory()
3913 * info pointer to device instance data
3915 * Return Value: None
3917 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3919 kfree(info
->intermediate_rxbuffer
);
3920 info
->intermediate_rxbuffer
= NULL
;
3921 kfree(info
->flag_buf
);
3922 info
->flag_buf
= NULL
;
3924 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3927 * mgsl_alloc_intermediate_txbuffer_memory()
3929 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3930 * This buffer is used to load transmit frames into the adapter's dma transfer
3931 * buffers when there is sufficient space.
3935 * info pointer to device instance data
3937 * Return Value: 0 if success, otherwise -ENOMEM
3939 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3943 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3944 printk("%s %s(%d) allocating %d tx holding buffers\n",
3945 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3947 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3949 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3950 info
->tx_holding_buffers
[i
].buffer
=
3951 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3952 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3953 for (--i
; i
>= 0; i
--) {
3954 kfree(info
->tx_holding_buffers
[i
].buffer
);
3955 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3963 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3966 * mgsl_free_intermediate_txbuffer_memory()
3971 * info pointer to device instance data
3973 * Return Value: None
3975 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3979 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3980 kfree(info
->tx_holding_buffers
[i
].buffer
);
3981 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3984 info
->get_tx_holding_index
= 0;
3985 info
->put_tx_holding_index
= 0;
3986 info
->tx_holding_count
= 0;
3988 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3992 * load_next_tx_holding_buffer()
3994 * attempts to load the next buffered tx request into the
3999 * info pointer to device instance data
4001 * Return Value: true if next buffered tx request loaded
4002 * into adapter's tx dma buffer,
4005 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4009 if ( info
->tx_holding_count
) {
4010 /* determine if we have enough tx dma buffers
4011 * to accommodate the next tx frame
4013 struct tx_holding_buffer
*ptx
=
4014 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4015 int num_free
= num_free_tx_dma_buffers(info
);
4016 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4017 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4020 if (num_needed
<= num_free
) {
4021 info
->xmit_cnt
= ptx
->buffer_size
;
4022 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4024 --info
->tx_holding_count
;
4025 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4026 info
->get_tx_holding_index
=0;
4028 /* restart transmit timer */
4029 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4039 * save_tx_buffer_request()
4041 * attempt to store transmit frame request for later transmission
4045 * info pointer to device instance data
4046 * Buffer pointer to buffer containing frame to load
4047 * BufferSize size in bytes of frame in Buffer
4049 * Return Value: 1 if able to store, 0 otherwise
4051 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4053 struct tx_holding_buffer
*ptx
;
4055 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4056 return 0; /* all buffers in use */
4059 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4060 ptx
->buffer_size
= BufferSize
;
4061 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4063 ++info
->tx_holding_count
;
4064 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4065 info
->put_tx_holding_index
=0;
4070 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4072 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4073 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4074 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4077 info
->io_addr_requested
= true;
4079 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4080 info
->device_name
, info
) < 0 ) {
4081 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4082 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4085 info
->irq_requested
= true;
4087 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4088 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4089 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4090 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4093 info
->shared_mem_requested
= true;
4094 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4095 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4096 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4099 info
->lcr_mem_requested
= true;
4101 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4103 if (!info
->memory_base
) {
4104 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4105 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4109 if ( !mgsl_memory_test(info
) ) {
4110 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4111 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4115 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4117 if (!info
->lcr_base
) {
4118 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4119 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4122 info
->lcr_base
+= info
->lcr_offset
;
4125 /* claim DMA channel */
4127 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4128 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4129 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4130 mgsl_release_resources( info
);
4133 info
->dma_requested
= true;
4135 /* ISA adapter uses bus master DMA */
4136 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4137 enable_dma(info
->dma_level
);
4140 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4141 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4142 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4148 mgsl_release_resources(info
);
4151 } /* end of mgsl_claim_resources() */
4153 static void mgsl_release_resources(struct mgsl_struct
*info
)
4155 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4156 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4157 __FILE__
,__LINE__
,info
->device_name
);
4159 if ( info
->irq_requested
) {
4160 free_irq(info
->irq_level
, info
);
4161 info
->irq_requested
= false;
4163 if ( info
->dma_requested
) {
4164 disable_dma(info
->dma_level
);
4165 free_dma(info
->dma_level
);
4166 info
->dma_requested
= false;
4168 mgsl_free_dma_buffers(info
);
4169 mgsl_free_intermediate_rxbuffer_memory(info
);
4170 mgsl_free_intermediate_txbuffer_memory(info
);
4172 if ( info
->io_addr_requested
) {
4173 release_region(info
->io_base
,info
->io_addr_size
);
4174 info
->io_addr_requested
= false;
4176 if ( info
->shared_mem_requested
) {
4177 release_mem_region(info
->phys_memory_base
,0x40000);
4178 info
->shared_mem_requested
= false;
4180 if ( info
->lcr_mem_requested
) {
4181 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4182 info
->lcr_mem_requested
= false;
4184 if (info
->memory_base
){
4185 iounmap(info
->memory_base
);
4186 info
->memory_base
= NULL
;
4188 if (info
->lcr_base
){
4189 iounmap(info
->lcr_base
- info
->lcr_offset
);
4190 info
->lcr_base
= NULL
;
4193 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4194 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4195 __FILE__
,__LINE__
,info
->device_name
);
4197 } /* end of mgsl_release_resources() */
4199 /* mgsl_add_device()
4201 * Add the specified device instance data structure to the
4202 * global linked list of devices and increment the device count.
4204 * Arguments: info pointer to device instance data
4205 * Return Value: None
4207 static void mgsl_add_device( struct mgsl_struct
*info
)
4209 info
->next_device
= NULL
;
4210 info
->line
= mgsl_device_count
;
4211 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4213 if (info
->line
< MAX_TOTAL_DEVICES
) {
4214 if (maxframe
[info
->line
])
4215 info
->max_frame_size
= maxframe
[info
->line
];
4217 if (txdmabufs
[info
->line
]) {
4218 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4219 if (info
->num_tx_dma_buffers
< 1)
4220 info
->num_tx_dma_buffers
= 1;
4223 if (txholdbufs
[info
->line
]) {
4224 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4225 if (info
->num_tx_holding_buffers
< 1)
4226 info
->num_tx_holding_buffers
= 1;
4227 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4228 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4232 mgsl_device_count
++;
4234 if ( !mgsl_device_list
)
4235 mgsl_device_list
= info
;
4237 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4238 while( current_dev
->next_device
)
4239 current_dev
= current_dev
->next_device
;
4240 current_dev
->next_device
= info
;
4243 if ( info
->max_frame_size
< 4096 )
4244 info
->max_frame_size
= 4096;
4245 else if ( info
->max_frame_size
> 65535 )
4246 info
->max_frame_size
= 65535;
4248 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4249 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4250 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4251 info
->phys_memory_base
, info
->phys_lcr_base
,
4252 info
->max_frame_size
);
4254 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4255 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4256 info
->max_frame_size
);
4259 #if SYNCLINK_GENERIC_HDLC
4263 } /* end of mgsl_add_device() */
4265 static const struct tty_port_operations mgsl_port_ops
= {
4266 .carrier_raised
= carrier_raised
,
4271 /* mgsl_allocate_device()
4273 * Allocate and initialize a device instance structure
4276 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4278 static struct mgsl_struct
* mgsl_allocate_device(void)
4280 struct mgsl_struct
*info
;
4282 info
= kzalloc(sizeof(struct mgsl_struct
),
4286 printk("Error can't allocate device instance data\n");
4288 tty_port_init(&info
->port
);
4289 info
->port
.ops
= &mgsl_port_ops
;
4290 info
->magic
= MGSL_MAGIC
;
4291 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4292 info
->max_frame_size
= 4096;
4293 info
->port
.close_delay
= 5*HZ
/10;
4294 info
->port
.closing_wait
= 30*HZ
;
4295 init_waitqueue_head(&info
->status_event_wait_q
);
4296 init_waitqueue_head(&info
->event_wait_q
);
4297 spin_lock_init(&info
->irq_spinlock
);
4298 spin_lock_init(&info
->netlock
);
4299 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4300 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4301 info
->num_tx_dma_buffers
= 1;
4302 info
->num_tx_holding_buffers
= 0;
4307 } /* end of mgsl_allocate_device()*/
4309 static const struct tty_operations mgsl_ops
= {
4310 .install
= mgsl_install
,
4312 .close
= mgsl_close
,
4313 .write
= mgsl_write
,
4314 .put_char
= mgsl_put_char
,
4315 .flush_chars
= mgsl_flush_chars
,
4316 .write_room
= mgsl_write_room
,
4317 .chars_in_buffer
= mgsl_chars_in_buffer
,
4318 .flush_buffer
= mgsl_flush_buffer
,
4319 .ioctl
= mgsl_ioctl
,
4320 .throttle
= mgsl_throttle
,
4321 .unthrottle
= mgsl_unthrottle
,
4322 .send_xchar
= mgsl_send_xchar
,
4323 .break_ctl
= mgsl_break
,
4324 .wait_until_sent
= mgsl_wait_until_sent
,
4325 .set_termios
= mgsl_set_termios
,
4327 .start
= mgsl_start
,
4328 .hangup
= mgsl_hangup
,
4329 .tiocmget
= tiocmget
,
4330 .tiocmset
= tiocmset
,
4331 .get_icount
= msgl_get_icount
,
4332 .proc_fops
= &mgsl_proc_fops
,
4336 * perform tty device initialization
4338 static int mgsl_init_tty(void)
4342 serial_driver
= alloc_tty_driver(128);
4346 serial_driver
->driver_name
= "synclink";
4347 serial_driver
->name
= "ttySL";
4348 serial_driver
->major
= ttymajor
;
4349 serial_driver
->minor_start
= 64;
4350 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4351 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4352 serial_driver
->init_termios
= tty_std_termios
;
4353 serial_driver
->init_termios
.c_cflag
=
4354 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4355 serial_driver
->init_termios
.c_ispeed
= 9600;
4356 serial_driver
->init_termios
.c_ospeed
= 9600;
4357 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4358 tty_set_operations(serial_driver
, &mgsl_ops
);
4359 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4360 printk("%s(%d):Couldn't register serial driver\n",
4362 put_tty_driver(serial_driver
);
4363 serial_driver
= NULL
;
4367 printk("%s %s, tty major#%d\n",
4368 driver_name
, driver_version
,
4369 serial_driver
->major
);
4373 /* enumerate user specified ISA adapters
4375 static void mgsl_enum_isa_devices(void)
4377 struct mgsl_struct
*info
;
4380 /* Check for user specified ISA devices */
4382 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4383 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4384 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4385 io
[i
], irq
[i
], dma
[i
] );
4387 info
= mgsl_allocate_device();
4389 /* error allocating device instance data */
4390 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4391 printk( "can't allocate device instance data.\n");
4395 /* Copy user configuration info to device instance data */
4396 info
->io_base
= (unsigned int)io
[i
];
4397 info
->irq_level
= (unsigned int)irq
[i
];
4398 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4399 info
->dma_level
= (unsigned int)dma
[i
];
4400 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4401 info
->io_addr_size
= 16;
4402 info
->irq_flags
= 0;
4404 mgsl_add_device( info
);
4408 static void synclink_cleanup(void)
4411 struct mgsl_struct
*info
;
4412 struct mgsl_struct
*tmp
;
4414 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4416 if (serial_driver
) {
4417 if ((rc
= tty_unregister_driver(serial_driver
)))
4418 printk("%s(%d) failed to unregister tty driver err=%d\n",
4419 __FILE__
,__LINE__
,rc
);
4420 put_tty_driver(serial_driver
);
4423 info
= mgsl_device_list
;
4425 #if SYNCLINK_GENERIC_HDLC
4428 mgsl_release_resources(info
);
4430 info
= info
->next_device
;
4431 tty_port_destroy(&tmp
->port
);
4436 pci_unregister_driver(&synclink_pci_driver
);
4439 static int __init
synclink_init(void)
4443 if (break_on_load
) {
4444 mgsl_get_text_ptr();
4448 printk("%s %s\n", driver_name
, driver_version
);
4450 mgsl_enum_isa_devices();
4451 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4452 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4454 pci_registered
= true;
4456 if ((rc
= mgsl_init_tty()) < 0)
4466 static void __exit
synclink_exit(void)
4471 module_init(synclink_init
);
4472 module_exit(synclink_exit
);
4477 * Issue a USC Receive/Transmit command to the
4478 * Channel Command/Address Register (CCAR).
4482 * The command is encoded in the most significant 5 bits <15..11>
4483 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4484 * and Bits <6..0> must be written as zeros.
4488 * info pointer to device information structure
4489 * Cmd command mask (use symbolic macros)
4495 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4497 /* output command to CCAR in bits <15..11> */
4498 /* preserve bits <10..7>, bits <6..0> must be zero */
4500 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4502 /* Read to flush write to CCAR */
4503 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4504 inw( info
->io_base
+ CCAR
);
4506 } /* end of usc_RTCmd() */
4511 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4515 * info pointer to device information structure
4516 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4522 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4524 /* write command mask to DCAR */
4525 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4527 /* Read to flush write to DCAR */
4528 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4529 inw( info
->io_base
);
4531 } /* end of usc_DmaCmd() */
4536 * Write a 16-bit value to a USC DMA register
4540 * info pointer to device info structure
4541 * RegAddr register address (number) for write
4542 * RegValue 16-bit value to write to register
4549 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4551 /* Note: The DCAR is located at the adapter base address */
4552 /* Note: must preserve state of BIT8 in DCAR */
4554 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4555 outw( RegValue
, info
->io_base
);
4557 /* Read to flush write to DCAR */
4558 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4559 inw( info
->io_base
);
4561 } /* end of usc_OutDmaReg() */
4566 * Read a 16-bit value from a DMA register
4570 * info pointer to device info structure
4571 * RegAddr register address (number) to read from
4575 * The 16-bit value read from register
4578 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4580 /* Note: The DCAR is located at the adapter base address */
4581 /* Note: must preserve state of BIT8 in DCAR */
4583 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4584 return inw( info
->io_base
);
4586 } /* end of usc_InDmaReg() */
4592 * Write a 16-bit value to a USC serial channel register
4596 * info pointer to device info structure
4597 * RegAddr register address (number) to write to
4598 * RegValue 16-bit value to write to register
4605 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4607 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4608 outw( RegValue
, info
->io_base
+ CCAR
);
4610 /* Read to flush write to CCAR */
4611 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4612 inw( info
->io_base
+ CCAR
);
4614 } /* end of usc_OutReg() */
4619 * Reads a 16-bit value from a USC serial channel register
4623 * info pointer to device extension
4624 * RegAddr register address (number) to read from
4628 * 16-bit value read from register
4630 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4632 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4633 return inw( info
->io_base
+ CCAR
);
4635 } /* end of usc_InReg() */
4637 /* usc_set_sdlc_mode()
4639 * Set up the adapter for SDLC DMA communications.
4641 * Arguments: info pointer to device instance data
4642 * Return Value: NONE
4644 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4650 * determine if the IUSC on the adapter is pre-SL1660. If
4651 * not, take advantage of the UnderWait feature of more
4652 * modern chips. If an underrun occurs and this bit is set,
4653 * the transmitter will idle the programmed idle pattern
4654 * until the driver has time to service the underrun. Otherwise,
4655 * the dma controller may get the cycles previously requested
4656 * and begin transmitting queued tx data.
4658 usc_OutReg(info
,TMCR
,0x1f);
4659 RegValue
=usc_InReg(info
,TMDR
);
4660 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4662 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4665 ** Channel Mode Register (CMR)
4667 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4668 ** <13> 0 0 = Transmit Disabled (initially)
4669 ** <12> 0 1 = Consecutive Idles share common 0
4670 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4671 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4672 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4674 ** 1000 1110 0000 0110 = 0x8e06
4678 /*--------------------------------------------------
4679 * ignore user options for UnderRun Actions and
4681 *--------------------------------------------------*/
4685 /* Channel mode Register (CMR)
4687 * <15..14> 00 Tx Sub modes, Underrun Action
4688 * <13> 0 1 = Send Preamble before opening flag
4689 * <12> 0 1 = Consecutive Idles share common 0
4690 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4691 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4692 * <3..0> 0110 Receiver mode = HDLC/SDLC
4694 * 0000 0110 0000 0110 = 0x0606
4696 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4697 RegValue
= 0x0001; /* Set Receive mode = external sync */
4699 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4700 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4704 * CMR <15> 0 Don't send CRC on Tx Underrun
4705 * CMR <14> x undefined
4706 * CMR <13> 0 Send preamble before openning sync
4707 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4710 * CMR <11-8) 0100 MonoSync
4712 * 0x00 0100 xxxx xxxx 04xx
4720 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4722 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4724 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4725 RegValue
|= BIT15
+ BIT14
;
4728 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4732 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4733 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4736 if ( info
->params
.addr_filter
!= 0xff )
4738 /* set up receive address filtering */
4739 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4743 usc_OutReg( info
, CMR
, RegValue
);
4744 info
->cmr_value
= RegValue
;
4746 /* Receiver mode Register (RMR)
4748 * <15..13> 000 encoding
4749 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4750 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4751 * <9> 0 1 = Include Receive chars in CRC
4752 * <8> 1 1 = Use Abort/PE bit as abort indicator
4753 * <7..6> 00 Even parity
4754 * <5> 0 parity disabled
4755 * <4..2> 000 Receive Char Length = 8 bits
4756 * <1..0> 00 Disable Receiver
4758 * 0000 0101 0000 0000 = 0x0500
4763 switch ( info
->params
.encoding
) {
4764 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4765 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4766 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4767 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4768 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4769 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4770 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4773 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4775 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4776 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4778 usc_OutReg( info
, RMR
, RegValue
);
4780 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4781 /* When an opening flag of an SDLC frame is recognized the */
4782 /* Receive Character count (RCC) is loaded with the value in */
4783 /* RCLR. The RCC is decremented for each received byte. The */
4784 /* value of RCC is stored after the closing flag of the frame */
4785 /* allowing the frame size to be computed. */
4787 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4789 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4791 /* Receive Interrupt Control Register (RICR)
4793 * <15..8> ? RxFIFO DMA Request Level
4794 * <7> 0 Exited Hunt IA (Interrupt Arm)
4795 * <6> 0 Idle Received IA
4796 * <5> 0 Break/Abort IA
4798 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4800 * <1> 1 Rx Overrun IA
4801 * <0> 0 Select TC0 value for readback
4803 * 0000 0000 0000 1000 = 0x000a
4806 /* Carry over the Exit Hunt and Idle Received bits */
4807 /* in case they have been armed by usc_ArmEvents. */
4809 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4811 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4812 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4814 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4816 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4818 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4819 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4821 /* Transmit mode Register (TMR)
4823 * <15..13> 000 encoding
4824 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4825 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4826 * <9> 0 1 = Tx CRC Enabled
4827 * <8> 0 1 = Append CRC to end of transmit frame
4828 * <7..6> 00 Transmit parity Even
4829 * <5> 0 Transmit parity Disabled
4830 * <4..2> 000 Tx Char Length = 8 bits
4831 * <1..0> 00 Disable Transmitter
4833 * 0000 0100 0000 0000 = 0x0400
4838 switch ( info
->params
.encoding
) {
4839 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4840 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4841 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4842 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4843 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4844 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4845 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4848 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4849 RegValue
|= BIT9
+ BIT8
;
4850 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4851 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4853 usc_OutReg( info
, TMR
, RegValue
);
4855 usc_set_txidle( info
);
4858 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4860 /* Transmit Interrupt Control Register (TICR)
4862 * <15..8> ? Transmit FIFO DMA Level
4863 * <7> 0 Present IA (Interrupt Arm)
4864 * <6> 0 Idle Sent IA
4865 * <5> 1 Abort Sent IA
4866 * <4> 1 EOF/EOM Sent IA
4868 * <2> 1 1 = Wait for SW Trigger to Start Frame
4869 * <1> 1 Tx Underrun IA
4870 * <0> 0 TC0 constant on read back
4872 * 0000 0000 0011 0110 = 0x0036
4875 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4876 usc_OutReg( info
, TICR
, 0x0736 );
4878 usc_OutReg( info
, TICR
, 0x1436 );
4880 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4881 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4884 ** Transmit Command/Status Register (TCSR)
4886 ** <15..12> 0000 TCmd
4887 ** <11> 0/1 UnderWait
4888 ** <10..08> 000 TxIdle
4892 ** <4> x EOF/EOM Sent
4898 ** 0000 0000 0000 0000 = 0x0000
4900 info
->tcsr_value
= 0;
4903 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4905 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4907 /* Clock mode Control Register (CMCR)
4909 * <15..14> 00 counter 1 Source = Disabled
4910 * <13..12> 00 counter 0 Source = Disabled
4911 * <11..10> 11 BRG1 Input is TxC Pin
4912 * <9..8> 11 BRG0 Input is TxC Pin
4913 * <7..6> 01 DPLL Input is BRG1 Output
4914 * <5..3> XXX TxCLK comes from Port 0
4915 * <2..0> XXX RxCLK comes from Port 1
4917 * 0000 1111 0111 0111 = 0x0f77
4922 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4923 RegValue
|= 0x0003; /* RxCLK from DPLL */
4924 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4925 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4926 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4927 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4929 RegValue
|= 0x0007; /* RxCLK from Port1 */
4931 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4932 RegValue
|= 0x0018; /* TxCLK from DPLL */
4933 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4934 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4935 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4936 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4938 RegValue
|= 0x0030; /* TxCLK from Port0 */
4940 usc_OutReg( info
, CMCR
, RegValue
);
4943 /* Hardware Configuration Register (HCR)
4945 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4946 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4947 * <12> 0 CVOK:0=report code violation in biphase
4948 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4949 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4950 * <7..6> 00 reserved
4951 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4953 * <3..2> 00 reserved
4954 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4960 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
4965 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4966 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4968 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4969 XtalSpeed
= 11059200;
4971 XtalSpeed
= 14745600;
4973 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4977 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4984 /* Tc = (Xtal/Speed) - 1 */
4985 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4986 /* then rounding up gives a more precise time constant. Instead */
4987 /* of rounding up and then subtracting 1 we just don't subtract */
4988 /* the one in this case. */
4990 /*--------------------------------------------------
4991 * ejz: for DPLL mode, application should use the
4992 * same clock speed as the partner system, even
4993 * though clocking is derived from the input RxData.
4994 * In case the user uses a 0 for the clock speed,
4995 * default to 0xffffffff and don't try to divide by
4997 *--------------------------------------------------*/
4998 if ( info
->params
.clock_speed
)
5000 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5001 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5002 / info
->params
.clock_speed
) )
5009 /* Write 16-bit Time Constant for BRG1 */
5010 usc_OutReg( info
, TC1R
, Tc
);
5012 RegValue
|= BIT4
; /* enable BRG1 */
5014 switch ( info
->params
.encoding
) {
5015 case HDLC_ENCODING_NRZ
:
5016 case HDLC_ENCODING_NRZB
:
5017 case HDLC_ENCODING_NRZI_MARK
:
5018 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5019 case HDLC_ENCODING_BIPHASE_MARK
:
5020 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5021 case HDLC_ENCODING_BIPHASE_LEVEL
:
5022 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5026 usc_OutReg( info
, HCR
, RegValue
);
5029 /* Channel Control/status Register (CCSR)
5031 * <15> X RCC FIFO Overflow status (RO)
5032 * <14> X RCC FIFO Not Empty status (RO)
5033 * <13> 0 1 = Clear RCC FIFO (WO)
5034 * <12> X DPLL Sync (RW)
5035 * <11> X DPLL 2 Missed Clocks status (RO)
5036 * <10> X DPLL 1 Missed Clock status (RO)
5037 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5038 * <7> X SDLC Loop On status (RO)
5039 * <6> X SDLC Loop Send status (RO)
5040 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5041 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5042 * <1..0> 00 reserved
5044 * 0000 0000 0010 0000 = 0x0020
5047 usc_OutReg( info
, CCSR
, 0x1020 );
5050 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5051 usc_OutReg( info
, SICR
,
5052 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5056 /* enable Master Interrupt Enable bit (MIE) */
5057 usc_EnableMasterIrqBit( info
);
5059 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5060 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5062 /* arm RCC underflow interrupt */
5063 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5064 usc_EnableInterrupts(info
, MISC
);
5067 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5068 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5069 info
->mbre_bit
= BIT8
;
5070 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5072 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5073 /* Enable DMAEN (Port 7, Bit 14) */
5074 /* This connects the DMA request signal to the ISA bus */
5075 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5078 /* DMA Control Register (DCR)
5080 * <15..14> 10 Priority mode = Alternating Tx/Rx
5081 * 01 Rx has priority
5082 * 00 Tx has priority
5084 * <13> 1 Enable Priority Preempt per DCR<15..14>
5085 * (WARNING DCR<11..10> must be 00 when this is 1)
5086 * 0 Choose activate channel per DCR<11..10>
5088 * <12> 0 Little Endian for Array/List
5089 * <11..10> 00 Both Channels can use each bus grant
5090 * <9..6> 0000 reserved
5091 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5092 * <4> 0 1 = drive D/C and S/D pins
5093 * <3> 1 1 = Add one wait state to all DMA cycles.
5094 * <2> 0 1 = Strobe /UAS on every transfer.
5095 * <1..0> 11 Addr incrementing only affects LS24 bits
5097 * 0110 0000 0000 1011 = 0x600b
5100 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5101 /* PCI adapter does not need DMA wait state */
5102 usc_OutDmaReg( info
, DCR
, 0xa00b );
5105 usc_OutDmaReg( info
, DCR
, 0x800b );
5108 /* Receive DMA mode Register (RDMR)
5110 * <15..14> 11 DMA mode = Linked List Buffer mode
5111 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5112 * <12> 1 Clear count of List Entry after fetching
5113 * <11..10> 00 Address mode = Increment
5114 * <9> 1 Terminate Buffer on RxBound
5115 * <8> 0 Bus Width = 16bits
5116 * <7..0> ? status Bits (write as 0s)
5118 * 1111 0010 0000 0000 = 0xf200
5121 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5124 /* Transmit DMA mode Register (TDMR)
5126 * <15..14> 11 DMA mode = Linked List Buffer mode
5127 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5128 * <12> 1 Clear count of List Entry after fetching
5129 * <11..10> 00 Address mode = Increment
5130 * <9> 1 Terminate Buffer on end of frame
5131 * <8> 0 Bus Width = 16bits
5132 * <7..0> ? status Bits (Read Only so write as 0)
5134 * 1111 0010 0000 0000 = 0xf200
5137 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5140 /* DMA Interrupt Control Register (DICR)
5142 * <15> 1 DMA Interrupt Enable
5143 * <14> 0 1 = Disable IEO from USC
5144 * <13> 0 1 = Don't provide vector during IntAck
5145 * <12> 1 1 = Include status in Vector
5146 * <10..2> 0 reserved, Must be 0s
5147 * <1> 0 1 = Rx DMA Interrupt Enabled
5148 * <0> 0 1 = Tx DMA Interrupt Enabled
5150 * 1001 0000 0000 0000 = 0x9000
5153 usc_OutDmaReg( info
, DICR
, 0x9000 );
5155 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5156 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5157 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5159 /* Channel Control Register (CCR)
5161 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5162 * <13> 0 Trigger Tx on SW Command Disabled
5163 * <12> 0 Flag Preamble Disabled
5164 * <11..10> 00 Preamble Length
5165 * <9..8> 00 Preamble Pattern
5166 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5167 * <5> 0 Trigger Rx on SW Command Disabled
5170 * 1000 0000 1000 0000 = 0x8080
5175 switch ( info
->params
.preamble_length
) {
5176 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5177 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5178 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5181 switch ( info
->params
.preamble
) {
5182 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5183 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5184 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5185 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5188 usc_OutReg( info
, CCR
, RegValue
);
5192 * Burst/Dwell Control Register
5194 * <15..8> 0x20 Maximum number of transfers per bus grant
5195 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5198 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5199 /* don't limit bus occupancy on PCI adapter */
5200 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5203 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5205 usc_stop_transmitter(info
);
5206 usc_stop_receiver(info
);
5208 } /* end of usc_set_sdlc_mode() */
5210 /* usc_enable_loopback()
5212 * Set the 16C32 for internal loopback mode.
5213 * The TxCLK and RxCLK signals are generated from the BRG0 and
5214 * the TxD is looped back to the RxD internally.
5216 * Arguments: info pointer to device instance data
5217 * enable 1 = enable loopback, 0 = disable
5218 * Return Value: None
5220 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5223 /* blank external TXD output */
5224 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5226 /* Clock mode Control Register (CMCR)
5228 * <15..14> 00 counter 1 Disabled
5229 * <13..12> 00 counter 0 Disabled
5230 * <11..10> 11 BRG1 Input is TxC Pin
5231 * <9..8> 11 BRG0 Input is TxC Pin
5232 * <7..6> 01 DPLL Input is BRG1 Output
5233 * <5..3> 100 TxCLK comes from BRG0
5234 * <2..0> 100 RxCLK comes from BRG0
5236 * 0000 1111 0110 0100 = 0x0f64
5239 usc_OutReg( info
, CMCR
, 0x0f64 );
5241 /* Write 16-bit Time Constant for BRG0 */
5242 /* use clock speed if available, otherwise use 8 for diagnostics */
5243 if (info
->params
.clock_speed
) {
5244 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5245 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5247 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5249 usc_OutReg(info
, TC0R
, (u16
)8);
5251 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5252 mode = Continuous Set Bit 0 to enable BRG0. */
5253 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5255 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5256 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5258 /* set Internal Data loopback mode */
5259 info
->loopback_bits
= 0x300;
5260 outw( 0x0300, info
->io_base
+ CCAR
);
5262 /* enable external TXD output */
5263 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5265 /* clear Internal Data loopback mode */
5266 info
->loopback_bits
= 0;
5267 outw( 0,info
->io_base
+ CCAR
);
5270 } /* end of usc_enable_loopback() */
5272 /* usc_enable_aux_clock()
5274 * Enabled the AUX clock output at the specified frequency.
5278 * info pointer to device extension
5279 * data_rate data rate of clock in bits per second
5280 * A data rate of 0 disables the AUX clock.
5282 * Return Value: None
5284 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5290 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5291 XtalSpeed
= 11059200;
5293 XtalSpeed
= 14745600;
5296 /* Tc = (Xtal/Speed) - 1 */
5297 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5298 /* then rounding up gives a more precise time constant. Instead */
5299 /* of rounding up and then subtracting 1 we just don't subtract */
5300 /* the one in this case. */
5303 Tc
= (u16
)(XtalSpeed
/data_rate
);
5304 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5307 /* Write 16-bit Time Constant for BRG0 */
5308 usc_OutReg( info
, TC0R
, Tc
);
5311 * Hardware Configuration Register (HCR)
5312 * Clear Bit 1, BRG0 mode = Continuous
5313 * Set Bit 0 to enable BRG0.
5316 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5318 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5319 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5321 /* data rate == 0 so turn off BRG0 */
5322 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5325 } /* end of usc_enable_aux_clock() */
5329 * usc_process_rxoverrun_sync()
5331 * This function processes a receive overrun by resetting the
5332 * receive DMA buffers and issuing a Purge Rx FIFO command
5333 * to allow the receiver to continue receiving.
5337 * info pointer to device extension
5339 * Return Value: None
5341 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5345 int frame_start_index
;
5346 bool start_of_frame_found
= false;
5347 bool end_of_frame_found
= false;
5348 bool reprogram_dma
= false;
5350 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5353 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5354 usc_RCmd( info
, RCmd_EnterHuntmode
);
5355 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5357 /* CurrentRxBuffer points to the 1st buffer of the next */
5358 /* possibly available receive frame. */
5360 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5362 /* Search for an unfinished string of buffers. This means */
5363 /* that a receive frame started (at least one buffer with */
5364 /* count set to zero) but there is no terminiting buffer */
5365 /* (status set to non-zero). */
5367 while( !buffer_list
[end_index
].count
)
5369 /* Count field has been reset to zero by 16C32. */
5370 /* This buffer is currently in use. */
5372 if ( !start_of_frame_found
)
5374 start_of_frame_found
= true;
5375 frame_start_index
= end_index
;
5376 end_of_frame_found
= false;
5379 if ( buffer_list
[end_index
].status
)
5381 /* Status field has been set by 16C32. */
5382 /* This is the last buffer of a received frame. */
5384 /* We want to leave the buffers for this frame intact. */
5385 /* Move on to next possible frame. */
5387 start_of_frame_found
= false;
5388 end_of_frame_found
= true;
5391 /* advance to next buffer entry in linked list */
5393 if ( end_index
== info
->rx_buffer_count
)
5396 if ( start_index
== end_index
)
5398 /* The entire list has been searched with all Counts == 0 and */
5399 /* all Status == 0. The receive buffers are */
5400 /* completely screwed, reset all receive buffers! */
5401 mgsl_reset_rx_dma_buffers( info
);
5402 frame_start_index
= 0;
5403 start_of_frame_found
= false;
5404 reprogram_dma
= true;
5409 if ( start_of_frame_found
&& !end_of_frame_found
)
5411 /* There is an unfinished string of receive DMA buffers */
5412 /* as a result of the receiver overrun. */
5414 /* Reset the buffers for the unfinished frame */
5415 /* and reprogram the receive DMA controller to start */
5416 /* at the 1st buffer of unfinished frame. */
5418 start_index
= frame_start_index
;
5422 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5424 /* Adjust index for wrap around. */
5425 if ( start_index
== info
->rx_buffer_count
)
5428 } while( start_index
!= end_index
);
5430 reprogram_dma
= true;
5433 if ( reprogram_dma
)
5435 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5436 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5437 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5439 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5441 /* This empties the receive FIFO and loads the RCC with RCLR */
5442 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5444 /* program 16C32 with physical address of 1st DMA buffer entry */
5445 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5446 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5447 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5449 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5450 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5451 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5453 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5454 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5456 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5457 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5458 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5459 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5460 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5462 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5466 /* This empties the receive FIFO and loads the RCC with RCLR */
5467 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5468 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5471 } /* end of usc_process_rxoverrun_sync() */
5473 /* usc_stop_receiver()
5475 * Disable USC receiver
5477 * Arguments: info pointer to device instance data
5478 * Return Value: None
5480 static void usc_stop_receiver( struct mgsl_struct
*info
)
5482 if (debug_level
>= DEBUG_LEVEL_ISR
)
5483 printk("%s(%d):usc_stop_receiver(%s)\n",
5484 __FILE__
,__LINE__
, info
->device_name
);
5486 /* Disable receive DMA channel. */
5487 /* This also disables receive DMA channel interrupts */
5488 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5490 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5491 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5492 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5494 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5496 /* This empties the receive FIFO and loads the RCC with RCLR */
5497 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5498 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5500 info
->rx_enabled
= false;
5501 info
->rx_overflow
= false;
5502 info
->rx_rcc_underrun
= false;
5504 } /* end of stop_receiver() */
5506 /* usc_start_receiver()
5508 * Enable the USC receiver
5510 * Arguments: info pointer to device instance data
5511 * Return Value: None
5513 static void usc_start_receiver( struct mgsl_struct
*info
)
5517 if (debug_level
>= DEBUG_LEVEL_ISR
)
5518 printk("%s(%d):usc_start_receiver(%s)\n",
5519 __FILE__
,__LINE__
, info
->device_name
);
5521 mgsl_reset_rx_dma_buffers( info
);
5522 usc_stop_receiver( info
);
5524 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5525 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5527 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5528 info
->params
.mode
== MGSL_MODE_RAW
) {
5529 /* DMA mode Transfers */
5530 /* Program the DMA controller. */
5531 /* Enable the DMA controller end of buffer interrupt. */
5533 /* program 16C32 with physical address of 1st DMA buffer entry */
5534 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5535 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5536 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5538 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5539 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5540 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5542 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5543 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5545 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5546 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5547 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5548 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5549 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5551 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5553 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5554 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5555 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5557 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5558 usc_RCmd( info
, RCmd_EnterHuntmode
);
5560 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5563 usc_OutReg( info
, CCSR
, 0x1020 );
5565 info
->rx_enabled
= true;
5567 } /* end of usc_start_receiver() */
5569 /* usc_start_transmitter()
5571 * Enable the USC transmitter and send a transmit frame if
5572 * one is loaded in the DMA buffers.
5574 * Arguments: info pointer to device instance data
5575 * Return Value: None
5577 static void usc_start_transmitter( struct mgsl_struct
*info
)
5580 unsigned int FrameSize
;
5582 if (debug_level
>= DEBUG_LEVEL_ISR
)
5583 printk("%s(%d):usc_start_transmitter(%s)\n",
5584 __FILE__
,__LINE__
, info
->device_name
);
5586 if ( info
->xmit_cnt
) {
5588 /* If auto RTS enabled and RTS is inactive, then assert */
5589 /* RTS and set a flag indicating that the driver should */
5590 /* negate RTS when the transmission completes. */
5592 info
->drop_rts_on_tx_done
= false;
5594 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5595 usc_get_serial_signals( info
);
5596 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5597 info
->serial_signals
|= SerialSignal_RTS
;
5598 usc_set_serial_signals( info
);
5599 info
->drop_rts_on_tx_done
= true;
5604 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5605 if ( !info
->tx_active
) {
5606 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5607 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5608 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5609 usc_load_txfifo(info
);
5612 /* Disable transmit DMA controller while programming. */
5613 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5615 /* Transmit DMA buffer is loaded, so program USC */
5616 /* to send the frame contained in the buffers. */
5618 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5620 /* if operating in Raw sync mode, reset the rcc component
5621 * of the tx dma buffer entry, otherwise, the serial controller
5622 * will send a closing sync char after this count.
5624 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5625 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5627 /* Program the Transmit Character Length Register (TCLR) */
5628 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5629 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5631 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5633 /* Program the address of the 1st DMA Buffer Entry in linked list */
5634 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5635 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5636 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5638 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5639 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5640 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5642 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5643 info
->num_tx_dma_buffers
> 1 ) {
5644 /* When running external sync mode, attempt to 'stream' transmit */
5645 /* by filling tx dma buffers as they become available. To do this */
5646 /* we need to enable Tx DMA EOB Status interrupts : */
5648 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5649 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5651 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5652 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5655 /* Initialize Transmit DMA Channel */
5656 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5658 usc_TCmd( info
, TCmd_SendFrame
);
5660 mod_timer(&info
->tx_timer
, jiffies
+
5661 msecs_to_jiffies(5000));
5663 info
->tx_active
= true;
5666 if ( !info
->tx_enabled
) {
5667 info
->tx_enabled
= true;
5668 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5669 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5671 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5674 } /* end of usc_start_transmitter() */
5676 /* usc_stop_transmitter()
5678 * Stops the transmitter and DMA
5680 * Arguments: info pointer to device isntance data
5681 * Return Value: None
5683 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5685 if (debug_level
>= DEBUG_LEVEL_ISR
)
5686 printk("%s(%d):usc_stop_transmitter(%s)\n",
5687 __FILE__
,__LINE__
, info
->device_name
);
5689 del_timer(&info
->tx_timer
);
5691 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5692 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5693 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5695 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5696 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5697 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5699 info
->tx_enabled
= false;
5700 info
->tx_active
= false;
5702 } /* end of usc_stop_transmitter() */
5704 /* usc_load_txfifo()
5706 * Fill the transmit FIFO until the FIFO is full or
5707 * there is no more data to load.
5709 * Arguments: info pointer to device extension (instance data)
5710 * Return Value: None
5712 static void usc_load_txfifo( struct mgsl_struct
*info
)
5717 if ( !info
->xmit_cnt
&& !info
->x_char
)
5720 /* Select transmit FIFO status readback in TICR */
5721 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5723 /* load the Transmit FIFO until FIFOs full or all data sent */
5725 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5726 /* there is more space in the transmit FIFO and */
5727 /* there is more data in transmit buffer */
5729 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5730 /* write a 16-bit word from transmit buffer to 16C32 */
5732 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5733 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5734 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5735 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5737 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5739 info
->xmit_cnt
-= 2;
5740 info
->icount
.tx
+= 2;
5742 /* only 1 byte left to transmit or 1 FIFO slot left */
5744 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5745 info
->io_base
+ CCAR
);
5748 /* transmit pending high priority char */
5749 outw( info
->x_char
,info
->io_base
+ CCAR
);
5752 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5753 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5760 } /* end of usc_load_txfifo() */
5764 * Reset the adapter to a known state and prepare it for further use.
5766 * Arguments: info pointer to device instance data
5767 * Return Value: None
5769 static void usc_reset( struct mgsl_struct
*info
)
5771 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5775 /* Set BIT30 of Misc Control Register */
5776 /* (Local Control Register 0x50) to force reset of USC. */
5778 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5779 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5781 info
->misc_ctrl_value
|= BIT30
;
5782 *MiscCtrl
= info
->misc_ctrl_value
;
5785 * Force at least 170ns delay before clearing
5786 * reset bit. Each read from LCR takes at least
5787 * 30ns so 10 times for 300ns to be safe.
5790 readval
= *MiscCtrl
;
5792 info
->misc_ctrl_value
&= ~BIT30
;
5793 *MiscCtrl
= info
->misc_ctrl_value
;
5795 *LCR0BRDR
= BUS_DESCRIPTOR(
5796 1, // Write Strobe Hold (0-3)
5797 2, // Write Strobe Delay (0-3)
5798 2, // Read Strobe Delay (0-3)
5799 0, // NWDD (Write data-data) (0-3)
5800 4, // NWAD (Write Addr-data) (0-31)
5801 0, // NXDA (Read/Write Data-Addr) (0-3)
5802 0, // NRDD (Read Data-Data) (0-3)
5803 5 // NRAD (Read Addr-Data) (0-31)
5807 outb( 0,info
->io_base
+ 8 );
5811 info
->loopback_bits
= 0;
5812 info
->usc_idle_mode
= 0;
5815 * Program the Bus Configuration Register (BCR)
5817 * <15> 0 Don't use separate address
5818 * <14..6> 0 reserved
5819 * <5..4> 00 IAckmode = Default, don't care
5820 * <3> 1 Bus Request Totem Pole output
5821 * <2> 1 Use 16 Bit data bus
5822 * <1> 0 IRQ Totem Pole output
5823 * <0> 0 Don't Shift Right Addr
5825 * 0000 0000 0000 1100 = 0x000c
5827 * By writing to io_base + SDPIN the Wait/Ack pin is
5828 * programmed to work as a Wait pin.
5831 outw( 0x000c,info
->io_base
+ SDPIN
);
5834 outw( 0,info
->io_base
);
5835 outw( 0,info
->io_base
+ CCAR
);
5837 /* select little endian byte ordering */
5838 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5841 /* Port Control Register (PCR)
5843 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5844 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5845 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5846 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5847 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5848 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5849 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5850 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5852 * 1111 0000 1111 0101 = 0xf0f5
5855 usc_OutReg( info
, PCR
, 0xf0f5 );
5859 * Input/Output Control Register
5861 * <15..14> 00 CTS is active low input
5862 * <13..12> 00 DCD is active low input
5863 * <11..10> 00 TxREQ pin is input (DSR)
5864 * <9..8> 00 RxREQ pin is input (RI)
5865 * <7..6> 00 TxD is output (Transmit Data)
5866 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5867 * <2..0> 100 RxC is Output (drive with BRG0)
5869 * 0000 0000 0000 0100 = 0x0004
5872 usc_OutReg( info
, IOCR
, 0x0004 );
5874 } /* end of usc_reset() */
5876 /* usc_set_async_mode()
5878 * Program adapter for asynchronous communications.
5880 * Arguments: info pointer to device instance data
5881 * Return Value: None
5883 static void usc_set_async_mode( struct mgsl_struct
*info
)
5887 /* disable interrupts while programming USC */
5888 usc_DisableMasterIrqBit( info
);
5890 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5891 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5893 usc_loopback_frame( info
);
5895 /* Channel mode Register (CMR)
5897 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5898 * <13..12> 00 00 = 16X Clock
5899 * <11..8> 0000 Transmitter mode = Asynchronous
5900 * <7..6> 00 reserved?
5901 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5902 * <3..0> 0000 Receiver mode = Asynchronous
5904 * 0000 0000 0000 0000 = 0x0
5908 if ( info
->params
.stop_bits
!= 1 )
5910 usc_OutReg( info
, CMR
, RegValue
);
5913 /* Receiver mode Register (RMR)
5915 * <15..13> 000 encoding = None
5916 * <12..08> 00000 reserved (Sync Only)
5917 * <7..6> 00 Even parity
5918 * <5> 0 parity disabled
5919 * <4..2> 000 Receive Char Length = 8 bits
5920 * <1..0> 00 Disable Receiver
5922 * 0000 0000 0000 0000 = 0x0
5927 if ( info
->params
.data_bits
!= 8 )
5928 RegValue
|= BIT4
+BIT3
+BIT2
;
5930 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5932 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5936 usc_OutReg( info
, RMR
, RegValue
);
5939 /* Set IRQ trigger level */
5941 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5944 /* Receive Interrupt Control Register (RICR)
5946 * <15..8> ? RxFIFO IRQ Request Level
5948 * Note: For async mode the receive FIFO level must be set
5949 * to 0 to avoid the situation where the FIFO contains fewer bytes
5950 * than the trigger level and no more data is expected.
5952 * <7> 0 Exited Hunt IA (Interrupt Arm)
5953 * <6> 0 Idle Received IA
5954 * <5> 0 Break/Abort IA
5956 * <3> 0 Queued status reflects oldest byte in FIFO
5958 * <1> 0 Rx Overrun IA
5959 * <0> 0 Select TC0 value for readback
5961 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5964 usc_OutReg( info
, RICR
, 0x0000 );
5966 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5967 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5970 /* Transmit mode Register (TMR)
5972 * <15..13> 000 encoding = None
5973 * <12..08> 00000 reserved (Sync Only)
5974 * <7..6> 00 Transmit parity Even
5975 * <5> 0 Transmit parity Disabled
5976 * <4..2> 000 Tx Char Length = 8 bits
5977 * <1..0> 00 Disable Transmitter
5979 * 0000 0000 0000 0000 = 0x0
5984 if ( info
->params
.data_bits
!= 8 )
5985 RegValue
|= BIT4
+BIT3
+BIT2
;
5987 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5989 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5993 usc_OutReg( info
, TMR
, RegValue
);
5995 usc_set_txidle( info
);
5998 /* Set IRQ trigger level */
6000 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6003 /* Transmit Interrupt Control Register (TICR)
6005 * <15..8> ? Transmit FIFO IRQ Level
6006 * <7> 0 Present IA (Interrupt Arm)
6007 * <6> 1 Idle Sent IA
6008 * <5> 0 Abort Sent IA
6009 * <4> 0 EOF/EOM Sent IA
6011 * <2> 0 1 = Wait for SW Trigger to Start Frame
6012 * <1> 0 Tx Underrun IA
6013 * <0> 0 TC0 constant on read back
6015 * 0000 0000 0100 0000 = 0x0040
6018 usc_OutReg( info
, TICR
, 0x1f40 );
6020 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6021 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6023 usc_enable_async_clock( info
, info
->params
.data_rate
);
6026 /* Channel Control/status Register (CCSR)
6028 * <15> X RCC FIFO Overflow status (RO)
6029 * <14> X RCC FIFO Not Empty status (RO)
6030 * <13> 0 1 = Clear RCC FIFO (WO)
6031 * <12> X DPLL in Sync status (RO)
6032 * <11> X DPLL 2 Missed Clocks status (RO)
6033 * <10> X DPLL 1 Missed Clock status (RO)
6034 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6035 * <7> X SDLC Loop On status (RO)
6036 * <6> X SDLC Loop Send status (RO)
6037 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6038 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6039 * <1..0> 00 reserved
6041 * 0000 0000 0010 0000 = 0x0020
6044 usc_OutReg( info
, CCSR
, 0x0020 );
6046 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6047 RECEIVE_DATA
+ RECEIVE_STATUS
);
6049 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6050 RECEIVE_DATA
+ RECEIVE_STATUS
);
6052 usc_EnableMasterIrqBit( info
);
6054 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6055 /* Enable INTEN (Port 6, Bit12) */
6056 /* This connects the IRQ request signal to the ISA bus */
6057 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6060 if (info
->params
.loopback
) {
6061 info
->loopback_bits
= 0x300;
6062 outw(0x0300, info
->io_base
+ CCAR
);
6065 } /* end of usc_set_async_mode() */
6067 /* usc_loopback_frame()
6069 * Loop back a small (2 byte) dummy SDLC frame.
6070 * Interrupts and DMA are NOT used. The purpose of this is to
6071 * clear any 'stale' status info left over from running in async mode.
6073 * The 16C32 shows the strange behaviour of marking the 1st
6074 * received SDLC frame with a CRC error even when there is no
6075 * CRC error. To get around this a small dummy from of 2 bytes
6076 * is looped back when switching from async to sync mode.
6078 * Arguments: info pointer to device instance data
6079 * Return Value: None
6081 static void usc_loopback_frame( struct mgsl_struct
*info
)
6084 unsigned long oldmode
= info
->params
.mode
;
6086 info
->params
.mode
= MGSL_MODE_HDLC
;
6088 usc_DisableMasterIrqBit( info
);
6090 usc_set_sdlc_mode( info
);
6091 usc_enable_loopback( info
, 1 );
6093 /* Write 16-bit Time Constant for BRG0 */
6094 usc_OutReg( info
, TC0R
, 0 );
6096 /* Channel Control Register (CCR)
6098 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6099 * <13> 0 Trigger Tx on SW Command Disabled
6100 * <12> 0 Flag Preamble Disabled
6101 * <11..10> 00 Preamble Length = 8-Bits
6102 * <9..8> 01 Preamble Pattern = flags
6103 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6104 * <5> 0 Trigger Rx on SW Command Disabled
6107 * 0000 0001 0000 0000 = 0x0100
6110 usc_OutReg( info
, CCR
, 0x0100 );
6112 /* SETUP RECEIVER */
6113 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6114 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6116 /* SETUP TRANSMITTER */
6117 /* Program the Transmit Character Length Register (TCLR) */
6118 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6119 usc_OutReg( info
, TCLR
, 2 );
6120 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6122 /* unlatch Tx status bits, and start transmit channel. */
6123 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6124 outw(0,info
->io_base
+ DATAREG
);
6126 /* ENABLE TRANSMITTER */
6127 usc_TCmd( info
, TCmd_SendFrame
);
6128 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6130 /* WAIT FOR RECEIVE COMPLETE */
6131 for (i
=0 ; i
<1000 ; i
++)
6132 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6135 /* clear Internal Data loopback mode */
6136 usc_enable_loopback(info
, 0);
6138 usc_EnableMasterIrqBit(info
);
6140 info
->params
.mode
= oldmode
;
6142 } /* end of usc_loopback_frame() */
6144 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6146 * Arguments: info pointer to adapter info structure
6147 * Return Value: None
6149 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6151 usc_loopback_frame( info
);
6152 usc_set_sdlc_mode( info
);
6154 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6155 /* Enable INTEN (Port 6, Bit12) */
6156 /* This connects the IRQ request signal to the ISA bus */
6157 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6160 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6162 if (info
->params
.loopback
)
6163 usc_enable_loopback(info
,1);
6165 } /* end of mgsl_set_sync_mode() */
6167 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6169 * Arguments: info pointer to device instance data
6170 * Return Value: None
6172 static void usc_set_txidle( struct mgsl_struct
*info
)
6174 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6176 /* Map API idle mode to USC register bits */
6178 switch( info
->idle_mode
){
6179 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6180 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6181 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6182 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6183 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6184 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6185 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6188 info
->usc_idle_mode
= usc_idle_mode
;
6189 //usc_OutReg(info, TCSR, usc_idle_mode);
6190 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6191 info
->tcsr_value
+= usc_idle_mode
;
6192 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6195 * if SyncLink WAN adapter is running in external sync mode, the
6196 * transmitter has been set to Monosync in order to try to mimic
6197 * a true raw outbound bit stream. Monosync still sends an open/close
6198 * sync char at the start/end of a frame. Try to match those sync
6199 * patterns to the idle mode set here
6201 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6202 unsigned char syncpat
= 0;
6203 switch( info
->idle_mode
) {
6204 case HDLC_TXIDLE_FLAGS
:
6207 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6210 case HDLC_TXIDLE_ZEROS
:
6211 case HDLC_TXIDLE_SPACE
:
6214 case HDLC_TXIDLE_ONES
:
6215 case HDLC_TXIDLE_MARK
:
6218 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6223 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6226 } /* end of usc_set_txidle() */
6228 /* usc_get_serial_signals()
6230 * Query the adapter for the state of the V24 status (input) signals.
6232 * Arguments: info pointer to device instance data
6233 * Return Value: None
6235 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6239 /* clear all serial signals except RTS and DTR */
6240 info
->serial_signals
&= SerialSignal_RTS
| SerialSignal_DTR
;
6242 /* Read the Misc Interrupt status Register (MISR) to get */
6243 /* the V24 status signals. */
6245 status
= usc_InReg( info
, MISR
);
6247 /* set serial signal bits to reflect MISR */
6249 if ( status
& MISCSTATUS_CTS
)
6250 info
->serial_signals
|= SerialSignal_CTS
;
6252 if ( status
& MISCSTATUS_DCD
)
6253 info
->serial_signals
|= SerialSignal_DCD
;
6255 if ( status
& MISCSTATUS_RI
)
6256 info
->serial_signals
|= SerialSignal_RI
;
6258 if ( status
& MISCSTATUS_DSR
)
6259 info
->serial_signals
|= SerialSignal_DSR
;
6261 } /* end of usc_get_serial_signals() */
6263 /* usc_set_serial_signals()
6265 * Set the state of RTS and DTR based on contents of
6266 * serial_signals member of device extension.
6268 * Arguments: info pointer to device instance data
6269 * Return Value: None
6271 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6274 unsigned char V24Out
= info
->serial_signals
;
6276 /* get the current value of the Port Control Register (PCR) */
6278 Control
= usc_InReg( info
, PCR
);
6280 if ( V24Out
& SerialSignal_RTS
)
6285 if ( V24Out
& SerialSignal_DTR
)
6290 usc_OutReg( info
, PCR
, Control
);
6292 } /* end of usc_set_serial_signals() */
6294 /* usc_enable_async_clock()
6296 * Enable the async clock at the specified frequency.
6298 * Arguments: info pointer to device instance data
6299 * data_rate data rate of clock in bps
6300 * 0 disables the AUX clock.
6301 * Return Value: None
6303 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6307 * Clock mode Control Register (CMCR)
6309 * <15..14> 00 counter 1 Disabled
6310 * <13..12> 00 counter 0 Disabled
6311 * <11..10> 11 BRG1 Input is TxC Pin
6312 * <9..8> 11 BRG0 Input is TxC Pin
6313 * <7..6> 01 DPLL Input is BRG1 Output
6314 * <5..3> 100 TxCLK comes from BRG0
6315 * <2..0> 100 RxCLK comes from BRG0
6317 * 0000 1111 0110 0100 = 0x0f64
6320 usc_OutReg( info
, CMCR
, 0x0f64 );
6324 * Write 16-bit Time Constant for BRG0
6325 * Time Constant = (ClkSpeed / data_rate) - 1
6326 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6329 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6330 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6332 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6336 * Hardware Configuration Register (HCR)
6337 * Clear Bit 1, BRG0 mode = Continuous
6338 * Set Bit 0 to enable BRG0.
6341 usc_OutReg( info
, HCR
,
6342 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6345 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6347 usc_OutReg( info
, IOCR
,
6348 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6350 /* data rate == 0 so turn off BRG0 */
6351 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6354 } /* end of usc_enable_async_clock() */
6357 * Buffer Structures:
6359 * Normal memory access uses virtual addresses that can make discontiguous
6360 * physical memory pages appear to be contiguous in the virtual address
6361 * space (the processors memory mapping handles the conversions).
6363 * DMA transfers require physically contiguous memory. This is because
6364 * the DMA system controller and DMA bus masters deal with memory using
6365 * only physical addresses.
6367 * This causes a problem under Windows NT when large DMA buffers are
6368 * needed. Fragmentation of the nonpaged pool prevents allocations of
6369 * physically contiguous buffers larger than the PAGE_SIZE.
6371 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6372 * allows DMA transfers to physically discontiguous buffers. Information
6373 * about each data transfer buffer is contained in a memory structure
6374 * called a 'buffer entry'. A list of buffer entries is maintained
6375 * to track and control the use of the data transfer buffers.
6377 * To support this strategy we will allocate sufficient PAGE_SIZE
6378 * contiguous memory buffers to allow for the total required buffer
6381 * The 16C32 accesses the list of buffer entries using Bus Master
6382 * DMA. Control information is read from the buffer entries by the
6383 * 16C32 to control data transfers. status information is written to
6384 * the buffer entries by the 16C32 to indicate the status of completed
6387 * The CPU writes control information to the buffer entries to control
6388 * the 16C32 and reads status information from the buffer entries to
6389 * determine information about received and transmitted frames.
6391 * Because the CPU and 16C32 (adapter) both need simultaneous access
6392 * to the buffer entries, the buffer entry memory is allocated with
6393 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6394 * entry list to PAGE_SIZE.
6396 * The actual data buffers on the other hand will only be accessed
6397 * by the CPU or the adapter but not by both simultaneously. This allows
6398 * Scatter/Gather packet based DMA procedures for using physically
6399 * discontiguous pages.
6403 * mgsl_reset_tx_dma_buffers()
6405 * Set the count for all transmit buffers to 0 to indicate the
6406 * buffer is available for use and set the current buffer to the
6407 * first buffer. This effectively makes all buffers free and
6408 * discards any data in buffers.
6410 * Arguments: info pointer to device instance data
6411 * Return Value: None
6413 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6417 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6418 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6421 info
->current_tx_buffer
= 0;
6422 info
->start_tx_dma_buffer
= 0;
6423 info
->tx_dma_buffers_used
= 0;
6425 info
->get_tx_holding_index
= 0;
6426 info
->put_tx_holding_index
= 0;
6427 info
->tx_holding_count
= 0;
6429 } /* end of mgsl_reset_tx_dma_buffers() */
6432 * num_free_tx_dma_buffers()
6434 * returns the number of free tx dma buffers available
6436 * Arguments: info pointer to device instance data
6437 * Return Value: number of free tx dma buffers
6439 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6441 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6445 * mgsl_reset_rx_dma_buffers()
6447 * Set the count for all receive buffers to DMABUFFERSIZE
6448 * and set the current buffer to the first buffer. This effectively
6449 * makes all buffers free and discards any data in buffers.
6451 * Arguments: info pointer to device instance data
6452 * Return Value: None
6454 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6458 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6459 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6460 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6461 // info->rx_buffer_list[i].status = 0;
6464 info
->current_rx_buffer
= 0;
6466 } /* end of mgsl_reset_rx_dma_buffers() */
6469 * mgsl_free_rx_frame_buffers()
6471 * Free the receive buffers used by a received SDLC
6472 * frame such that the buffers can be reused.
6476 * info pointer to device instance data
6477 * StartIndex index of 1st receive buffer of frame
6478 * EndIndex index of last receive buffer of frame
6480 * Return Value: None
6482 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6485 DMABUFFERENTRY
*pBufEntry
;
6488 /* Starting with 1st buffer entry of the frame clear the status */
6489 /* field and set the count field to DMA Buffer Size. */
6494 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6496 if ( Index
== EndIndex
) {
6497 /* This is the last buffer of the frame! */
6501 /* reset current buffer for reuse */
6502 // pBufEntry->status = 0;
6503 // pBufEntry->count = DMABUFFERSIZE;
6504 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6506 /* advance to next buffer entry in linked list */
6508 if ( Index
== info
->rx_buffer_count
)
6512 /* set current buffer to next buffer after last buffer of frame */
6513 info
->current_rx_buffer
= Index
;
6515 } /* end of free_rx_frame_buffers() */
6517 /* mgsl_get_rx_frame()
6519 * This function attempts to return a received SDLC frame from the
6520 * receive DMA buffers. Only frames received without errors are returned.
6522 * Arguments: info pointer to device extension
6523 * Return Value: true if frame returned, otherwise false
6525 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6527 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6528 unsigned short status
;
6529 DMABUFFERENTRY
*pBufEntry
;
6530 unsigned int framesize
= 0;
6531 bool ReturnCode
= false;
6532 unsigned long flags
;
6533 struct tty_struct
*tty
= info
->port
.tty
;
6534 bool return_frame
= false;
6537 * current_rx_buffer points to the 1st buffer of the next available
6538 * receive frame. To find the last buffer of the frame look for
6539 * a non-zero status field in the buffer entries. (The status
6540 * field is set by the 16C32 after completing a receive frame.
6543 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6545 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6547 * If the count field of the buffer entry is non-zero then
6548 * this buffer has not been used. (The 16C32 clears the count
6549 * field when it starts using the buffer.) If an unused buffer
6550 * is encountered then there are no frames available.
6553 if ( info
->rx_buffer_list
[EndIndex
].count
)
6556 /* advance to next buffer entry in linked list */
6558 if ( EndIndex
== info
->rx_buffer_count
)
6561 /* if entire list searched then no frame available */
6562 if ( EndIndex
== StartIndex
) {
6563 /* If this occurs then something bad happened,
6564 * all buffers have been 'used' but none mark
6565 * the end of a frame. Reset buffers and receiver.
6568 if ( info
->rx_enabled
){
6569 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6570 usc_start_receiver(info
);
6571 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6578 /* check status of receive frame */
6580 status
= info
->rx_buffer_list
[EndIndex
].status
;
6582 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6583 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6584 if ( status
& RXSTATUS_SHORT_FRAME
)
6585 info
->icount
.rxshort
++;
6586 else if ( status
& RXSTATUS_ABORT
)
6587 info
->icount
.rxabort
++;
6588 else if ( status
& RXSTATUS_OVERRUN
)
6589 info
->icount
.rxover
++;
6591 info
->icount
.rxcrc
++;
6592 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6593 return_frame
= true;
6596 #if SYNCLINK_GENERIC_HDLC
6598 info
->netdev
->stats
.rx_errors
++;
6599 info
->netdev
->stats
.rx_frame_errors
++;
6603 return_frame
= true;
6605 if ( return_frame
) {
6606 /* receive frame has no errors, get frame size.
6607 * The frame size is the starting value of the RCC (which was
6608 * set to 0xffff) minus the ending value of the RCC (decremented
6609 * once for each receive character) minus 2 for the 16-bit CRC.
6612 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6614 /* adjust frame size for CRC if any */
6615 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6617 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6621 if ( debug_level
>= DEBUG_LEVEL_BH
)
6622 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6623 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6625 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6626 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6627 min_t(int, framesize
, DMABUFFERSIZE
),0);
6630 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6631 ((framesize
+1) > info
->max_frame_size
) ) ||
6632 (framesize
> info
->max_frame_size
) )
6633 info
->icount
.rxlong
++;
6635 /* copy dma buffer(s) to contiguous intermediate buffer */
6636 int copy_count
= framesize
;
6637 int index
= StartIndex
;
6638 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6640 if ( !(status
& RXSTATUS_CRC_ERROR
))
6641 info
->icount
.rxok
++;
6645 if ( copy_count
> DMABUFFERSIZE
)
6646 partial_count
= DMABUFFERSIZE
;
6648 partial_count
= copy_count
;
6650 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6651 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6652 ptmp
+= partial_count
;
6653 copy_count
-= partial_count
;
6655 if ( ++index
== info
->rx_buffer_count
)
6659 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6661 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6665 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6666 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6667 __FILE__
,__LINE__
,info
->device_name
,
6671 #if SYNCLINK_GENERIC_HDLC
6673 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6676 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6679 /* Free the buffers used by this frame. */
6680 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6686 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6687 /* The receiver needs to restarted because of
6688 * a receive overflow (buffer or FIFO). If the
6689 * receive buffers are now empty, then restart receiver.
6692 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6693 info
->rx_buffer_list
[EndIndex
].count
) {
6694 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6695 usc_start_receiver(info
);
6696 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6702 } /* end of mgsl_get_rx_frame() */
6704 /* mgsl_get_raw_rx_frame()
6706 * This function attempts to return a received frame from the
6707 * receive DMA buffers when running in external loop mode. In this mode,
6708 * we will return at most one DMABUFFERSIZE frame to the application.
6709 * The USC receiver is triggering off of DCD going active to start a new
6710 * frame, and DCD going inactive to terminate the frame (similar to
6711 * processing a closing flag character).
6713 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6714 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6715 * status field and the RCC field will indicate the length of the
6716 * entire received frame. We take this RCC field and get the modulus
6717 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6718 * last Rx DMA buffer and return that last portion of the frame.
6720 * Arguments: info pointer to device extension
6721 * Return Value: true if frame returned, otherwise false
6723 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6725 unsigned int CurrentIndex
, NextIndex
;
6726 unsigned short status
;
6727 DMABUFFERENTRY
*pBufEntry
;
6728 unsigned int framesize
= 0;
6729 bool ReturnCode
= false;
6730 unsigned long flags
;
6731 struct tty_struct
*tty
= info
->port
.tty
;
6734 * current_rx_buffer points to the 1st buffer of the next available
6735 * receive frame. The status field is set by the 16C32 after
6736 * completing a receive frame. If the status field of this buffer
6737 * is zero, either the USC is still filling this buffer or this
6738 * is one of a series of buffers making up a received frame.
6740 * If the count field of this buffer is zero, the USC is either
6741 * using this buffer or has used this buffer. Look at the count
6742 * field of the next buffer. If that next buffer's count is
6743 * non-zero, the USC is still actively using the current buffer.
6744 * Otherwise, if the next buffer's count field is zero, the
6745 * current buffer is complete and the USC is using the next
6748 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6750 if ( NextIndex
== info
->rx_buffer_count
)
6753 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6754 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6755 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6757 * Either the status field of this dma buffer is non-zero
6758 * (indicating the last buffer of a receive frame) or the next
6759 * buffer is marked as in use -- implying this buffer is complete
6760 * and an intermediate buffer for this received frame.
6763 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6765 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6766 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6767 if ( status
& RXSTATUS_SHORT_FRAME
)
6768 info
->icount
.rxshort
++;
6769 else if ( status
& RXSTATUS_ABORT
)
6770 info
->icount
.rxabort
++;
6771 else if ( status
& RXSTATUS_OVERRUN
)
6772 info
->icount
.rxover
++;
6774 info
->icount
.rxcrc
++;
6778 * A receive frame is available, get frame size and status.
6780 * The frame size is the starting value of the RCC (which was
6781 * set to 0xffff) minus the ending value of the RCC (decremented
6782 * once for each receive character) minus 2 or 4 for the 16-bit
6785 * If the status field is zero, this is an intermediate buffer.
6788 * If the DMA Buffer Entry's Status field is non-zero, the
6789 * receive operation completed normally (ie: DCD dropped). The
6790 * RCC field is valid and holds the received frame size.
6791 * It is possible that the RCC field will be zero on a DMA buffer
6792 * entry with a non-zero status. This can occur if the total
6793 * frame size (number of bytes between the time DCD goes active
6794 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6795 * case the 16C32 has underrun on the RCC count and appears to
6796 * stop updating this counter to let us know the actual received
6797 * frame size. If this happens (non-zero status and zero RCC),
6798 * simply return the entire RxDMA Buffer
6802 * In the event that the final RxDMA Buffer is
6803 * terminated with a non-zero status and the RCC
6804 * field is zero, we interpret this as the RCC
6805 * having underflowed (received frame > 65535 bytes).
6807 * Signal the event to the user by passing back
6808 * a status of RxStatus_CrcError returning the full
6809 * buffer and let the app figure out what data is
6812 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6813 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6815 framesize
= DMABUFFERSIZE
;
6818 framesize
= DMABUFFERSIZE
;
6821 if ( framesize
> DMABUFFERSIZE
) {
6823 * if running in raw sync mode, ISR handler for
6824 * End Of Buffer events terminates all buffers at 4K.
6825 * If this frame size is said to be >4K, get the
6826 * actual number of bytes of the frame in this buffer.
6828 framesize
= framesize
% DMABUFFERSIZE
;
6832 if ( debug_level
>= DEBUG_LEVEL_BH
)
6833 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6834 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6836 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6837 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6838 min_t(int, framesize
, DMABUFFERSIZE
),0);
6841 /* copy dma buffer(s) to contiguous intermediate buffer */
6842 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6844 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6845 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6846 info
->icount
.rxok
++;
6848 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6851 /* Free the buffers used by this frame. */
6852 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6858 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6859 /* The receiver needs to restarted because of
6860 * a receive overflow (buffer or FIFO). If the
6861 * receive buffers are now empty, then restart receiver.
6864 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6865 info
->rx_buffer_list
[CurrentIndex
].count
) {
6866 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6867 usc_start_receiver(info
);
6868 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6874 } /* end of mgsl_get_raw_rx_frame() */
6876 /* mgsl_load_tx_dma_buffer()
6878 * Load the transmit DMA buffer with the specified data.
6882 * info pointer to device extension
6883 * Buffer pointer to buffer containing frame to load
6884 * BufferSize size in bytes of frame in Buffer
6886 * Return Value: None
6888 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6889 const char *Buffer
, unsigned int BufferSize
)
6891 unsigned short Copycount
;
6893 DMABUFFERENTRY
*pBufEntry
;
6895 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6896 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6898 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6899 /* set CMR:13 to start transmit when
6900 * next GoAhead (abort) is received
6902 info
->cmr_value
|= BIT13
;
6905 /* begin loading the frame in the next available tx dma
6906 * buffer, remember it's starting location for setting
6907 * up tx dma operation
6909 i
= info
->current_tx_buffer
;
6910 info
->start_tx_dma_buffer
= i
;
6912 /* Setup the status and RCC (Frame Size) fields of the 1st */
6913 /* buffer entry in the transmit DMA buffer list. */
6915 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6916 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6917 info
->tx_buffer_list
[i
].count
= BufferSize
;
6919 /* Copy frame data from 1st source buffer to the DMA buffers. */
6920 /* The frame data may span multiple DMA buffers. */
6922 while( BufferSize
){
6923 /* Get a pointer to next DMA buffer entry. */
6924 pBufEntry
= &info
->tx_buffer_list
[i
++];
6926 if ( i
== info
->tx_buffer_count
)
6929 /* Calculate the number of bytes that can be copied from */
6930 /* the source buffer to this DMA buffer. */
6931 if ( BufferSize
> DMABUFFERSIZE
)
6932 Copycount
= DMABUFFERSIZE
;
6934 Copycount
= BufferSize
;
6936 /* Actually copy data from source buffer to DMA buffer. */
6937 /* Also set the data count for this individual DMA buffer. */
6938 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6939 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6941 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6943 pBufEntry
->count
= Copycount
;
6945 /* Advance source pointer and reduce remaining data count. */
6946 Buffer
+= Copycount
;
6947 BufferSize
-= Copycount
;
6949 ++info
->tx_dma_buffers_used
;
6952 /* remember next available tx dma buffer */
6953 info
->current_tx_buffer
= i
;
6955 } /* end of mgsl_load_tx_dma_buffer() */
6958 * mgsl_register_test()
6960 * Performs a register test of the 16C32.
6962 * Arguments: info pointer to device instance data
6963 * Return Value: true if test passed, otherwise false
6965 static bool mgsl_register_test( struct mgsl_struct
*info
)
6967 static unsigned short BitPatterns
[] =
6968 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6969 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
6972 unsigned long flags
;
6974 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6977 /* Verify the reset state of some registers. */
6979 if ( (usc_InReg( info
, SICR
) != 0) ||
6980 (usc_InReg( info
, IVR
) != 0) ||
6981 (usc_InDmaReg( info
, DIVR
) != 0) ){
6986 /* Write bit patterns to various registers but do it out of */
6987 /* sync, then read back and verify values. */
6989 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6990 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6991 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6992 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6993 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6994 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6995 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6997 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6998 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6999 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7000 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7001 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7002 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7010 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7014 } /* end of mgsl_register_test() */
7016 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7018 * Arguments: info pointer to device instance data
7019 * Return Value: true if test passed, otherwise false
7021 static bool mgsl_irq_test( struct mgsl_struct
*info
)
7023 unsigned long EndTime
;
7024 unsigned long flags
;
7026 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7030 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7031 * The ISR sets irq_occurred to true.
7034 info
->irq_occurred
= false;
7036 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7037 /* Enable INTEN (Port 6, Bit12) */
7038 /* This connects the IRQ request signal to the ISA bus */
7039 /* on the ISA adapter. This has no effect for the PCI adapter */
7040 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7042 usc_EnableMasterIrqBit(info
);
7043 usc_EnableInterrupts(info
, IO_PIN
);
7044 usc_ClearIrqPendingBits(info
, IO_PIN
);
7046 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7047 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7049 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7052 while( EndTime
-- && !info
->irq_occurred
) {
7053 msleep_interruptible(10);
7056 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7058 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7060 return info
->irq_occurred
;
7062 } /* end of mgsl_irq_test() */
7066 * Perform a DMA test of the 16C32. A small frame is
7067 * transmitted via DMA from a transmit buffer to a receive buffer
7068 * using single buffer DMA mode.
7070 * Arguments: info pointer to device instance data
7071 * Return Value: true if test passed, otherwise false
7073 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7075 unsigned short FifoLevel
;
7076 unsigned long phys_addr
;
7077 unsigned int FrameSize
;
7081 unsigned short status
=0;
7082 unsigned long EndTime
;
7083 unsigned long flags
;
7084 MGSL_PARAMS tmp_params
;
7086 /* save current port options */
7087 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7088 /* load default port options */
7089 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7091 #define TESTFRAMESIZE 40
7093 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7095 /* setup 16C32 for SDLC DMA transfer mode */
7098 usc_set_sdlc_mode(info
);
7099 usc_enable_loopback(info
,1);
7101 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7102 * field of the buffer entry after fetching buffer address. This
7103 * way we can detect a DMA failure for a DMA read (which should be
7104 * non-destructive to system memory) before we try and write to
7105 * memory (where a failure could corrupt system memory).
7108 /* Receive DMA mode Register (RDMR)
7110 * <15..14> 11 DMA mode = Linked List Buffer mode
7111 * <13> 1 RSBinA/L = store Rx status Block in List entry
7112 * <12> 0 1 = Clear count of List Entry after fetching
7113 * <11..10> 00 Address mode = Increment
7114 * <9> 1 Terminate Buffer on RxBound
7115 * <8> 0 Bus Width = 16bits
7116 * <7..0> ? status Bits (write as 0s)
7118 * 1110 0010 0000 0000 = 0xe200
7121 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7123 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7126 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7128 FrameSize
= TESTFRAMESIZE
;
7130 /* setup 1st transmit buffer entry: */
7131 /* with frame size and transmit control word */
7133 info
->tx_buffer_list
[0].count
= FrameSize
;
7134 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7135 info
->tx_buffer_list
[0].status
= 0x4000;
7137 /* build a transmit frame in 1st transmit DMA buffer */
7139 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7140 for (i
= 0; i
< FrameSize
; i
++ )
7143 /* setup 1st receive buffer entry: */
7144 /* clear status, set max receive buffer size */
7146 info
->rx_buffer_list
[0].status
= 0;
7147 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7149 /* zero out the 1st receive buffer */
7151 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7153 /* Set count field of next buffer entries to prevent */
7154 /* 16C32 from using buffers after the 1st one. */
7156 info
->tx_buffer_list
[1].count
= 0;
7157 info
->rx_buffer_list
[1].count
= 0;
7160 /***************************/
7161 /* Program 16C32 receiver. */
7162 /***************************/
7164 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7166 /* setup DMA transfers */
7167 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7169 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7170 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7171 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7172 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7174 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7175 usc_InDmaReg( info
, RDMR
);
7176 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7178 /* Enable Receiver (RMR <1..0> = 10) */
7179 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7181 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7184 /*************************************************************/
7185 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7186 /*************************************************************/
7188 /* Wait 100ms for interrupt. */
7189 EndTime
= jiffies
+ msecs_to_jiffies(100);
7192 if (time_after(jiffies
, EndTime
)) {
7197 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7198 status
= usc_InDmaReg( info
, RDMR
);
7199 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7201 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7202 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7203 /* BUSY (BIT 5) is active (channel still active). */
7204 /* This means the buffer entry read has completed. */
7210 /******************************/
7211 /* Program 16C32 transmitter. */
7212 /******************************/
7214 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7216 /* Program the Transmit Character Length Register (TCLR) */
7217 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7219 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7220 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7222 /* Program the address of the 1st DMA Buffer Entry in linked list */
7224 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7225 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7226 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7228 /* unlatch Tx status bits, and start transmit channel. */
7230 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7231 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7233 /* wait for DMA controller to fill transmit FIFO */
7235 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7237 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7240 /**********************************/
7241 /* WAIT FOR TRANSMIT FIFO TO FILL */
7242 /**********************************/
7245 EndTime
= jiffies
+ msecs_to_jiffies(100);
7248 if (time_after(jiffies
, EndTime
)) {
7253 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7254 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7255 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7257 if ( FifoLevel
< 16 )
7260 if ( FrameSize
< 32 ) {
7261 /* This frame is smaller than the entire transmit FIFO */
7262 /* so wait for the entire frame to be loaded. */
7263 if ( FifoLevel
<= (32 - FrameSize
) )
7271 /* Enable 16C32 transmitter. */
7273 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7275 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7276 usc_TCmd( info
, TCmd_SendFrame
);
7277 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7279 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7282 /******************************/
7283 /* WAIT FOR TRANSMIT COMPLETE */
7284 /******************************/
7287 EndTime
= jiffies
+ msecs_to_jiffies(100);
7289 /* While timer not expired wait for transmit complete */
7291 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7292 status
= usc_InReg( info
, TCSR
);
7293 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7295 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7296 if (time_after(jiffies
, EndTime
)) {
7301 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7302 status
= usc_InReg( info
, TCSR
);
7303 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7309 /* CHECK FOR TRANSMIT ERRORS */
7310 if ( status
& (BIT5
+ BIT1
) )
7315 /* WAIT FOR RECEIVE COMPLETE */
7318 EndTime
= jiffies
+ msecs_to_jiffies(100);
7320 /* Wait for 16C32 to write receive status to buffer entry. */
7321 status
=info
->rx_buffer_list
[0].status
;
7322 while ( status
== 0 ) {
7323 if (time_after(jiffies
, EndTime
)) {
7327 status
=info
->rx_buffer_list
[0].status
;
7333 /* CHECK FOR RECEIVE ERRORS */
7334 status
= info
->rx_buffer_list
[0].status
;
7336 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7337 /* receive error has occurred */
7340 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7341 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7347 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7349 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7351 /* restore current port options */
7352 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7356 } /* end of mgsl_dma_test() */
7358 /* mgsl_adapter_test()
7360 * Perform the register, IRQ, and DMA tests for the 16C32.
7362 * Arguments: info pointer to device instance data
7363 * Return Value: 0 if success, otherwise -ENODEV
7365 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7367 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7368 printk( "%s(%d):Testing device %s\n",
7369 __FILE__
,__LINE__
,info
->device_name
);
7371 if ( !mgsl_register_test( info
) ) {
7372 info
->init_error
= DiagStatus_AddressFailure
;
7373 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7374 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7378 if ( !mgsl_irq_test( info
) ) {
7379 info
->init_error
= DiagStatus_IrqFailure
;
7380 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7381 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7385 if ( !mgsl_dma_test( info
) ) {
7386 info
->init_error
= DiagStatus_DmaFailure
;
7387 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7388 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7392 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7393 printk( "%s(%d):device %s passed diagnostics\n",
7394 __FILE__
,__LINE__
,info
->device_name
);
7398 } /* end of mgsl_adapter_test() */
7400 /* mgsl_memory_test()
7402 * Test the shared memory on a PCI adapter.
7404 * Arguments: info pointer to device instance data
7405 * Return Value: true if test passed, otherwise false
7407 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7409 static unsigned long BitPatterns
[] =
7410 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7411 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7413 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7414 unsigned long * TestAddr
;
7416 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7419 TestAddr
= (unsigned long *)info
->memory_base
;
7421 /* Test data lines with test pattern at one location. */
7423 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7424 *TestAddr
= BitPatterns
[i
];
7425 if ( *TestAddr
!= BitPatterns
[i
] )
7429 /* Test address lines with incrementing pattern over */
7430 /* entire address range. */
7432 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7437 TestAddr
= (unsigned long *)info
->memory_base
;
7439 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7440 if ( *TestAddr
!= i
* 4 )
7445 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7449 } /* End Of mgsl_memory_test() */
7452 /* mgsl_load_pci_memory()
7454 * Load a large block of data into the PCI shared memory.
7455 * Use this instead of memcpy() or memmove() to move data
7456 * into the PCI shared memory.
7460 * This function prevents the PCI9050 interface chip from hogging
7461 * the adapter local bus, which can starve the 16C32 by preventing
7462 * 16C32 bus master cycles.
7464 * The PCI9050 documentation says that the 9050 will always release
7465 * control of the local bus after completing the current read
7466 * or write operation.
7468 * It appears that as long as the PCI9050 write FIFO is full, the
7469 * PCI9050 treats all of the writes as a single burst transaction
7470 * and will not release the bus. This causes DMA latency problems
7471 * at high speeds when copying large data blocks to the shared
7474 * This function in effect, breaks the a large shared memory write
7475 * into multiple transations by interleaving a shared memory read
7476 * which will flush the write FIFO and 'complete' the write
7477 * transation. This allows any pending DMA request to gain control
7478 * of the local bus in a timely fasion.
7482 * TargetPtr pointer to target address in PCI shared memory
7483 * SourcePtr pointer to source buffer for data
7484 * count count in bytes of data to copy
7486 * Return Value: None
7488 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7489 unsigned short count
)
7491 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7492 #define PCI_LOAD_INTERVAL 64
7494 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7495 unsigned short Index
;
7496 unsigned long Dummy
;
7498 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7500 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7501 Dummy
= *((volatile unsigned long *)TargetPtr
);
7502 TargetPtr
+= PCI_LOAD_INTERVAL
;
7503 SourcePtr
+= PCI_LOAD_INTERVAL
;
7506 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7508 } /* End Of mgsl_load_pci_memory() */
7510 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7515 printk("%s tx data:\n",info
->device_name
);
7517 printk("%s rx data:\n",info
->device_name
);
7525 for(i
=0;i
<linecount
;i
++)
7526 printk("%02X ",(unsigned char)data
[i
]);
7529 for(i
=0;i
<linecount
;i
++) {
7530 if (data
[i
]>=040 && data
[i
]<=0176)
7531 printk("%c",data
[i
]);
7540 } /* end of mgsl_trace_block() */
7542 /* mgsl_tx_timeout()
7544 * called when HDLC frame times out
7545 * update stats and do tx completion processing
7547 * Arguments: context pointer to device instance data
7548 * Return Value: None
7550 static void mgsl_tx_timeout(unsigned long context
)
7552 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7553 unsigned long flags
;
7555 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7556 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7557 __FILE__
,__LINE__
,info
->device_name
);
7558 if(info
->tx_active
&&
7559 (info
->params
.mode
== MGSL_MODE_HDLC
||
7560 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7561 info
->icount
.txtimeout
++;
7563 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7564 info
->tx_active
= false;
7565 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7567 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7568 usc_loopmode_cancel_transmit( info
);
7570 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7572 #if SYNCLINK_GENERIC_HDLC
7574 hdlcdev_tx_done(info
);
7577 mgsl_bh_transmit(info
);
7579 } /* end of mgsl_tx_timeout() */
7581 /* signal that there are no more frames to send, so that
7582 * line is 'released' by echoing RxD to TxD when current
7583 * transmission is complete (or immediately if no tx in progress).
7585 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7587 unsigned long flags
;
7589 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7590 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7591 if (info
->tx_active
)
7592 info
->loopmode_send_done_requested
= true;
7594 usc_loopmode_send_done(info
);
7596 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7601 /* release the line by echoing RxD to TxD
7602 * upon completion of a transmit frame
7604 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7606 info
->loopmode_send_done_requested
= false;
7607 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7608 info
->cmr_value
&= ~BIT13
;
7609 usc_OutReg(info
, CMR
, info
->cmr_value
);
7612 /* abort a transmit in progress while in HDLC LoopMode
7614 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7616 /* reset tx dma channel and purge TxFifo */
7617 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7618 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7619 usc_loopmode_send_done( info
);
7622 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7623 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7624 * we must clear CMR:13 to begin repeating TxData to RxData
7626 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7628 info
->loopmode_insert_requested
= true;
7630 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7631 * begin repeating TxData on RxData (complete insertion)
7633 usc_OutReg( info
, RICR
,
7634 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7636 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7637 info
->cmr_value
|= BIT13
;
7638 usc_OutReg(info
, CMR
, info
->cmr_value
);
7641 /* return 1 if station is inserted into the loop, otherwise 0
7643 static int usc_loopmode_active( struct mgsl_struct
* info
)
7645 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7648 #if SYNCLINK_GENERIC_HDLC
7651 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7652 * set encoding and frame check sequence (FCS) options
7654 * dev pointer to network device structure
7655 * encoding serial encoding setting
7656 * parity FCS setting
7658 * returns 0 if success, otherwise error code
7660 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7661 unsigned short parity
)
7663 struct mgsl_struct
*info
= dev_to_port(dev
);
7664 unsigned char new_encoding
;
7665 unsigned short new_crctype
;
7667 /* return error if TTY interface open */
7668 if (info
->port
.count
)
7673 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7674 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7675 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7676 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7677 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7678 default: return -EINVAL
;
7683 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7684 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7685 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7686 default: return -EINVAL
;
7689 info
->params
.encoding
= new_encoding
;
7690 info
->params
.crc_type
= new_crctype
;
7692 /* if network interface up, reprogram hardware */
7694 mgsl_program_hw(info
);
7700 * called by generic HDLC layer to send frame
7702 * skb socket buffer containing HDLC frame
7703 * dev pointer to network device structure
7705 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
7706 struct net_device
*dev
)
7708 struct mgsl_struct
*info
= dev_to_port(dev
);
7709 unsigned long flags
;
7711 if (debug_level
>= DEBUG_LEVEL_INFO
)
7712 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7714 /* stop sending until this frame completes */
7715 netif_stop_queue(dev
);
7717 /* copy data to device buffers */
7718 info
->xmit_cnt
= skb
->len
;
7719 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7721 /* update network statistics */
7722 dev
->stats
.tx_packets
++;
7723 dev
->stats
.tx_bytes
+= skb
->len
;
7725 /* done with socket buffer, so free it */
7728 /* save start time for transmit timeout detection */
7729 dev
->trans_start
= jiffies
;
7731 /* start hardware transmitter if necessary */
7732 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7733 if (!info
->tx_active
)
7734 usc_start_transmitter(info
);
7735 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7737 return NETDEV_TX_OK
;
7741 * called by network layer when interface enabled
7742 * claim resources and initialize hardware
7744 * dev pointer to network device structure
7746 * returns 0 if success, otherwise error code
7748 static int hdlcdev_open(struct net_device
*dev
)
7750 struct mgsl_struct
*info
= dev_to_port(dev
);
7752 unsigned long flags
;
7754 if (debug_level
>= DEBUG_LEVEL_INFO
)
7755 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7757 /* generic HDLC layer open processing */
7758 if ((rc
= hdlc_open(dev
)))
7761 /* arbitrate between network and tty opens */
7762 spin_lock_irqsave(&info
->netlock
, flags
);
7763 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7764 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7765 spin_unlock_irqrestore(&info
->netlock
, flags
);
7769 spin_unlock_irqrestore(&info
->netlock
, flags
);
7771 /* claim resources and init adapter */
7772 if ((rc
= startup(info
)) != 0) {
7773 spin_lock_irqsave(&info
->netlock
, flags
);
7775 spin_unlock_irqrestore(&info
->netlock
, flags
);
7779 /* assert RTS and DTR, apply hardware settings */
7780 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
7781 mgsl_program_hw(info
);
7783 /* enable network layer transmit */
7784 dev
->trans_start
= jiffies
;
7785 netif_start_queue(dev
);
7787 /* inform generic HDLC layer of current DCD status */
7788 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7789 usc_get_serial_signals(info
);
7790 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7791 if (info
->serial_signals
& SerialSignal_DCD
)
7792 netif_carrier_on(dev
);
7794 netif_carrier_off(dev
);
7799 * called by network layer when interface is disabled
7800 * shutdown hardware and release resources
7802 * dev pointer to network device structure
7804 * returns 0 if success, otherwise error code
7806 static int hdlcdev_close(struct net_device
*dev
)
7808 struct mgsl_struct
*info
= dev_to_port(dev
);
7809 unsigned long flags
;
7811 if (debug_level
>= DEBUG_LEVEL_INFO
)
7812 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7814 netif_stop_queue(dev
);
7816 /* shutdown adapter and release resources */
7821 spin_lock_irqsave(&info
->netlock
, flags
);
7823 spin_unlock_irqrestore(&info
->netlock
, flags
);
7829 * called by network layer to process IOCTL call to network device
7831 * dev pointer to network device structure
7832 * ifr pointer to network interface request structure
7833 * cmd IOCTL command code
7835 * returns 0 if success, otherwise error code
7837 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7839 const size_t size
= sizeof(sync_serial_settings
);
7840 sync_serial_settings new_line
;
7841 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7842 struct mgsl_struct
*info
= dev_to_port(dev
);
7845 if (debug_level
>= DEBUG_LEVEL_INFO
)
7846 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7848 /* return error if TTY interface open */
7849 if (info
->port
.count
)
7852 if (cmd
!= SIOCWANDEV
)
7853 return hdlc_ioctl(dev
, ifr
, cmd
);
7855 switch(ifr
->ifr_settings
.type
) {
7856 case IF_GET_IFACE
: /* return current sync_serial_settings */
7858 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7859 if (ifr
->ifr_settings
.size
< size
) {
7860 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7864 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7865 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7866 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7867 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7870 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7871 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7872 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7873 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7874 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7877 new_line
.clock_rate
= info
->params
.clock_speed
;
7878 new_line
.loopback
= info
->params
.loopback
? 1:0;
7880 if (copy_to_user(line
, &new_line
, size
))
7884 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7886 if(!capable(CAP_NET_ADMIN
))
7888 if (copy_from_user(&new_line
, line
, size
))
7891 switch (new_line
.clock_type
)
7893 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7894 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7895 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7896 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7897 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7898 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7899 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7900 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7901 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7902 default: return -EINVAL
;
7905 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7908 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7909 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7910 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7911 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7912 info
->params
.flags
|= flags
;
7914 info
->params
.loopback
= new_line
.loopback
;
7916 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7917 info
->params
.clock_speed
= new_line
.clock_rate
;
7919 info
->params
.clock_speed
= 0;
7921 /* if network interface up, reprogram hardware */
7923 mgsl_program_hw(info
);
7927 return hdlc_ioctl(dev
, ifr
, cmd
);
7932 * called by network layer when transmit timeout is detected
7934 * dev pointer to network device structure
7936 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7938 struct mgsl_struct
*info
= dev_to_port(dev
);
7939 unsigned long flags
;
7941 if (debug_level
>= DEBUG_LEVEL_INFO
)
7942 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7944 dev
->stats
.tx_errors
++;
7945 dev
->stats
.tx_aborted_errors
++;
7947 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7948 usc_stop_transmitter(info
);
7949 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7951 netif_wake_queue(dev
);
7955 * called by device driver when transmit completes
7956 * reenable network layer transmit if stopped
7958 * info pointer to device instance information
7960 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
7962 if (netif_queue_stopped(info
->netdev
))
7963 netif_wake_queue(info
->netdev
);
7967 * called by device driver when frame received
7968 * pass frame to network layer
7970 * info pointer to device instance information
7971 * buf pointer to buffer contianing frame data
7972 * size count of data bytes in buf
7974 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
7976 struct sk_buff
*skb
= dev_alloc_skb(size
);
7977 struct net_device
*dev
= info
->netdev
;
7979 if (debug_level
>= DEBUG_LEVEL_INFO
)
7980 printk("hdlcdev_rx(%s)\n", dev
->name
);
7983 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
7985 dev
->stats
.rx_dropped
++;
7989 memcpy(skb_put(skb
, size
), buf
, size
);
7991 skb
->protocol
= hdlc_type_trans(skb
, dev
);
7993 dev
->stats
.rx_packets
++;
7994 dev
->stats
.rx_bytes
+= size
;
7999 static const struct net_device_ops hdlcdev_ops
= {
8000 .ndo_open
= hdlcdev_open
,
8001 .ndo_stop
= hdlcdev_close
,
8002 .ndo_change_mtu
= hdlc_change_mtu
,
8003 .ndo_start_xmit
= hdlc_start_xmit
,
8004 .ndo_do_ioctl
= hdlcdev_ioctl
,
8005 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
8009 * called by device driver when adding device instance
8010 * do generic HDLC initialization
8012 * info pointer to device instance information
8014 * returns 0 if success, otherwise error code
8016 static int hdlcdev_init(struct mgsl_struct
*info
)
8019 struct net_device
*dev
;
8022 /* allocate and initialize network and HDLC layer objects */
8024 if (!(dev
= alloc_hdlcdev(info
))) {
8025 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8029 /* for network layer reporting purposes only */
8030 dev
->base_addr
= info
->io_base
;
8031 dev
->irq
= info
->irq_level
;
8032 dev
->dma
= info
->dma_level
;
8034 /* network layer callbacks and settings */
8035 dev
->netdev_ops
= &hdlcdev_ops
;
8036 dev
->watchdog_timeo
= 10 * HZ
;
8037 dev
->tx_queue_len
= 50;
8039 /* generic HDLC layer callbacks and settings */
8040 hdlc
= dev_to_hdlc(dev
);
8041 hdlc
->attach
= hdlcdev_attach
;
8042 hdlc
->xmit
= hdlcdev_xmit
;
8044 /* register objects with HDLC layer */
8045 if ((rc
= register_hdlc_device(dev
))) {
8046 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8056 * called by device driver when removing device instance
8057 * do generic HDLC cleanup
8059 * info pointer to device instance information
8061 static void hdlcdev_exit(struct mgsl_struct
*info
)
8063 unregister_hdlc_device(info
->netdev
);
8064 free_netdev(info
->netdev
);
8065 info
->netdev
= NULL
;
8068 #endif /* CONFIG_HDLC */
8071 static int synclink_init_one (struct pci_dev
*dev
,
8072 const struct pci_device_id
*ent
)
8074 struct mgsl_struct
*info
;
8076 if (pci_enable_device(dev
)) {
8077 printk("error enabling pci device %p\n", dev
);
8081 if (!(info
= mgsl_allocate_device())) {
8082 printk("can't allocate device instance data.\n");
8086 /* Copy user configuration info to device instance data */
8088 info
->io_base
= pci_resource_start(dev
, 2);
8089 info
->irq_level
= dev
->irq
;
8090 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8092 /* Because veremap only works on page boundaries we must map
8093 * a larger area than is actually implemented for the LCR
8094 * memory range. We map a full page starting at the page boundary.
8096 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8097 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8098 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8100 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8101 info
->io_addr_size
= 8;
8102 info
->irq_flags
= IRQF_SHARED
;
8104 if (dev
->device
== 0x0210) {
8105 /* Version 1 PCI9030 based universal PCI adapter */
8106 info
->misc_ctrl_value
= 0x007c4080;
8107 info
->hw_version
= 1;
8109 /* Version 0 PCI9050 based 5V PCI adapter
8110 * A PCI9050 bug prevents reading LCR registers if
8111 * LCR base address bit 7 is set. Maintain shadow
8112 * value so we can write to LCR misc control reg.
8114 info
->misc_ctrl_value
= 0x087e4546;
8115 info
->hw_version
= 0;
8118 mgsl_add_device(info
);
8123 static void synclink_remove_one (struct pci_dev
*dev
)