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x86: hpet: Fix copy-and-paste mistake in earlier change
[linux/fpc-iii.git] / drivers / gpu / drm / mga / mga_dma.c
blob507aa3df0168961a90f751b05caa72164d8474c2
1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 /**
29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400.
31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include "drmP.h"
39 #include "drm.h"
40 #include "drm_sarea.h"
41 #include "mga_drm.h"
42 #include "mga_drv.h"
43
44 #define MGA_DEFAULT_USEC_TIMEOUT 10000
45 #define MGA_FREELIST_DEBUG 0
46
47 #define MINIMAL_CLEANUP 0
48 #define FULL_CLEANUP 1
49 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
50
51 /* ================================================================
52 * Engine control
53 */
54
55 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv)
56 {
57 u32 status = 0;
58 int i;
59 DRM_DEBUG("\n");
60
61 for (i = 0; i < dev_priv->usec_timeout; i++) {
62 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
63 if (status == MGA_ENDPRDMASTS) {
64 MGA_WRITE8(MGA_CRTC_INDEX, 0);
65 return 0;
66 }
67 DRM_UDELAY(1);
68 }
69
70 #if MGA_DMA_DEBUG
71 DRM_ERROR("failed!\n");
72 DRM_INFO(" status=0x%08x\n", status);
73 #endif
74 return -EBUSY;
75 }
76
77 static int mga_do_dma_reset(drm_mga_private_t *dev_priv)
78 {
79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
80 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
81
82 DRM_DEBUG("\n");
83
84 /* The primary DMA stream should look like new right about now.
85 */
86 primary->tail = 0;
87 primary->space = primary->size;
88 primary->last_flush = 0;
89
90 sarea_priv->last_wrap = 0;
91
92 /* FIXME: Reset counters, buffer ages etc...
93 */
94
95 /* FIXME: What else do we need to reinitialize? WARP stuff?
96 */
97
98 return 0;
99 }
100
101 /* ================================================================
102 * Primary DMA stream
103 */
104
105 void mga_do_dma_flush(drm_mga_private_t *dev_priv)
106 {
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
108 u32 head, tail;
109 u32 status = 0;
110 int i;
111 DMA_LOCALS;
112 DRM_DEBUG("\n");
113
114 /* We need to wait so that we can do an safe flush */
115 for (i = 0; i < dev_priv->usec_timeout; i++) {
116 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
117 if (status == MGA_ENDPRDMASTS)
118 break;
119 DRM_UDELAY(1);
120 }
121
122 if (primary->tail == primary->last_flush) {
123 DRM_DEBUG(" bailing out...\n");
124 return;
125 }
126
127 tail = primary->tail + dev_priv->primary->offset;
128
129 /* We need to pad the stream between flushes, as the card
130 * actually (partially?) reads the first of these commands.
131 * See page 4-16 in the G400 manual, middle of the page or so.
132 */
133 BEGIN_DMA(1);
134
135 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
136 MGA_DMAPAD, 0x00000000,
137 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
138
139 ADVANCE_DMA();
140
141 primary->last_flush = primary->tail;
142
143 head = MGA_READ(MGA_PRIMADDRESS);
144
145 if (head <= tail)
146 primary->space = primary->size - primary->tail;
147 else
148 primary->space = head - tail;
149
150 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
151 DRM_DEBUG(" tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset));
152 DRM_DEBUG(" space = 0x%06x\n", primary->space);
153
154 mga_flush_write_combine();
155 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
156
157 DRM_DEBUG("done.\n");
158 }
159
160 void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv)
161 {
162 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
163 u32 head, tail;
164 DMA_LOCALS;
165 DRM_DEBUG("\n");
166
167 BEGIN_DMA_WRAP();
168
169 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000,
171 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
172
173 ADVANCE_DMA();
174
175 tail = primary->tail + dev_priv->primary->offset;
176
177 primary->tail = 0;
178 primary->last_flush = 0;
179 primary->last_wrap++;
180
181 head = MGA_READ(MGA_PRIMADDRESS);
182
183 if (head == dev_priv->primary->offset)
184 primary->space = primary->size;
185 else
186 primary->space = head - dev_priv->primary->offset;
187
188 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
189 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
190 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
191 DRM_DEBUG(" space = 0x%06x\n", primary->space);
192
193 mga_flush_write_combine();
194 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
195
196 set_bit(0, &primary->wrapped);
197 DRM_DEBUG("done.\n");
198 }
199
200 void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv)
201 {
202 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 u32 head = dev_priv->primary->offset;
205 DRM_DEBUG("\n");
206
207 sarea_priv->last_wrap++;
208 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
209
210 mga_flush_write_combine();
211 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
212
213 clear_bit(0, &primary->wrapped);
214 DRM_DEBUG("done.\n");
215 }
216
217 /* ================================================================
218 * Freelist management
219 */
220
221 #define MGA_BUFFER_USED (~0)
222 #define MGA_BUFFER_FREE 0
223
224 #if MGA_FREELIST_DEBUG
225 static void mga_freelist_print(struct drm_device *dev)
226 {
227 drm_mga_private_t *dev_priv = dev->dev_private;
228 drm_mga_freelist_t *entry;
229
230 DRM_INFO("\n");
231 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
232 dev_priv->sarea_priv->last_dispatch,
233 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
234 dev_priv->primary->offset));
235 DRM_INFO("current freelist:\n");
236
237 for (entry = dev_priv->head->next; entry; entry = entry->next) {
238 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
239 entry, entry->buf->idx, entry->age.head,
240 (unsigned long)(entry->age.head - dev_priv->primary->offset));
241 }
242 DRM_INFO("\n");
243 }
244 #endif
245
246 static int mga_freelist_init(struct drm_device *dev, drm_mga_private_t *dev_priv)
247 {
248 struct drm_device_dma *dma = dev->dma;
249 struct drm_buf *buf;
250 drm_mga_buf_priv_t *buf_priv;
251 drm_mga_freelist_t *entry;
252 int i;
253 DRM_DEBUG("count=%d\n", dma->buf_count);
254
255 dev_priv->head = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
256 if (dev_priv->head == NULL)
257 return -ENOMEM;
258
259 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
260
261 for (i = 0; i < dma->buf_count; i++) {
262 buf = dma->buflist[i];
263 buf_priv = buf->dev_private;
264
265 entry = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
266 if (entry == NULL)
267 return -ENOMEM;
268
269 entry->next = dev_priv->head->next;
270 entry->prev = dev_priv->head;
271 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
272 entry->buf = buf;
273
274 if (dev_priv->head->next != NULL)
275 dev_priv->head->next->prev = entry;
276 if (entry->next == NULL)
277 dev_priv->tail = entry;
278
279 buf_priv->list_entry = entry;
280 buf_priv->discard = 0;
281 buf_priv->dispatched = 0;
282
283 dev_priv->head->next = entry;
284 }
285
286 return 0;
287 }
288
289 static void mga_freelist_cleanup(struct drm_device *dev)
290 {
291 drm_mga_private_t *dev_priv = dev->dev_private;
292 drm_mga_freelist_t *entry;
293 drm_mga_freelist_t *next;
294 DRM_DEBUG("\n");
295
296 entry = dev_priv->head;
297 while (entry) {
298 next = entry->next;
299 kfree(entry);
300 entry = next;
301 }
302
303 dev_priv->head = dev_priv->tail = NULL;
304 }
305
306 #if 0
307 /* FIXME: Still needed?
308 */
309 static void mga_freelist_reset(struct drm_device *dev)
310 {
311 struct drm_device_dma *dma = dev->dma;
312 struct drm_buf *buf;
313 drm_mga_buf_priv_t *buf_priv;
314 int i;
315
316 for (i = 0; i < dma->buf_count; i++) {
317 buf = dma->buflist[i];
318 buf_priv = buf->dev_private;
319 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
320 }
321 }
322 #endif
323
324 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
325 {
326 drm_mga_private_t *dev_priv = dev->dev_private;
327 drm_mga_freelist_t *next;
328 drm_mga_freelist_t *prev;
329 drm_mga_freelist_t *tail = dev_priv->tail;
330 u32 head, wrap;
331 DRM_DEBUG("\n");
332
333 head = MGA_READ(MGA_PRIMADDRESS);
334 wrap = dev_priv->sarea_priv->last_wrap;
335
336 DRM_DEBUG(" tail=0x%06lx %d\n",
337 tail->age.head ?
338 (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0,
339 tail->age.wrap);
340 DRM_DEBUG(" head=0x%06lx %d\n",
341 (unsigned long)(head - dev_priv->primary->offset), wrap);
342
343 if (TEST_AGE(&tail->age, head, wrap)) {
344 prev = dev_priv->tail->prev;
345 next = dev_priv->tail;
346 prev->next = NULL;
347 next->prev = next->next = NULL;
348 dev_priv->tail = prev;
349 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
350 return next->buf;
351 }
352
353 DRM_DEBUG("returning NULL!\n");
354 return NULL;
355 }
356
357 int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf)
358 {
359 drm_mga_private_t *dev_priv = dev->dev_private;
360 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
361 drm_mga_freelist_t *head, *entry, *prev;
362
363 DRM_DEBUG("age=0x%06lx wrap=%d\n",
364 (unsigned long)(buf_priv->list_entry->age.head -
365 dev_priv->primary->offset),
366 buf_priv->list_entry->age.wrap);
367
368 entry = buf_priv->list_entry;
369 head = dev_priv->head;
370
371 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
372 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
373 prev = dev_priv->tail;
374 prev->next = entry;
375 entry->prev = prev;
376 entry->next = NULL;
377 } else {
378 prev = head->next;
379 head->next = entry;
380 prev->prev = entry;
381 entry->prev = head;
382 entry->next = prev;
383 }
384
385 return 0;
386 }
387
388 /* ================================================================
389 * DMA initialization, cleanup
390 */
391
392 int mga_driver_load(struct drm_device *dev, unsigned long flags)
393 {
394 drm_mga_private_t *dev_priv;
395 int ret;
396
397 dev_priv = kzalloc(sizeof(drm_mga_private_t), GFP_KERNEL);
398 if (!dev_priv)
399 return -ENOMEM;
400
401 dev->dev_private = (void *)dev_priv;
402
403 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
404 dev_priv->chipset = flags;
405
406 pci_set_master(dev->pdev);
407
408 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
409 dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
410
411 dev->counters += 3;
412 dev->types[6] = _DRM_STAT_IRQ;
413 dev->types[7] = _DRM_STAT_PRIMARY;
414 dev->types[8] = _DRM_STAT_SECONDARY;
415
416 ret = drm_vblank_init(dev, 1);
417
418 if (ret) {
419 (void) mga_driver_unload(dev);
420 return ret;
421 }
422
423 return 0;
424 }
425
426 #if __OS_HAS_AGP
427 /**
428 * Bootstrap the driver for AGP DMA.
429 *
430 * \todo
431 * Investigate whether there is any benefit to storing the WARP microcode in
432 * AGP memory. If not, the microcode may as well always be put in PCI
433 * memory.
434 *
435 * \todo
436 * This routine needs to set dma_bs->agp_mode to the mode actually configured
437 * in the hardware. Looking just at the Linux AGP driver code, I don't see
438 * an easy way to determine this.
439 *
440 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
441 */
442 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
443 drm_mga_dma_bootstrap_t *dma_bs)
444 {
445 drm_mga_private_t *const dev_priv =
446 (drm_mga_private_t *) dev->dev_private;
447 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
448 int err;
449 unsigned offset;
450 const unsigned secondary_size = dma_bs->secondary_bin_count
451 * dma_bs->secondary_bin_size;
452 const unsigned agp_size = (dma_bs->agp_size << 20);
453 struct drm_buf_desc req;
454 struct drm_agp_mode mode;
455 struct drm_agp_info info;
456 struct drm_agp_buffer agp_req;
457 struct drm_agp_binding bind_req;
458
459 /* Acquire AGP. */
460 err = drm_agp_acquire(dev);
461 if (err) {
462 DRM_ERROR("Unable to acquire AGP: %d\n", err);
463 return err;
464 }
465
466 err = drm_agp_info(dev, &info);
467 if (err) {
468 DRM_ERROR("Unable to get AGP info: %d\n", err);
469 return err;
470 }
471
472 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
473 err = drm_agp_enable(dev, mode);
474 if (err) {
475 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
476 return err;
477 }
478
479 /* In addition to the usual AGP mode configuration, the G200 AGP cards
480 * need to have the AGP mode "manually" set.
481 */
482
483 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
484 if (mode.mode & 0x02)
485 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
486 else
487 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
488 }
489
490 /* Allocate and bind AGP memory. */
491 agp_req.size = agp_size;
492 agp_req.type = 0;
493 err = drm_agp_alloc(dev, &agp_req);
494 if (err) {
495 dev_priv->agp_size = 0;
496 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
497 dma_bs->agp_size);
498 return err;
499 }
500
501 dev_priv->agp_size = agp_size;
502 dev_priv->agp_handle = agp_req.handle;
503
504 bind_req.handle = agp_req.handle;
505 bind_req.offset = 0;
506 err = drm_agp_bind(dev, &bind_req);
507 if (err) {
508 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
509 return err;
510 }
511
512 /* Make drm_addbufs happy by not trying to create a mapping for less
513 * than a page.
514 */
515 if (warp_size < PAGE_SIZE)
516 warp_size = PAGE_SIZE;
517
518 offset = 0;
519 err = drm_addmap(dev, offset, warp_size,
520 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
521 if (err) {
522 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
523 return err;
524 }
525
526 offset += warp_size;
527 err = drm_addmap(dev, offset, dma_bs->primary_size,
528 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
529 if (err) {
530 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
531 return err;
532 }
533
534 offset += dma_bs->primary_size;
535 err = drm_addmap(dev, offset, secondary_size,
536 _DRM_AGP, 0, &dev->agp_buffer_map);
537 if (err) {
538 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
539 return err;
540 }
541
542 (void)memset(&req, 0, sizeof(req));
543 req.count = dma_bs->secondary_bin_count;
544 req.size = dma_bs->secondary_bin_size;
545 req.flags = _DRM_AGP_BUFFER;
546 req.agp_start = offset;
547
548 err = drm_addbufs_agp(dev, &req);
549 if (err) {
550 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
551 return err;
552 }
553
554 {
555 struct drm_map_list *_entry;
556 unsigned long agp_token = 0;
557
558 list_for_each_entry(_entry, &dev->maplist, head) {
559 if (_entry->map == dev->agp_buffer_map)
560 agp_token = _entry->user_token;
561 }
562 if (!agp_token)
563 return -EFAULT;
564
565 dev->agp_buffer_token = agp_token;
566 }
567
568 offset += secondary_size;
569 err = drm_addmap(dev, offset, agp_size - offset,
570 _DRM_AGP, 0, &dev_priv->agp_textures);
571 if (err) {
572 DRM_ERROR("Unable to map AGP texture region %d\n", err);
573 return err;
574 }
575
576 drm_core_ioremap(dev_priv->warp, dev);
577 drm_core_ioremap(dev_priv->primary, dev);
578 drm_core_ioremap(dev->agp_buffer_map, dev);
579
580 if (!dev_priv->warp->handle ||
581 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
582 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
583 dev_priv->warp->handle, dev_priv->primary->handle,
584 dev->agp_buffer_map->handle);
585 return -ENOMEM;
586 }
587
588 dev_priv->dma_access = MGA_PAGPXFER;
589 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
590
591 DRM_INFO("Initialized card for AGP DMA.\n");
592 return 0;
593 }
594 #else
595 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
596 drm_mga_dma_bootstrap_t *dma_bs)
597 {
598 return -EINVAL;
599 }
600 #endif
601
602 /**
603 * Bootstrap the driver for PCI DMA.
604 *
605 * \todo
606 * The algorithm for decreasing the size of the primary DMA buffer could be
607 * better. The size should be rounded up to the nearest page size, then
608 * decrease the request size by a single page each pass through the loop.
609 *
610 * \todo
611 * Determine whether the maximum address passed to drm_pci_alloc is correct.
612 * The same goes for drm_addbufs_pci.
613 *
614 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
615 */
616 static int mga_do_pci_dma_bootstrap(struct drm_device *dev,
617 drm_mga_dma_bootstrap_t *dma_bs)
618 {
619 drm_mga_private_t *const dev_priv =
620 (drm_mga_private_t *) dev->dev_private;
621 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
622 unsigned int primary_size;
623 unsigned int bin_count;
624 int err;
625 struct drm_buf_desc req;
626
627 if (dev->dma == NULL) {
628 DRM_ERROR("dev->dma is NULL\n");
629 return -EFAULT;
630 }
631
632 /* Make drm_addbufs happy by not trying to create a mapping for less
633 * than a page.
634 */
635 if (warp_size < PAGE_SIZE)
636 warp_size = PAGE_SIZE;
637
638 /* The proper alignment is 0x100 for this mapping */
639 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
640 _DRM_READ_ONLY, &dev_priv->warp);
641 if (err != 0) {
642 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
643 err);
644 return err;
645 }
646
647 /* Other than the bottom two bits being used to encode other
648 * information, there don't appear to be any restrictions on the
649 * alignment of the primary or secondary DMA buffers.
650 */
651
652 for (primary_size = dma_bs->primary_size; primary_size != 0;
653 primary_size >>= 1) {
654 /* The proper alignment for this mapping is 0x04 */
655 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
656 _DRM_READ_ONLY, &dev_priv->primary);
657 if (!err)
658 break;
659 }
660
661 if (err != 0) {
662 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
663 return -ENOMEM;
664 }
665
666 if (dev_priv->primary->size != dma_bs->primary_size) {
667 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
668 dma_bs->primary_size,
669 (unsigned)dev_priv->primary->size);
670 dma_bs->primary_size = dev_priv->primary->size;
671 }
672
673 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
674 bin_count--) {
675 (void)memset(&req, 0, sizeof(req));
676 req.count = bin_count;
677 req.size = dma_bs->secondary_bin_size;
678
679 err = drm_addbufs_pci(dev, &req);
680 if (!err)
681 break;
682 }
683
684 if (bin_count == 0) {
685 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
686 return err;
687 }
688
689 if (bin_count != dma_bs->secondary_bin_count) {
690 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
691 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
692
693 dma_bs->secondary_bin_count = bin_count;
694 }
695
696 dev_priv->dma_access = 0;
697 dev_priv->wagp_enable = 0;
698
699 dma_bs->agp_mode = 0;
700
701 DRM_INFO("Initialized card for PCI DMA.\n");
702 return 0;
703 }
704
705 static int mga_do_dma_bootstrap(struct drm_device *dev,
706 drm_mga_dma_bootstrap_t *dma_bs)
707 {
708 const int is_agp = (dma_bs->agp_mode != 0) && drm_pci_device_is_agp(dev);
709 int err;
710 drm_mga_private_t *const dev_priv =
711 (drm_mga_private_t *) dev->dev_private;
712
713 dev_priv->used_new_dma_init = 1;
714
715 /* The first steps are the same for both PCI and AGP based DMA. Map
716 * the cards MMIO registers and map a status page.
717 */
718 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
719 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
720 if (err) {
721 DRM_ERROR("Unable to map MMIO region: %d\n", err);
722 return err;
723 }
724
725 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
726 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
727 &dev_priv->status);
728 if (err) {
729 DRM_ERROR("Unable to map status region: %d\n", err);
730 return err;
731 }
732
733 /* The DMA initialization procedure is slightly different for PCI and
734 * AGP cards. AGP cards just allocate a large block of AGP memory and
735 * carve off portions of it for internal uses. The remaining memory
736 * is returned to user-mode to be used for AGP textures.
737 */
738 if (is_agp)
739 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
740
741 /* If we attempted to initialize the card for AGP DMA but failed,
742 * clean-up any mess that may have been created.
743 */
744
745 if (err)
746 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
747
748 /* Not only do we want to try and initialized PCI cards for PCI DMA,
749 * but we also try to initialized AGP cards that could not be
750 * initialized for AGP DMA. This covers the case where we have an AGP
751 * card in a system with an unsupported AGP chipset. In that case the
752 * card will be detected as AGP, but we won't be able to allocate any
753 * AGP memory, etc.
754 */
755
756 if (!is_agp || err)
757 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
758
759 return err;
760 }
761
762 int mga_dma_bootstrap(struct drm_device *dev, void *data,
763 struct drm_file *file_priv)
764 {
765 drm_mga_dma_bootstrap_t *bootstrap = data;
766 int err;
767 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
768 const drm_mga_private_t *const dev_priv =
769 (drm_mga_private_t *) dev->dev_private;
770
771 err = mga_do_dma_bootstrap(dev, bootstrap);
772 if (err) {
773 mga_do_cleanup_dma(dev, FULL_CLEANUP);
774 return err;
775 }
776
777 if (dev_priv->agp_textures != NULL) {
778 bootstrap->texture_handle = dev_priv->agp_textures->offset;
779 bootstrap->texture_size = dev_priv->agp_textures->size;
780 } else {
781 bootstrap->texture_handle = 0;
782 bootstrap->texture_size = 0;
783 }
784
785 bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
786
787 return err;
788 }
789
790 static int mga_do_init_dma(struct drm_device *dev, drm_mga_init_t *init)
791 {
792 drm_mga_private_t *dev_priv;
793 int ret;
794 DRM_DEBUG("\n");
795
796 dev_priv = dev->dev_private;
797
798 if (init->sgram)
799 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
800 else
801 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
802 dev_priv->maccess = init->maccess;
803
804 dev_priv->fb_cpp = init->fb_cpp;
805 dev_priv->front_offset = init->front_offset;
806 dev_priv->front_pitch = init->front_pitch;
807 dev_priv->back_offset = init->back_offset;
808 dev_priv->back_pitch = init->back_pitch;
809
810 dev_priv->depth_cpp = init->depth_cpp;
811 dev_priv->depth_offset = init->depth_offset;
812 dev_priv->depth_pitch = init->depth_pitch;
813
814 /* FIXME: Need to support AGP textures...
815 */
816 dev_priv->texture_offset = init->texture_offset[0];
817 dev_priv->texture_size = init->texture_size[0];
818
819 dev_priv->sarea = drm_getsarea(dev);
820 if (!dev_priv->sarea) {
821 DRM_ERROR("failed to find sarea!\n");
822 return -EINVAL;
823 }
824
825 if (!dev_priv->used_new_dma_init) {
826
827 dev_priv->dma_access = MGA_PAGPXFER;
828 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
829
830 dev_priv->status = drm_core_findmap(dev, init->status_offset);
831 if (!dev_priv->status) {
832 DRM_ERROR("failed to find status page!\n");
833 return -EINVAL;
834 }
835 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
836 if (!dev_priv->mmio) {
837 DRM_ERROR("failed to find mmio region!\n");
838 return -EINVAL;
839 }
840 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
841 if (!dev_priv->warp) {
842 DRM_ERROR("failed to find warp microcode region!\n");
843 return -EINVAL;
844 }
845 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
846 if (!dev_priv->primary) {
847 DRM_ERROR("failed to find primary dma region!\n");
848 return -EINVAL;
849 }
850 dev->agp_buffer_token = init->buffers_offset;
851 dev->agp_buffer_map =
852 drm_core_findmap(dev, init->buffers_offset);
853 if (!dev->agp_buffer_map) {
854 DRM_ERROR("failed to find dma buffer region!\n");
855 return -EINVAL;
856 }
857
858 drm_core_ioremap(dev_priv->warp, dev);
859 drm_core_ioremap(dev_priv->primary, dev);
860 drm_core_ioremap(dev->agp_buffer_map, dev);
861 }
862
863 dev_priv->sarea_priv =
864 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
865 init->sarea_priv_offset);
866
867 if (!dev_priv->warp->handle ||
868 !dev_priv->primary->handle ||
869 ((dev_priv->dma_access != 0) &&
870 ((dev->agp_buffer_map == NULL) ||
871 (dev->agp_buffer_map->handle == NULL)))) {
872 DRM_ERROR("failed to ioremap agp regions!\n");
873 return -ENOMEM;
874 }
875
876 ret = mga_warp_install_microcode(dev_priv);
877 if (ret < 0) {
878 DRM_ERROR("failed to install WARP ucode!: %d\n", ret);
879 return ret;
880 }
881
882 ret = mga_warp_init(dev_priv);
883 if (ret < 0) {
884 DRM_ERROR("failed to init WARP engine!: %d\n", ret);
885 return ret;
886 }
887
888 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
889
890 mga_do_wait_for_idle(dev_priv);
891
892 /* Init the primary DMA registers.
893 */
894 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
895 #if 0
896 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
897 MGA_PRIMPTREN1); /* DWGSYNC */
898 #endif
899
900 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
901 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
902 + dev_priv->primary->size);
903 dev_priv->prim.size = dev_priv->primary->size;
904
905 dev_priv->prim.tail = 0;
906 dev_priv->prim.space = dev_priv->prim.size;
907 dev_priv->prim.wrapped = 0;
908
909 dev_priv->prim.last_flush = 0;
910 dev_priv->prim.last_wrap = 0;
911
912 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
913
914 dev_priv->prim.status[0] = dev_priv->primary->offset;
915 dev_priv->prim.status[1] = 0;
916
917 dev_priv->sarea_priv->last_wrap = 0;
918 dev_priv->sarea_priv->last_frame.head = 0;
919 dev_priv->sarea_priv->last_frame.wrap = 0;
920
921 if (mga_freelist_init(dev, dev_priv) < 0) {
922 DRM_ERROR("could not initialize freelist\n");
923 return -ENOMEM;
924 }
925
926 return 0;
927 }
928
929 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
930 {
931 int err = 0;
932 DRM_DEBUG("\n");
933
934 /* Make sure interrupts are disabled here because the uninstall ioctl
935 * may not have been called from userspace and after dev_private
936 * is freed, it's too late.
937 */
938 if (dev->irq_enabled)
939 drm_irq_uninstall(dev);
940
941 if (dev->dev_private) {
942 drm_mga_private_t *dev_priv = dev->dev_private;
943
944 if ((dev_priv->warp != NULL)
945 && (dev_priv->warp->type != _DRM_CONSISTENT))
946 drm_core_ioremapfree(dev_priv->warp, dev);
947
948 if ((dev_priv->primary != NULL)
949 && (dev_priv->primary->type != _DRM_CONSISTENT))
950 drm_core_ioremapfree(dev_priv->primary, dev);
951
952 if (dev->agp_buffer_map != NULL)
953 drm_core_ioremapfree(dev->agp_buffer_map, dev);
954
955 if (dev_priv->used_new_dma_init) {
956 #if __OS_HAS_AGP
957 if (dev_priv->agp_handle != 0) {
958 struct drm_agp_binding unbind_req;
959 struct drm_agp_buffer free_req;
960
961 unbind_req.handle = dev_priv->agp_handle;
962 drm_agp_unbind(dev, &unbind_req);
963
964 free_req.handle = dev_priv->agp_handle;
965 drm_agp_free(dev, &free_req);
966
967 dev_priv->agp_textures = NULL;
968 dev_priv->agp_size = 0;
969 dev_priv->agp_handle = 0;
970 }
971
972 if ((dev->agp != NULL) && dev->agp->acquired)
973 err = drm_agp_release(dev);
974 #endif
975 }
976
977 dev_priv->warp = NULL;
978 dev_priv->primary = NULL;
979 dev_priv->sarea = NULL;
980 dev_priv->sarea_priv = NULL;
981 dev->agp_buffer_map = NULL;
982
983 if (full_cleanup) {
984 dev_priv->mmio = NULL;
985 dev_priv->status = NULL;
986 dev_priv->used_new_dma_init = 0;
987 }
988
989 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
990 dev_priv->warp_pipe = 0;
991 memset(dev_priv->warp_pipe_phys, 0,
992 sizeof(dev_priv->warp_pipe_phys));
993
994 if (dev_priv->head != NULL)
995 mga_freelist_cleanup(dev);
996 }
997
998 return err;
999 }
1000
1001 int mga_dma_init(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv)
1003 {
1004 drm_mga_init_t *init = data;
1005 int err;
1006
1007 LOCK_TEST_WITH_RETURN(dev, file_priv);
1008
1009 switch (init->func) {
1010 case MGA_INIT_DMA:
1011 err = mga_do_init_dma(dev, init);
1012 if (err)
1013 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1014 return err;
1015 case MGA_CLEANUP_DMA:
1016 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1017 }
1018
1019 return -EINVAL;
1020 }
1021
1022 /* ================================================================
1023 * Primary DMA stream management
1024 */
1025
1026 int mga_dma_flush(struct drm_device *dev, void *data,
1027 struct drm_file *file_priv)
1028 {
1029 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1030 struct drm_lock *lock = data;
1031
1032 LOCK_TEST_WITH_RETURN(dev, file_priv);
1033
1034 DRM_DEBUG("%s%s%s\n",
1035 (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1036 (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1037 (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1038
1039 WRAP_WAIT_WITH_RETURN(dev_priv);
1040
1041 if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL))
1042 mga_do_dma_flush(dev_priv);
1043
1044 if (lock->flags & _DRM_LOCK_QUIESCENT) {
1045 #if MGA_DMA_DEBUG
1046 int ret = mga_do_wait_for_idle(dev_priv);
1047 if (ret < 0)
1048 DRM_INFO("-EBUSY\n");
1049 return ret;
1050 #else
1051 return mga_do_wait_for_idle(dev_priv);
1052 #endif
1053 } else {
1054 return 0;
1055 }
1056 }
1057
1058 int mga_dma_reset(struct drm_device *dev, void *data,
1059 struct drm_file *file_priv)
1060 {
1061 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1062
1063 LOCK_TEST_WITH_RETURN(dev, file_priv);
1064
1065 return mga_do_dma_reset(dev_priv);
1066 }
1067
1068 /* ================================================================
1069 * DMA buffer management
1070 */
1071
1072 static int mga_dma_get_buffers(struct drm_device *dev,
1073 struct drm_file *file_priv, struct drm_dma *d)
1074 {
1075 struct drm_buf *buf;
1076 int i;
1077
1078 for (i = d->granted_count; i < d->request_count; i++) {
1079 buf = mga_freelist_get(dev);
1080 if (!buf)
1081 return -EAGAIN;
1082
1083 buf->file_priv = file_priv;
1084
1085 if (DRM_COPY_TO_USER(&d->request_indices[i],
1086 &buf->idx, sizeof(buf->idx)))
1087 return -EFAULT;
1088 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1089 &buf->total, sizeof(buf->total)))
1090 return -EFAULT;
1091
1092 d->granted_count++;
1093 }
1094 return 0;
1095 }
1096
1097 int mga_dma_buffers(struct drm_device *dev, void *data,
1098 struct drm_file *file_priv)
1099 {
1100 struct drm_device_dma *dma = dev->dma;
1101 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1102 struct drm_dma *d = data;
1103 int ret = 0;
1104
1105 LOCK_TEST_WITH_RETURN(dev, file_priv);
1106
1107 /* Please don't send us buffers.
1108 */
1109 if (d->send_count != 0) {
1110 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1111 DRM_CURRENTPID, d->send_count);
1112 return -EINVAL;
1113 }
1114
1115 /* We'll send you buffers.
1116 */
1117 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1118 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1119 DRM_CURRENTPID, d->request_count, dma->buf_count);
1120 return -EINVAL;
1121 }
1122
1123 WRAP_TEST_WITH_RETURN(dev_priv);
1124
1125 d->granted_count = 0;
1126
1127 if (d->request_count)
1128 ret = mga_dma_get_buffers(dev, file_priv, d);
1129
1130 return ret;
1131 }
1132
1133 /**
1134 * Called just before the module is unloaded.
1135 */
1136 int mga_driver_unload(struct drm_device *dev)
1137 {
1138 kfree(dev->dev_private);
1139 dev->dev_private = NULL;
1140
1141 return 0;
1142 }
1143
1144 /**
1145 * Called when the last opener of the device is closed.
1146 */
1147 void mga_driver_lastclose(struct drm_device *dev)
1148 {
1149 mga_do_cleanup_dma(dev, FULL_CLEANUP);
1150 }
1151
1152 int mga_driver_dma_quiescent(struct drm_device *dev)
1153 {
1154 drm_mga_private_t *dev_priv = dev->dev_private;
1155 return mga_do_wait_for_idle(dev_priv);
1156 }
Linux with added FPC-III support