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block: fix module reference leak on put_disk() call for cgroups throttle
[linux/fpc-iii.git] / sound / pci / hda / hda_intel.c
blobe6de496bffbeb29c193989dd24f82bfa9bd1b7b5
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_HDA_CGCTL 0x48
94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
95 #define INTEL_SCH_HDA_DEVC 0x78
96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98 /* Define IN stream 0 FIFO size offset in VIA controller */
99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100 /* Define VIA HD Audio Device ID*/
101 #define VIA_HDAC_DEVICE_ID 0x3288
102
103 /* max number of SDs */
104 /* ICH, ATI and VIA have 4 playback and 4 capture */
105 #define ICH6_NUM_CAPTURE 4
106 #define ICH6_NUM_PLAYBACK 4
107
108 /* ULI has 6 playback and 5 capture */
109 #define ULI_NUM_CAPTURE 5
110 #define ULI_NUM_PLAYBACK 6
111
112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
113 #define ATIHDMI_NUM_CAPTURE 0
114 #define ATIHDMI_NUM_PLAYBACK 8
115
116 /* TERA has 4 playback and 3 capture */
117 #define TERA_NUM_CAPTURE 3
118 #define TERA_NUM_PLAYBACK 4
119
120
121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
124 static char *model[SNDRV_CARDS];
125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_only[SNDRV_CARDS];
129 static int jackpoll_ms[SNDRV_CARDS];
130 static bool single_cmd;
131 static int enable_msi = -1;
132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
133 static char *patch[SNDRV_CARDS];
134 #endif
135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138 #endif
139
140 module_param_array(index, int, NULL, 0444);
141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
142 module_param_array(id, charp, NULL, 0444);
143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
144 module_param_array(enable, bool, NULL, 0444);
145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146 module_param_array(model, charp, NULL, 0444);
147 MODULE_PARM_DESC(model, "Use the given board model.");
148 module_param_array(position_fix, int, NULL, 0444);
149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
151 module_param_array(bdl_pos_adj, int, NULL, 0644);
152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
153 module_param_array(probe_mask, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
155 module_param_array(probe_only, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
157 module_param_array(jackpoll_ms, int, NULL, 0444);
158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
159 module_param(single_cmd, bool, 0444);
160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
162 module_param(enable_msi, bint, 0444);
163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
165 module_param_array(patch, charp, NULL, 0444);
166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167 #endif
168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
169 module_param_array(beep_mode, bool, NULL, 0444);
170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
171 "(0=off, 1=on) (default=1).");
172 #endif
173
174 #ifdef CONFIG_PM
175 static int param_set_xint(const char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops param_ops_xint = {
177 .set = param_set_xint,
178 .get = param_get_int,
179 };
180 #define param_check_xint param_check_int
181
182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
183 module_param(power_save, xint, 0644);
184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
186
187 /* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
191 static bool power_save_controller = 1;
192 module_param(power_save_controller, bool, 0644);
193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
194 #else
195 #define power_save 0
196 #endif /* CONFIG_PM */
197
198 static int align_buffer_size = -1;
199 module_param(align_buffer_size, bint, 0644);
200 MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
203 #ifdef CONFIG_X86
204 static int hda_snoop = -1;
205 module_param_named(snoop, hda_snoop, bint, 0444);
206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
207 #else
208 #define hda_snoop true
209 #endif
210
211
212 MODULE_LICENSE("GPL");
213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
215 "{Intel, ICH7},"
216 "{Intel, ESB2},"
217 "{Intel, ICH8},"
218 "{Intel, ICH9},"
219 "{Intel, ICH10},"
220 "{Intel, PCH},"
221 "{Intel, CPT},"
222 "{Intel, PPT},"
223 "{Intel, LPT},"
224 "{Intel, LPT_LP},"
225 "{Intel, WPT_LP},"
226 "{Intel, SPT},"
227 "{Intel, SPT_LP},"
228 "{Intel, HPT},"
229 "{Intel, PBG},"
230 "{Intel, SCH},"
231 "{ATI, SB450},"
232 "{ATI, SB600},"
233 "{ATI, RS600},"
234 "{ATI, RS690},"
235 "{ATI, RS780},"
236 "{ATI, R600},"
237 "{ATI, RV630},"
238 "{ATI, RV610},"
239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
243 "{VIA, VT8251},"
244 "{VIA, VT8237A},"
245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
247 MODULE_DESCRIPTION("Intel HDA driver");
248
249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
251 #define SUPPORT_VGA_SWITCHEROO
252 #endif
253 #endif
254
255
256 /*
257 */
258
259 /* driver types */
260 enum {
261 AZX_DRIVER_ICH,
262 AZX_DRIVER_PCH,
263 AZX_DRIVER_SCH,
264 AZX_DRIVER_HDMI,
265 AZX_DRIVER_ATI,
266 AZX_DRIVER_ATIHDMI,
267 AZX_DRIVER_ATIHDMI_NS,
268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
271 AZX_DRIVER_NVIDIA,
272 AZX_DRIVER_TERA,
273 AZX_DRIVER_CTX,
274 AZX_DRIVER_CTHDA,
275 AZX_DRIVER_CMEDIA,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
287
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_NOPM \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
292
293 #define AZX_DCAPS_INTEL_PCH \
294 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
295
296 #define AZX_DCAPS_INTEL_HASWELL \
297 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
299 AZX_DCAPS_SNOOP_TYPE(SCH))
300
301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
302 #define AZX_DCAPS_INTEL_BROADWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
306
307 #define AZX_DCAPS_INTEL_BAYTRAIL \
308 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
309
310 #define AZX_DCAPS_INTEL_BRASWELL \
311 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
312
313 #define AZX_DCAPS_INTEL_SKYLAKE \
314 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
315 AZX_DCAPS_I915_POWERWELL)
316
317 #define AZX_DCAPS_INTEL_BROXTON \
318 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
319 AZX_DCAPS_I915_POWERWELL)
320
321 /* quirks for ATI SB / AMD Hudson */
322 #define AZX_DCAPS_PRESET_ATI_SB \
323 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
324 AZX_DCAPS_SNOOP_TYPE(ATI))
325
326 /* quirks for ATI/AMD HDMI */
327 #define AZX_DCAPS_PRESET_ATI_HDMI \
328 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
329 AZX_DCAPS_NO_MSI64)
330
331 /* quirks for ATI HDMI with snoop off */
332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
333 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
334
335 /* quirks for Nvidia */
336 #define AZX_DCAPS_PRESET_NVIDIA \
337 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
338 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
339
340 #define AZX_DCAPS_PRESET_CTHDA \
341 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
342 AZX_DCAPS_NO_64BIT |\
343 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
344
345 /*
346 * vga_switcheroo support
347 */
348 #ifdef SUPPORT_VGA_SWITCHEROO
349 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
350 #else
351 #define use_vga_switcheroo(chip) 0
352 #endif
353
354 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
355 ((pci)->device == 0x0c0c) || \
356 ((pci)->device == 0x0d0c) || \
357 ((pci)->device == 0x160c))
358
359 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
360 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
361 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
362 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
363 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
364 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
365 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
366 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
367
368 static char *driver_short_names[] = {
369 [AZX_DRIVER_ICH] = "HDA Intel",
370 [AZX_DRIVER_PCH] = "HDA Intel PCH",
371 [AZX_DRIVER_SCH] = "HDA Intel MID",
372 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
373 [AZX_DRIVER_ATI] = "HDA ATI SB",
374 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
375 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
376 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
377 [AZX_DRIVER_SIS] = "HDA SIS966",
378 [AZX_DRIVER_ULI] = "HDA ULI M5461",
379 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
380 [AZX_DRIVER_TERA] = "HDA Teradici",
381 [AZX_DRIVER_CTX] = "HDA Creative",
382 [AZX_DRIVER_CTHDA] = "HDA Creative",
383 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
384 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
385 };
386
387 #ifdef CONFIG_X86
388 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
389 {
390 int pages;
391
392 if (azx_snoop(chip))
393 return;
394 if (!dmab || !dmab->area || !dmab->bytes)
395 return;
396
397 #ifdef CONFIG_SND_DMA_SGBUF
398 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
399 struct snd_sg_buf *sgbuf = dmab->private_data;
400 if (chip->driver_type == AZX_DRIVER_CMEDIA)
401 return; /* deal with only CORB/RIRB buffers */
402 if (on)
403 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
404 else
405 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
406 return;
407 }
408 #endif
409
410 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
411 if (on)
412 set_memory_wc((unsigned long)dmab->area, pages);
413 else
414 set_memory_wb((unsigned long)dmab->area, pages);
415 }
416
417 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419 {
420 __mark_pages_wc(chip, buf, on);
421 }
422 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
423 struct snd_pcm_substream *substream, bool on)
424 {
425 if (azx_dev->wc_marked != on) {
426 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
427 azx_dev->wc_marked = on;
428 }
429 }
430 #else
431 /* NOP for other archs */
432 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
433 bool on)
434 {
435 }
436 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
437 struct snd_pcm_substream *substream, bool on)
438 {
439 }
440 #endif
441
442 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
443
444 /*
445 * initialize the PCI registers
446 */
447 /* update bits in a PCI register byte */
448 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
449 unsigned char mask, unsigned char val)
450 {
451 unsigned char data;
452
453 pci_read_config_byte(pci, reg, &data);
454 data &= ~mask;
455 data |= (val & mask);
456 pci_write_config_byte(pci, reg, data);
457 }
458
459 static void azx_init_pci(struct azx *chip)
460 {
461 int snoop_type = azx_get_snoop_type(chip);
462
463 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
464 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
465 * Ensuring these bits are 0 clears playback static on some HD Audio
466 * codecs.
467 * The PCI register TCSEL is defined in the Intel manuals.
468 */
469 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
470 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
471 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
472 }
473
474 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
475 * we need to enable snoop.
476 */
477 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
478 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
479 azx_snoop(chip));
480 update_pci_byte(chip->pci,
481 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
482 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
483 }
484
485 /* For NVIDIA HDA, enable snoop */
486 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
487 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
488 azx_snoop(chip));
489 update_pci_byte(chip->pci,
490 NVIDIA_HDA_TRANSREG_ADDR,
491 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_ISTRM_COH,
494 0x01, NVIDIA_HDA_ENABLE_COHBIT);
495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_OSTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 }
499
500 /* Enable SCH/PCH snoop if needed */
501 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
502 unsigned short snoop;
503 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
504 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
505 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
506 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
507 if (!azx_snoop(chip))
508 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
509 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
510 pci_read_config_word(chip->pci,
511 INTEL_SCH_HDA_DEVC, &snoop);
512 }
513 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
514 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
515 "Disabled" : "Enabled");
516 }
517 }
518
519 /*
520 * In BXT-P A0, HD-Audio DMA requests is later than expected,
521 * and makes an audio stream sensitive to system latencies when
522 * 24/32 bits are playing.
523 * Adjusting threshold of DMA fifo to force the DMA request
524 * sooner to improve latency tolerance at the expense of power.
525 */
526 static void bxt_reduce_dma_latency(struct azx *chip)
527 {
528 u32 val;
529
530 val = azx_readl(chip, SKL_EM4L);
531 val &= (0x3 << 20);
532 azx_writel(chip, SKL_EM4L, val);
533 }
534
535 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
536 {
537 struct hdac_bus *bus = azx_bus(chip);
538 struct pci_dev *pci = chip->pci;
539 u32 val;
540
541 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
542 snd_hdac_set_codec_wakeup(bus, true);
543 if (IS_SKL_PLUS(pci)) {
544 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
545 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
546 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
547 }
548 azx_init_chip(chip, full_reset);
549 if (IS_SKL_PLUS(pci)) {
550 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
551 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
552 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
553 }
554 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
555 snd_hdac_set_codec_wakeup(bus, false);
556
557 /* reduce dma latency to avoid noise */
558 if (IS_BXT(pci))
559 bxt_reduce_dma_latency(chip);
560 }
561
562 /* calculate runtime delay from LPIB */
563 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
564 unsigned int pos)
565 {
566 struct snd_pcm_substream *substream = azx_dev->core.substream;
567 int stream = substream->stream;
568 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
569 int delay;
570
571 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
572 delay = pos - lpib_pos;
573 else
574 delay = lpib_pos - pos;
575 if (delay < 0) {
576 if (delay >= azx_dev->core.delay_negative_threshold)
577 delay = 0;
578 else
579 delay += azx_dev->core.bufsize;
580 }
581
582 if (delay >= azx_dev->core.period_bytes) {
583 dev_info(chip->card->dev,
584 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
585 delay, azx_dev->core.period_bytes);
586 delay = 0;
587 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
588 chip->get_delay[stream] = NULL;
589 }
590
591 return bytes_to_frames(substream->runtime, delay);
592 }
593
594 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
595
596 /* called from IRQ */
597 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
598 {
599 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
600 int ok;
601
602 ok = azx_position_ok(chip, azx_dev);
603 if (ok == 1) {
604 azx_dev->irq_pending = 0;
605 return ok;
606 } else if (ok == 0) {
607 /* bogus IRQ, process it later */
608 azx_dev->irq_pending = 1;
609 schedule_work(&hda->irq_pending_work);
610 }
611 return 0;
612 }
613
614 /* Enable/disable i915 display power for the link */
615 static int azx_intel_link_power(struct azx *chip, bool enable)
616 {
617 struct hdac_bus *bus = azx_bus(chip);
618
619 return snd_hdac_display_power(bus, enable);
620 }
621
622 /*
623 * Check whether the current DMA position is acceptable for updating
624 * periods. Returns non-zero if it's OK.
625 *
626 * Many HD-audio controllers appear pretty inaccurate about
627 * the update-IRQ timing. The IRQ is issued before actually the
628 * data is processed. So, we need to process it afterwords in a
629 * workqueue.
630 */
631 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
632 {
633 struct snd_pcm_substream *substream = azx_dev->core.substream;
634 int stream = substream->stream;
635 u32 wallclk;
636 unsigned int pos;
637
638 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
639 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
640 return -1; /* bogus (too early) interrupt */
641
642 if (chip->get_position[stream])
643 pos = chip->get_position[stream](chip, azx_dev);
644 else { /* use the position buffer as default */
645 pos = azx_get_pos_posbuf(chip, azx_dev);
646 if (!pos || pos == (u32)-1) {
647 dev_info(chip->card->dev,
648 "Invalid position buffer, using LPIB read method instead.\n");
649 chip->get_position[stream] = azx_get_pos_lpib;
650 if (chip->get_position[0] == azx_get_pos_lpib &&
651 chip->get_position[1] == azx_get_pos_lpib)
652 azx_bus(chip)->use_posbuf = false;
653 pos = azx_get_pos_lpib(chip, azx_dev);
654 chip->get_delay[stream] = NULL;
655 } else {
656 chip->get_position[stream] = azx_get_pos_posbuf;
657 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
658 chip->get_delay[stream] = azx_get_delay_from_lpib;
659 }
660 }
661
662 if (pos >= azx_dev->core.bufsize)
663 pos = 0;
664
665 if (WARN_ONCE(!azx_dev->core.period_bytes,
666 "hda-intel: zero azx_dev->period_bytes"))
667 return -1; /* this shouldn't happen! */
668 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
669 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
670 /* NG - it's below the first next period boundary */
671 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
672 azx_dev->core.start_wallclk += wallclk;
673 return 1; /* OK, it's fine */
674 }
675
676 /*
677 * The work for pending PCM period updates.
678 */
679 static void azx_irq_pending_work(struct work_struct *work)
680 {
681 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
682 struct azx *chip = &hda->chip;
683 struct hdac_bus *bus = azx_bus(chip);
684 struct hdac_stream *s;
685 int pending, ok;
686
687 if (!hda->irq_pending_warned) {
688 dev_info(chip->card->dev,
689 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
690 chip->card->number);
691 hda->irq_pending_warned = 1;
692 }
693
694 for (;;) {
695 pending = 0;
696 spin_lock_irq(&bus->reg_lock);
697 list_for_each_entry(s, &bus->stream_list, list) {
698 struct azx_dev *azx_dev = stream_to_azx_dev(s);
699 if (!azx_dev->irq_pending ||
700 !s->substream ||
701 !s->running)
702 continue;
703 ok = azx_position_ok(chip, azx_dev);
704 if (ok > 0) {
705 azx_dev->irq_pending = 0;
706 spin_unlock(&bus->reg_lock);
707 snd_pcm_period_elapsed(s->substream);
708 spin_lock(&bus->reg_lock);
709 } else if (ok < 0) {
710 pending = 0; /* too early */
711 } else
712 pending++;
713 }
714 spin_unlock_irq(&bus->reg_lock);
715 if (!pending)
716 return;
717 msleep(1);
718 }
719 }
720
721 /* clear irq_pending flags and assure no on-going workq */
722 static void azx_clear_irq_pending(struct azx *chip)
723 {
724 struct hdac_bus *bus = azx_bus(chip);
725 struct hdac_stream *s;
726
727 spin_lock_irq(&bus->reg_lock);
728 list_for_each_entry(s, &bus->stream_list, list) {
729 struct azx_dev *azx_dev = stream_to_azx_dev(s);
730 azx_dev->irq_pending = 0;
731 }
732 spin_unlock_irq(&bus->reg_lock);
733 }
734
735 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
736 {
737 struct hdac_bus *bus = azx_bus(chip);
738
739 if (request_irq(chip->pci->irq, azx_interrupt,
740 chip->msi ? 0 : IRQF_SHARED,
741 KBUILD_MODNAME, chip)) {
742 dev_err(chip->card->dev,
743 "unable to grab IRQ %d, disabling device\n",
744 chip->pci->irq);
745 if (do_disconnect)
746 snd_card_disconnect(chip->card);
747 return -1;
748 }
749 bus->irq = chip->pci->irq;
750 pci_intx(chip->pci, !chip->msi);
751 return 0;
752 }
753
754 /* get the current DMA position with correction on VIA chips */
755 static unsigned int azx_via_get_position(struct azx *chip,
756 struct azx_dev *azx_dev)
757 {
758 unsigned int link_pos, mini_pos, bound_pos;
759 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
760 unsigned int fifo_size;
761
762 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
763 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
764 /* Playback, no problem using link position */
765 return link_pos;
766 }
767
768 /* Capture */
769 /* For new chipset,
770 * use mod to get the DMA position just like old chipset
771 */
772 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
773 mod_dma_pos %= azx_dev->core.period_bytes;
774
775 /* azx_dev->fifo_size can't get FIFO size of in stream.
776 * Get from base address + offset.
777 */
778 fifo_size = readw(azx_bus(chip)->remap_addr +
779 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
780
781 if (azx_dev->insufficient) {
782 /* Link position never gather than FIFO size */
783 if (link_pos <= fifo_size)
784 return 0;
785
786 azx_dev->insufficient = 0;
787 }
788
789 if (link_pos <= fifo_size)
790 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
791 else
792 mini_pos = link_pos - fifo_size;
793
794 /* Find nearest previous boudary */
795 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
796 mod_link_pos = link_pos % azx_dev->core.period_bytes;
797 if (mod_link_pos >= fifo_size)
798 bound_pos = link_pos - mod_link_pos;
799 else if (mod_dma_pos >= mod_mini_pos)
800 bound_pos = mini_pos - mod_mini_pos;
801 else {
802 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
803 if (bound_pos >= azx_dev->core.bufsize)
804 bound_pos = 0;
805 }
806
807 /* Calculate real DMA position we want */
808 return bound_pos + mod_dma_pos;
809 }
810
811 #ifdef CONFIG_PM
812 static DEFINE_MUTEX(card_list_lock);
813 static LIST_HEAD(card_list);
814
815 static void azx_add_card_list(struct azx *chip)
816 {
817 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
818 mutex_lock(&card_list_lock);
819 list_add(&hda->list, &card_list);
820 mutex_unlock(&card_list_lock);
821 }
822
823 static void azx_del_card_list(struct azx *chip)
824 {
825 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
826 mutex_lock(&card_list_lock);
827 list_del_init(&hda->list);
828 mutex_unlock(&card_list_lock);
829 }
830
831 /* trigger power-save check at writing parameter */
832 static int param_set_xint(const char *val, const struct kernel_param *kp)
833 {
834 struct hda_intel *hda;
835 struct azx *chip;
836 int prev = power_save;
837 int ret = param_set_int(val, kp);
838
839 if (ret || prev == power_save)
840 return ret;
841
842 mutex_lock(&card_list_lock);
843 list_for_each_entry(hda, &card_list, list) {
844 chip = &hda->chip;
845 if (!hda->probe_continued || chip->disabled)
846 continue;
847 snd_hda_set_power_save(&chip->bus, power_save * 1000);
848 }
849 mutex_unlock(&card_list_lock);
850 return 0;
851 }
852 #else
853 #define azx_add_card_list(chip) /* NOP */
854 #define azx_del_card_list(chip) /* NOP */
855 #endif /* CONFIG_PM */
856
857 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
858 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
859 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
860 * BCLK = CDCLK * M / N
861 * The values will be lost when the display power well is disabled and need to
862 * be restored to avoid abnormal playback speed.
863 */
864 static void haswell_set_bclk(struct hda_intel *hda)
865 {
866 struct azx *chip = &hda->chip;
867 int cdclk_freq;
868 unsigned int bclk_m, bclk_n;
869
870 if (!hda->need_i915_power)
871 return;
872
873 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
874 switch (cdclk_freq) {
875 case 337500:
876 bclk_m = 16;
877 bclk_n = 225;
878 break;
879
880 case 450000:
881 default: /* default CDCLK 450MHz */
882 bclk_m = 4;
883 bclk_n = 75;
884 break;
885
886 case 540000:
887 bclk_m = 4;
888 bclk_n = 90;
889 break;
890
891 case 675000:
892 bclk_m = 8;
893 bclk_n = 225;
894 break;
895 }
896
897 azx_writew(chip, HSW_EM4, bclk_m);
898 azx_writew(chip, HSW_EM5, bclk_n);
899 }
900
901 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
902 /*
903 * power management
904 */
905 static int azx_suspend(struct device *dev)
906 {
907 struct snd_card *card = dev_get_drvdata(dev);
908 struct azx *chip;
909 struct hda_intel *hda;
910 struct hdac_bus *bus;
911
912 if (!card)
913 return 0;
914
915 chip = card->private_data;
916 hda = container_of(chip, struct hda_intel, chip);
917 if (chip->disabled || hda->init_failed || !chip->running)
918 return 0;
919
920 bus = azx_bus(chip);
921 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
922 azx_clear_irq_pending(chip);
923 azx_stop_chip(chip);
924 azx_enter_link_reset(chip);
925 if (bus->irq >= 0) {
926 free_irq(bus->irq, chip);
927 bus->irq = -1;
928 }
929
930 if (chip->msi)
931 pci_disable_msi(chip->pci);
932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
933 && hda->need_i915_power)
934 snd_hdac_display_power(bus, false);
935
936 trace_azx_suspend(chip);
937 return 0;
938 }
939
940 static int azx_resume(struct device *dev)
941 {
942 struct pci_dev *pci = to_pci_dev(dev);
943 struct snd_card *card = dev_get_drvdata(dev);
944 struct azx *chip;
945 struct hda_intel *hda;
946 struct hdac_bus *bus;
947
948 if (!card)
949 return 0;
950
951 chip = card->private_data;
952 hda = container_of(chip, struct hda_intel, chip);
953 bus = azx_bus(chip);
954 if (chip->disabled || hda->init_failed || !chip->running)
955 return 0;
956
957 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
958 snd_hdac_display_power(bus, true);
959 if (hda->need_i915_power)
960 haswell_set_bclk(hda);
961 }
962
963 if (chip->msi)
964 if (pci_enable_msi(pci) < 0)
965 chip->msi = 0;
966 if (azx_acquire_irq(chip, 1) < 0)
967 return -EIO;
968 azx_init_pci(chip);
969
970 hda_intel_init_chip(chip, true);
971
972 /* power down again for link-controlled chips */
973 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
974 !hda->need_i915_power)
975 snd_hdac_display_power(bus, false);
976
977 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
978
979 trace_azx_resume(chip);
980 return 0;
981 }
982 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
983
984 #ifdef CONFIG_PM_SLEEP
985 /* put codec down to D3 at hibernation for Intel SKL+;
986 * otherwise BIOS may still access the codec and screw up the driver
987 */
988 static int azx_freeze_noirq(struct device *dev)
989 {
990 struct pci_dev *pci = to_pci_dev(dev);
991
992 if (IS_SKL_PLUS(pci))
993 pci_set_power_state(pci, PCI_D3hot);
994
995 return 0;
996 }
997
998 static int azx_thaw_noirq(struct device *dev)
999 {
1000 struct pci_dev *pci = to_pci_dev(dev);
1001
1002 if (IS_SKL_PLUS(pci))
1003 pci_set_power_state(pci, PCI_D0);
1004
1005 return 0;
1006 }
1007 #endif /* CONFIG_PM_SLEEP */
1008
1009 #ifdef CONFIG_PM
1010 static int azx_runtime_suspend(struct device *dev)
1011 {
1012 struct snd_card *card = dev_get_drvdata(dev);
1013 struct azx *chip;
1014 struct hda_intel *hda;
1015
1016 if (!card)
1017 return 0;
1018
1019 chip = card->private_data;
1020 hda = container_of(chip, struct hda_intel, chip);
1021 if (chip->disabled || hda->init_failed)
1022 return 0;
1023
1024 if (!azx_has_pm_runtime(chip))
1025 return 0;
1026
1027 /* enable controller wake up event */
1028 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1029 STATESTS_INT_MASK);
1030
1031 azx_stop_chip(chip);
1032 azx_enter_link_reset(chip);
1033 azx_clear_irq_pending(chip);
1034 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1035 && hda->need_i915_power)
1036 snd_hdac_display_power(azx_bus(chip), false);
1037
1038 trace_azx_runtime_suspend(chip);
1039 return 0;
1040 }
1041
1042 static int azx_runtime_resume(struct device *dev)
1043 {
1044 struct snd_card *card = dev_get_drvdata(dev);
1045 struct azx *chip;
1046 struct hda_intel *hda;
1047 struct hdac_bus *bus;
1048 struct hda_codec *codec;
1049 int status;
1050
1051 if (!card)
1052 return 0;
1053
1054 chip = card->private_data;
1055 hda = container_of(chip, struct hda_intel, chip);
1056 bus = azx_bus(chip);
1057 if (chip->disabled || hda->init_failed)
1058 return 0;
1059
1060 if (!azx_has_pm_runtime(chip))
1061 return 0;
1062
1063 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1064 snd_hdac_display_power(bus, true);
1065 if (hda->need_i915_power)
1066 haswell_set_bclk(hda);
1067 }
1068
1069 /* Read STATESTS before controller reset */
1070 status = azx_readw(chip, STATESTS);
1071
1072 azx_init_pci(chip);
1073 hda_intel_init_chip(chip, true);
1074
1075 if (status) {
1076 list_for_each_codec(codec, &chip->bus)
1077 if (status & (1 << codec->addr))
1078 schedule_delayed_work(&codec->jackpoll_work,
1079 codec->jackpoll_interval);
1080 }
1081
1082 /* disable controller Wake Up event*/
1083 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1084 ~STATESTS_INT_MASK);
1085
1086 /* power down again for link-controlled chips */
1087 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1088 !hda->need_i915_power)
1089 snd_hdac_display_power(bus, false);
1090
1091 trace_azx_runtime_resume(chip);
1092 return 0;
1093 }
1094
1095 static int azx_runtime_idle(struct device *dev)
1096 {
1097 struct snd_card *card = dev_get_drvdata(dev);
1098 struct azx *chip;
1099 struct hda_intel *hda;
1100
1101 if (!card)
1102 return 0;
1103
1104 chip = card->private_data;
1105 hda = container_of(chip, struct hda_intel, chip);
1106 if (chip->disabled || hda->init_failed)
1107 return 0;
1108
1109 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1110 azx_bus(chip)->codec_powered || !chip->running)
1111 return -EBUSY;
1112
1113 return 0;
1114 }
1115
1116 static const struct dev_pm_ops azx_pm = {
1117 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1118 #ifdef CONFIG_PM_SLEEP
1119 .freeze_noirq = azx_freeze_noirq,
1120 .thaw_noirq = azx_thaw_noirq,
1121 #endif
1122 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1123 };
1124
1125 #define AZX_PM_OPS &azx_pm
1126 #else
1127 #define AZX_PM_OPS NULL
1128 #endif /* CONFIG_PM */
1129
1130
1131 static int azx_probe_continue(struct azx *chip);
1132
1133 #ifdef SUPPORT_VGA_SWITCHEROO
1134 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1135
1136 static void azx_vs_set_state(struct pci_dev *pci,
1137 enum vga_switcheroo_state state)
1138 {
1139 struct snd_card *card = pci_get_drvdata(pci);
1140 struct azx *chip = card->private_data;
1141 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1142 bool disabled;
1143
1144 wait_for_completion(&hda->probe_wait);
1145 if (hda->init_failed)
1146 return;
1147
1148 disabled = (state == VGA_SWITCHEROO_OFF);
1149 if (chip->disabled == disabled)
1150 return;
1151
1152 if (!hda->probe_continued) {
1153 chip->disabled = disabled;
1154 if (!disabled) {
1155 dev_info(chip->card->dev,
1156 "Start delayed initialization\n");
1157 if (azx_probe_continue(chip) < 0) {
1158 dev_err(chip->card->dev, "initialization error\n");
1159 hda->init_failed = true;
1160 }
1161 }
1162 } else {
1163 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1164 disabled ? "Disabling" : "Enabling");
1165 if (disabled) {
1166 pm_runtime_put_sync_suspend(card->dev);
1167 azx_suspend(card->dev);
1168 /* when we get suspended by vga_switcheroo we end up in D3cold,
1169 * however we have no ACPI handle, so pci/acpi can't put us there,
1170 * put ourselves there */
1171 pci->current_state = PCI_D3cold;
1172 chip->disabled = true;
1173 if (snd_hda_lock_devices(&chip->bus))
1174 dev_warn(chip->card->dev,
1175 "Cannot lock devices!\n");
1176 } else {
1177 snd_hda_unlock_devices(&chip->bus);
1178 pm_runtime_get_noresume(card->dev);
1179 chip->disabled = false;
1180 azx_resume(card->dev);
1181 }
1182 }
1183 }
1184
1185 static bool azx_vs_can_switch(struct pci_dev *pci)
1186 {
1187 struct snd_card *card = pci_get_drvdata(pci);
1188 struct azx *chip = card->private_data;
1189 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1190
1191 wait_for_completion(&hda->probe_wait);
1192 if (hda->init_failed)
1193 return false;
1194 if (chip->disabled || !hda->probe_continued)
1195 return true;
1196 if (snd_hda_lock_devices(&chip->bus))
1197 return false;
1198 snd_hda_unlock_devices(&chip->bus);
1199 return true;
1200 }
1201
1202 static void init_vga_switcheroo(struct azx *chip)
1203 {
1204 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1205 struct pci_dev *p = get_bound_vga(chip->pci);
1206 if (p) {
1207 dev_info(chip->card->dev,
1208 "Handle vga_switcheroo audio client\n");
1209 hda->use_vga_switcheroo = 1;
1210 pci_dev_put(p);
1211 }
1212 }
1213
1214 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1215 .set_gpu_state = azx_vs_set_state,
1216 .can_switch = azx_vs_can_switch,
1217 };
1218
1219 static int register_vga_switcheroo(struct azx *chip)
1220 {
1221 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1222 int err;
1223
1224 if (!hda->use_vga_switcheroo)
1225 return 0;
1226 /* FIXME: currently only handling DIS controller
1227 * is there any machine with two switchable HDMI audio controllers?
1228 */
1229 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1230 VGA_SWITCHEROO_DIS);
1231 if (err < 0)
1232 return err;
1233 hda->vga_switcheroo_registered = 1;
1234
1235 /* register as an optimus hdmi audio power domain */
1236 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1237 &hda->hdmi_pm_domain);
1238 return 0;
1239 }
1240 #else
1241 #define init_vga_switcheroo(chip) /* NOP */
1242 #define register_vga_switcheroo(chip) 0
1243 #define check_hdmi_disabled(pci) false
1244 #endif /* SUPPORT_VGA_SWITCHER */
1245
1246 /*
1247 * destructor
1248 */
1249 static int azx_free(struct azx *chip)
1250 {
1251 struct pci_dev *pci = chip->pci;
1252 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1253 struct hdac_bus *bus = azx_bus(chip);
1254
1255 if (azx_has_pm_runtime(chip) && chip->running)
1256 pm_runtime_get_noresume(&pci->dev);
1257
1258 azx_del_card_list(chip);
1259
1260 hda->init_failed = 1; /* to be sure */
1261 complete_all(&hda->probe_wait);
1262
1263 if (use_vga_switcheroo(hda)) {
1264 if (chip->disabled && hda->probe_continued)
1265 snd_hda_unlock_devices(&chip->bus);
1266 if (hda->vga_switcheroo_registered) {
1267 vga_switcheroo_unregister_client(chip->pci);
1268 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1269 }
1270 }
1271
1272 if (bus->chip_init) {
1273 azx_clear_irq_pending(chip);
1274 azx_stop_all_streams(chip);
1275 azx_stop_chip(chip);
1276 }
1277
1278 if (bus->irq >= 0)
1279 free_irq(bus->irq, (void*)chip);
1280 if (chip->msi)
1281 pci_disable_msi(chip->pci);
1282 iounmap(bus->remap_addr);
1283
1284 azx_free_stream_pages(chip);
1285 azx_free_streams(chip);
1286 snd_hdac_bus_exit(bus);
1287
1288 if (chip->region_requested)
1289 pci_release_regions(chip->pci);
1290
1291 pci_disable_device(chip->pci);
1292 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1293 release_firmware(chip->fw);
1294 #endif
1295
1296 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1297 if (hda->need_i915_power)
1298 snd_hdac_display_power(bus, false);
1299 snd_hdac_i915_exit(bus);
1300 }
1301 kfree(hda);
1302
1303 return 0;
1304 }
1305
1306 static int azx_dev_disconnect(struct snd_device *device)
1307 {
1308 struct azx *chip = device->device_data;
1309
1310 chip->bus.shutdown = 1;
1311 return 0;
1312 }
1313
1314 static int azx_dev_free(struct snd_device *device)
1315 {
1316 return azx_free(device->device_data);
1317 }
1318
1319 #ifdef SUPPORT_VGA_SWITCHEROO
1320 /*
1321 * Check of disabled HDMI controller by vga_switcheroo
1322 */
1323 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1324 {
1325 struct pci_dev *p;
1326
1327 /* check only discrete GPU */
1328 switch (pci->vendor) {
1329 case PCI_VENDOR_ID_ATI:
1330 case PCI_VENDOR_ID_AMD:
1331 case PCI_VENDOR_ID_NVIDIA:
1332 if (pci->devfn == 1) {
1333 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1334 pci->bus->number, 0);
1335 if (p) {
1336 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1337 return p;
1338 pci_dev_put(p);
1339 }
1340 }
1341 break;
1342 }
1343 return NULL;
1344 }
1345
1346 static bool check_hdmi_disabled(struct pci_dev *pci)
1347 {
1348 bool vga_inactive = false;
1349 struct pci_dev *p = get_bound_vga(pci);
1350
1351 if (p) {
1352 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1353 vga_inactive = true;
1354 pci_dev_put(p);
1355 }
1356 return vga_inactive;
1357 }
1358 #endif /* SUPPORT_VGA_SWITCHEROO */
1359
1360 /*
1361 * white/black-listing for position_fix
1362 */
1363 static struct snd_pci_quirk position_fix_list[] = {
1364 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1365 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1366 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1367 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1368 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1369 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1370 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1371 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1372 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1373 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1374 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1375 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1376 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1377 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1378 {}
1379 };
1380
1381 static int check_position_fix(struct azx *chip, int fix)
1382 {
1383 const struct snd_pci_quirk *q;
1384
1385 switch (fix) {
1386 case POS_FIX_AUTO:
1387 case POS_FIX_LPIB:
1388 case POS_FIX_POSBUF:
1389 case POS_FIX_VIACOMBO:
1390 case POS_FIX_COMBO:
1391 return fix;
1392 }
1393
1394 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1395 if (q) {
1396 dev_info(chip->card->dev,
1397 "position_fix set to %d for device %04x:%04x\n",
1398 q->value, q->subvendor, q->subdevice);
1399 return q->value;
1400 }
1401
1402 /* Check VIA/ATI HD Audio Controller exist */
1403 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1404 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1405 return POS_FIX_VIACOMBO;
1406 }
1407 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1408 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1409 return POS_FIX_LPIB;
1410 }
1411 return POS_FIX_AUTO;
1412 }
1413
1414 static void assign_position_fix(struct azx *chip, int fix)
1415 {
1416 static azx_get_pos_callback_t callbacks[] = {
1417 [POS_FIX_AUTO] = NULL,
1418 [POS_FIX_LPIB] = azx_get_pos_lpib,
1419 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1420 [POS_FIX_VIACOMBO] = azx_via_get_position,
1421 [POS_FIX_COMBO] = azx_get_pos_lpib,
1422 };
1423
1424 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1425
1426 /* combo mode uses LPIB only for playback */
1427 if (fix == POS_FIX_COMBO)
1428 chip->get_position[1] = NULL;
1429
1430 if (fix == POS_FIX_POSBUF &&
1431 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1432 chip->get_delay[0] = chip->get_delay[1] =
1433 azx_get_delay_from_lpib;
1434 }
1435
1436 }
1437
1438 /*
1439 * black-lists for probe_mask
1440 */
1441 static struct snd_pci_quirk probe_mask_list[] = {
1442 /* Thinkpad often breaks the controller communication when accessing
1443 * to the non-working (or non-existing) modem codec slot.
1444 */
1445 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1446 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1447 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1448 /* broken BIOS */
1449 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1450 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1451 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1452 /* forced codec slots */
1453 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1454 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1455 /* WinFast VP200 H (Teradici) user reported broken communication */
1456 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1457 {}
1458 };
1459
1460 #define AZX_FORCE_CODEC_MASK 0x100
1461
1462 static void check_probe_mask(struct azx *chip, int dev)
1463 {
1464 const struct snd_pci_quirk *q;
1465
1466 chip->codec_probe_mask = probe_mask[dev];
1467 if (chip->codec_probe_mask == -1) {
1468 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1469 if (q) {
1470 dev_info(chip->card->dev,
1471 "probe_mask set to 0x%x for device %04x:%04x\n",
1472 q->value, q->subvendor, q->subdevice);
1473 chip->codec_probe_mask = q->value;
1474 }
1475 }
1476
1477 /* check forced option */
1478 if (chip->codec_probe_mask != -1 &&
1479 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1480 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1481 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1482 (int)azx_bus(chip)->codec_mask);
1483 }
1484 }
1485
1486 /*
1487 * white/black-list for enable_msi
1488 */
1489 static struct snd_pci_quirk msi_black_list[] = {
1490 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1491 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1492 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1493 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1494 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1495 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1496 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1497 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1498 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1499 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1500 {}
1501 };
1502
1503 static void check_msi(struct azx *chip)
1504 {
1505 const struct snd_pci_quirk *q;
1506
1507 if (enable_msi >= 0) {
1508 chip->msi = !!enable_msi;
1509 return;
1510 }
1511 chip->msi = 1; /* enable MSI as default */
1512 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1513 if (q) {
1514 dev_info(chip->card->dev,
1515 "msi for device %04x:%04x set to %d\n",
1516 q->subvendor, q->subdevice, q->value);
1517 chip->msi = q->value;
1518 return;
1519 }
1520
1521 /* NVidia chipsets seem to cause troubles with MSI */
1522 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1523 dev_info(chip->card->dev, "Disabling MSI\n");
1524 chip->msi = 0;
1525 }
1526 }
1527
1528 /* check the snoop mode availability */
1529 static void azx_check_snoop_available(struct azx *chip)
1530 {
1531 int snoop = hda_snoop;
1532
1533 if (snoop >= 0) {
1534 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1535 snoop ? "snoop" : "non-snoop");
1536 chip->snoop = snoop;
1537 return;
1538 }
1539
1540 snoop = true;
1541 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1542 chip->driver_type == AZX_DRIVER_VIA) {
1543 /* force to non-snoop mode for a new VIA controller
1544 * when BIOS is set
1545 */
1546 u8 val;
1547 pci_read_config_byte(chip->pci, 0x42, &val);
1548 if (!(val & 0x80) && chip->pci->revision == 0x30)
1549 snoop = false;
1550 }
1551
1552 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1553 snoop = false;
1554
1555 chip->snoop = snoop;
1556 if (!snoop)
1557 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1558 }
1559
1560 static void azx_probe_work(struct work_struct *work)
1561 {
1562 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1563 azx_probe_continue(&hda->chip);
1564 }
1565
1566 /*
1567 * constructor
1568 */
1569 static const struct hdac_io_ops pci_hda_io_ops;
1570 static const struct hda_controller_ops pci_hda_ops;
1571
1572 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1573 int dev, unsigned int driver_caps,
1574 struct azx **rchip)
1575 {
1576 static struct snd_device_ops ops = {
1577 .dev_disconnect = azx_dev_disconnect,
1578 .dev_free = azx_dev_free,
1579 };
1580 struct hda_intel *hda;
1581 struct azx *chip;
1582 int err;
1583
1584 *rchip = NULL;
1585
1586 err = pci_enable_device(pci);
1587 if (err < 0)
1588 return err;
1589
1590 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1591 if (!hda) {
1592 pci_disable_device(pci);
1593 return -ENOMEM;
1594 }
1595
1596 chip = &hda->chip;
1597 mutex_init(&chip->open_mutex);
1598 chip->card = card;
1599 chip->pci = pci;
1600 chip->ops = &pci_hda_ops;
1601 chip->driver_caps = driver_caps;
1602 chip->driver_type = driver_caps & 0xff;
1603 check_msi(chip);
1604 chip->dev_index = dev;
1605 chip->jackpoll_ms = jackpoll_ms;
1606 INIT_LIST_HEAD(&chip->pcm_list);
1607 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1608 INIT_LIST_HEAD(&hda->list);
1609 init_vga_switcheroo(chip);
1610 init_completion(&hda->probe_wait);
1611
1612 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1613
1614 check_probe_mask(chip, dev);
1615
1616 chip->single_cmd = single_cmd;
1617 azx_check_snoop_available(chip);
1618
1619 if (bdl_pos_adj[dev] < 0) {
1620 switch (chip->driver_type) {
1621 case AZX_DRIVER_ICH:
1622 case AZX_DRIVER_PCH:
1623 bdl_pos_adj[dev] = 1;
1624 break;
1625 default:
1626 bdl_pos_adj[dev] = 32;
1627 break;
1628 }
1629 }
1630 chip->bdl_pos_adj = bdl_pos_adj;
1631
1632 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1633 if (err < 0) {
1634 kfree(hda);
1635 pci_disable_device(pci);
1636 return err;
1637 }
1638
1639 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1640 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1641 chip->bus.needs_damn_long_delay = 1;
1642 }
1643
1644 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1645 if (err < 0) {
1646 dev_err(card->dev, "Error creating device [card]!\n");
1647 azx_free(chip);
1648 return err;
1649 }
1650
1651 /* continue probing in work context as may trigger request module */
1652 INIT_WORK(&hda->probe_work, azx_probe_work);
1653
1654 *rchip = chip;
1655
1656 return 0;
1657 }
1658
1659 static int azx_first_init(struct azx *chip)
1660 {
1661 int dev = chip->dev_index;
1662 struct pci_dev *pci = chip->pci;
1663 struct snd_card *card = chip->card;
1664 struct hdac_bus *bus = azx_bus(chip);
1665 int err;
1666 unsigned short gcap;
1667 unsigned int dma_bits = 64;
1668
1669 #if BITS_PER_LONG != 64
1670 /* Fix up base address on ULI M5461 */
1671 if (chip->driver_type == AZX_DRIVER_ULI) {
1672 u16 tmp3;
1673 pci_read_config_word(pci, 0x40, &tmp3);
1674 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1675 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1676 }
1677 #endif
1678
1679 err = pci_request_regions(pci, "ICH HD audio");
1680 if (err < 0)
1681 return err;
1682 chip->region_requested = 1;
1683
1684 bus->addr = pci_resource_start(pci, 0);
1685 bus->remap_addr = pci_ioremap_bar(pci, 0);
1686 if (bus->remap_addr == NULL) {
1687 dev_err(card->dev, "ioremap error\n");
1688 return -ENXIO;
1689 }
1690
1691 if (chip->msi) {
1692 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1693 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1694 pci->no_64bit_msi = true;
1695 }
1696 if (pci_enable_msi(pci) < 0)
1697 chip->msi = 0;
1698 }
1699
1700 if (azx_acquire_irq(chip, 0) < 0)
1701 return -EBUSY;
1702
1703 pci_set_master(pci);
1704 synchronize_irq(bus->irq);
1705
1706 gcap = azx_readw(chip, GCAP);
1707 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1708
1709 /* AMD devices support 40 or 48bit DMA, take the safe one */
1710 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1711 dma_bits = 40;
1712
1713 /* disable SB600 64bit support for safety */
1714 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1715 struct pci_dev *p_smbus;
1716 dma_bits = 40;
1717 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1718 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1719 NULL);
1720 if (p_smbus) {
1721 if (p_smbus->revision < 0x30)
1722 gcap &= ~AZX_GCAP_64OK;
1723 pci_dev_put(p_smbus);
1724 }
1725 }
1726
1727 /* NVidia hardware normally only supports up to 40 bits of DMA */
1728 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1729 dma_bits = 40;
1730
1731 /* disable 64bit DMA address on some devices */
1732 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1733 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1734 gcap &= ~AZX_GCAP_64OK;
1735 }
1736
1737 /* disable buffer size rounding to 128-byte multiples if supported */
1738 if (align_buffer_size >= 0)
1739 chip->align_buffer_size = !!align_buffer_size;
1740 else {
1741 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1742 chip->align_buffer_size = 0;
1743 else
1744 chip->align_buffer_size = 1;
1745 }
1746
1747 /* allow 64bit DMA address if supported by H/W */
1748 if (!(gcap & AZX_GCAP_64OK))
1749 dma_bits = 32;
1750 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1751 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1752 } else {
1753 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1754 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1755 }
1756
1757 /* read number of streams from GCAP register instead of using
1758 * hardcoded value
1759 */
1760 chip->capture_streams = (gcap >> 8) & 0x0f;
1761 chip->playback_streams = (gcap >> 12) & 0x0f;
1762 if (!chip->playback_streams && !chip->capture_streams) {
1763 /* gcap didn't give any info, switching to old method */
1764
1765 switch (chip->driver_type) {
1766 case AZX_DRIVER_ULI:
1767 chip->playback_streams = ULI_NUM_PLAYBACK;
1768 chip->capture_streams = ULI_NUM_CAPTURE;
1769 break;
1770 case AZX_DRIVER_ATIHDMI:
1771 case AZX_DRIVER_ATIHDMI_NS:
1772 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1773 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1774 break;
1775 case AZX_DRIVER_GENERIC:
1776 default:
1777 chip->playback_streams = ICH6_NUM_PLAYBACK;
1778 chip->capture_streams = ICH6_NUM_CAPTURE;
1779 break;
1780 }
1781 }
1782 chip->capture_index_offset = 0;
1783 chip->playback_index_offset = chip->capture_streams;
1784 chip->num_streams = chip->playback_streams + chip->capture_streams;
1785
1786 /* initialize streams */
1787 err = azx_init_streams(chip);
1788 if (err < 0)
1789 return err;
1790
1791 err = azx_alloc_stream_pages(chip);
1792 if (err < 0)
1793 return err;
1794
1795 /* initialize chip */
1796 azx_init_pci(chip);
1797
1798 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1799 struct hda_intel *hda;
1800
1801 hda = container_of(chip, struct hda_intel, chip);
1802 haswell_set_bclk(hda);
1803 }
1804
1805 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1806
1807 /* codec detection */
1808 if (!azx_bus(chip)->codec_mask) {
1809 dev_err(card->dev, "no codecs found!\n");
1810 return -ENODEV;
1811 }
1812
1813 strcpy(card->driver, "HDA-Intel");
1814 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1815 sizeof(card->shortname));
1816 snprintf(card->longname, sizeof(card->longname),
1817 "%s at 0x%lx irq %i",
1818 card->shortname, bus->addr, bus->irq);
1819
1820 return 0;
1821 }
1822
1823 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1824 /* callback from request_firmware_nowait() */
1825 static void azx_firmware_cb(const struct firmware *fw, void *context)
1826 {
1827 struct snd_card *card = context;
1828 struct azx *chip = card->private_data;
1829 struct pci_dev *pci = chip->pci;
1830
1831 if (!fw) {
1832 dev_err(card->dev, "Cannot load firmware, aborting\n");
1833 goto error;
1834 }
1835
1836 chip->fw = fw;
1837 if (!chip->disabled) {
1838 /* continue probing */
1839 if (azx_probe_continue(chip))
1840 goto error;
1841 }
1842 return; /* OK */
1843
1844 error:
1845 snd_card_free(card);
1846 pci_set_drvdata(pci, NULL);
1847 }
1848 #endif
1849
1850 /*
1851 * HDA controller ops.
1852 */
1853
1854 /* PCI register access. */
1855 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1856 {
1857 writel(value, addr);
1858 }
1859
1860 static u32 pci_azx_readl(u32 __iomem *addr)
1861 {
1862 return readl(addr);
1863 }
1864
1865 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1866 {
1867 writew(value, addr);
1868 }
1869
1870 static u16 pci_azx_readw(u16 __iomem *addr)
1871 {
1872 return readw(addr);
1873 }
1874
1875 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1876 {
1877 writeb(value, addr);
1878 }
1879
1880 static u8 pci_azx_readb(u8 __iomem *addr)
1881 {
1882 return readb(addr);
1883 }
1884
1885 static int disable_msi_reset_irq(struct azx *chip)
1886 {
1887 struct hdac_bus *bus = azx_bus(chip);
1888 int err;
1889
1890 free_irq(bus->irq, chip);
1891 bus->irq = -1;
1892 pci_disable_msi(chip->pci);
1893 chip->msi = 0;
1894 err = azx_acquire_irq(chip, 1);
1895 if (err < 0)
1896 return err;
1897
1898 return 0;
1899 }
1900
1901 /* DMA page allocation helpers. */
1902 static int dma_alloc_pages(struct hdac_bus *bus,
1903 int type,
1904 size_t size,
1905 struct snd_dma_buffer *buf)
1906 {
1907 struct azx *chip = bus_to_azx(bus);
1908 int err;
1909
1910 err = snd_dma_alloc_pages(type,
1911 bus->dev,
1912 size, buf);
1913 if (err < 0)
1914 return err;
1915 mark_pages_wc(chip, buf, true);
1916 return 0;
1917 }
1918
1919 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1920 {
1921 struct azx *chip = bus_to_azx(bus);
1922
1923 mark_pages_wc(chip, buf, false);
1924 snd_dma_free_pages(buf);
1925 }
1926
1927 static int substream_alloc_pages(struct azx *chip,
1928 struct snd_pcm_substream *substream,
1929 size_t size)
1930 {
1931 struct azx_dev *azx_dev = get_azx_dev(substream);
1932 int ret;
1933
1934 mark_runtime_wc(chip, azx_dev, substream, false);
1935 ret = snd_pcm_lib_malloc_pages(substream, size);
1936 if (ret < 0)
1937 return ret;
1938 mark_runtime_wc(chip, azx_dev, substream, true);
1939 return 0;
1940 }
1941
1942 static int substream_free_pages(struct azx *chip,
1943 struct snd_pcm_substream *substream)
1944 {
1945 struct azx_dev *azx_dev = get_azx_dev(substream);
1946 mark_runtime_wc(chip, azx_dev, substream, false);
1947 return snd_pcm_lib_free_pages(substream);
1948 }
1949
1950 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1951 struct vm_area_struct *area)
1952 {
1953 #ifdef CONFIG_X86
1954 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1955 struct azx *chip = apcm->chip;
1956 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1957 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1958 #endif
1959 }
1960
1961 static const struct hdac_io_ops pci_hda_io_ops = {
1962 .reg_writel = pci_azx_writel,
1963 .reg_readl = pci_azx_readl,
1964 .reg_writew = pci_azx_writew,
1965 .reg_readw = pci_azx_readw,
1966 .reg_writeb = pci_azx_writeb,
1967 .reg_readb = pci_azx_readb,
1968 .dma_alloc_pages = dma_alloc_pages,
1969 .dma_free_pages = dma_free_pages,
1970 };
1971
1972 static const struct hda_controller_ops pci_hda_ops = {
1973 .disable_msi_reset_irq = disable_msi_reset_irq,
1974 .substream_alloc_pages = substream_alloc_pages,
1975 .substream_free_pages = substream_free_pages,
1976 .pcm_mmap_prepare = pcm_mmap_prepare,
1977 .position_check = azx_position_check,
1978 .link_power = azx_intel_link_power,
1979 };
1980
1981 static int azx_probe(struct pci_dev *pci,
1982 const struct pci_device_id *pci_id)
1983 {
1984 static int dev;
1985 struct snd_card *card;
1986 struct hda_intel *hda;
1987 struct azx *chip;
1988 bool schedule_probe;
1989 int err;
1990
1991 if (dev >= SNDRV_CARDS)
1992 return -ENODEV;
1993 if (!enable[dev]) {
1994 dev++;
1995 return -ENOENT;
1996 }
1997
1998 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1999 0, &card);
2000 if (err < 0) {
2001 dev_err(&pci->dev, "Error creating card!\n");
2002 return err;
2003 }
2004
2005 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2006 if (err < 0)
2007 goto out_free;
2008 card->private_data = chip;
2009 hda = container_of(chip, struct hda_intel, chip);
2010
2011 pci_set_drvdata(pci, card);
2012
2013 err = register_vga_switcheroo(chip);
2014 if (err < 0) {
2015 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2016 goto out_free;
2017 }
2018
2019 if (check_hdmi_disabled(pci)) {
2020 dev_info(card->dev, "VGA controller is disabled\n");
2021 dev_info(card->dev, "Delaying initialization\n");
2022 chip->disabled = true;
2023 }
2024
2025 schedule_probe = !chip->disabled;
2026
2027 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2028 if (patch[dev] && *patch[dev]) {
2029 dev_info(card->dev, "Applying patch firmware '%s'\n",
2030 patch[dev]);
2031 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2032 &pci->dev, GFP_KERNEL, card,
2033 azx_firmware_cb);
2034 if (err < 0)
2035 goto out_free;
2036 schedule_probe = false; /* continued in azx_firmware_cb() */
2037 }
2038 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2039
2040 #ifndef CONFIG_SND_HDA_I915
2041 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2042 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2043 #endif
2044
2045 if (schedule_probe)
2046 schedule_work(&hda->probe_work);
2047
2048 dev++;
2049 if (chip->disabled)
2050 complete_all(&hda->probe_wait);
2051 return 0;
2052
2053 out_free:
2054 snd_card_free(card);
2055 return err;
2056 }
2057
2058 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2059 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2060 [AZX_DRIVER_NVIDIA] = 8,
2061 [AZX_DRIVER_TERA] = 1,
2062 };
2063
2064 static int azx_probe_continue(struct azx *chip)
2065 {
2066 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2067 struct hdac_bus *bus = azx_bus(chip);
2068 struct pci_dev *pci = chip->pci;
2069 int dev = chip->dev_index;
2070 int err;
2071
2072 hda->probe_continued = 1;
2073
2074 /* Request display power well for the HDA controller or codec. For
2075 * Haswell/Broadwell, both the display HDA controller and codec need
2076 * this power. For other platforms, like Baytrail/Braswell, only the
2077 * display codec needs the power and it can be released after probe.
2078 */
2079 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2080 /* HSW/BDW controllers need this power */
2081 if (CONTROLLER_IN_GPU(pci))
2082 hda->need_i915_power = 1;
2083
2084 err = snd_hdac_i915_init(bus);
2085 if (err < 0) {
2086 /* if the controller is bound only with HDMI/DP
2087 * (for HSW and BDW), we need to abort the probe;
2088 * for other chips, still continue probing as other
2089 * codecs can be on the same link.
2090 */
2091 if (CONTROLLER_IN_GPU(pci))
2092 goto out_free;
2093 else
2094 goto skip_i915;
2095 }
2096
2097 err = snd_hdac_display_power(bus, true);
2098 if (err < 0) {
2099 dev_err(chip->card->dev,
2100 "Cannot turn on display power on i915\n");
2101 goto i915_power_fail;
2102 }
2103 }
2104
2105 skip_i915:
2106 err = azx_first_init(chip);
2107 if (err < 0)
2108 goto out_free;
2109
2110 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2111 chip->beep_mode = beep_mode[dev];
2112 #endif
2113
2114 /* create codec instances */
2115 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2116 if (err < 0)
2117 goto out_free;
2118
2119 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2120 if (chip->fw) {
2121 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2122 chip->fw->data);
2123 if (err < 0)
2124 goto out_free;
2125 #ifndef CONFIG_PM
2126 release_firmware(chip->fw); /* no longer needed */
2127 chip->fw = NULL;
2128 #endif
2129 }
2130 #endif
2131 if ((probe_only[dev] & 1) == 0) {
2132 err = azx_codec_configure(chip);
2133 if (err < 0)
2134 goto out_free;
2135 }
2136
2137 err = snd_card_register(chip->card);
2138 if (err < 0)
2139 goto out_free;
2140
2141 chip->running = 1;
2142 azx_add_card_list(chip);
2143 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2144 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2145 pm_runtime_put_noidle(&pci->dev);
2146
2147 out_free:
2148 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2149 && !hda->need_i915_power)
2150 snd_hdac_display_power(bus, false);
2151
2152 i915_power_fail:
2153 if (err < 0)
2154 hda->init_failed = 1;
2155 complete_all(&hda->probe_wait);
2156 return err;
2157 }
2158
2159 static void azx_remove(struct pci_dev *pci)
2160 {
2161 struct snd_card *card = pci_get_drvdata(pci);
2162 struct azx *chip;
2163 struct hda_intel *hda;
2164
2165 if (card) {
2166 /* cancel the pending probing work */
2167 chip = card->private_data;
2168 hda = container_of(chip, struct hda_intel, chip);
2169 /* FIXME: below is an ugly workaround.
2170 * Both device_release_driver() and driver_probe_device()
2171 * take *both* the device's and its parent's lock before
2172 * calling the remove() and probe() callbacks. The codec
2173 * probe takes the locks of both the codec itself and its
2174 * parent, i.e. the PCI controller dev. Meanwhile, when
2175 * the PCI controller is unbound, it takes its lock, too
2176 * ==> ouch, a deadlock!
2177 * As a workaround, we unlock temporarily here the controller
2178 * device during cancel_work_sync() call.
2179 */
2180 device_unlock(&pci->dev);
2181 cancel_work_sync(&hda->probe_work);
2182 device_lock(&pci->dev);
2183
2184 snd_card_free(card);
2185 }
2186 }
2187
2188 static void azx_shutdown(struct pci_dev *pci)
2189 {
2190 struct snd_card *card = pci_get_drvdata(pci);
2191 struct azx *chip;
2192
2193 if (!card)
2194 return;
2195 chip = card->private_data;
2196 if (chip && chip->running)
2197 azx_stop_chip(chip);
2198 }
2199
2200 /* PCI IDs */
2201 static const struct pci_device_id azx_ids[] = {
2202 /* CPT */
2203 { PCI_DEVICE(0x8086, 0x1c20),
2204 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2205 /* PBG */
2206 { PCI_DEVICE(0x8086, 0x1d20),
2207 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2208 /* Panther Point */
2209 { PCI_DEVICE(0x8086, 0x1e20),
2210 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2211 /* Lynx Point */
2212 { PCI_DEVICE(0x8086, 0x8c20),
2213 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2214 /* 9 Series */
2215 { PCI_DEVICE(0x8086, 0x8ca0),
2216 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2217 /* Wellsburg */
2218 { PCI_DEVICE(0x8086, 0x8d20),
2219 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2220 { PCI_DEVICE(0x8086, 0x8d21),
2221 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2222 /* Lewisburg */
2223 { PCI_DEVICE(0x8086, 0xa1f0),
2224 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2225 { PCI_DEVICE(0x8086, 0xa270),
2226 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2227 /* Lynx Point-LP */
2228 { PCI_DEVICE(0x8086, 0x9c20),
2229 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2230 /* Lynx Point-LP */
2231 { PCI_DEVICE(0x8086, 0x9c21),
2232 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2233 /* Wildcat Point-LP */
2234 { PCI_DEVICE(0x8086, 0x9ca0),
2235 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2236 /* Sunrise Point */
2237 { PCI_DEVICE(0x8086, 0xa170),
2238 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2239 /* Sunrise Point-LP */
2240 { PCI_DEVICE(0x8086, 0x9d70),
2241 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2242 /* Kabylake */
2243 { PCI_DEVICE(0x8086, 0xa171),
2244 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2245 /* Kabylake-LP */
2246 { PCI_DEVICE(0x8086, 0x9d71),
2247 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2248 /* Kabylake-H */
2249 { PCI_DEVICE(0x8086, 0xa2f0),
2250 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2251 /* Broxton-P(Apollolake) */
2252 { PCI_DEVICE(0x8086, 0x5a98),
2253 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2254 /* Broxton-T */
2255 { PCI_DEVICE(0x8086, 0x1a98),
2256 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2257 /* Haswell */
2258 { PCI_DEVICE(0x8086, 0x0a0c),
2259 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2260 { PCI_DEVICE(0x8086, 0x0c0c),
2261 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2262 { PCI_DEVICE(0x8086, 0x0d0c),
2263 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2264 /* Broadwell */
2265 { PCI_DEVICE(0x8086, 0x160c),
2266 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2267 /* 5 Series/3400 */
2268 { PCI_DEVICE(0x8086, 0x3b56),
2269 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2270 /* Poulsbo */
2271 { PCI_DEVICE(0x8086, 0x811b),
2272 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2273 /* Oaktrail */
2274 { PCI_DEVICE(0x8086, 0x080a),
2275 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2276 /* BayTrail */
2277 { PCI_DEVICE(0x8086, 0x0f04),
2278 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2279 /* Braswell */
2280 { PCI_DEVICE(0x8086, 0x2284),
2281 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2282 /* ICH6 */
2283 { PCI_DEVICE(0x8086, 0x2668),
2284 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2285 /* ICH7 */
2286 { PCI_DEVICE(0x8086, 0x27d8),
2287 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2288 /* ESB2 */
2289 { PCI_DEVICE(0x8086, 0x269a),
2290 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2291 /* ICH8 */
2292 { PCI_DEVICE(0x8086, 0x284b),
2293 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2294 /* ICH9 */
2295 { PCI_DEVICE(0x8086, 0x293e),
2296 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2297 /* ICH9 */
2298 { PCI_DEVICE(0x8086, 0x293f),
2299 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2300 /* ICH10 */
2301 { PCI_DEVICE(0x8086, 0x3a3e),
2302 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2303 /* ICH10 */
2304 { PCI_DEVICE(0x8086, 0x3a6e),
2305 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2306 /* Generic Intel */
2307 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2308 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2309 .class_mask = 0xffffff,
2310 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2311 /* ATI SB 450/600/700/800/900 */
2312 { PCI_DEVICE(0x1002, 0x437b),
2313 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2314 { PCI_DEVICE(0x1002, 0x4383),
2315 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2316 /* AMD Hudson */
2317 { PCI_DEVICE(0x1022, 0x780d),
2318 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2319 /* ATI HDMI */
2320 { PCI_DEVICE(0x1002, 0x0002),
2321 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2322 { PCI_DEVICE(0x1002, 0x1308),
2323 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2324 { PCI_DEVICE(0x1002, 0x157a),
2325 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2326 { PCI_DEVICE(0x1002, 0x15b3),
2327 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2328 { PCI_DEVICE(0x1002, 0x793b),
2329 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2330 { PCI_DEVICE(0x1002, 0x7919),
2331 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2332 { PCI_DEVICE(0x1002, 0x960f),
2333 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2334 { PCI_DEVICE(0x1002, 0x970f),
2335 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2336 { PCI_DEVICE(0x1002, 0x9840),
2337 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2338 { PCI_DEVICE(0x1002, 0xaa00),
2339 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2340 { PCI_DEVICE(0x1002, 0xaa08),
2341 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2342 { PCI_DEVICE(0x1002, 0xaa10),
2343 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2344 { PCI_DEVICE(0x1002, 0xaa18),
2345 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2346 { PCI_DEVICE(0x1002, 0xaa20),
2347 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2348 { PCI_DEVICE(0x1002, 0xaa28),
2349 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2350 { PCI_DEVICE(0x1002, 0xaa30),
2351 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2352 { PCI_DEVICE(0x1002, 0xaa38),
2353 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2354 { PCI_DEVICE(0x1002, 0xaa40),
2355 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2356 { PCI_DEVICE(0x1002, 0xaa48),
2357 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2358 { PCI_DEVICE(0x1002, 0xaa50),
2359 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2360 { PCI_DEVICE(0x1002, 0xaa58),
2361 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2362 { PCI_DEVICE(0x1002, 0xaa60),
2363 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2364 { PCI_DEVICE(0x1002, 0xaa68),
2365 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2366 { PCI_DEVICE(0x1002, 0xaa80),
2367 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2368 { PCI_DEVICE(0x1002, 0xaa88),
2369 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2370 { PCI_DEVICE(0x1002, 0xaa90),
2371 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2372 { PCI_DEVICE(0x1002, 0xaa98),
2373 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2374 { PCI_DEVICE(0x1002, 0x9902),
2375 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2376 { PCI_DEVICE(0x1002, 0xaaa0),
2377 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2378 { PCI_DEVICE(0x1002, 0xaaa8),
2379 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2380 { PCI_DEVICE(0x1002, 0xaab0),
2381 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2382 { PCI_DEVICE(0x1002, 0xaac0),
2383 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2384 { PCI_DEVICE(0x1002, 0xaac8),
2385 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2386 { PCI_DEVICE(0x1002, 0xaad8),
2387 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2388 { PCI_DEVICE(0x1002, 0xaae8),
2389 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2390 { PCI_DEVICE(0x1002, 0xaae0),
2391 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2392 { PCI_DEVICE(0x1002, 0xaaf0),
2393 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2394 /* VIA VT8251/VT8237A */
2395 { PCI_DEVICE(0x1106, 0x3288),
2396 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2397 /* VIA GFX VT7122/VX900 */
2398 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2399 /* VIA GFX VT6122/VX11 */
2400 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2401 /* SIS966 */
2402 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2403 /* ULI M5461 */
2404 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2405 /* NVIDIA MCP */
2406 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2407 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2408 .class_mask = 0xffffff,
2409 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2410 /* Teradici */
2411 { PCI_DEVICE(0x6549, 0x1200),
2412 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2413 { PCI_DEVICE(0x6549, 0x2200),
2414 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2415 /* Creative X-Fi (CA0110-IBG) */
2416 /* CTHDA chips */
2417 { PCI_DEVICE(0x1102, 0x0010),
2418 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2419 { PCI_DEVICE(0x1102, 0x0012),
2420 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2421 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2422 /* the following entry conflicts with snd-ctxfi driver,
2423 * as ctxfi driver mutates from HD-audio to native mode with
2424 * a special command sequence.
2425 */
2426 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2427 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2428 .class_mask = 0xffffff,
2429 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2430 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2431 #else
2432 /* this entry seems still valid -- i.e. without emu20kx chip */
2433 { PCI_DEVICE(0x1102, 0x0009),
2434 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2435 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2436 #endif
2437 /* CM8888 */
2438 { PCI_DEVICE(0x13f6, 0x5011),
2439 .driver_data = AZX_DRIVER_CMEDIA |
2440 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2441 /* Vortex86MX */
2442 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2443 /* VMware HDAudio */
2444 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2445 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2446 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2447 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2448 .class_mask = 0xffffff,
2449 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2450 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2451 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2452 .class_mask = 0xffffff,
2453 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2454 { 0, }
2455 };
2456 MODULE_DEVICE_TABLE(pci, azx_ids);
2457
2458 /* pci_driver definition */
2459 static struct pci_driver azx_driver = {
2460 .name = KBUILD_MODNAME,
2461 .id_table = azx_ids,
2462 .probe = azx_probe,
2463 .remove = azx_remove,
2464 .shutdown = azx_shutdown,
2465 .driver = {
2466 .pm = AZX_PM_OPS,
2467 },
2468 };
2469
2470 module_pci_driver(azx_driver);
Linux with added FPC-III support