arch/mips/alchemy/gpr/board_setup.c

   1 /*
   2  * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * Copyright 2000-2003, 2008 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/gpio.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/delay.h>
  32 #include <linux/pm.h>
  33
  34 #include <asm/reboot.h>
  35 #include <asm/mach-au1x00/au1000.h>
  36
  37 #include <prom.h>
  38
  39 #define UART1_ADDR      KSEG1ADDR(UART1_PHYS_ADDR)
  40 #define UART3_ADDR      KSEG1ADDR(UART3_PHYS_ADDR)
  41
  42 char irq_tab_alchemy[][5] __initdata = {
  43         [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
  44 };
  45
  46 static void gpr_reset(char *c)
  47 {
  48         /* switch System-LED to orange (red# and green# on) */
  49         alchemy_gpio_direction_output(4, 0);
  50         alchemy_gpio_direction_output(5, 0);
  51
  52         /* trigger watchdog to reset board in 200ms */
  53         printk(KERN_EMERG "Triggering watchdog soft reset...\n");
  54         raw_local_irq_disable();
  55         alchemy_gpio_direction_output(1, 0);
  56         udelay(1);
  57         alchemy_gpio_set_value(1, 1);
  58         while (1)
  59                 cpu_wait();
  60 }
  61
  62 static void gpr_power_off(void)
  63 {
  64         while (1)
  65                 cpu_wait();
  66 }
  67
  68 void __init board_setup(void)
  69 {
  70         printk(KERN_INFO "Tarpeze ITS GPR board\n");
  71
  72         pm_power_off = gpr_power_off;
  73         _machine_halt = gpr_power_off;
  74         _machine_restart = gpr_reset;
  75
  76         /* Enable UART3 */
  77         au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
  78         au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
  79         /* Enable UART1 */
  80         au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
  81         au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
  82
  83         /* Take away Reset of UMTS-card */
  84         alchemy_gpio_direction_output(215, 1);
  85
  86 #ifdef CONFIG_PCI
  87 #if defined(__MIPSEB__)
  88         au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
  89 #else
  90         au_writel(0xf, Au1500_PCI_CFG);
  91 #endif
  92 #endif
  93 }