include/drm/radeon_drm.h

   1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  *    Keith Whitwell <keith@tungstengraphics.com>
  31  */
  32
  33 #ifndef __RADEON_DRM_H__
  34 #define __RADEON_DRM_H__
  35
  36 #include "drm.h"
  37
  38 /* WARNING: If you change any of these defines, make sure to change the
  39  * defines in the X server file (radeon_sarea.h)
  40  */
  41 #ifndef __RADEON_SAREA_DEFINES__
  42 #define __RADEON_SAREA_DEFINES__
  43
  44 /* Old style state flags, required for sarea interface (1.1 and 1.2
  45  * clears) and 1.2 drm_vertex2 ioctl.
  46  */
  47 #define RADEON_UPLOAD_CONTEXT           0x00000001
  48 #define RADEON_UPLOAD_VERTFMT           0x00000002
  49 #define RADEON_UPLOAD_LINE              0x00000004
  50 #define RADEON_UPLOAD_BUMPMAP           0x00000008
  51 #define RADEON_UPLOAD_MASKS             0x00000010
  52 #define RADEON_UPLOAD_VIEWPORT          0x00000020
  53 #define RADEON_UPLOAD_SETUP             0x00000040
  54 #define RADEON_UPLOAD_TCL               0x00000080
  55 #define RADEON_UPLOAD_MISC              0x00000100
  56 #define RADEON_UPLOAD_TEX0              0x00000200
  57 #define RADEON_UPLOAD_TEX1              0x00000400
  58 #define RADEON_UPLOAD_TEX2              0x00000800
  59 #define RADEON_UPLOAD_TEX0IMAGES        0x00001000
  60 #define RADEON_UPLOAD_TEX1IMAGES        0x00002000
  61 #define RADEON_UPLOAD_TEX2IMAGES        0x00004000
  62 #define RADEON_UPLOAD_CLIPRECTS         0x00008000      /* handled client-side */
  63 #define RADEON_REQUIRE_QUIESCENCE       0x00010000
  64 #define RADEON_UPLOAD_ZBIAS             0x00020000      /* version 1.2 and newer */
  65 #define RADEON_UPLOAD_ALL               0x003effff
  66 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
  67
  68 /* New style per-packet identifiers for use in cmd_buffer ioctl with
  69  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
  70  * state bits and the packet size:
  71  */
  72 #define RADEON_EMIT_PP_MISC                         0   /* context/7 */
  73 #define RADEON_EMIT_PP_CNTL                         1   /* context/3 */
  74 #define RADEON_EMIT_RB3D_COLORPITCH                 2   /* context/1 */
  75 #define RADEON_EMIT_RE_LINE_PATTERN                 3   /* line/2 */
  76 #define RADEON_EMIT_SE_LINE_WIDTH                   4   /* line/1 */
  77 #define RADEON_EMIT_PP_LUM_MATRIX                   5   /* bumpmap/1 */
  78 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6   /* bumpmap/2 */
  79 #define RADEON_EMIT_RB3D_STENCILREFMASK             7   /* masks/3 */
  80 #define RADEON_EMIT_SE_VPORT_XSCALE                 8   /* viewport/6 */
  81 #define RADEON_EMIT_SE_CNTL                         9   /* setup/2 */
  82 #define RADEON_EMIT_SE_CNTL_STATUS                  10  /* setup/1 */
  83 #define RADEON_EMIT_RE_MISC                         11  /* misc/1 */
  84 #define RADEON_EMIT_PP_TXFILTER_0                   12  /* tex0/6 */
  85 #define RADEON_EMIT_PP_BORDER_COLOR_0               13  /* tex0/1 */
  86 #define RADEON_EMIT_PP_TXFILTER_1                   14  /* tex1/6 */
  87 #define RADEON_EMIT_PP_BORDER_COLOR_1               15  /* tex1/1 */
  88 #define RADEON_EMIT_PP_TXFILTER_2                   16  /* tex2/6 */
  89 #define RADEON_EMIT_PP_BORDER_COLOR_2               17  /* tex2/1 */
  90 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18  /* zbias/2 */
  91 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19  /* tcl/11 */
  92 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20  /* material/17 */
  93 #define R200_EMIT_PP_TXCBLEND_0                     21  /* tex0/4 */
  94 #define R200_EMIT_PP_TXCBLEND_1                     22  /* tex1/4 */
  95 #define R200_EMIT_PP_TXCBLEND_2                     23  /* tex2/4 */
  96 #define R200_EMIT_PP_TXCBLEND_3                     24  /* tex3/4 */
  97 #define R200_EMIT_PP_TXCBLEND_4                     25  /* tex4/4 */
  98 #define R200_EMIT_PP_TXCBLEND_5                     26  /* tex5/4 */
  99 #define R200_EMIT_PP_TXCBLEND_6                     27  /* /4 */
 100 #define R200_EMIT_PP_TXCBLEND_7                     28  /* /4 */
 101 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29  /* tcl/7 */
 102 #define R200_EMIT_TFACTOR_0                         30  /* tf/7 */
 103 #define R200_EMIT_VTX_FMT_0                         31  /* vtx/5 */
 104 #define R200_EMIT_VAP_CTL                           32  /* vap/1 */
 105 #define R200_EMIT_MATRIX_SELECT_0                   33  /* msl/5 */
 106 #define R200_EMIT_TEX_PROC_CTL_2                    34  /* tcg/5 */
 107 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35  /* tcl/1 */
 108 #define R200_EMIT_PP_TXFILTER_0                     36  /* tex0/6 */
 109 #define R200_EMIT_PP_TXFILTER_1                     37  /* tex1/6 */
 110 #define R200_EMIT_PP_TXFILTER_2                     38  /* tex2/6 */
 111 #define R200_EMIT_PP_TXFILTER_3                     39  /* tex3/6 */
 112 #define R200_EMIT_PP_TXFILTER_4                     40  /* tex4/6 */
 113 #define R200_EMIT_PP_TXFILTER_5                     41  /* tex5/6 */
 114 #define R200_EMIT_PP_TXOFFSET_0                     42  /* tex0/1 */
 115 #define R200_EMIT_PP_TXOFFSET_1                     43  /* tex1/1 */
 116 #define R200_EMIT_PP_TXOFFSET_2                     44  /* tex2/1 */
 117 #define R200_EMIT_PP_TXOFFSET_3                     45  /* tex3/1 */
 118 #define R200_EMIT_PP_TXOFFSET_4                     46  /* tex4/1 */
 119 #define R200_EMIT_PP_TXOFFSET_5                     47  /* tex5/1 */
 120 #define R200_EMIT_VTE_CNTL                          48  /* vte/1 */
 121 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49  /* vtx/1 */
 122 #define R200_EMIT_PP_TAM_DEBUG3                     50  /* tam/1 */
 123 #define R200_EMIT_PP_CNTL_X                         51  /* cst/1 */
 124 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52  /* cst/1 */
 125 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53  /* cst/1 */
 126 #define R200_EMIT_RE_SCISSOR_TL_0                   54  /* cst/2 */
 127 #define R200_EMIT_RE_SCISSOR_TL_1                   55  /* cst/2 */
 128 #define R200_EMIT_RE_SCISSOR_TL_2                   56  /* cst/2 */
 129 #define R200_EMIT_SE_VAP_CNTL_STATUS                57  /* cst/1 */
 130 #define R200_EMIT_SE_VTX_STATE_CNTL                 58  /* cst/1 */
 131 #define R200_EMIT_RE_POINTSIZE                      59  /* cst/1 */
 132 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60  /* cst/4 */
 133 #define R200_EMIT_PP_CUBIC_FACES_0                  61
 134 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
 135 #define R200_EMIT_PP_CUBIC_FACES_1                  63
 136 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
 137 #define R200_EMIT_PP_CUBIC_FACES_2                  65
 138 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
 139 #define R200_EMIT_PP_CUBIC_FACES_3                  67
 140 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
 141 #define R200_EMIT_PP_CUBIC_FACES_4                  69
 142 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
 143 #define R200_EMIT_PP_CUBIC_FACES_5                  71
 144 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
 145 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 146 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 147 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
 148 #define R200_EMIT_RB3D_BLENDCOLOR                   76
 149 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
 150 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
 151 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
 152 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
 153 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
 154 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
 155 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
 156 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
 157 #define R200_EMIT_PP_AFS_0                          85
 158 #define R200_EMIT_PP_AFS_1                          86
 159 #define R200_EMIT_ATF_TFACTOR                       87
 160 #define R200_EMIT_PP_TXCTLALL_0                     88
 161 #define R200_EMIT_PP_TXCTLALL_1                     89
 162 #define R200_EMIT_PP_TXCTLALL_2                     90
 163 #define R200_EMIT_PP_TXCTLALL_3                     91
 164 #define R200_EMIT_PP_TXCTLALL_4                     92
 165 #define R200_EMIT_PP_TXCTLALL_5                     93
 166 #define R200_EMIT_VAP_PVS_CNTL                      94
 167 #define RADEON_MAX_STATE_PACKETS                    95
 168
 169 /* Commands understood by cmd_buffer ioctl.  More can be added but
 170  * obviously these can't be removed or changed:
 171  */
 172 #define RADEON_CMD_PACKET      1        /* emit one of the register packets above */
 173 #define RADEON_CMD_SCALARS     2        /* emit scalar data */
 174 #define RADEON_CMD_VECTORS     3        /* emit vector data */
 175 #define RADEON_CMD_DMA_DISCARD 4        /* discard current dma buf */
 176 #define RADEON_CMD_PACKET3     5        /* emit hw packet */
 177 #define RADEON_CMD_PACKET3_CLIP 6       /* emit hw packet wrapped in cliprects */
 178 #define RADEON_CMD_SCALARS2     7       /* r200 stopgap */
 179 #define RADEON_CMD_WAIT         8       /* emit hw wait commands -- note:
 180                                          *  doesn't make the cpu wait, just
 181                                          *  the graphics hardware */
 182 #define RADEON_CMD_VECLINEAR    9       /* another r200 stopgap */
 183
 184 typedef union {
 185         int i;
 186         struct {
 187                 unsigned char cmd_type, pad0, pad1, pad2;
 188         } header;
 189         struct {
 190                 unsigned char cmd_type, packet_id, pad0, pad1;
 191         } packet;
 192         struct {
 193                 unsigned char cmd_type, offset, stride, count;
 194         } scalars;
 195         struct {
 196                 unsigned char cmd_type, offset, stride, count;
 197         } vectors;
 198         struct {
 199                 unsigned char cmd_type, addr_lo, addr_hi, count;
 200         } veclinear;
 201         struct {
 202                 unsigned char cmd_type, buf_idx, pad0, pad1;
 203         } dma;
 204         struct {
 205                 unsigned char cmd_type, flags, pad0, pad1;
 206         } wait;
 207 } drm_radeon_cmd_header_t;
 208
 209 #define RADEON_WAIT_2D  0x1
 210 #define RADEON_WAIT_3D  0x2
 211
 212 /* Allowed parameters for R300_CMD_PACKET3
 213  */
 214 #define R300_CMD_PACKET3_CLEAR          0
 215 #define R300_CMD_PACKET3_RAW            1
 216
 217 /* Commands understood by cmd_buffer ioctl for R300.
 218  * The interface has not been stabilized, so some of these may be removed
 219  * and eventually reordered before stabilization.
 220  */
 221 #define R300_CMD_PACKET0                1
 222 #define R300_CMD_VPU                    2       /* emit vertex program upload */
 223 #define R300_CMD_PACKET3                3       /* emit a packet3 */
 224 #define R300_CMD_END3D                  4       /* emit sequence ending 3d rendering */
 225 #define R300_CMD_CP_DELAY               5
 226 #define R300_CMD_DMA_DISCARD            6
 227 #define R300_CMD_WAIT                   7
 228 #       define R300_WAIT_2D             0x1
 229 #       define R300_WAIT_3D             0x2
 230 /* these two defines are DOING IT WRONG - however
 231  * we have userspace which relies on using these.
 232  * The wait interface is backwards compat new
 233  * code should use the NEW_WAIT defines below
 234  * THESE ARE NOT BIT FIELDS
 235  */
 236 #       define R300_WAIT_2D_CLEAN       0x3
 237 #       define R300_WAIT_3D_CLEAN       0x4
 238
 239 #       define R300_NEW_WAIT_2D_3D      0x3
 240 #       define R300_NEW_WAIT_2D_2D_CLEAN        0x4
 241 #       define R300_NEW_WAIT_3D_3D_CLEAN        0x6
 242 #       define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN    0x8
 243
 244 #define R300_CMD_SCRATCH                8
 245 #define R300_CMD_R500FP                 9
 246
 247 typedef union {
 248         unsigned int u;
 249         struct {
 250                 unsigned char cmd_type, pad0, pad1, pad2;
 251         } header;
 252         struct {
 253                 unsigned char cmd_type, count, reglo, reghi;
 254         } packet0;
 255         struct {
 256                 unsigned char cmd_type, count, adrlo, adrhi;
 257         } vpu;
 258         struct {
 259                 unsigned char cmd_type, packet, pad0, pad1;
 260         } packet3;
 261         struct {
 262                 unsigned char cmd_type, packet;
 263                 unsigned short count;   /* amount of packet2 to emit */
 264         } delay;
 265         struct {
 266                 unsigned char cmd_type, buf_idx, pad0, pad1;
 267         } dma;
 268         struct {
 269                 unsigned char cmd_type, flags, pad0, pad1;
 270         } wait;
 271         struct {
 272                 unsigned char cmd_type, reg, n_bufs, flags;
 273         } scratch;
 274         struct {
 275                 unsigned char cmd_type, count, adrlo, adrhi_flags;
 276         } r500fp;
 277 } drm_r300_cmd_header_t;
 278
 279 #define RADEON_FRONT                    0x1
 280 #define RADEON_BACK                     0x2
 281 #define RADEON_DEPTH                    0x4
 282 #define RADEON_STENCIL                  0x8
 283 #define RADEON_CLEAR_FASTZ              0x80000000
 284 #define RADEON_USE_HIERZ                0x40000000
 285 #define RADEON_USE_COMP_ZBUF            0x20000000
 286
 287 #define R500FP_CONSTANT_TYPE  (1 << 1)
 288 #define R500FP_CONSTANT_CLAMP (1 << 2)
 289
 290 /* Primitive types
 291  */
 292 #define RADEON_POINTS                   0x1
 293 #define RADEON_LINES                    0x2
 294 #define RADEON_LINE_STRIP               0x3
 295 #define RADEON_TRIANGLES                0x4
 296 #define RADEON_TRIANGLE_FAN             0x5
 297 #define RADEON_TRIANGLE_STRIP           0x6
 298
 299 /* Vertex/indirect buffer size
 300  */
 301 #define RADEON_BUFFER_SIZE              65536
 302
 303 /* Byte offsets for indirect buffer data
 304  */
 305 #define RADEON_INDEX_PRIM_OFFSET        20
 306
 307 #define RADEON_SCRATCH_REG_OFFSET       32
 308
 309 #define R600_SCRATCH_REG_OFFSET         256
 310
 311 #define RADEON_NR_SAREA_CLIPRECTS       12
 312
 313 /* There are 2 heaps (local/GART).  Each region within a heap is a
 314  * minimum of 64k, and there are at most 64 of them per heap.
 315  */
 316 #define RADEON_LOCAL_TEX_HEAP           0
 317 #define RADEON_GART_TEX_HEAP            1
 318 #define RADEON_NR_TEX_HEAPS             2
 319 #define RADEON_NR_TEX_REGIONS           64
 320 #define RADEON_LOG_TEX_GRANULARITY      16
 321
 322 #define RADEON_MAX_TEXTURE_LEVELS       12
 323 #define RADEON_MAX_TEXTURE_UNITS        3
 324
 325 #define RADEON_MAX_SURFACES             8
 326
 327 /* Blits have strict offset rules.  All blit offset must be aligned on
 328  * a 1K-byte boundary.
 329  */
 330 #define RADEON_OFFSET_SHIFT             10
 331 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
 332 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
 333
 334 #endif                          /* __RADEON_SAREA_DEFINES__ */
 335
 336 typedef struct {
 337         unsigned int red;
 338         unsigned int green;
 339         unsigned int blue;
 340         unsigned int alpha;
 341 } radeon_color_regs_t;
 342
 343 typedef struct {
 344         /* Context state */
 345         unsigned int pp_misc;   /* 0x1c14 */
 346         unsigned int pp_fog_color;
 347         unsigned int re_solid_color;
 348         unsigned int rb3d_blendcntl;
 349         unsigned int rb3d_depthoffset;
 350         unsigned int rb3d_depthpitch;
 351         unsigned int rb3d_zstencilcntl;
 352
 353         unsigned int pp_cntl;   /* 0x1c38 */
 354         unsigned int rb3d_cntl;
 355         unsigned int rb3d_coloroffset;
 356         unsigned int re_width_height;
 357         unsigned int rb3d_colorpitch;
 358         unsigned int se_cntl;
 359
 360         /* Vertex format state */
 361         unsigned int se_coord_fmt;      /* 0x1c50 */
 362
 363         /* Line state */
 364         unsigned int re_line_pattern;   /* 0x1cd0 */
 365         unsigned int re_line_state;
 366
 367         unsigned int se_line_width;     /* 0x1db8 */
 368
 369         /* Bumpmap state */
 370         unsigned int pp_lum_matrix;     /* 0x1d00 */
 371
 372         unsigned int pp_rot_matrix_0;   /* 0x1d58 */
 373         unsigned int pp_rot_matrix_1;
 374
 375         /* Mask state */
 376         unsigned int rb3d_stencilrefmask;       /* 0x1d7c */
 377         unsigned int rb3d_ropcntl;
 378         unsigned int rb3d_planemask;
 379
 380         /* Viewport state */
 381         unsigned int se_vport_xscale;   /* 0x1d98 */
 382         unsigned int se_vport_xoffset;
 383         unsigned int se_vport_yscale;
 384         unsigned int se_vport_yoffset;
 385         unsigned int se_vport_zscale;
 386         unsigned int se_vport_zoffset;
 387
 388         /* Setup state */
 389         unsigned int se_cntl_status;    /* 0x2140 */
 390
 391         /* Misc state */
 392         unsigned int re_top_left;       /* 0x26c0 */
 393         unsigned int re_misc;
 394 } drm_radeon_context_regs_t;
 395
 396 typedef struct {
 397         /* Zbias state */
 398         unsigned int se_zbias_factor;   /* 0x1dac */
 399         unsigned int se_zbias_constant;
 400 } drm_radeon_context2_regs_t;
 401
 402 /* Setup registers for each texture unit
 403  */
 404 typedef struct {
 405         unsigned int pp_txfilter;
 406         unsigned int pp_txformat;
 407         unsigned int pp_txoffset;
 408         unsigned int pp_txcblend;
 409         unsigned int pp_txablend;
 410         unsigned int pp_tfactor;
 411         unsigned int pp_border_color;
 412 } drm_radeon_texture_regs_t;
 413
 414 typedef struct {
 415         unsigned int start;
 416         unsigned int finish;
 417         unsigned int prim:8;
 418         unsigned int stateidx:8;
 419         unsigned int numverts:16;       /* overloaded as offset/64 for elt prims */
 420         unsigned int vc_format; /* vertex format */
 421 } drm_radeon_prim_t;
 422
 423 typedef struct {
 424         drm_radeon_context_regs_t context;
 425         drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
 426         drm_radeon_context2_regs_t context2;
 427         unsigned int dirty;
 428 } drm_radeon_state_t;
 429
 430 typedef struct {
 431         /* The channel for communication of state information to the
 432          * kernel on firing a vertex buffer with either of the
 433          * obsoleted vertex/index ioctls.
 434          */
 435         drm_radeon_context_regs_t context_state;
 436         drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
 437         unsigned int dirty;
 438         unsigned int vertsize;
 439         unsigned int vc_format;
 440
 441         /* The current cliprects, or a subset thereof.
 442          */
 443         struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
 444         unsigned int nbox;
 445
 446         /* Counters for client-side throttling of rendering clients.
 447          */
 448         unsigned int last_frame;
 449         unsigned int last_dispatch;
 450         unsigned int last_clear;
 451
 452         struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
 453                                                        1];
 454         unsigned int tex_age[RADEON_NR_TEX_HEAPS];
 455         int ctx_owner;
 456         int pfState;            /* number of 3d windows (0,1,2ormore) */
 457         int pfCurrentPage;      /* which buffer is being displayed? */
 458         int crtc2_base;         /* CRTC2 frame offset */
 459         int tiling_enabled;     /* set by drm, read by 2d + 3d clients */
 460 } drm_radeon_sarea_t;
 461
 462 /* WARNING: If you change any of these defines, make sure to change the
 463  * defines in the Xserver file (xf86drmRadeon.h)
 464  *
 465  * KW: actually it's illegal to change any of this (backwards compatibility).
 466  */
 467
 468 /* Radeon specific ioctls
 469  * The device specific ioctl range is 0x40 to 0x79.
 470  */
 471 #define DRM_RADEON_CP_INIT    0x00
 472 #define DRM_RADEON_CP_START   0x01
 473 #define DRM_RADEON_CP_STOP    0x02
 474 #define DRM_RADEON_CP_RESET   0x03
 475 #define DRM_RADEON_CP_IDLE    0x04
 476 #define DRM_RADEON_RESET      0x05
 477 #define DRM_RADEON_FULLSCREEN 0x06
 478 #define DRM_RADEON_SWAP       0x07
 479 #define DRM_RADEON_CLEAR      0x08
 480 #define DRM_RADEON_VERTEX     0x09
 481 #define DRM_RADEON_INDICES    0x0A
 482 #define DRM_RADEON_NOT_USED
 483 #define DRM_RADEON_STIPPLE    0x0C
 484 #define DRM_RADEON_INDIRECT   0x0D
 485 #define DRM_RADEON_TEXTURE    0x0E
 486 #define DRM_RADEON_VERTEX2    0x0F
 487 #define DRM_RADEON_CMDBUF     0x10
 488 #define DRM_RADEON_GETPARAM   0x11
 489 #define DRM_RADEON_FLIP       0x12
 490 #define DRM_RADEON_ALLOC      0x13
 491 #define DRM_RADEON_FREE       0x14
 492 #define DRM_RADEON_INIT_HEAP  0x15
 493 #define DRM_RADEON_IRQ_EMIT   0x16
 494 #define DRM_RADEON_IRQ_WAIT   0x17
 495 #define DRM_RADEON_CP_RESUME  0x18
 496 #define DRM_RADEON_SETPARAM   0x19
 497 #define DRM_RADEON_SURF_ALLOC 0x1a
 498 #define DRM_RADEON_SURF_FREE  0x1b
 499 /* KMS ioctl */
 500 #define DRM_RADEON_GEM_INFO             0x1c
 501 #define DRM_RADEON_GEM_CREATE           0x1d
 502 #define DRM_RADEON_GEM_MMAP             0x1e
 503 #define DRM_RADEON_GEM_PREAD            0x21
 504 #define DRM_RADEON_GEM_PWRITE           0x22
 505 #define DRM_RADEON_GEM_SET_DOMAIN       0x23
 506 #define DRM_RADEON_GEM_WAIT_IDLE        0x24
 507 #define DRM_RADEON_CS                   0x26
 508 #define DRM_RADEON_INFO                 0x27
 509 #define DRM_RADEON_GEM_SET_TILING       0x28
 510 #define DRM_RADEON_GEM_GET_TILING       0x29
 511 #define DRM_RADEON_GEM_BUSY             0x2a
 512 #define DRM_RADEON_GEM_VA               0x2b
 513
 514 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 515 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 516 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 517 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 518 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 519 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
 520 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 521 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 522 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 523 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 524 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 525 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 526 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 527 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 528 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 529 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 530 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 531 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 532 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 533 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 534 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 535 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 536 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 537 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 538 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 539 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 540 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 541 /* KMS */
 542 #define DRM_IOCTL_RADEON_GEM_INFO       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
 543 #define DRM_IOCTL_RADEON_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
 544 #define DRM_IOCTL_RADEON_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
 545 #define DRM_IOCTL_RADEON_GEM_PREAD      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
 546 #define DRM_IOCTL_RADEON_GEM_PWRITE     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
 547 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
 548 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE  DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
 549 #define DRM_IOCTL_RADEON_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 550 #define DRM_IOCTL_RADEON_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
 551 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
 552 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
 553 #define DRM_IOCTL_RADEON_GEM_BUSY       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 554 #define DRM_IOCTL_RADEON_GEM_VA         DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
 555
 556 typedef struct drm_radeon_init {
 557         enum {
 558                 RADEON_INIT_CP = 0x01,
 559                 RADEON_CLEANUP_CP = 0x02,
 560                 RADEON_INIT_R200_CP = 0x03,
 561                 RADEON_INIT_R300_CP = 0x04,
 562                 RADEON_INIT_R600_CP = 0x05
 563         } func;
 564         unsigned long sarea_priv_offset;
 565         int is_pci;
 566         int cp_mode;
 567         int gart_size;
 568         int ring_size;
 569         int usec_timeout;
 570
 571         unsigned int fb_bpp;
 572         unsigned int front_offset, front_pitch;
 573         unsigned int back_offset, back_pitch;
 574         unsigned int depth_bpp;
 575         unsigned int depth_offset, depth_pitch;
 576
 577         unsigned long fb_offset;
 578         unsigned long mmio_offset;
 579         unsigned long ring_offset;
 580         unsigned long ring_rptr_offset;
 581         unsigned long buffers_offset;
 582         unsigned long gart_textures_offset;
 583 } drm_radeon_init_t;
 584
 585 typedef struct drm_radeon_cp_stop {
 586         int flush;
 587         int idle;
 588 } drm_radeon_cp_stop_t;
 589
 590 typedef struct drm_radeon_fullscreen {
 591         enum {
 592                 RADEON_INIT_FULLSCREEN = 0x01,
 593                 RADEON_CLEANUP_FULLSCREEN = 0x02
 594         } func;
 595 } drm_radeon_fullscreen_t;
 596
 597 #define CLEAR_X1        0
 598 #define CLEAR_Y1        1
 599 #define CLEAR_X2        2
 600 #define CLEAR_Y2        3
 601 #define CLEAR_DEPTH     4
 602
 603 typedef union drm_radeon_clear_rect {
 604         float f[5];
 605         unsigned int ui[5];
 606 } drm_radeon_clear_rect_t;
 607
 608 typedef struct drm_radeon_clear {
 609         unsigned int flags;
 610         unsigned int clear_color;
 611         unsigned int clear_depth;
 612         unsigned int color_mask;
 613         unsigned int depth_mask;        /* misnamed field:  should be stencil */
 614         drm_radeon_clear_rect_t __user *depth_boxes;
 615 } drm_radeon_clear_t;
 616
 617 typedef struct drm_radeon_vertex {
 618         int prim;
 619         int idx;                /* Index of vertex buffer */
 620         int count;              /* Number of vertices in buffer */
 621         int discard;            /* Client finished with buffer? */
 622 } drm_radeon_vertex_t;
 623
 624 typedef struct drm_radeon_indices {
 625         int prim;
 626         int idx;
 627         int start;
 628         int end;
 629         int discard;            /* Client finished with buffer? */
 630 } drm_radeon_indices_t;
 631
 632 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
 633  *      - allows multiple primitives and state changes in a single ioctl
 634  *      - supports driver change to emit native primitives
 635  */
 636 typedef struct drm_radeon_vertex2 {
 637         int idx;                /* Index of vertex buffer */
 638         int discard;            /* Client finished with buffer? */
 639         int nr_states;
 640         drm_radeon_state_t __user *state;
 641         int nr_prims;
 642         drm_radeon_prim_t __user *prim;
 643 } drm_radeon_vertex2_t;
 644
 645 /* v1.3 - obsoletes drm_radeon_vertex2
 646  *      - allows arbitrarily large cliprect list
 647  *      - allows updating of tcl packet, vector and scalar state
 648  *      - allows memory-efficient description of state updates
 649  *      - allows state to be emitted without a primitive
 650  *           (for clears, ctx switches)
 651  *      - allows more than one dma buffer to be referenced per ioctl
 652  *      - supports tcl driver
 653  *      - may be extended in future versions with new cmd types, packets
 654  */
 655 typedef struct drm_radeon_cmd_buffer {
 656         int bufsz;
 657         char __user *buf;
 658         int nbox;
 659         struct drm_clip_rect __user *boxes;
 660 } drm_radeon_cmd_buffer_t;
 661
 662 typedef struct drm_radeon_tex_image {
 663         unsigned int x, y;      /* Blit coordinates */
 664         unsigned int width, height;
 665         const void __user *data;
 666 } drm_radeon_tex_image_t;
 667
 668 typedef struct drm_radeon_texture {
 669         unsigned int offset;
 670         int pitch;
 671         int format;
 672         int width;              /* Texture image coordinates */
 673         int height;
 674         drm_radeon_tex_image_t __user *image;
 675 } drm_radeon_texture_t;
 676
 677 typedef struct drm_radeon_stipple {
 678         unsigned int __user *mask;
 679 } drm_radeon_stipple_t;
 680
 681 typedef struct drm_radeon_indirect {
 682         int idx;
 683         int start;
 684         int end;
 685         int discard;
 686 } drm_radeon_indirect_t;
 687
 688 /* enum for card type parameters */
 689 #define RADEON_CARD_PCI 0
 690 #define RADEON_CARD_AGP 1
 691 #define RADEON_CARD_PCIE 2
 692
 693 /* 1.3: An ioctl to get parameters that aren't available to the 3d
 694  * client any other way.
 695  */
 696 #define RADEON_PARAM_GART_BUFFER_OFFSET    1    /* card offset of 1st GART buffer */
 697 #define RADEON_PARAM_LAST_FRAME            2
 698 #define RADEON_PARAM_LAST_DISPATCH         3
 699 #define RADEON_PARAM_LAST_CLEAR            4
 700 /* Added with DRM version 1.6. */
 701 #define RADEON_PARAM_IRQ_NR                5
 702 #define RADEON_PARAM_GART_BASE             6    /* card offset of GART base */
 703 /* Added with DRM version 1.8. */
 704 #define RADEON_PARAM_REGISTER_HANDLE       7    /* for drmMap() */
 705 #define RADEON_PARAM_STATUS_HANDLE         8
 706 #define RADEON_PARAM_SAREA_HANDLE          9
 707 #define RADEON_PARAM_GART_TEX_HANDLE       10
 708 #define RADEON_PARAM_SCRATCH_OFFSET        11
 709 #define RADEON_PARAM_CARD_TYPE             12
 710 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 711 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 712 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 713 #define RADEON_PARAM_DEVICE_ID             16
 714 #define RADEON_PARAM_NUM_Z_PIPES           17   /* num Z pipes */
 715
 716 typedef struct drm_radeon_getparam {
 717         int param;
 718         void __user *value;
 719 } drm_radeon_getparam_t;
 720
 721 /* 1.6: Set up a memory manager for regions of shared memory:
 722  */
 723 #define RADEON_MEM_REGION_GART 1
 724 #define RADEON_MEM_REGION_FB   2
 725
 726 typedef struct drm_radeon_mem_alloc {
 727         int region;
 728         int alignment;
 729         int size;
 730         int __user *region_offset;      /* offset from start of fb or GART */
 731 } drm_radeon_mem_alloc_t;
 732
 733 typedef struct drm_radeon_mem_free {
 734         int region;
 735         int region_offset;
 736 } drm_radeon_mem_free_t;
 737
 738 typedef struct drm_radeon_mem_init_heap {
 739         int region;
 740         int size;
 741         int start;
 742 } drm_radeon_mem_init_heap_t;
 743
 744 /* 1.6: Userspace can request & wait on irq's:
 745  */
 746 typedef struct drm_radeon_irq_emit {
 747         int __user *irq_seq;
 748 } drm_radeon_irq_emit_t;
 749
 750 typedef struct drm_radeon_irq_wait {
 751         int irq_seq;
 752 } drm_radeon_irq_wait_t;
 753
 754 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
 755  * the card's address space, via a new generic ioctl to set parameters
 756  */
 757
 758 typedef struct drm_radeon_setparam {
 759         unsigned int param;
 760         __s64 value;
 761 } drm_radeon_setparam_t;
 762
 763 #define RADEON_SETPARAM_FB_LOCATION    1        /* determined framebuffer location */
 764 #define RADEON_SETPARAM_SWITCH_TILING  2        /* enable/disable color tiling */
 765 #define RADEON_SETPARAM_PCIGART_LOCATION 3      /* PCI Gart Location */
 766 #define RADEON_SETPARAM_NEW_MEMMAP 4            /* Use new memory map */
 767 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 768 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
 769 /* 1.14: Clients can allocate/free a surface
 770  */
 771 typedef struct drm_radeon_surface_alloc {
 772         unsigned int address;
 773         unsigned int size;
 774         unsigned int flags;
 775 } drm_radeon_surface_alloc_t;
 776
 777 typedef struct drm_radeon_surface_free {
 778         unsigned int address;
 779 } drm_radeon_surface_free_t;
 780
 781 #define DRM_RADEON_VBLANK_CRTC1         1
 782 #define DRM_RADEON_VBLANK_CRTC2         2
 783
 784 /*
 785  * Kernel modesetting world below.
 786  */
 787 #define RADEON_GEM_DOMAIN_CPU           0x1
 788 #define RADEON_GEM_DOMAIN_GTT           0x2
 789 #define RADEON_GEM_DOMAIN_VRAM          0x4
 790
 791 struct drm_radeon_gem_info {
 792         uint64_t        gart_size;
 793         uint64_t        vram_size;
 794         uint64_t        vram_visible;
 795 };
 796
 797 #define RADEON_GEM_NO_BACKING_STORE 1
 798
 799 struct drm_radeon_gem_create {
 800         uint64_t        size;
 801         uint64_t        alignment;
 802         uint32_t        handle;
 803         uint32_t        initial_domain;
 804         uint32_t        flags;
 805 };
 806
 807 #define RADEON_TILING_MACRO                             0x1
 808 #define RADEON_TILING_MICRO                             0x2
 809 #define RADEON_TILING_SWAP_16BIT                        0x4
 810 #define RADEON_TILING_SWAP_32BIT                        0x8
 811 /* this object requires a surface when mapped - i.e. front buffer */
 812 #define RADEON_TILING_SURFACE                           0x10
 813 #define RADEON_TILING_MICRO_SQUARE                      0x20
 814 #define RADEON_TILING_EG_BANKW_SHIFT                    8
 815 #define RADEON_TILING_EG_BANKW_MASK                     0xf
 816 #define RADEON_TILING_EG_BANKH_SHIFT                    12
 817 #define RADEON_TILING_EG_BANKH_MASK                     0xf
 818 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT        16
 819 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK         0xf
 820 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT               24
 821 #define RADEON_TILING_EG_TILE_SPLIT_MASK                0xf
 822 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT       28
 823 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK        0xf
 824
 825 struct drm_radeon_gem_set_tiling {
 826         uint32_t        handle;
 827         uint32_t        tiling_flags;
 828         uint32_t        pitch;
 829 };
 830
 831 struct drm_radeon_gem_get_tiling {
 832         uint32_t        handle;
 833         uint32_t        tiling_flags;
 834         uint32_t        pitch;
 835 };
 836
 837 struct drm_radeon_gem_mmap {
 838         uint32_t        handle;
 839         uint32_t        pad;
 840         uint64_t        offset;
 841         uint64_t        size;
 842         uint64_t        addr_ptr;
 843 };
 844
 845 struct drm_radeon_gem_set_domain {
 846         uint32_t        handle;
 847         uint32_t        read_domains;
 848         uint32_t        write_domain;
 849 };
 850
 851 struct drm_radeon_gem_wait_idle {
 852         uint32_t        handle;
 853         uint32_t        pad;
 854 };
 855
 856 struct drm_radeon_gem_busy {
 857         uint32_t        handle;
 858         uint32_t        domain;
 859 };
 860
 861 struct drm_radeon_gem_pread {
 862         /** Handle for the object being read. */
 863         uint32_t handle;
 864         uint32_t pad;
 865         /** Offset into the object to read from */
 866         uint64_t offset;
 867         /** Length of data to read */
 868         uint64_t size;
 869         /** Pointer to write the data into. */
 870         /* void *, but pointers are not 32/64 compatible */
 871         uint64_t data_ptr;
 872 };
 873
 874 struct drm_radeon_gem_pwrite {
 875         /** Handle for the object being written to. */
 876         uint32_t handle;
 877         uint32_t pad;
 878         /** Offset into the object to write to */
 879         uint64_t offset;
 880         /** Length of data to write */
 881         uint64_t size;
 882         /** Pointer to read the data from. */
 883         /* void *, but pointers are not 32/64 compatible */
 884         uint64_t data_ptr;
 885 };
 886
 887 #define RADEON_VA_MAP                   1
 888 #define RADEON_VA_UNMAP                 2
 889
 890 #define RADEON_VA_RESULT_OK             0
 891 #define RADEON_VA_RESULT_ERROR          1
 892 #define RADEON_VA_RESULT_VA_EXIST       2
 893
 894 #define RADEON_VM_PAGE_VALID            (1 << 0)
 895 #define RADEON_VM_PAGE_READABLE         (1 << 1)
 896 #define RADEON_VM_PAGE_WRITEABLE        (1 << 2)
 897 #define RADEON_VM_PAGE_SYSTEM           (1 << 3)
 898 #define RADEON_VM_PAGE_SNOOPED          (1 << 4)
 899
 900 struct drm_radeon_gem_va {
 901         uint32_t                handle;
 902         uint32_t                operation;
 903         uint32_t                vm_id;
 904         uint32_t                flags;
 905         uint64_t                offset;
 906 };
 907
 908 #define RADEON_CHUNK_ID_RELOCS  0x01
 909 #define RADEON_CHUNK_ID_IB      0x02
 910 #define RADEON_CHUNK_ID_FLAGS   0x03
 911 #define RADEON_CHUNK_ID_CONST_IB        0x04
 912
 913 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
 914 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
 915 #define RADEON_CS_USE_VM            0x02
 916 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
 917 #define RADEON_CS_RING_GFX          0
 918 #define RADEON_CS_RING_COMPUTE      1
 919 /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
 920 /* 0 = normal, + = higher priority, - = lower priority */
 921
 922 struct drm_radeon_cs_chunk {
 923         uint32_t                chunk_id;
 924         uint32_t                length_dw;
 925         uint64_t                chunk_data;
 926 };
 927
 928 /* drm_radeon_cs_reloc.flags */
 929
 930 struct drm_radeon_cs_reloc {
 931         uint32_t                handle;
 932         uint32_t                read_domains;
 933         uint32_t                write_domain;
 934         uint32_t                flags;
 935 };
 936
 937 struct drm_radeon_cs {
 938         uint32_t                num_chunks;
 939         uint32_t                cs_id;
 940         /* this points to uint64_t * which point to cs chunks */
 941         uint64_t                chunks;
 942         /* updates to the limits after this CS ioctl */
 943         uint64_t                gart_limit;
 944         uint64_t                vram_limit;
 945 };
 946
 947 #define RADEON_INFO_DEVICE_ID           0x00
 948 #define RADEON_INFO_NUM_GB_PIPES        0x01
 949 #define RADEON_INFO_NUM_Z_PIPES         0x02
 950 #define RADEON_INFO_ACCEL_WORKING       0x03
 951 #define RADEON_INFO_CRTC_FROM_ID        0x04
 952 #define RADEON_INFO_ACCEL_WORKING2      0x05
 953 #define RADEON_INFO_TILING_CONFIG       0x06
 954 #define RADEON_INFO_WANT_HYPERZ         0x07
 955 #define RADEON_INFO_WANT_CMASK          0x08 /* get access to CMASK on r300 */
 956 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ  0x09 /* clock crystal frequency */
 957 #define RADEON_INFO_NUM_BACKENDS        0x0a /* DB/backends for r600+ - need for OQ */
 958 #define RADEON_INFO_NUM_TILE_PIPES      0x0b /* tile pipes for r600+ */
 959 #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
 960 #define RADEON_INFO_BACKEND_MAP         0x0d /* pipe to backend map, needed by mesa */
 961 /* virtual address start, va < start are reserved by the kernel */
 962 #define RADEON_INFO_VA_START            0x0e
 963 /* maximum size of ib using the virtual memory cs */
 964 #define RADEON_INFO_IB_VM_MAX_SIZE      0x0f
 965 /* max pipes - needed for compute shaders */
 966 #define RADEON_INFO_MAX_PIPES           0x10
 967 /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
 968 #define RADEON_INFO_TIMESTAMP           0x11
 969
 970 struct drm_radeon_info {
 971         uint32_t                request;
 972         uint32_t                pad;
 973         uint64_t                value;
 974 };
 975
 976 #endif