| blob | 5d3b470f1be591d291b0146f2173253b1c404423 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SDM845 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
14 #include <dt-bindings/interconnect/qcom,sdm845.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
22 #include <dt-bindings/thermal/thermal.h>
24 / {
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
30 aliases {
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 i2c3 = &i2c3;
35 i2c4 = &i2c4;
36 i2c5 = &i2c5;
37 i2c6 = &i2c6;
38 i2c7 = &i2c7;
39 i2c8 = &i2c8;
40 i2c9 = &i2c9;
41 i2c10 = &i2c10;
42 i2c11 = &i2c11;
43 i2c12 = &i2c12;
44 i2c13 = &i2c13;
45 i2c14 = &i2c14;
46 i2c15 = &i2c15;
47 spi0 = &spi0;
48 spi1 = &spi1;
49 spi2 = &spi2;
50 spi3 = &spi3;
51 spi4 = &spi4;
52 spi5 = &spi5;
53 spi6 = &spi6;
54 spi7 = &spi7;
55 spi8 = &spi8;
56 spi9 = &spi9;
57 spi10 = &spi10;
58 spi11 = &spi11;
59 spi12 = &spi12;
60 spi13 = &spi13;
61 spi14 = &spi14;
62 spi15 = &spi15;
63 };
65 chosen { };
67 memory@80000000 {
68 device_type = "memory";
69 /* We expect the bootloader to fill in the size */
70 reg = <0 0x80000000 0 0>;
71 };
73 reserved-memory {
74 #address-cells = <2>;
75 #size-cells = <2>;
76 ranges;
78 hyp_mem: memory@85700000 {
79 reg = <0 0x85700000 0 0x600000>;
80 no-map;
81 };
83 xbl_mem: memory@85e00000 {
84 reg = <0 0x85e00000 0 0x100000>;
85 no-map;
86 };
88 aop_mem: memory@85fc0000 {
89 reg = <0 0x85fc0000 0 0x20000>;
90 no-map;
91 };
93 aop_cmd_db_mem: memory@85fe0000 {
94 compatible = "qcom,cmd-db";
95 reg = <0x0 0x85fe0000 0 0x20000>;
96 no-map;
97 };
99 smem_mem: memory@86000000 {
100 reg = <0x0 0x86000000 0 0x200000>;
101 no-map;
102 };
104 tz_mem: memory@86200000 {
105 reg = <0 0x86200000 0 0x2d00000>;
106 no-map;
107 };
109 rmtfs_mem: memory@88f00000 {
110 compatible = "qcom,rmtfs-mem";
111 reg = <0 0x88f00000 0 0x200000>;
112 no-map;
114 qcom,client-id = <1>;
115 qcom,vmid = <15>;
116 };
118 qseecom_mem: memory@8ab00000 {
119 reg = <0 0x8ab00000 0 0x1400000>;
120 no-map;
121 };
123 camera_mem: memory@8bf00000 {
124 reg = <0 0x8bf00000 0 0x500000>;
125 no-map;
126 };
128 ipa_fw_mem: memory@8c400000 {
129 reg = <0 0x8c400000 0 0x10000>;
130 no-map;
131 };
133 ipa_gsi_mem: memory@8c410000 {
134 reg = <0 0x8c410000 0 0x5000>;
135 no-map;
136 };
138 gpu_mem: memory@8c415000 {
139 reg = <0 0x8c415000 0 0x2000>;
140 no-map;
141 };
143 adsp_mem: memory@8c500000 {
144 reg = <0 0x8c500000 0 0x1a00000>;
145 no-map;
146 };
148 wlan_msa_mem: memory@8df00000 {
149 reg = <0 0x8df00000 0 0x100000>;
150 no-map;
151 };
153 mpss_region: memory@8e000000 {
154 reg = <0 0x8e000000 0 0x7800000>;
155 no-map;
156 };
158 venus_mem: memory@95800000 {
159 reg = <0 0x95800000 0 0x500000>;
160 no-map;
161 };
163 cdsp_mem: memory@95d00000 {
164 reg = <0 0x95d00000 0 0x800000>;
165 no-map;
166 };
168 mba_region: memory@96500000 {
169 reg = <0 0x96500000 0 0x200000>;
170 no-map;
171 };
173 slpi_mem: memory@96700000 {
174 reg = <0 0x96700000 0 0x1400000>;
175 no-map;
176 };
178 spss_mem: memory@97b00000 {
179 reg = <0 0x97b00000 0 0x100000>;
180 no-map;
181 };
182 };
184 cpus {
185 #address-cells = <2>;
186 #size-cells = <0>;
188 CPU0: cpu@0 {
189 device_type = "cpu";
190 compatible = "qcom,kryo385";
191 reg = <0x0 0x0>;
192 enable-method = "psci";
193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
194 &LITTLE_CPU_SLEEP_1
195 &CLUSTER_SLEEP_0>;
196 capacity-dmips-mhz = <607>;
197 dynamic-power-coefficient = <100>;
198 qcom,freq-domain = <&cpufreq_hw 0>;
199 #cooling-cells = <2>;
200 next-level-cache = <&L2_0>;
201 L2_0: l2-cache {
202 compatible = "cache";
203 next-level-cache = <&L3_0>;
204 L3_0: l3-cache {
205 compatible = "cache";
206 };
207 };
208 };
210 CPU1: cpu@100 {
211 device_type = "cpu";
212 compatible = "qcom,kryo385";
213 reg = <0x0 0x100>;
214 enable-method = "psci";
215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
216 &LITTLE_CPU_SLEEP_1
217 &CLUSTER_SLEEP_0>;
218 capacity-dmips-mhz = <607>;
219 dynamic-power-coefficient = <100>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 #cooling-cells = <2>;
222 next-level-cache = <&L2_100>;
223 L2_100: l2-cache {
224 compatible = "cache";
225 next-level-cache = <&L3_0>;
226 };
227 };
229 CPU2: cpu@200 {
230 device_type = "cpu";
231 compatible = "qcom,kryo385";
232 reg = <0x0 0x200>;
233 enable-method = "psci";
234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
235 &LITTLE_CPU_SLEEP_1
236 &CLUSTER_SLEEP_0>;
237 capacity-dmips-mhz = <607>;
238 dynamic-power-coefficient = <100>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
240 #cooling-cells = <2>;
241 next-level-cache = <&L2_200>;
242 L2_200: l2-cache {
243 compatible = "cache";
244 next-level-cache = <&L3_0>;
245 };
246 };
248 CPU3: cpu@300 {
249 device_type = "cpu";
250 compatible = "qcom,kryo385";
251 reg = <0x0 0x300>;
252 enable-method = "psci";
253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
254 &LITTLE_CPU_SLEEP_1
255 &CLUSTER_SLEEP_0>;
256 capacity-dmips-mhz = <607>;
257 dynamic-power-coefficient = <100>;
258 qcom,freq-domain = <&cpufreq_hw 0>;
259 #cooling-cells = <2>;
260 next-level-cache = <&L2_300>;
261 L2_300: l2-cache {
262 compatible = "cache";
263 next-level-cache = <&L3_0>;
264 };
265 };
267 CPU4: cpu@400 {
268 device_type = "cpu";
269 compatible = "qcom,kryo385";
270 reg = <0x0 0x400>;
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 cpu-idle-states = <&BIG_CPU_SLEEP_0
274 &BIG_CPU_SLEEP_1
275 &CLUSTER_SLEEP_0>;
276 dynamic-power-coefficient = <396>;
277 qcom,freq-domain = <&cpufreq_hw 1>;
278 #cooling-cells = <2>;
279 next-level-cache = <&L2_400>;
280 L2_400: l2-cache {
281 compatible = "cache";
282 next-level-cache = <&L3_0>;
283 };
284 };
286 CPU5: cpu@500 {
287 device_type = "cpu";
288 compatible = "qcom,kryo385";
289 reg = <0x0 0x500>;
290 enable-method = "psci";
291 capacity-dmips-mhz = <1024>;
292 cpu-idle-states = <&BIG_CPU_SLEEP_0
293 &BIG_CPU_SLEEP_1
294 &CLUSTER_SLEEP_0>;
295 dynamic-power-coefficient = <396>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
297 #cooling-cells = <2>;
298 next-level-cache = <&L2_500>;
299 L2_500: l2-cache {
300 compatible = "cache";
301 next-level-cache = <&L3_0>;
302 };
303 };
305 CPU6: cpu@600 {
306 device_type = "cpu";
307 compatible = "qcom,kryo385";
308 reg = <0x0 0x600>;
309 enable-method = "psci";
310 capacity-dmips-mhz = <1024>;
311 cpu-idle-states = <&BIG_CPU_SLEEP_0
312 &BIG_CPU_SLEEP_1
313 &CLUSTER_SLEEP_0>;
314 dynamic-power-coefficient = <396>;
315 qcom,freq-domain = <&cpufreq_hw 1>;
316 #cooling-cells = <2>;
317 next-level-cache = <&L2_600>;
318 L2_600: l2-cache {
319 compatible = "cache";
320 next-level-cache = <&L3_0>;
321 };
322 };
324 CPU7: cpu@700 {
325 device_type = "cpu";
326 compatible = "qcom,kryo385";
327 reg = <0x0 0x700>;
328 enable-method = "psci";
329 capacity-dmips-mhz = <1024>;
330 cpu-idle-states = <&BIG_CPU_SLEEP_0
331 &BIG_CPU_SLEEP_1
332 &CLUSTER_SLEEP_0>;
333 dynamic-power-coefficient = <396>;
334 qcom,freq-domain = <&cpufreq_hw 1>;
335 #cooling-cells = <2>;
336 next-level-cache = <&L2_700>;
337 L2_700: l2-cache {
338 compatible = "cache";
339 next-level-cache = <&L3_0>;
340 };
341 };
343 cpu-map {
344 cluster0 {
345 core0 {
346 cpu = <&CPU0>;
347 };
349 core1 {
350 cpu = <&CPU1>;
351 };
353 core2 {
354 cpu = <&CPU2>;
355 };
357 core3 {
358 cpu = <&CPU3>;
359 };
361 core4 {
362 cpu = <&CPU4>;
363 };
365 core5 {
366 cpu = <&CPU5>;
367 };
369 core6 {
370 cpu = <&CPU6>;
371 };
373 core7 {
374 cpu = <&CPU7>;
375 };
376 };
377 };
379 idle-states {
380 entry-method = "psci";
382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
383 compatible = "arm,idle-state";
384 idle-state-name = "little-power-down";
385 arm,psci-suspend-param = <0x40000003>;
386 entry-latency-us = <350>;
387 exit-latency-us = <461>;
388 min-residency-us = <1890>;
389 local-timer-stop;
390 };
392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
393 compatible = "arm,idle-state";
394 idle-state-name = "little-rail-power-down";
395 arm,psci-suspend-param = <0x40000004>;
396 entry-latency-us = <360>;
397 exit-latency-us = <531>;
398 min-residency-us = <3934>;
399 local-timer-stop;
400 };
402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
403 compatible = "arm,idle-state";
404 idle-state-name = "big-power-down";
405 arm,psci-suspend-param = <0x40000003>;
406 entry-latency-us = <264>;
407 exit-latency-us = <621>;
408 min-residency-us = <952>;
409 local-timer-stop;
410 };
412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
413 compatible = "arm,idle-state";
414 idle-state-name = "big-rail-power-down";
415 arm,psci-suspend-param = <0x40000004>;
416 entry-latency-us = <702>;
417 exit-latency-us = <1061>;
418 min-residency-us = <4488>;
419 local-timer-stop;
420 };
422 CLUSTER_SLEEP_0: cluster-sleep-0 {
423 compatible = "arm,idle-state";
424 idle-state-name = "cluster-power-down";
425 arm,psci-suspend-param = <0x400000F4>;
426 entry-latency-us = <3263>;
427 exit-latency-us = <6562>;
428 min-residency-us = <9987>;
429 local-timer-stop;
430 };
431 };
432 };
434 pmu {
435 compatible = "arm,armv8-pmuv3";
436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
437 };
439 timer {
440 compatible = "arm,armv8-timer";
441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
445 };
447 clocks {
448 xo_board: xo-board {
449 compatible = "fixed-clock";
450 #clock-cells = <0>;
451 clock-frequency = <38400000>;
452 clock-output-names = "xo_board";
453 };
455 sleep_clk: sleep-clk {
456 compatible = "fixed-clock";
457 #clock-cells = <0>;
458 clock-frequency = <32764>;
459 };
460 };
462 firmware {
463 scm {
464 compatible = "qcom,scm-sdm845", "qcom,scm";
465 };
466 };
468 adsp_pas: remoteproc-adsp {
469 compatible = "qcom,sdm845-adsp-pas";
471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
476 interrupt-names = "wdog", "fatal", "ready",
477 "handover", "stop-ack";
479 clocks = <&rpmhcc RPMH_CXO_CLK>;
480 clock-names = "xo";
482 memory-region = <&adsp_mem>;
484 qcom,smem-states = <&adsp_smp2p_out 0>;
485 qcom,smem-state-names = "stop";
487 status = "disabled";
489 glink-edge {
490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
491 label = "lpass";
492 qcom,remote-pid = <2>;
493 mboxes = <&apss_shared 8>;
494 fastrpc {
495 compatible = "qcom,fastrpc";
496 qcom,glink-channels = "fastrpcglink-apps-dsp";
497 label = "adsp";
498 #address-cells = <1>;
499 #size-cells = <0>;
501 compute-cb@3 {
502 compatible = "qcom,fastrpc-compute-cb";
503 reg = <3>;
504 iommus = <&apps_smmu 0x1823 0x0>;
505 };
507 compute-cb@4 {
508 compatible = "qcom,fastrpc-compute-cb";
509 reg = <4>;
510 iommus = <&apps_smmu 0x1824 0x0>;
511 };
512 };
513 };
514 };
516 cdsp_pas: remoteproc-cdsp {
517 compatible = "qcom,sdm845-cdsp-pas";
519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
524 interrupt-names = "wdog", "fatal", "ready",
525 "handover", "stop-ack";
527 clocks = <&rpmhcc RPMH_CXO_CLK>;
528 clock-names = "xo";
530 memory-region = <&cdsp_mem>;
532 qcom,smem-states = <&cdsp_smp2p_out 0>;
533 qcom,smem-state-names = "stop";
535 status = "disabled";
537 glink-edge {
538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
539 label = "turing";
540 qcom,remote-pid = <5>;
541 mboxes = <&apss_shared 4>;
542 fastrpc {
543 compatible = "qcom,fastrpc";
544 qcom,glink-channels = "fastrpcglink-apps-dsp";
545 label = "cdsp";
546 #address-cells = <1>;
547 #size-cells = <0>;
549 compute-cb@1 {
550 compatible = "qcom,fastrpc-compute-cb";
551 reg = <1>;
552 iommus = <&apps_smmu 0x1401 0x30>;
553 };
555 compute-cb@2 {
556 compatible = "qcom,fastrpc-compute-cb";
557 reg = <2>;
558 iommus = <&apps_smmu 0x1402 0x30>;
559 };
561 compute-cb@3 {
562 compatible = "qcom,fastrpc-compute-cb";
563 reg = <3>;
564 iommus = <&apps_smmu 0x1403 0x30>;
565 };
567 compute-cb@4 {
568 compatible = "qcom,fastrpc-compute-cb";
569 reg = <4>;
570 iommus = <&apps_smmu 0x1404 0x30>;
571 };
573 compute-cb@5 {
574 compatible = "qcom,fastrpc-compute-cb";
575 reg = <5>;
576 iommus = <&apps_smmu 0x1405 0x30>;
577 };
579 compute-cb@6 {
580 compatible = "qcom,fastrpc-compute-cb";
581 reg = <6>;
582 iommus = <&apps_smmu 0x1406 0x30>;
583 };
585 compute-cb@7 {
586 compatible = "qcom,fastrpc-compute-cb";
587 reg = <7>;
588 iommus = <&apps_smmu 0x1407 0x30>;
589 };
591 compute-cb@8 {
592 compatible = "qcom,fastrpc-compute-cb";
593 reg = <8>;
594 iommus = <&apps_smmu 0x1408 0x30>;
595 };
596 };
597 };
598 };
600 tcsr_mutex: hwlock {
601 compatible = "qcom,tcsr-mutex";
602 syscon = <&tcsr_mutex_regs 0 0x1000>;
603 #hwlock-cells = <1>;
604 };
606 smem {
607 compatible = "qcom,smem";
608 memory-region = <&smem_mem>;
609 hwlocks = <&tcsr_mutex 3>;
610 };
612 smp2p-cdsp {
613 compatible = "qcom,smp2p";
614 qcom,smem = <94>, <432>;
616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
618 mboxes = <&apss_shared 6>;
620 qcom,local-pid = <0>;
621 qcom,remote-pid = <5>;
623 cdsp_smp2p_out: master-kernel {
624 qcom,entry-name = "master-kernel";
625 #qcom,smem-state-cells = <1>;
626 };
628 cdsp_smp2p_in: slave-kernel {
629 qcom,entry-name = "slave-kernel";
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 };
634 };
636 smp2p-lpass {
637 compatible = "qcom,smp2p";
638 qcom,smem = <443>, <429>;
640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
642 mboxes = <&apss_shared 10>;
644 qcom,local-pid = <0>;
645 qcom,remote-pid = <2>;
647 adsp_smp2p_out: master-kernel {
648 qcom,entry-name = "master-kernel";
649 #qcom,smem-state-cells = <1>;
650 };
652 adsp_smp2p_in: slave-kernel {
653 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
657 };
658 };
660 smp2p-mpss {
661 compatible = "qcom,smp2p";
662 qcom,smem = <435>, <428>;
663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&apss_shared 14>;
665 qcom,local-pid = <0>;
666 qcom,remote-pid = <1>;
668 modem_smp2p_out: master-kernel {
669 qcom,entry-name = "master-kernel";
670 #qcom,smem-state-cells = <1>;
671 };
673 modem_smp2p_in: slave-kernel {
674 qcom,entry-name = "slave-kernel";
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 };
678 };
680 smp2p-slpi {
681 compatible = "qcom,smp2p";
682 qcom,smem = <481>, <430>;
683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
684 mboxes = <&apss_shared 26>;
685 qcom,local-pid = <0>;
686 qcom,remote-pid = <3>;
688 slpi_smp2p_out: master-kernel {
689 qcom,entry-name = "master-kernel";
690 #qcom,smem-state-cells = <1>;
691 };
693 slpi_smp2p_in: slave-kernel {
694 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
697 };
698 };
700 psci {
701 compatible = "arm,psci-1.0";
702 method = "smc";
703 };
705 soc: soc@0 {
706 #address-cells = <2>;
707 #size-cells = <2>;
708 ranges = <0 0 0 0 0x10 0>;
709 dma-ranges = <0 0 0 0 0x10 0>;
710 compatible = "simple-bus";
712 gcc: clock-controller@100000 {
713 compatible = "qcom,gcc-sdm845";
714 reg = <0 0x00100000 0 0x1f0000>;
715 #clock-cells = <1>;
716 #reset-cells = <1>;
717 #power-domain-cells = <1>;
718 };
720 qfprom@784000 {
721 compatible = "qcom,qfprom";
722 reg = <0 0x00784000 0 0x8ff>;
723 #address-cells = <1>;
724 #size-cells = <1>;
726 qusb2p_hstx_trim: hstx-trim-primary@1eb {
727 reg = <0x1eb 0x1>;
728 bits = <1 4>;
729 };
731 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
732 reg = <0x1eb 0x2>;
733 bits = <6 4>;
734 };
735 };
737 rng: rng@793000 {
738 compatible = "qcom,prng-ee";
739 reg = <0 0x00793000 0 0x1000>;
740 clocks = <&gcc GCC_PRNG_AHB_CLK>;
741 clock-names = "core";
742 };
744 qupv3_id_0: geniqup@8c0000 {
745 compatible = "qcom,geni-se-qup";
746 reg = <0 0x008c0000 0 0x6000>;
747 clock-names = "m-ahb", "s-ahb";
748 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
749 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
750 #address-cells = <2>;
751 #size-cells = <2>;
752 ranges;
753 status = "disabled";
755 i2c0: i2c@880000 {
756 compatible = "qcom,geni-i2c";
757 reg = <0 0x00880000 0 0x4000>;
758 clock-names = "se";
759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&qup_i2c0_default>;
762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
763 #address-cells = <1>;
764 #size-cells = <0>;
765 status = "disabled";
766 };
768 spi0: spi@880000 {
769 compatible = "qcom,geni-spi";
770 reg = <0 0x00880000 0 0x4000>;
771 clock-names = "se";
772 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
773 pinctrl-names = "default";
774 pinctrl-0 = <&qup_spi0_default>;
775 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
776 #address-cells = <1>;
777 #size-cells = <0>;
778 status = "disabled";
779 };
781 uart0: serial@880000 {
782 compatible = "qcom,geni-uart";
783 reg = <0 0x00880000 0 0x4000>;
784 clock-names = "se";
785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
786 pinctrl-names = "default";
787 pinctrl-0 = <&qup_uart0_default>;
788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
789 status = "disabled";
790 };
792 i2c1: i2c@884000 {
793 compatible = "qcom,geni-i2c";
794 reg = <0 0x00884000 0 0x4000>;
795 clock-names = "se";
796 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&qup_i2c1_default>;
799 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 status = "disabled";
803 };
805 spi1: spi@884000 {
806 compatible = "qcom,geni-spi";
807 reg = <0 0x00884000 0 0x4000>;
808 clock-names = "se";
809 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_spi1_default>;
812 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
813 #address-cells = <1>;
814 #size-cells = <0>;
815 status = "disabled";
816 };
818 uart1: serial@884000 {
819 compatible = "qcom,geni-uart";
820 reg = <0 0x00884000 0 0x4000>;
821 clock-names = "se";
822 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
823 pinctrl-names = "default";
824 pinctrl-0 = <&qup_uart1_default>;
825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
826 status = "disabled";
827 };
829 i2c2: i2c@888000 {
830 compatible = "qcom,geni-i2c";
831 reg = <0 0x00888000 0 0x4000>;
832 clock-names = "se";
833 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_i2c2_default>;
836 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 status = "disabled";
840 };
842 spi2: spi@888000 {
843 compatible = "qcom,geni-spi";
844 reg = <0 0x00888000 0 0x4000>;
845 clock-names = "se";
846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_spi2_default>;
849 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
850 #address-cells = <1>;
851 #size-cells = <0>;
852 status = "disabled";
853 };
855 uart2: serial@888000 {
856 compatible = "qcom,geni-uart";
857 reg = <0 0x00888000 0 0x4000>;
858 clock-names = "se";
859 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
860 pinctrl-names = "default";
861 pinctrl-0 = <&qup_uart2_default>;
862 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
863 status = "disabled";
864 };
866 i2c3: i2c@88c000 {
867 compatible = "qcom,geni-i2c";
868 reg = <0 0x0088c000 0 0x4000>;
869 clock-names = "se";
870 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
871 pinctrl-names = "default";
872 pinctrl-0 = <&qup_i2c3_default>;
873 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
877 };
879 spi3: spi@88c000 {
880 compatible = "qcom,geni-spi";
881 reg = <0 0x0088c000 0 0x4000>;
882 clock-names = "se";
883 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
884 pinctrl-names = "default";
885 pinctrl-0 = <&qup_spi3_default>;
886 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
887 #address-cells = <1>;
888 #size-cells = <0>;
889 status = "disabled";
890 };
892 uart3: serial@88c000 {
893 compatible = "qcom,geni-uart";
894 reg = <0 0x0088c000 0 0x4000>;
895 clock-names = "se";
896 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
897 pinctrl-names = "default";
898 pinctrl-0 = <&qup_uart3_default>;
899 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
900 status = "disabled";
901 };
903 i2c4: i2c@890000 {
904 compatible = "qcom,geni-i2c";
905 reg = <0 0x00890000 0 0x4000>;
906 clock-names = "se";
907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_i2c4_default>;
910 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
911 #address-cells = <1>;
912 #size-cells = <0>;
913 status = "disabled";
914 };
916 spi4: spi@890000 {
917 compatible = "qcom,geni-spi";
918 reg = <0 0x00890000 0 0x4000>;
919 clock-names = "se";
920 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&qup_spi4_default>;
923 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
924 #address-cells = <1>;
925 #size-cells = <0>;
926 status = "disabled";
927 };
929 uart4: serial@890000 {
930 compatible = "qcom,geni-uart";
931 reg = <0 0x00890000 0 0x4000>;
932 clock-names = "se";
933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
934 pinctrl-names = "default";
935 pinctrl-0 = <&qup_uart4_default>;
936 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
937 status = "disabled";
938 };
940 i2c5: i2c@894000 {
941 compatible = "qcom,geni-i2c";
942 reg = <0 0x00894000 0 0x4000>;
943 clock-names = "se";
944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c5_default>;
947 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
948 #address-cells = <1>;
949 #size-cells = <0>;
950 status = "disabled";
951 };
953 spi5: spi@894000 {
954 compatible = "qcom,geni-spi";
955 reg = <0 0x00894000 0 0x4000>;
956 clock-names = "se";
957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
958 pinctrl-names = "default";
959 pinctrl-0 = <&qup_spi5_default>;
960 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
961 #address-cells = <1>;
962 #size-cells = <0>;
963 status = "disabled";
964 };
966 uart5: serial@894000 {
967 compatible = "qcom,geni-uart";
968 reg = <0 0x00894000 0 0x4000>;
969 clock-names = "se";
970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&qup_uart5_default>;
973 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
974 status = "disabled";
975 };
977 i2c6: i2c@898000 {
978 compatible = "qcom,geni-i2c";
979 reg = <0 0x00898000 0 0x4000>;
980 clock-names = "se";
981 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c6_default>;
984 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
985 #address-cells = <1>;
986 #size-cells = <0>;
987 status = "disabled";
988 };
990 spi6: spi@898000 {
991 compatible = "qcom,geni-spi";
992 reg = <0 0x00898000 0 0x4000>;
993 clock-names = "se";
994 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
995 pinctrl-names = "default";
996 pinctrl-0 = <&qup_spi6_default>;
997 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1000 status = "disabled";
1001 };
1003 uart6: serial@898000 {
1004 compatible = "qcom,geni-uart";
1005 reg = <0 0x00898000 0 0x4000>;
1006 clock-names = "se";
1007 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_uart6_default>;
1010 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1011 status = "disabled";
1012 };
1014 i2c7: i2c@89c000 {
1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x0089c000 0 0x4000>;
1017 clock-names = "se";
1018 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_i2c7_default>;
1021 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 status = "disabled";
1025 };
1027 spi7: spi@89c000 {
1028 compatible = "qcom,geni-spi";
1029 reg = <0 0x0089c000 0 0x4000>;
1030 clock-names = "se";
1031 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_spi7_default>;
1034 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 status = "disabled";
1038 };
1040 uart7: serial@89c000 {
1041 compatible = "qcom,geni-uart";
1042 reg = <0 0x0089c000 0 0x4000>;
1043 clock-names = "se";
1044 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_uart7_default>;
1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1048 status = "disabled";
1049 };
1050 };
1052 qupv3_id_1: geniqup@ac0000 {
1053 compatible = "qcom,geni-se-qup";
1054 reg = <0 0x00ac0000 0 0x6000>;
1055 clock-names = "m-ahb", "s-ahb";
1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1058 #address-cells = <2>;
1059 #size-cells = <2>;
1060 ranges;
1061 status = "disabled";
1063 i2c8: i2c@a80000 {
1064 compatible = "qcom,geni-i2c";
1065 reg = <0 0x00a80000 0 0x4000>;
1066 clock-names = "se";
1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_i2c8_default>;
1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 status = "disabled";
1074 };
1076 spi8: spi@a80000 {
1077 compatible = "qcom,geni-spi";
1078 reg = <0 0x00a80000 0 0x4000>;
1079 clock-names = "se";
1080 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&qup_spi8_default>;
1083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 status = "disabled";
1087 };
1089 uart8: serial@a80000 {
1090 compatible = "qcom,geni-uart";
1091 reg = <0 0x00a80000 0 0x4000>;
1092 clock-names = "se";
1093 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&qup_uart8_default>;
1096 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1097 status = "disabled";
1098 };
1100 i2c9: i2c@a84000 {
1101 compatible = "qcom,geni-i2c";
1102 reg = <0 0x00a84000 0 0x4000>;
1103 clock-names = "se";
1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_i2c9_default>;
1107 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 status = "disabled";
1111 };
1113 spi9: spi@a84000 {
1114 compatible = "qcom,geni-spi";
1115 reg = <0 0x00a84000 0 0x4000>;
1116 clock-names = "se";
1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi9_default>;
1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 status = "disabled";
1124 };
1126 uart9: serial@a84000 {
1127 compatible = "qcom,geni-debug-uart";
1128 reg = <0 0x00a84000 0 0x4000>;
1129 clock-names = "se";
1130 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&qup_uart9_default>;
1133 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1134 status = "disabled";
1135 };
1137 i2c10: i2c@a88000 {
1138 compatible = "qcom,geni-i2c";
1139 reg = <0 0x00a88000 0 0x4000>;
1140 clock-names = "se";
1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&qup_i2c10_default>;
1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 status = "disabled";
1148 };
1150 spi10: spi@a88000 {
1151 compatible = "qcom,geni-spi";
1152 reg = <0 0x00a88000 0 0x4000>;
1153 clock-names = "se";
1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&qup_spi10_default>;
1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 status = "disabled";
1161 };
1163 uart10: serial@a88000 {
1164 compatible = "qcom,geni-uart";
1165 reg = <0 0x00a88000 0 0x4000>;
1166 clock-names = "se";
1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_uart10_default>;
1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1171 status = "disabled";
1172 };
1174 i2c11: i2c@a8c000 {
1175 compatible = "qcom,geni-i2c";
1176 reg = <0 0x00a8c000 0 0x4000>;
1177 clock-names = "se";
1178 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&qup_i2c11_default>;
1181 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1184 status = "disabled";
1185 };
1187 spi11: spi@a8c000 {
1188 compatible = "qcom,geni-spi";
1189 reg = <0 0x00a8c000 0 0x4000>;
1190 clock-names = "se";
1191 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&qup_spi11_default>;
1194 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 status = "disabled";
1198 };
1200 uart11: serial@a8c000 {
1201 compatible = "qcom,geni-uart";
1202 reg = <0 0x00a8c000 0 0x4000>;
1203 clock-names = "se";
1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1205 pinctrl-names = "default";
1206 pinctrl-0 = <&qup_uart11_default>;
1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1208 status = "disabled";
1209 };
1211 i2c12: i2c@a90000 {
1212 compatible = "qcom,geni-i2c";
1213 reg = <0 0x00a90000 0 0x4000>;
1214 clock-names = "se";
1215 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_i2c12_default>;
1218 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 status = "disabled";
1222 };
1224 spi12: spi@a90000 {
1225 compatible = "qcom,geni-spi";
1226 reg = <0 0x00a90000 0 0x4000>;
1227 clock-names = "se";
1228 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_spi12_default>;
1231 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1232 #address-cells = <1>;
1233 #size-cells = <0>;
1234 status = "disabled";
1235 };
1237 uart12: serial@a90000 {
1238 compatible = "qcom,geni-uart";
1239 reg = <0 0x00a90000 0 0x4000>;
1240 clock-names = "se";
1241 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&qup_uart12_default>;
1244 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1245 status = "disabled";
1246 };
1248 i2c13: i2c@a94000 {
1249 compatible = "qcom,geni-i2c";
1250 reg = <0 0x00a94000 0 0x4000>;
1251 clock-names = "se";
1252 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_i2c13_default>;
1255 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1258 status = "disabled";
1259 };
1261 spi13: spi@a94000 {
1262 compatible = "qcom,geni-spi";
1263 reg = <0 0x00a94000 0 0x4000>;
1264 clock-names = "se";
1265 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_spi13_default>;
1268 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1271 status = "disabled";
1272 };
1274 uart13: serial@a94000 {
1275 compatible = "qcom,geni-uart";
1276 reg = <0 0x00a94000 0 0x4000>;
1277 clock-names = "se";
1278 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&qup_uart13_default>;
1281 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1282 status = "disabled";
1283 };
1285 i2c14: i2c@a98000 {
1286 compatible = "qcom,geni-i2c";
1287 reg = <0 0x00a98000 0 0x4000>;
1288 clock-names = "se";
1289 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&qup_i2c14_default>;
1292 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1295 status = "disabled";
1296 };
1298 spi14: spi@a98000 {
1299 compatible = "qcom,geni-spi";
1300 reg = <0 0x00a98000 0 0x4000>;
1301 clock-names = "se";
1302 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_spi14_default>;
1305 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 status = "disabled";
1309 };
1311 uart14: serial@a98000 {
1312 compatible = "qcom,geni-uart";
1313 reg = <0 0x00a98000 0 0x4000>;
1314 clock-names = "se";
1315 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&qup_uart14_default>;
1318 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1319 status = "disabled";
1320 };
1322 i2c15: i2c@a9c000 {
1323 compatible = "qcom,geni-i2c";
1324 reg = <0 0x00a9c000 0 0x4000>;
1325 clock-names = "se";
1326 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c15_default>;
1329 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332 status = "disabled";
1333 };
1335 spi15: spi@a9c000 {
1336 compatible = "qcom,geni-spi";
1337 reg = <0 0x00a9c000 0 0x4000>;
1338 clock-names = "se";
1339 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&qup_spi15_default>;
1342 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1345 status = "disabled";
1346 };
1348 uart15: serial@a9c000 {
1349 compatible = "qcom,geni-uart";
1350 reg = <0 0x00a9c000 0 0x4000>;
1351 clock-names = "se";
1352 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_uart15_default>;
1355 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1356 status = "disabled";
1357 };
1358 };
1360 system-cache-controller@1100000 {
1361 compatible = "qcom,sdm845-llcc";
1362 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1363 reg-names = "llcc_base", "llcc_broadcast_base";
1364 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1365 };
1367 ufs_mem_hc: ufshc@1d84000 {
1368 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1369 "jedec,ufs-2.0";
1370 reg = <0 0x01d84000 0 0x2500>;
1371 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1372 phys = <&ufs_mem_phy_lanes>;
1373 phy-names = "ufsphy";
1374 lanes-per-direction = <2>;
1375 power-domains = <&gcc UFS_PHY_GDSC>;
1376 #reset-cells = <1>;
1378 iommus = <&apps_smmu 0x100 0xf>;
1380 clock-names =
1381 "core_clk",
1382 "bus_aggr_clk",
1383 "iface_clk",
1384 "core_clk_unipro",
1385 "ref_clk",
1386 "tx_lane0_sync_clk",
1387 "rx_lane0_sync_clk",
1388 "rx_lane1_sync_clk";
1389 clocks =
1390 <&gcc GCC_UFS_PHY_AXI_CLK>,
1391 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1392 <&gcc GCC_UFS_PHY_AHB_CLK>,
1393 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1394 <&rpmhcc RPMH_CXO_CLK>,
1395 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1396 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1397 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1398 freq-table-hz =
1399 <50000000 200000000>,
1400 <0 0>,
1401 <0 0>,
1402 <37500000 150000000>,
1403 <0 0>,
1404 <0 0>,
1405 <0 0>,
1406 <0 0>;
1408 status = "disabled";
1409 };
1411 ufs_mem_phy: phy@1d87000 {
1412 compatible = "qcom,sdm845-qmp-ufs-phy";
1413 reg = <0 0x01d87000 0 0x18c>;
1414 #address-cells = <2>;
1415 #size-cells = <2>;
1416 ranges;
1417 clock-names = "ref",
1418 "ref_aux";
1419 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1420 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1422 resets = <&ufs_mem_hc 0>;
1423 reset-names = "ufsphy";
1424 status = "disabled";
1426 ufs_mem_phy_lanes: lanes@1d87400 {
1427 reg = <0 0x01d87400 0 0x108>,
1428 <0 0x01d87600 0 0x1e0>,
1429 <0 0x01d87c00 0 0x1dc>,
1430 <0 0x01d87800 0 0x108>,
1431 <0 0x01d87a00 0 0x1e0>;
1432 #phy-cells = <0>;
1433 };
1434 };
1436 tcsr_mutex_regs: syscon@1f40000 {
1437 compatible = "syscon";
1438 reg = <0 0x01f40000 0 0x40000>;
1439 };
1441 tlmm: pinctrl@3400000 {
1442 compatible = "qcom,sdm845-pinctrl";
1443 reg = <0 0x03400000 0 0xc00000>;
1444 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1445 gpio-controller;
1446 #gpio-cells = <2>;
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1449 gpio-ranges = <&tlmm 0 0 150>;
1450 wakeup-parent = <&pdc_intc>;
1452 qspi_clk: qspi-clk {
1453 pinmux {
1454 pins = "gpio95";
1455 function = "qspi_clk";
1456 };
1457 };
1459 qspi_cs0: qspi-cs0 {
1460 pinmux {
1461 pins = "gpio90";
1462 function = "qspi_cs";
1463 };
1464 };
1466 qspi_cs1: qspi-cs1 {
1467 pinmux {
1468 pins = "gpio89";
1469 function = "qspi_cs";
1470 };
1471 };
1473 qspi_data01: qspi-data01 {
1474 pinmux-data {
1475 pins = "gpio91", "gpio92";
1476 function = "qspi_data";
1477 };
1478 };
1480 qspi_data12: qspi-data12 {
1481 pinmux-data {
1482 pins = "gpio93", "gpio94";
1483 function = "qspi_data";
1484 };
1485 };
1487 qup_i2c0_default: qup-i2c0-default {
1488 pinmux {
1489 pins = "gpio0", "gpio1";
1490 function = "qup0";
1491 };
1492 };
1494 qup_i2c1_default: qup-i2c1-default {
1495 pinmux {
1496 pins = "gpio17", "gpio18";
1497 function = "qup1";
1498 };
1499 };
1501 qup_i2c2_default: qup-i2c2-default {
1502 pinmux {
1503 pins = "gpio27", "gpio28";
1504 function = "qup2";
1505 };
1506 };
1508 qup_i2c3_default: qup-i2c3-default {
1509 pinmux {
1510 pins = "gpio41", "gpio42";
1511 function = "qup3";
1512 };
1513 };
1515 qup_i2c4_default: qup-i2c4-default {
1516 pinmux {
1517 pins = "gpio89", "gpio90";
1518 function = "qup4";
1519 };
1520 };
1522 qup_i2c5_default: qup-i2c5-default {
1523 pinmux {
1524 pins = "gpio85", "gpio86";
1525 function = "qup5";
1526 };
1527 };
1529 qup_i2c6_default: qup-i2c6-default {
1530 pinmux {
1531 pins = "gpio45", "gpio46";
1532 function = "qup6";
1533 };
1534 };
1536 qup_i2c7_default: qup-i2c7-default {
1537 pinmux {
1538 pins = "gpio93", "gpio94";
1539 function = "qup7";
1540 };
1541 };
1543 qup_i2c8_default: qup-i2c8-default {
1544 pinmux {
1545 pins = "gpio65", "gpio66";
1546 function = "qup8";
1547 };
1548 };
1550 qup_i2c9_default: qup-i2c9-default {
1551 pinmux {
1552 pins = "gpio6", "gpio7";
1553 function = "qup9";
1554 };
1555 };
1557 qup_i2c10_default: qup-i2c10-default {
1558 pinmux {
1559 pins = "gpio55", "gpio56";
1560 function = "qup10";
1561 };
1562 };
1564 qup_i2c11_default: qup-i2c11-default {
1565 pinmux {
1566 pins = "gpio31", "gpio32";
1567 function = "qup11";
1568 };
1569 };
1571 qup_i2c12_default: qup-i2c12-default {
1572 pinmux {
1573 pins = "gpio49", "gpio50";
1574 function = "qup12";
1575 };
1576 };
1578 qup_i2c13_default: qup-i2c13-default {
1579 pinmux {
1580 pins = "gpio105", "gpio106";
1581 function = "qup13";
1582 };
1583 };
1585 qup_i2c14_default: qup-i2c14-default {
1586 pinmux {
1587 pins = "gpio33", "gpio34";
1588 function = "qup14";
1589 };
1590 };
1592 qup_i2c15_default: qup-i2c15-default {
1593 pinmux {
1594 pins = "gpio81", "gpio82";
1595 function = "qup15";
1596 };
1597 };
1599 qup_spi0_default: qup-spi0-default {
1600 pinmux {
1601 pins = "gpio0", "gpio1",
1602 "gpio2", "gpio3";
1603 function = "qup0";
1604 };
1605 };
1607 qup_spi1_default: qup-spi1-default {
1608 pinmux {
1609 pins = "gpio17", "gpio18",
1610 "gpio19", "gpio20";
1611 function = "qup1";
1612 };
1613 };
1615 qup_spi2_default: qup-spi2-default {
1616 pinmux {
1617 pins = "gpio27", "gpio28",
1618 "gpio29", "gpio30";
1619 function = "qup2";
1620 };
1621 };
1623 qup_spi3_default: qup-spi3-default {
1624 pinmux {
1625 pins = "gpio41", "gpio42",
1626 "gpio43", "gpio44";
1627 function = "qup3";
1628 };
1629 };
1631 qup_spi4_default: qup-spi4-default {
1632 pinmux {
1633 pins = "gpio89", "gpio90",
1634 "gpio91", "gpio92";
1635 function = "qup4";
1636 };
1637 };
1639 qup_spi5_default: qup-spi5-default {
1640 pinmux {
1641 pins = "gpio85", "gpio86",
1642 "gpio87", "gpio88";
1643 function = "qup5";
1644 };
1645 };
1647 qup_spi6_default: qup-spi6-default {
1648 pinmux {
1649 pins = "gpio45", "gpio46",
1650 "gpio47", "gpio48";
1651 function = "qup6";
1652 };
1653 };
1655 qup_spi7_default: qup-spi7-default {
1656 pinmux {
1657 pins = "gpio93", "gpio94",
1658 "gpio95", "gpio96";
1659 function = "qup7";
1660 };
1661 };
1663 qup_spi8_default: qup-spi8-default {
1664 pinmux {
1665 pins = "gpio65", "gpio66",
1666 "gpio67", "gpio68";
1667 function = "qup8";
1668 };
1669 };
1671 qup_spi9_default: qup-spi9-default {
1672 pinmux {
1673 pins = "gpio6", "gpio7",
1674 "gpio4", "gpio5";
1675 function = "qup9";
1676 };
1677 };
1679 qup_spi10_default: qup-spi10-default {
1680 pinmux {
1681 pins = "gpio55", "gpio56",
1682 "gpio53", "gpio54";
1683 function = "qup10";
1684 };
1685 };
1687 qup_spi11_default: qup-spi11-default {
1688 pinmux {
1689 pins = "gpio31", "gpio32",
1690 "gpio33", "gpio34";
1691 function = "qup11";
1692 };
1693 };
1695 qup_spi12_default: qup-spi12-default {
1696 pinmux {
1697 pins = "gpio49", "gpio50",
1698 "gpio51", "gpio52";
1699 function = "qup12";
1700 };
1701 };
1703 qup_spi13_default: qup-spi13-default {
1704 pinmux {
1705 pins = "gpio105", "gpio106",
1706 "gpio107", "gpio108";
1707 function = "qup13";
1708 };
1709 };
1711 qup_spi14_default: qup-spi14-default {
1712 pinmux {
1713 pins = "gpio33", "gpio34",
1714 "gpio31", "gpio32";
1715 function = "qup14";
1716 };
1717 };
1719 qup_spi15_default: qup-spi15-default {
1720 pinmux {
1721 pins = "gpio81", "gpio82",
1722 "gpio83", "gpio84";
1723 function = "qup15";
1724 };
1725 };
1727 qup_uart0_default: qup-uart0-default {
1728 pinmux {
1729 pins = "gpio2", "gpio3";
1730 function = "qup0";
1731 };
1732 };
1734 qup_uart1_default: qup-uart1-default {
1735 pinmux {
1736 pins = "gpio19", "gpio20";
1737 function = "qup1";
1738 };
1739 };
1741 qup_uart2_default: qup-uart2-default {
1742 pinmux {
1743 pins = "gpio29", "gpio30";
1744 function = "qup2";
1745 };
1746 };
1748 qup_uart3_default: qup-uart3-default {
1749 pinmux {
1750 pins = "gpio43", "gpio44";
1751 function = "qup3";
1752 };
1753 };
1755 qup_uart4_default: qup-uart4-default {
1756 pinmux {
1757 pins = "gpio91", "gpio92";
1758 function = "qup4";
1759 };
1760 };
1762 qup_uart5_default: qup-uart5-default {
1763 pinmux {
1764 pins = "gpio87", "gpio88";
1765 function = "qup5";
1766 };
1767 };
1769 qup_uart6_default: qup-uart6-default {
1770 pinmux {
1771 pins = "gpio47", "gpio48";
1772 function = "qup6";
1773 };
1774 };
1776 qup_uart7_default: qup-uart7-default {
1777 pinmux {
1778 pins = "gpio95", "gpio96";
1779 function = "qup7";
1780 };
1781 };
1783 qup_uart8_default: qup-uart8-default {
1784 pinmux {
1785 pins = "gpio67", "gpio68";
1786 function = "qup8";
1787 };
1788 };
1790 qup_uart9_default: qup-uart9-default {
1791 pinmux {
1792 pins = "gpio4", "gpio5";
1793 function = "qup9";
1794 };
1795 };
1797 qup_uart10_default: qup-uart10-default {
1798 pinmux {
1799 pins = "gpio53", "gpio54";
1800 function = "qup10";
1801 };
1802 };
1804 qup_uart11_default: qup-uart11-default {
1805 pinmux {
1806 pins = "gpio33", "gpio34";
1807 function = "qup11";
1808 };
1809 };
1811 qup_uart12_default: qup-uart12-default {
1812 pinmux {
1813 pins = "gpio51", "gpio52";
1814 function = "qup12";
1815 };
1816 };
1818 qup_uart13_default: qup-uart13-default {
1819 pinmux {
1820 pins = "gpio107", "gpio108";
1821 function = "qup13";
1822 };
1823 };
1825 qup_uart14_default: qup-uart14-default {
1826 pinmux {
1827 pins = "gpio31", "gpio32";
1828 function = "qup14";
1829 };
1830 };
1832 qup_uart15_default: qup-uart15-default {
1833 pinmux {
1834 pins = "gpio83", "gpio84";
1835 function = "qup15";
1836 };
1837 };
1838 };
1840 mss_pil: remoteproc@4080000 {
1841 compatible = "qcom,sdm845-mss-pil";
1842 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
1843 reg-names = "qdsp6", "rmb";
1845 interrupts-extended =
1846 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1847 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1848 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1849 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1850 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1851 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1852 interrupt-names = "wdog", "fatal", "ready",
1853 "handover", "stop-ack",
1854 "shutdown-ack";
1856 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1857 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1858 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1859 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1860 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1861 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1862 <&gcc GCC_PRNG_AHB_CLK>,
1863 <&rpmhcc RPMH_CXO_CLK>;
1864 clock-names = "iface", "bus", "mem", "gpll0_mss",
1865 "snoc_axi", "mnoc_axi", "prng", "xo";
1867 qcom,smem-states = <&modem_smp2p_out 0>;
1868 qcom,smem-state-names = "stop";
1870 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1871 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1872 reset-names = "mss_restart", "pdc_reset";
1874 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1876 power-domains = <&aoss_qmp 2>,
1877 <&rpmhpd SDM845_CX>,
1878 <&rpmhpd SDM845_MX>,
1879 <&rpmhpd SDM845_MSS>;
1880 power-domain-names = "load_state", "cx", "mx", "mss";
1882 mba {
1883 memory-region = <&mba_region>;
1884 };
1886 mpss {
1887 memory-region = <&mpss_region>;
1888 };
1890 glink-edge {
1891 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1892 label = "modem";
1893 qcom,remote-pid = <1>;
1894 mboxes = <&apss_shared 12>;
1895 };
1896 };
1898 gpucc: clock-controller@5090000 {
1899 compatible = "qcom,sdm845-gpucc";
1900 reg = <0 0x05090000 0 0x9000>;
1901 #clock-cells = <1>;
1902 #reset-cells = <1>;
1903 #power-domain-cells = <1>;
1904 clocks = <&rpmhcc RPMH_CXO_CLK>;
1905 clock-names = "xo";
1906 };
1908 stm@6002000 {
1909 compatible = "arm,coresight-stm", "arm,primecell";
1910 reg = <0 0x06002000 0 0x1000>,
1911 <0 0x16280000 0 0x180000>;
1912 reg-names = "stm-base", "stm-stimulus-base";
1914 clocks = <&aoss_qmp>;
1915 clock-names = "apb_pclk";
1917 out-ports {
1918 port {
1919 stm_out: endpoint {
1920 remote-endpoint =
1921 <&funnel0_in7>;
1922 };
1923 };
1924 };
1925 };
1927 funnel@6041000 {
1928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1929 reg = <0 0x06041000 0 0x1000>;
1931 clocks = <&aoss_qmp>;
1932 clock-names = "apb_pclk";
1934 out-ports {
1935 port {
1936 funnel0_out: endpoint {
1937 remote-endpoint =
1938 <&merge_funnel_in0>;
1939 };
1940 };
1941 };
1943 in-ports {
1944 #address-cells = <1>;
1945 #size-cells = <0>;
1947 port@7 {
1948 reg = <7>;
1949 funnel0_in7: endpoint {
1950 remote-endpoint = <&stm_out>;
1951 };
1952 };
1953 };
1954 };
1956 funnel@6043000 {
1957 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1958 reg = <0 0x06043000 0 0x1000>;
1960 clocks = <&aoss_qmp>;
1961 clock-names = "apb_pclk";
1963 out-ports {
1964 port {
1965 funnel2_out: endpoint {
1966 remote-endpoint =
1967 <&merge_funnel_in2>;
1968 };
1969 };
1970 };
1972 in-ports {
1973 #address-cells = <1>;
1974 #size-cells = <0>;
1976 port@5 {
1977 reg = <5>;
1978 funnel2_in5: endpoint {
1979 remote-endpoint =
1980 <&apss_merge_funnel_out>;
1981 };
1982 };
1983 };
1984 };
1986 funnel@6045000 {
1987 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1988 reg = <0 0x06045000 0 0x1000>;
1990 clocks = <&aoss_qmp>;
1991 clock-names = "apb_pclk";
1993 out-ports {
1994 port {
1995 merge_funnel_out: endpoint {
1996 remote-endpoint = <&etf_in>;
1997 };
1998 };
1999 };
2001 in-ports {
2002 #address-cells = <1>;
2003 #size-cells = <0>;
2005 port@0 {
2006 reg = <0>;
2007 merge_funnel_in0: endpoint {
2008 remote-endpoint =
2009 <&funnel0_out>;
2010 };
2011 };
2013 port@2 {
2014 reg = <2>;
2015 merge_funnel_in2: endpoint {
2016 remote-endpoint =
2017 <&funnel2_out>;
2018 };
2019 };
2020 };
2021 };
2023 replicator@6046000 {
2024 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2025 reg = <0 0x06046000 0 0x1000>;
2027 clocks = <&aoss_qmp>;
2028 clock-names = "apb_pclk";
2030 out-ports {
2031 port {
2032 replicator_out: endpoint {
2033 remote-endpoint = <&etr_in>;
2034 };
2035 };
2036 };
2038 in-ports {
2039 port {
2040 replicator_in: endpoint {
2041 remote-endpoint = <&etf_out>;
2042 };
2043 };
2044 };
2045 };
2047 etf@6047000 {
2048 compatible = "arm,coresight-tmc", "arm,primecell";
2049 reg = <0 0x06047000 0 0x1000>;
2051 clocks = <&aoss_qmp>;
2052 clock-names = "apb_pclk";
2054 out-ports {
2055 port {
2056 etf_out: endpoint {
2057 remote-endpoint =
2058 <&replicator_in>;
2059 };
2060 };
2061 };
2063 in-ports {
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2067 port@1 {
2068 reg = <1>;
2069 etf_in: endpoint {
2070 remote-endpoint =
2071 <&merge_funnel_out>;
2072 };
2073 };
2074 };
2075 };
2077 etr@6048000 {
2078 compatible = "arm,coresight-tmc", "arm,primecell";
2079 reg = <0 0x06048000 0 0x1000>;
2081 clocks = <&aoss_qmp>;
2082 clock-names = "apb_pclk";
2083 arm,scatter-gather;
2085 in-ports {
2086 port {
2087 etr_in: endpoint {
2088 remote-endpoint =
2089 <&replicator_out>;
2090 };
2091 };
2092 };
2093 };
2095 etm@7040000 {
2096 compatible = "arm,coresight-etm4x", "arm,primecell";
2097 reg = <0 0x07040000 0 0x1000>;
2099 cpu = <&CPU0>;
2101 clocks = <&aoss_qmp>;
2102 clock-names = "apb_pclk";
2104 out-ports {
2105 port {
2106 etm0_out: endpoint {
2107 remote-endpoint =
2108 <&apss_funnel_in0>;
2109 };
2110 };
2111 };
2112 };
2114 etm@7140000 {
2115 compatible = "arm,coresight-etm4x", "arm,primecell";
2116 reg = <0 0x07140000 0 0x1000>;
2118 cpu = <&CPU1>;
2120 clocks = <&aoss_qmp>;
2121 clock-names = "apb_pclk";
2123 out-ports {
2124 port {
2125 etm1_out: endpoint {
2126 remote-endpoint =
2127 <&apss_funnel_in1>;
2128 };
2129 };
2130 };
2131 };
2133 etm@7240000 {
2134 compatible = "arm,coresight-etm4x", "arm,primecell";
2135 reg = <0 0x07240000 0 0x1000>;
2137 cpu = <&CPU2>;
2139 clocks = <&aoss_qmp>;
2140 clock-names = "apb_pclk";
2142 out-ports {
2143 port {
2144 etm2_out: endpoint {
2145 remote-endpoint =
2146 <&apss_funnel_in2>;
2147 };
2148 };
2149 };
2150 };
2152 etm@7340000 {
2153 compatible = "arm,coresight-etm4x", "arm,primecell";
2154 reg = <0 0x07340000 0 0x1000>;
2156 cpu = <&CPU3>;
2158 clocks = <&aoss_qmp>;
2159 clock-names = "apb_pclk";
2161 out-ports {
2162 port {
2163 etm3_out: endpoint {
2164 remote-endpoint =
2165 <&apss_funnel_in3>;
2166 };
2167 };
2168 };
2169 };
2171 etm@7440000 {
2172 compatible = "arm,coresight-etm4x", "arm,primecell";
2173 reg = <0 0x07440000 0 0x1000>;
2175 cpu = <&CPU4>;
2177 clocks = <&aoss_qmp>;
2178 clock-names = "apb_pclk";
2180 out-ports {
2181 port {
2182 etm4_out: endpoint {
2183 remote-endpoint =
2184 <&apss_funnel_in4>;
2185 };
2186 };
2187 };
2188 };
2190 etm@7540000 {
2191 compatible = "arm,coresight-etm4x", "arm,primecell";
2192 reg = <0 0x07540000 0 0x1000>;
2194 cpu = <&CPU5>;
2196 clocks = <&aoss_qmp>;
2197 clock-names = "apb_pclk";
2199 out-ports {
2200 port {
2201 etm5_out: endpoint {
2202 remote-endpoint =
2203 <&apss_funnel_in5>;
2204 };
2205 };
2206 };
2207 };
2209 etm@7640000 {
2210 compatible = "arm,coresight-etm4x", "arm,primecell";
2211 reg = <0 0x07640000 0 0x1000>;
2213 cpu = <&CPU6>;
2215 clocks = <&aoss_qmp>;
2216 clock-names = "apb_pclk";
2218 out-ports {
2219 port {
2220 etm6_out: endpoint {
2221 remote-endpoint =
2222 <&apss_funnel_in6>;
2223 };
2224 };
2225 };
2226 };
2228 etm@7740000 {
2229 compatible = "arm,coresight-etm4x", "arm,primecell";
2230 reg = <0 0x07740000 0 0x1000>;
2232 cpu = <&CPU7>;
2234 clocks = <&aoss_qmp>;
2235 clock-names = "apb_pclk";
2237 out-ports {
2238 port {
2239 etm7_out: endpoint {
2240 remote-endpoint =
2241 <&apss_funnel_in7>;
2242 };
2243 };
2244 };
2245 };
2247 funnel@7800000 { /* APSS Funnel */
2248 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2249 reg = <0 0x07800000 0 0x1000>;
2251 clocks = <&aoss_qmp>;
2252 clock-names = "apb_pclk";
2254 out-ports {
2255 port {
2256 apss_funnel_out: endpoint {
2257 remote-endpoint =
2258 <&apss_merge_funnel_in>;
2259 };
2260 };
2261 };
2263 in-ports {
2264 #address-cells = <1>;
2265 #size-cells = <0>;
2267 port@0 {
2268 reg = <0>;
2269 apss_funnel_in0: endpoint {
2270 remote-endpoint =
2271 <&etm0_out>;
2272 };
2273 };
2275 port@1 {
2276 reg = <1>;
2277 apss_funnel_in1: endpoint {
2278 remote-endpoint =
2279 <&etm1_out>;
2280 };
2281 };
2283 port@2 {
2284 reg = <2>;
2285 apss_funnel_in2: endpoint {
2286 remote-endpoint =
2287 <&etm2_out>;
2288 };
2289 };
2291 port@3 {
2292 reg = <3>;
2293 apss_funnel_in3: endpoint {
2294 remote-endpoint =
2295 <&etm3_out>;
2296 };
2297 };
2299 port@4 {
2300 reg = <4>;
2301 apss_funnel_in4: endpoint {
2302 remote-endpoint =
2303 <&etm4_out>;
2304 };
2305 };
2307 port@5 {
2308 reg = <5>;
2309 apss_funnel_in5: endpoint {
2310 remote-endpoint =
2311 <&etm5_out>;
2312 };
2313 };
2315 port@6 {
2316 reg = <6>;
2317 apss_funnel_in6: endpoint {
2318 remote-endpoint =
2319 <&etm6_out>;
2320 };
2321 };
2323 port@7 {
2324 reg = <7>;
2325 apss_funnel_in7: endpoint {
2326 remote-endpoint =
2327 <&etm7_out>;
2328 };
2329 };
2330 };
2331 };
2333 funnel@7810000 {
2334 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2335 reg = <0 0x07810000 0 0x1000>;
2337 clocks = <&aoss_qmp>;
2338 clock-names = "apb_pclk";
2340 out-ports {
2341 port {
2342 apss_merge_funnel_out: endpoint {
2343 remote-endpoint =
2344 <&funnel2_in5>;
2345 };
2346 };
2347 };
2349 in-ports {
2350 port {
2351 apss_merge_funnel_in: endpoint {
2352 remote-endpoint =
2353 <&apss_funnel_out>;
2354 };
2355 };
2356 };
2357 };
2359 sdhc_2: sdhci@8804000 {
2360 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2361 reg = <0 0x08804000 0 0x1000>;
2363 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2365 interrupt-names = "hc_irq", "pwr_irq";
2367 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2368 <&gcc GCC_SDCC2_APPS_CLK>;
2369 clock-names = "iface", "core";
2370 iommus = <&apps_smmu 0xa0 0xf>;
2372 status = "disabled";
2373 };
2375 qspi: spi@88df000 {
2376 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2377 reg = <0 0x088df000 0 0x600>;
2378 #address-cells = <1>;
2379 #size-cells = <0>;
2380 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2381 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2382 <&gcc GCC_QSPI_CORE_CLK>;
2383 clock-names = "iface", "core";
2384 status = "disabled";
2385 };
2387 usb_1_hsphy: phy@88e2000 {
2388 compatible = "qcom,sdm845-qusb2-phy";
2389 reg = <0 0x088e2000 0 0x400>;
2390 status = "disabled";
2391 #phy-cells = <0>;
2393 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2394 <&rpmhcc RPMH_CXO_CLK>;
2395 clock-names = "cfg_ahb", "ref";
2397 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2399 nvmem-cells = <&qusb2p_hstx_trim>;
2400 };
2402 usb_2_hsphy: phy@88e3000 {
2403 compatible = "qcom,sdm845-qusb2-phy";
2404 reg = <0 0x088e3000 0 0x400>;
2405 status = "disabled";
2406 #phy-cells = <0>;
2408 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2409 <&rpmhcc RPMH_CXO_CLK>;
2410 clock-names = "cfg_ahb", "ref";
2412 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2414 nvmem-cells = <&qusb2s_hstx_trim>;
2415 };
2417 usb_1_qmpphy: phy@88e9000 {
2418 compatible = "qcom,sdm845-qmp-usb3-phy";
2419 reg = <0 0x088e9000 0 0x18c>,
2420 <0 0x088e8000 0 0x10>;
2421 reg-names = "reg-base", "dp_com";
2422 status = "disabled";
2423 #clock-cells = <1>;
2424 #address-cells = <2>;
2425 #size-cells = <2>;
2426 ranges;
2428 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2429 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2430 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2431 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2432 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2434 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2435 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2436 reset-names = "phy", "common";
2438 usb_1_ssphy: lanes@88e9200 {
2439 reg = <0 0x088e9200 0 0x128>,
2440 <0 0x088e9400 0 0x200>,
2441 <0 0x088e9c00 0 0x218>,
2442 <0 0x088e9600 0 0x128>,
2443 <0 0x088e9800 0 0x200>,
2444 <0 0x088e9a00 0 0x100>;
2445 #phy-cells = <0>;
2446 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2447 clock-names = "pipe0";
2448 clock-output-names = "usb3_phy_pipe_clk_src";
2449 };
2450 };
2452 usb_2_qmpphy: phy@88eb000 {
2453 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
2454 reg = <0 0x088eb000 0 0x18c>;
2455 status = "disabled";
2456 #clock-cells = <1>;
2457 #address-cells = <2>;
2458 #size-cells = <2>;
2459 ranges;
2461 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2462 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2463 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2464 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2465 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2467 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2468 <&gcc GCC_USB3_PHY_SEC_BCR>;
2469 reset-names = "phy", "common";
2471 usb_2_ssphy: lane@88eb200 {
2472 reg = <0 0x088eb200 0 0x128>,
2473 <0 0x088eb400 0 0x1fc>,
2474 <0 0x088eb800 0 0x218>,
2475 <0 0x088eb600 0 0x70>;
2476 #phy-cells = <0>;
2477 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2478 clock-names = "pipe0";
2479 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2480 };
2481 };
2483 usb_1: usb@a6f8800 {
2484 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2485 reg = <0 0x0a6f8800 0 0x400>;
2486 status = "disabled";
2487 #address-cells = <2>;
2488 #size-cells = <2>;
2489 ranges;
2490 dma-ranges;
2492 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2493 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2494 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2495 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2496 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2497 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2498 "sleep";
2500 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2501 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2502 assigned-clock-rates = <19200000>, <150000000>;
2504 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2505 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2506 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2507 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2508 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2509 "dm_hs_phy_irq", "dp_hs_phy_irq";
2511 power-domains = <&gcc USB30_PRIM_GDSC>;
2513 resets = <&gcc GCC_USB30_PRIM_BCR>;
2515 usb_1_dwc3: dwc3@a600000 {
2516 compatible = "snps,dwc3";
2517 reg = <0 0x0a600000 0 0xcd00>;
2518 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2519 iommus = <&apps_smmu 0x740 0>;
2520 snps,dis_u2_susphy_quirk;
2521 snps,dis_enblslpm_quirk;
2522 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2523 phy-names = "usb2-phy", "usb3-phy";
2524 };
2525 };
2527 usb_2: usb@a8f8800 {
2528 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2529 reg = <0 0x0a8f8800 0 0x400>;
2530 status = "disabled";
2531 #address-cells = <2>;
2532 #size-cells = <2>;
2533 ranges;
2534 dma-ranges;
2536 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2537 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2538 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2539 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2540 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
2541 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2542 "sleep";
2544 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2545 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2546 assigned-clock-rates = <19200000>, <150000000>;
2548 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2549 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2550 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
2551 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
2552 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2553 "dm_hs_phy_irq", "dp_hs_phy_irq";
2555 power-domains = <&gcc USB30_SEC_GDSC>;
2557 resets = <&gcc GCC_USB30_SEC_BCR>;
2559 usb_2_dwc3: dwc3@a800000 {
2560 compatible = "snps,dwc3";
2561 reg = <0 0x0a800000 0 0xcd00>;
2562 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2563 iommus = <&apps_smmu 0x760 0>;
2564 snps,dis_u2_susphy_quirk;
2565 snps,dis_enblslpm_quirk;
2566 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2567 phy-names = "usb2-phy", "usb3-phy";
2568 };
2569 };
2571 video-codec@aa00000 {
2572 compatible = "qcom,sdm845-venus";
2573 reg = <0 0x0aa00000 0 0xff000>;
2574 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2575 power-domains = <&videocc VENUS_GDSC>;
2576 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2577 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2578 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2579 clock-names = "core", "iface", "bus";
2580 iommus = <&apps_smmu 0x10a0 0x8>,
2581 <&apps_smmu 0x10b0 0x0>;
2582 memory-region = <&venus_mem>;
2584 video-core0 {
2585 compatible = "venus-decoder";
2586 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2587 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2588 clock-names = "core", "bus";
2589 power-domains = <&videocc VCODEC0_GDSC>;
2590 };
2592 video-core1 {
2593 compatible = "venus-encoder";
2594 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
2595 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
2596 clock-names = "core", "bus";
2597 power-domains = <&videocc VCODEC1_GDSC>;
2598 };
2599 };
2601 videocc: clock-controller@ab00000 {
2602 compatible = "qcom,sdm845-videocc";
2603 reg = <0 0x0ab00000 0 0x10000>;
2604 #clock-cells = <1>;
2605 #power-domain-cells = <1>;
2606 #reset-cells = <1>;
2607 };
2609 mdss: mdss@ae00000 {
2610 compatible = "qcom,sdm845-mdss";
2611 reg = <0 0x0ae00000 0 0x1000>;
2612 reg-names = "mdss";
2614 power-domains = <&dispcc MDSS_GDSC>;
2616 clocks = <&gcc GCC_DISP_AHB_CLK>,
2617 <&gcc GCC_DISP_AXI_CLK>,
2618 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2619 clock-names = "iface", "bus", "core";
2621 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2622 assigned-clock-rates = <300000000>;
2624 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2625 interrupt-controller;
2626 #interrupt-cells = <1>;
2628 iommus = <&apps_smmu 0x880 0x8>,
2629 <&apps_smmu 0xc80 0x8>;
2631 status = "disabled";
2633 #address-cells = <2>;
2634 #size-cells = <2>;
2635 ranges;
2637 mdss_mdp: mdp@ae01000 {
2638 compatible = "qcom,sdm845-dpu";
2639 reg = <0 0x0ae01000 0 0x8f000>,
2640 <0 0x0aeb0000 0 0x2008>;
2641 reg-names = "mdp", "vbif";
2643 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2644 <&dispcc DISP_CC_MDSS_AXI_CLK>,
2645 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2646 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2647 clock-names = "iface", "bus", "core", "vsync";
2649 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2650 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2651 assigned-clock-rates = <300000000>,
2652 <19200000>;
2654 interrupt-parent = <&mdss>;
2655 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2657 status = "disabled";
2659 ports {
2660 #address-cells = <1>;
2661 #size-cells = <0>;
2663 port@0 {
2664 reg = <0>;
2665 dpu_intf1_out: endpoint {
2666 remote-endpoint = <&dsi0_in>;
2667 };
2668 };
2670 port@1 {
2671 reg = <1>;
2672 dpu_intf2_out: endpoint {
2673 remote-endpoint = <&dsi1_in>;
2674 };
2675 };
2676 };
2677 };
2679 dsi0: dsi@ae94000 {
2680 compatible = "qcom,mdss-dsi-ctrl";
2681 reg = <0 0x0ae94000 0 0x400>;
2682 reg-names = "dsi_ctrl";
2684 interrupt-parent = <&mdss>;
2685 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2687 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2688 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2689 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2690 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2691 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2692 <&dispcc DISP_CC_MDSS_AXI_CLK>;
2693 clock-names = "byte",
2694 "byte_intf",
2695 "pixel",
2696 "core",
2697 "iface",
2698 "bus";
2700 phys = <&dsi0_phy>;
2701 phy-names = "dsi";
2703 status = "disabled";
2705 ports {
2706 #address-cells = <1>;
2707 #size-cells = <0>;
2709 port@0 {
2710 reg = <0>;
2711 dsi0_in: endpoint {
2712 remote-endpoint = <&dpu_intf1_out>;
2713 };
2714 };
2716 port@1 {
2717 reg = <1>;
2718 dsi0_out: endpoint {
2719 };
2720 };
2721 };
2722 };
2724 dsi0_phy: dsi-phy@ae94400 {
2725 compatible = "qcom,dsi-phy-10nm";
2726 reg = <0 0x0ae94400 0 0x200>,
2727 <0 0x0ae94600 0 0x280>,
2728 <0 0x0ae94a00 0 0x1e0>;
2729 reg-names = "dsi_phy",
2730 "dsi_phy_lane",
2731 "dsi_pll";
2733 #clock-cells = <1>;
2734 #phy-cells = <0>;
2736 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2737 <&rpmhcc RPMH_CXO_CLK>;
2738 clock-names = "iface", "ref";
2740 status = "disabled";
2741 };
2743 dsi1: dsi@ae96000 {
2744 compatible = "qcom,mdss-dsi-ctrl";
2745 reg = <0 0x0ae96000 0 0x400>;
2746 reg-names = "dsi_ctrl";
2748 interrupt-parent = <&mdss>;
2749 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2752 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2753 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2754 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2755 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2756 <&dispcc DISP_CC_MDSS_AXI_CLK>;
2757 clock-names = "byte",
2758 "byte_intf",
2759 "pixel",
2760 "core",
2761 "iface",
2762 "bus";
2764 phys = <&dsi1_phy>;
2765 phy-names = "dsi";
2767 status = "disabled";
2769 ports {
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2773 port@0 {
2774 reg = <0>;
2775 dsi1_in: endpoint {
2776 remote-endpoint = <&dpu_intf2_out>;
2777 };
2778 };
2780 port@1 {
2781 reg = <1>;
2782 dsi1_out: endpoint {
2783 };
2784 };
2785 };
2786 };
2788 dsi1_phy: dsi-phy@ae96400 {
2789 compatible = "qcom,dsi-phy-10nm";
2790 reg = <0 0x0ae96400 0 0x200>,
2791 <0 0x0ae96600 0 0x280>,
2792 <0 0x0ae96a00 0 0x10e>;
2793 reg-names = "dsi_phy",
2794 "dsi_phy_lane",
2795 "dsi_pll";
2797 #clock-cells = <1>;
2798 #phy-cells = <0>;
2800 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2801 <&rpmhcc RPMH_CXO_CLK>;
2802 clock-names = "iface", "ref";
2804 status = "disabled";
2805 };
2806 };
2808 gpu@5000000 {
2809 compatible = "qcom,adreno-630.2", "qcom,adreno";
2810 #stream-id-cells = <16>;
2812 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
2813 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
2815 /*
2816 * Look ma, no clocks! The GPU clocks and power are
2817 * controlled entirely by the GMU
2818 */
2820 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2822 iommus = <&adreno_smmu 0>;
2824 operating-points-v2 = <&gpu_opp_table>;
2826 qcom,gmu = <&gmu>;
2828 zap_shader: zap-shader {
2829 memory-region = <&gpu_mem>;
2830 };
2832 gpu_opp_table: opp-table {
2833 compatible = "operating-points-v2";
2835 opp-710000000 {
2836 opp-hz = /bits/ 64 <710000000>;
2837 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2838 };
2840 opp-675000000 {
2841 opp-hz = /bits/ 64 <675000000>;
2842 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2843 };
2845 opp-596000000 {
2846 opp-hz = /bits/ 64 <596000000>;
2847 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2848 };
2850 opp-520000000 {
2851 opp-hz = /bits/ 64 <520000000>;
2852 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2853 };
2855 opp-414000000 {
2856 opp-hz = /bits/ 64 <414000000>;
2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2858 };
2860 opp-342000000 {
2861 opp-hz = /bits/ 64 <342000000>;
2862 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2863 };
2865 opp-257000000 {
2866 opp-hz = /bits/ 64 <257000000>;
2867 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2868 };
2869 };
2870 };
2872 adreno_smmu: iommu@5040000 {
2873 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
2874 reg = <0 0x5040000 0 0x10000>;
2875 #iommu-cells = <1>;
2876 #global-interrupts = <2>;
2877 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2878 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2880 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2881 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2882 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2883 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2884 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2885 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2886 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2887 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2888 <&gcc GCC_GPU_CFG_AHB_CLK>;
2889 clock-names = "bus", "iface";
2891 power-domains = <&gpucc GPU_CX_GDSC>;
2892 };
2894 gmu: gmu@506a000 {
2895 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
2897 reg = <0 0x506a000 0 0x30000>,
2898 <0 0xb280000 0 0x10000>,
2899 <0 0xb480000 0 0x10000>;
2900 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2902 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2903 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2904 interrupt-names = "hfi", "gmu";
2906 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2907 <&gpucc GPU_CC_CXO_CLK>,
2908 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2909 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2910 clock-names = "gmu", "cxo", "axi", "memnoc";
2912 power-domains = <&gpucc GPU_CX_GDSC>,
2913 <&gpucc GPU_GX_GDSC>;
2914 power-domain-names = "cx", "gx";
2916 iommus = <&adreno_smmu 5>;
2918 operating-points-v2 = <&gmu_opp_table>;
2920 gmu_opp_table: opp-table {
2921 compatible = "operating-points-v2";
2923 opp-400000000 {
2924 opp-hz = /bits/ 64 <400000000>;
2925 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2926 };
2928 opp-200000000 {
2929 opp-hz = /bits/ 64 <200000000>;
2930 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2931 };
2932 };
2933 };
2935 dispcc: clock-controller@af00000 {
2936 compatible = "qcom,sdm845-dispcc";
2937 reg = <0 0x0af00000 0 0x10000>;
2938 #clock-cells = <1>;
2939 #reset-cells = <1>;
2940 #power-domain-cells = <1>;
2941 };
2943 pdc_intc: interrupt-controller@b220000 {
2944 compatible = "qcom,sdm845-pdc", "qcom,pdc";
2945 reg = <0 0x0b220000 0 0x30000>;
2946 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
2947 #interrupt-cells = <2>;
2948 interrupt-parent = <&intc>;
2949 interrupt-controller;
2950 };
2952 pdc_reset: reset-controller@b2e0000 {
2953 compatible = "qcom,sdm845-pdc-global";
2954 reg = <0 0x0b2e0000 0 0x20000>;
2955 #reset-cells = <1>;
2956 };
2958 tsens0: thermal-sensor@c263000 {
2959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2960 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2961 <0 0x0c222000 0 0x1ff>; /* SROT */
2962 #qcom,sensors = <13>;
2963 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2964 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2965 interrupt-names = "uplow", "critical";
2966 #thermal-sensor-cells = <1>;
2967 };
2969 tsens1: thermal-sensor@c265000 {
2970 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2971 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2972 <0 0x0c223000 0 0x1ff>; /* SROT */
2973 #qcom,sensors = <8>;
2974 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2975 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2976 interrupt-names = "uplow", "critical";
2977 #thermal-sensor-cells = <1>;
2978 };
2980 aoss_reset: reset-controller@c2a0000 {
2981 compatible = "qcom,sdm845-aoss-cc";
2982 reg = <0 0x0c2a0000 0 0x31000>;
2983 #reset-cells = <1>;
2984 };
2986 aoss_qmp: qmp@c300000 {
2987 compatible = "qcom,sdm845-aoss-qmp";
2988 reg = <0 0x0c300000 0 0x100000>;
2989 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
2990 mboxes = <&apss_shared 0>;
2992 #clock-cells = <0>;
2993 #power-domain-cells = <1>;
2995 cx_cdev: cx {
2996 #cooling-cells = <2>;
2997 };
2999 ebi_cdev: ebi {
3000 #cooling-cells = <2>;
3001 };
3002 };
3004 spmi_bus: spmi@c440000 {
3005 compatible = "qcom,spmi-pmic-arb";
3006 reg = <0 0x0c440000 0 0x1100>,
3007 <0 0x0c600000 0 0x2000000>,
3008 <0 0x0e600000 0 0x100000>,
3009 <0 0x0e700000 0 0xa0000>,
3010 <0 0x0c40a000 0 0x26000>;
3011 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3012 interrupt-names = "periph_irq";
3013 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3014 qcom,ee = <0>;
3015 qcom,channel = <0>;
3016 #address-cells = <2>;
3017 #size-cells = <0>;
3018 interrupt-controller;
3019 #interrupt-cells = <4>;
3020 cell-index = <0>;
3021 };
3023 apps_smmu: iommu@15000000 {
3024 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3025 reg = <0 0x15000000 0 0x80000>;
3026 #iommu-cells = <2>;
3027 #global-interrupts = <1>;
3028 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3029 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3030 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3031 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3032 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3033 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3034 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3035 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3036 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3037 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3038 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3039 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3040 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3041 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3042 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3043 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3044 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3045 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3046 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3047 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3048 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3049 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3050 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3051 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3061 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3062 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3063 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3064 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3068 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3070 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3071 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3072 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3073 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3074 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3075 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3076 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3077 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3078 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3079 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3080 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3081 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3082 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3083 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3084 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3085 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3086 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3087 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3088 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3089 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3090 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3091 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3092 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
3093 };
3095 lpasscc: clock-controller@17014000 {
3096 compatible = "qcom,sdm845-lpasscc";
3097 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
3098 reg-names = "cc", "qdsp6ss";
3099 #clock-cells = <1>;
3100 status = "disabled";
3101 };
3103 watchdog@17980000 {
3104 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
3105 reg = <0 0x17980000 0 0x1000>;
3106 clocks = <&sleep_clk>;
3107 };
3109 apss_shared: mailbox@17990000 {
3110 compatible = "qcom,sdm845-apss-shared";
3111 reg = <0 0x17990000 0 0x1000>;
3112 #mbox-cells = <1>;
3113 };
3115 apps_rsc: rsc@179c0000 {
3116 label = "apps_rsc";
3117 compatible = "qcom,rpmh-rsc";
3118 reg = <0 0x179c0000 0 0x10000>,
3119 <0 0x179d0000 0 0x10000>,
3120 <0 0x179e0000 0 0x10000>;
3121 reg-names = "drv-0", "drv-1", "drv-2";
3122 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3124 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3125 qcom,tcs-offset = <0xd00>;
3126 qcom,drv-id = <2>;
3127 qcom,tcs-config = <ACTIVE_TCS 2>,
3128 <SLEEP_TCS 3>,
3129 <WAKE_TCS 3>,
3130 <CONTROL_TCS 1>;
3132 rpmhcc: clock-controller {
3133 compatible = "qcom,sdm845-rpmh-clk";
3134 #clock-cells = <1>;
3135 clock-names = "xo";
3136 clocks = <&xo_board>;
3137 };
3139 rpmhpd: power-controller {
3140 compatible = "qcom,sdm845-rpmhpd";
3141 #power-domain-cells = <1>;
3142 operating-points-v2 = <&rpmhpd_opp_table>;
3144 rpmhpd_opp_table: opp-table {
3145 compatible = "operating-points-v2";
3147 rpmhpd_opp_ret: opp1 {
3148 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3149 };
3151 rpmhpd_opp_min_svs: opp2 {
3152 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3153 };
3155 rpmhpd_opp_low_svs: opp3 {
3156 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3157 };
3159 rpmhpd_opp_svs: opp4 {
3160 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3161 };
3163 rpmhpd_opp_svs_l1: opp5 {
3164 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3165 };
3167 rpmhpd_opp_nom: opp6 {
3168 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3169 };
3171 rpmhpd_opp_nom_l1: opp7 {
3172 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3173 };
3175 rpmhpd_opp_nom_l2: opp8 {
3176 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3177 };
3179 rpmhpd_opp_turbo: opp9 {
3180 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3181 };
3183 rpmhpd_opp_turbo_l1: opp10 {
3184 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3185 };
3186 };
3187 };
3189 rsc_hlos: interconnect {
3190 compatible = "qcom,sdm845-rsc-hlos";
3191 #interconnect-cells = <1>;
3192 };
3193 };
3195 intc: interrupt-controller@17a00000 {
3196 compatible = "arm,gic-v3";
3197 #address-cells = <2>;
3198 #size-cells = <2>;
3199 ranges;
3200 #interrupt-cells = <3>;
3201 interrupt-controller;
3202 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3203 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3204 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3206 msi-controller@17a40000 {
3207 compatible = "arm,gic-v3-its";
3208 msi-controller;
3209 #msi-cells = <1>;
3210 reg = <0 0x17a40000 0 0x20000>;
3211 status = "disabled";
3212 };
3213 };
3215 timer@17c90000 {
3216 #address-cells = <2>;
3217 #size-cells = <2>;
3218 ranges;
3219 compatible = "arm,armv7-timer-mem";
3220 reg = <0 0x17c90000 0 0x1000>;
3222 frame@17ca0000 {
3223 frame-number = <0>;
3224 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
3225 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3226 reg = <0 0x17ca0000 0 0x1000>,
3227 <0 0x17cb0000 0 0x1000>;
3228 };
3230 frame@17cc0000 {
3231 frame-number = <1>;
3232 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3233 reg = <0 0x17cc0000 0 0x1000>;
3234 status = "disabled";
3235 };
3237 frame@17cd0000 {
3238 frame-number = <2>;
3239 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3240 reg = <0 0x17cd0000 0 0x1000>;
3241 status = "disabled";
3242 };
3244 frame@17ce0000 {
3245 frame-number = <3>;
3246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3247 reg = <0 0x17ce0000 0 0x1000>;
3248 status = "disabled";
3249 };
3251 frame@17cf0000 {
3252 frame-number = <4>;
3253 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3254 reg = <0 0x17cf0000 0 0x1000>;
3255 status = "disabled";
3256 };
3258 frame@17d00000 {
3259 frame-number = <5>;
3260 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3261 reg = <0 0x17d00000 0 0x1000>;
3262 status = "disabled";
3263 };
3265 frame@17d10000 {
3266 frame-number = <6>;
3267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3268 reg = <0 0x17d10000 0 0x1000>;
3269 status = "disabled";
3270 };
3271 };
3273 cpufreq_hw: cpufreq@17d43000 {
3274 compatible = "qcom,cpufreq-hw";
3275 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
3276 reg-names = "freq-domain0", "freq-domain1";
3278 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3279 clock-names = "xo", "alternate";
3281 #freq-domain-cells = <1>;
3282 };
3284 wifi: wifi@18800000 {
3285 compatible = "qcom,wcn3990-wifi";
3286 status = "disabled";
3287 reg = <0 0x18800000 0 0x800000>;
3288 reg-names = "membase";
3289 memory-region = <&wlan_msa_mem>;
3290 clock-names = "cxo_ref_clk_pin";
3291 clocks = <&rpmhcc RPMH_RF_CLK2>;
3292 interrupts =
3293 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3297 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3298 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3299 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3300 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3301 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3302 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3303 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3304 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3305 iommus = <&apps_smmu 0x0040 0x1>;
3306 };
3307 };
3309 thermal-zones {
3310 cpu0-thermal {
3311 polling-delay-passive = <250>;
3312 polling-delay = <1000>;
3314 thermal-sensors = <&tsens0 1>;
3316 trips {
3317 cpu0_alert0: trip-point0 {
3318 temperature = <90000>;
3319 hysteresis = <2000>;
3320 type = "passive";
3321 };
3323 cpu0_alert1: trip-point1 {
3324 temperature = <95000>;
3325 hysteresis = <2000>;
3326 type = "passive";
3327 };
3329 cpu0_crit: cpu_crit {
3330 temperature = <110000>;
3331 hysteresis = <1000>;
3332 type = "critical";
3333 };
3334 };
3336 cooling-maps {
3337 map0 {
3338 trip = <&cpu0_alert0>;
3339 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3340 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3341 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3342 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3343 };
3344 map1 {
3345 trip = <&cpu0_alert1>;
3346 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3347 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3348 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3349 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3350 };
3351 };
3352 };
3354 cpu1-thermal {
3355 polling-delay-passive = <250>;
3356 polling-delay = <1000>;
3358 thermal-sensors = <&tsens0 2>;
3360 trips {
3361 cpu1_alert0: trip-point0 {
3362 temperature = <90000>;
3363 hysteresis = <2000>;
3364 type = "passive";
3365 };
3367 cpu1_alert1: trip-point1 {
3368 temperature = <95000>;
3369 hysteresis = <2000>;
3370 type = "passive";
3371 };
3373 cpu1_crit: cpu_crit {
3374 temperature = <110000>;
3375 hysteresis = <1000>;
3376 type = "critical";
3377 };
3378 };
3380 cooling-maps {
3381 map0 {
3382 trip = <&cpu1_alert0>;
3383 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3384 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3385 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3386 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3387 };
3388 map1 {
3389 trip = <&cpu1_alert1>;
3390 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3391 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3392 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3393 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3394 };
3395 };
3396 };
3398 cpu2-thermal {
3399 polling-delay-passive = <250>;
3400 polling-delay = <1000>;
3402 thermal-sensors = <&tsens0 3>;
3404 trips {
3405 cpu2_alert0: trip-point0 {
3406 temperature = <90000>;
3407 hysteresis = <2000>;
3408 type = "passive";
3409 };
3411 cpu2_alert1: trip-point1 {
3412 temperature = <95000>;
3413 hysteresis = <2000>;
3414 type = "passive";
3415 };
3417 cpu2_crit: cpu_crit {
3418 temperature = <110000>;
3419 hysteresis = <1000>;
3420 type = "critical";
3421 };
3422 };
3424 cooling-maps {
3425 map0 {
3426 trip = <&cpu2_alert0>;
3427 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3428 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3429 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3430 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3431 };
3432 map1 {
3433 trip = <&cpu2_alert1>;
3434 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3435 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3436 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3437 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3438 };
3439 };
3440 };
3442 cpu3-thermal {
3443 polling-delay-passive = <250>;
3444 polling-delay = <1000>;
3446 thermal-sensors = <&tsens0 4>;
3448 trips {
3449 cpu3_alert0: trip-point0 {
3450 temperature = <90000>;
3451 hysteresis = <2000>;
3452 type = "passive";
3453 };
3455 cpu3_alert1: trip-point1 {
3456 temperature = <95000>;
3457 hysteresis = <2000>;
3458 type = "passive";
3459 };
3461 cpu3_crit: cpu_crit {
3462 temperature = <110000>;
3463 hysteresis = <1000>;
3464 type = "critical";
3465 };
3466 };
3468 cooling-maps {
3469 map0 {
3470 trip = <&cpu3_alert0>;
3471 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3472 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3473 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3474 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3475 };
3476 map1 {
3477 trip = <&cpu3_alert1>;
3478 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3479 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3480 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3481 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3482 };
3483 };
3484 };
3486 cpu4-thermal {
3487 polling-delay-passive = <250>;
3488 polling-delay = <1000>;
3490 thermal-sensors = <&tsens0 7>;
3492 trips {
3493 cpu4_alert0: trip-point0 {
3494 temperature = <90000>;
3495 hysteresis = <2000>;
3496 type = "passive";
3497 };
3499 cpu4_alert1: trip-point1 {
3500 temperature = <95000>;
3501 hysteresis = <2000>;
3502 type = "passive";
3503 };
3505 cpu4_crit: cpu_crit {
3506 temperature = <110000>;
3507 hysteresis = <1000>;
3508 type = "critical";
3509 };
3510 };
3512 cooling-maps {
3513 map0 {
3514 trip = <&cpu4_alert0>;
3515 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3516 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3517 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3518 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3519 };
3520 map1 {
3521 trip = <&cpu4_alert1>;
3522 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3523 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3524 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3525 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3526 };
3527 };
3528 };
3530 cpu5-thermal {
3531 polling-delay-passive = <250>;
3532 polling-delay = <1000>;
3534 thermal-sensors = <&tsens0 8>;
3536 trips {
3537 cpu5_alert0: trip-point0 {
3538 temperature = <90000>;
3539 hysteresis = <2000>;
3540 type = "passive";
3541 };
3543 cpu5_alert1: trip-point1 {
3544 temperature = <95000>;
3545 hysteresis = <2000>;
3546 type = "passive";
3547 };
3549 cpu5_crit: cpu_crit {
3550 temperature = <110000>;
3551 hysteresis = <1000>;
3552 type = "critical";
3553 };
3554 };
3556 cooling-maps {
3557 map0 {
3558 trip = <&cpu5_alert0>;
3559 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3560 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3561 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3562 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3563 };
3564 map1 {
3565 trip = <&cpu5_alert1>;
3566 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3567 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3568 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3569 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3570 };
3571 };
3572 };
3574 cpu6-thermal {
3575 polling-delay-passive = <250>;
3576 polling-delay = <1000>;
3578 thermal-sensors = <&tsens0 9>;
3580 trips {
3581 cpu6_alert0: trip-point0 {
3582 temperature = <90000>;
3583 hysteresis = <2000>;
3584 type = "passive";
3585 };
3587 cpu6_alert1: trip-point1 {
3588 temperature = <95000>;
3589 hysteresis = <2000>;
3590 type = "passive";
3591 };
3593 cpu6_crit: cpu_crit {
3594 temperature = <110000>;
3595 hysteresis = <1000>;
3596 type = "critical";
3597 };
3598 };
3600 cooling-maps {
3601 map0 {
3602 trip = <&cpu6_alert0>;
3603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3607 };
3608 map1 {
3609 trip = <&cpu6_alert1>;
3610 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3611 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3612 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3613 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3614 };
3615 };
3616 };
3618 cpu7-thermal {
3619 polling-delay-passive = <250>;
3620 polling-delay = <1000>;
3622 thermal-sensors = <&tsens0 10>;
3624 trips {
3625 cpu7_alert0: trip-point0 {
3626 temperature = <90000>;
3627 hysteresis = <2000>;
3628 type = "passive";
3629 };
3631 cpu7_alert1: trip-point1 {
3632 temperature = <95000>;
3633 hysteresis = <2000>;
3634 type = "passive";
3635 };
3637 cpu7_crit: cpu_crit {
3638 temperature = <110000>;
3639 hysteresis = <1000>;
3640 type = "critical";
3641 };
3642 };
3644 cooling-maps {
3645 map0 {
3646 trip = <&cpu7_alert0>;
3647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3651 };
3652 map1 {
3653 trip = <&cpu7_alert1>;
3654 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3655 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3658 };
3659 };
3660 };
3662 aoss0-thermal {
3663 polling-delay-passive = <250>;
3664 polling-delay = <1000>;
3666 thermal-sensors = <&tsens0 0>;
3668 trips {
3669 aoss0_alert0: trip-point0 {
3670 temperature = <90000>;
3671 hysteresis = <2000>;
3672 type = "hot";
3673 };
3674 };
3675 };
3677 cluster0-thermal {
3678 polling-delay-passive = <250>;
3679 polling-delay = <1000>;
3681 thermal-sensors = <&tsens0 5>;
3683 trips {
3684 cluster0_alert0: trip-point0 {
3685 temperature = <90000>;
3686 hysteresis = <2000>;
3687 type = "hot";
3688 };
3689 cluster0_crit: cluster0_crit {
3690 temperature = <110000>;
3691 hysteresis = <2000>;
3692 type = "critical";
3693 };
3694 };
3695 };
3697 cluster1-thermal {
3698 polling-delay-passive = <250>;
3699 polling-delay = <1000>;
3701 thermal-sensors = <&tsens0 6>;
3703 trips {
3704 cluster1_alert0: trip-point0 {
3705 temperature = <90000>;
3706 hysteresis = <2000>;
3707 type = "hot";
3708 };
3709 cluster1_crit: cluster1_crit {
3710 temperature = <110000>;
3711 hysteresis = <2000>;
3712 type = "critical";
3713 };
3714 };
3715 };
3717 gpu-thermal-top {
3718 polling-delay-passive = <250>;
3719 polling-delay = <1000>;
3721 thermal-sensors = <&tsens0 11>;
3723 trips {
3724 gpu1_alert0: trip-point0 {
3725 temperature = <90000>;
3726 hysteresis = <2000>;
3727 type = "hot";
3728 };
3729 };
3730 };
3732 gpu-thermal-bottom {
3733 polling-delay-passive = <250>;
3734 polling-delay = <1000>;
3736 thermal-sensors = <&tsens0 12>;
3738 trips {
3739 gpu2_alert0: trip-point0 {
3740 temperature = <90000>;
3741 hysteresis = <2000>;
3742 type = "hot";
3743 };
3744 };
3745 };
3747 aoss1-thermal {
3748 polling-delay-passive = <250>;
3749 polling-delay = <1000>;
3751 thermal-sensors = <&tsens1 0>;
3753 trips {
3754 aoss1_alert0: trip-point0 {
3755 temperature = <90000>;
3756 hysteresis = <2000>;
3757 type = "hot";
3758 };
3759 };
3760 };
3762 q6-modem-thermal {
3763 polling-delay-passive = <250>;
3764 polling-delay = <1000>;
3766 thermal-sensors = <&tsens1 1>;
3768 trips {
3769 q6_modem_alert0: trip-point0 {
3770 temperature = <90000>;
3771 hysteresis = <2000>;
3772 type = "hot";
3773 };
3774 };
3775 };
3777 mem-thermal {
3778 polling-delay-passive = <250>;
3779 polling-delay = <1000>;
3781 thermal-sensors = <&tsens1 2>;
3783 trips {
3784 mem_alert0: trip-point0 {
3785 temperature = <90000>;
3786 hysteresis = <2000>;
3787 type = "hot";
3788 };
3789 };
3790 };
3792 wlan-thermal {
3793 polling-delay-passive = <250>;
3794 polling-delay = <1000>;
3796 thermal-sensors = <&tsens1 3>;
3798 trips {
3799 wlan_alert0: trip-point0 {
3800 temperature = <90000>;
3801 hysteresis = <2000>;
3802 type = "hot";
3803 };
3804 };
3805 };
3807 q6-hvx-thermal {
3808 polling-delay-passive = <250>;
3809 polling-delay = <1000>;
3811 thermal-sensors = <&tsens1 4>;
3813 trips {
3814 q6_hvx_alert0: trip-point0 {
3815 temperature = <90000>;
3816 hysteresis = <2000>;
3817 type = "hot";
3818 };
3819 };
3820 };
3822 camera-thermal {
3823 polling-delay-passive = <250>;
3824 polling-delay = <1000>;
3826 thermal-sensors = <&tsens1 5>;
3828 trips {
3829 camera_alert0: trip-point0 {
3830 temperature = <90000>;
3831 hysteresis = <2000>;
3832 type = "hot";
3833 };
3834 };
3835 };
3837 video-thermal {
3838 polling-delay-passive = <250>;
3839 polling-delay = <1000>;
3841 thermal-sensors = <&tsens1 6>;
3843 trips {
3844 video_alert0: trip-point0 {
3845 temperature = <90000>;
3846 hysteresis = <2000>;
3847 type = "hot";
3848 };
3849 };
3850 };
3852 modem-thermal {
3853 polling-delay-passive = <250>;
3854 polling-delay = <1000>;
3856 thermal-sensors = <&tsens1 7>;
3858 trips {
3859 modem_alert0: trip-point0 {
3860 temperature = <90000>;
3861 hysteresis = <2000>;
3862 type = "hot";
3863 };
3864 };
3865 };
3866 };
3867 };