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mtd: add ECC info for nand_flash_dev{}
[linux/fpc-iii.git] / sound / soc / codecs / max98090.c
blobad5313f98f286b8f95223b56ef88ae4718f7a73d
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 #define DEBUG
27 #define EXTMIC_METHOD
28 #define EXTMIC_METHOD_TEST
29
30 /* Allows for sparsely populated register maps */
31 static struct reg_default max98090_reg[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
46
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
97
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
253 };
254
255 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256 {
257 switch (reg) {
258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
261 return true;
262 default:
263 return false;
264 }
265 }
266
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
268 {
269 switch (reg) {
270 case M98090_REG_DEVICE_STATUS:
271 case M98090_REG_JACK_STATUS:
272 case M98090_REG_INTERRUPT_S:
273 case M98090_REG_RESERVED:
274 case M98090_REG_LINE_INPUT_CONFIG:
275 case M98090_REG_LINE_INPUT_LEVEL:
276 case M98090_REG_INPUT_MODE:
277 case M98090_REG_MIC1_INPUT_LEVEL:
278 case M98090_REG_MIC2_INPUT_LEVEL:
279 case M98090_REG_MIC_BIAS_VOLTAGE:
280 case M98090_REG_DIGITAL_MIC_ENABLE:
281 case M98090_REG_DIGITAL_MIC_CONFIG:
282 case M98090_REG_LEFT_ADC_MIXER:
283 case M98090_REG_RIGHT_ADC_MIXER:
284 case M98090_REG_LEFT_ADC_LEVEL:
285 case M98090_REG_RIGHT_ADC_LEVEL:
286 case M98090_REG_ADC_BIQUAD_LEVEL:
287 case M98090_REG_ADC_SIDETONE:
288 case M98090_REG_SYSTEM_CLOCK:
289 case M98090_REG_CLOCK_MODE:
290 case M98090_REG_CLOCK_RATIO_NI_MSB:
291 case M98090_REG_CLOCK_RATIO_NI_LSB:
292 case M98090_REG_CLOCK_RATIO_MI_MSB:
293 case M98090_REG_CLOCK_RATIO_MI_LSB:
294 case M98090_REG_MASTER_MODE:
295 case M98090_REG_INTERFACE_FORMAT:
296 case M98090_REG_TDM_CONTROL:
297 case M98090_REG_TDM_FORMAT:
298 case M98090_REG_IO_CONFIGURATION:
299 case M98090_REG_FILTER_CONFIG:
300 case M98090_REG_DAI_PLAYBACK_LEVEL:
301 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
302 case M98090_REG_LEFT_HP_MIXER:
303 case M98090_REG_RIGHT_HP_MIXER:
304 case M98090_REG_HP_CONTROL:
305 case M98090_REG_LEFT_HP_VOLUME:
306 case M98090_REG_RIGHT_HP_VOLUME:
307 case M98090_REG_LEFT_SPK_MIXER:
308 case M98090_REG_RIGHT_SPK_MIXER:
309 case M98090_REG_SPK_CONTROL:
310 case M98090_REG_LEFT_SPK_VOLUME:
311 case M98090_REG_RIGHT_SPK_VOLUME:
312 case M98090_REG_DRC_TIMING:
313 case M98090_REG_DRC_COMPRESSOR:
314 case M98090_REG_DRC_EXPANDER:
315 case M98090_REG_DRC_GAIN:
316 case M98090_REG_RCV_LOUTL_MIXER:
317 case M98090_REG_RCV_LOUTL_CONTROL:
318 case M98090_REG_RCV_LOUTL_VOLUME:
319 case M98090_REG_LOUTR_MIXER:
320 case M98090_REG_LOUTR_CONTROL:
321 case M98090_REG_LOUTR_VOLUME:
322 case M98090_REG_JACK_DETECT:
323 case M98090_REG_INPUT_ENABLE:
324 case M98090_REG_OUTPUT_ENABLE:
325 case M98090_REG_LEVEL_CONTROL:
326 case M98090_REG_DSP_FILTER_ENABLE:
327 case M98090_REG_BIAS_CONTROL:
328 case M98090_REG_DAC_CONTROL:
329 case M98090_REG_ADC_CONTROL:
330 case M98090_REG_DEVICE_SHUTDOWN:
331 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
332 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
333 case M98090_REG_DMIC3_VOLUME:
334 case M98090_REG_DMIC4_VOLUME:
335 case M98090_REG_DMIC34_BQ_PREATTEN:
336 case M98090_REG_RECORD_TDM_SLOT:
337 case M98090_REG_SAMPLE_RATE:
338 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
339 return true;
340 default:
341 return false;
342 }
343 }
344
345 static int max98090_reset(struct max98090_priv *max98090)
346 {
347 int ret;
348
349 /* Reset the codec by writing to this write-only reset register */
350 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
351 M98090_SWRESET_MASK);
352 if (ret < 0) {
353 dev_err(max98090->codec->dev,
354 "Failed to reset codec: %d\n", ret);
355 return ret;
356 }
357
358 msleep(20);
359 return ret;
360 }
361
362 static const unsigned int max98090_micboost_tlv[] = {
363 TLV_DB_RANGE_HEAD(2),
364 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
365 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
366 };
367
368 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
369
370 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
371 -600, 600, 0);
372
373 static const unsigned int max98090_line_tlv[] = {
374 TLV_DB_RANGE_HEAD(2),
375 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
376 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
377 };
378
379 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
380 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
381
382 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
383 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
384
385 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
386
387 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
388 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
389 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
391
392 static const unsigned int max98090_mixout_tlv[] = {
393 TLV_DB_RANGE_HEAD(2),
394 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
395 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
396 };
397
398 static const unsigned int max98090_hp_tlv[] = {
399 TLV_DB_RANGE_HEAD(5),
400 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
401 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
402 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
403 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
404 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
405 };
406
407 static const unsigned int max98090_spk_tlv[] = {
408 TLV_DB_RANGE_HEAD(5),
409 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
410 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
411 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
412 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
413 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
414 };
415
416 static const unsigned int max98090_rcv_lout_tlv[] = {
417 TLV_DB_RANGE_HEAD(5),
418 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
419 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
420 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
421 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
422 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
423 };
424
425 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
430 struct soc_mixer_control *mc =
431 (struct soc_mixer_control *)kcontrol->private_value;
432 unsigned int mask = (1 << fls(mc->max)) - 1;
433 unsigned int val = snd_soc_read(codec, mc->reg);
434 unsigned int *select;
435
436 switch (mc->reg) {
437 case M98090_REG_MIC1_INPUT_LEVEL:
438 select = &(max98090->pa1en);
439 break;
440 case M98090_REG_MIC2_INPUT_LEVEL:
441 select = &(max98090->pa2en);
442 break;
443 case M98090_REG_ADC_SIDETONE:
444 select = &(max98090->sidetone);
445 break;
446 default:
447 return -EINVAL;
448 }
449
450 val = (val >> mc->shift) & mask;
451
452 if (val >= 1) {
453 /* If on, return the volume */
454 val = val - 1;
455 *select = val;
456 } else {
457 /* If off, return last stored value */
458 val = *select;
459 }
460
461 ucontrol->value.integer.value[0] = val;
462 return 0;
463 }
464
465 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
466 struct snd_ctl_elem_value *ucontrol)
467 {
468 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
469 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
470 struct soc_mixer_control *mc =
471 (struct soc_mixer_control *)kcontrol->private_value;
472 unsigned int mask = (1 << fls(mc->max)) - 1;
473 unsigned int sel = ucontrol->value.integer.value[0];
474 unsigned int val = snd_soc_read(codec, mc->reg);
475 unsigned int *select;
476
477 switch (mc->reg) {
478 case M98090_REG_MIC1_INPUT_LEVEL:
479 select = &(max98090->pa1en);
480 break;
481 case M98090_REG_MIC2_INPUT_LEVEL:
482 select = &(max98090->pa2en);
483 break;
484 case M98090_REG_ADC_SIDETONE:
485 select = &(max98090->sidetone);
486 break;
487 default:
488 return -EINVAL;
489 }
490
491 val = (val >> mc->shift) & mask;
492
493 *select = sel;
494
495 /* Setting a volume is only valid if it is already On */
496 if (val >= 1) {
497 sel = sel + 1;
498 } else {
499 /* Write what was already there */
500 sel = val;
501 }
502
503 snd_soc_update_bits(codec, mc->reg,
504 mask << mc->shift,
505 sel << mc->shift);
506
507 return 0;
508 }
509
510 static const char *max98090_perf_pwr_text[] =
511 { "High Performance", "Low Power" };
512 static const char *max98090_pwr_perf_text[] =
513 { "Low Power", "High Performance" };
514
515 static const struct soc_enum max98090_vcmbandgap_enum =
516 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT,
517 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
518
519 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
520
521 static const struct soc_enum max98090_osr128_enum =
522 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT,
523 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text);
524
525 static const char *max98090_mode_text[] = { "Voice", "Music" };
526
527 static const struct soc_enum max98090_mode_enum =
528 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT,
529 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
530
531 static const struct soc_enum max98090_filter_dmic34mode_enum =
532 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG,
533 M98090_FLT_DMIC34MODE_SHIFT,
534 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
535
536 static const char *max98090_drcatk_text[] =
537 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
538
539 static const struct soc_enum max98090_drcatk_enum =
540 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT,
541 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text);
542
543 static const char *max98090_drcrls_text[] =
544 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
545
546 static const struct soc_enum max98090_drcrls_enum =
547 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT,
548 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text);
549
550 static const char *max98090_alccmp_text[] =
551 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
552
553 static const struct soc_enum max98090_alccmp_enum =
554 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT,
555 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text);
556
557 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
558
559 static const struct soc_enum max98090_drcexp_enum =
560 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT,
561 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text);
562
563 static const struct soc_enum max98090_dac_perfmode_enum =
564 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT,
565 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text);
566
567 static const struct soc_enum max98090_dachp_enum =
568 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT,
569 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
570
571 static const struct soc_enum max98090_adchp_enum =
572 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT,
573 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
574
575 static const struct snd_kcontrol_new max98090_snd_controls[] = {
576 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
577
578 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
579 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
580
581 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
582 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
583 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
584 max98090_put_enab_tlv, max98090_micboost_tlv),
585
586 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
587 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
588 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
589 max98090_put_enab_tlv, max98090_micboost_tlv),
590
591 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
592 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
593 max98090_mic_tlv),
594
595 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
596 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
597 max98090_mic_tlv),
598
599 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
600 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
601 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
602
603 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
604 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
605 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
606
607 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
608 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
609 max98090_line_tlv),
610
611 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
612 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
613 max98090_line_tlv),
614
615 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
616 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
617 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
618 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
619
620 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
621 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
622 max98090_avg_tlv),
623 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
624 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
625 max98090_avg_tlv),
626
627 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
628 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
629 max98090_av_tlv),
630 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
631 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
632 max98090_av_tlv),
633
634 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
635 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
636 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
637 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
638
639 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
640 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
641 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
642 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
643 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
644 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
645 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
646 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
647 SOC_ENUM("Filter Mode", max98090_mode_enum),
648 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
649 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
650 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
651 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
652 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
653 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
654 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
655 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
656 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
657 max98090_put_enab_tlv, max98090_micboost_tlv),
658 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
659 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
660 max98090_dvg_tlv),
661 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
662 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
663 max98090_dv_tlv),
664 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
665 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
666 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
667 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
668 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
669 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
670 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
671 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
672 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
673 1),
674 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
675 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
676 max98090_dv_tlv),
677
678 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
679 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
680 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
681 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
682 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
683 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
684 max98090_alcmakeup_tlv),
685 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
686 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
687 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
688 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
689 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
690 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
691 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
692 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
693
694 SOC_ENUM("DAC HP Playback Performance Mode",
695 max98090_dac_perfmode_enum),
696 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
697
698 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
699 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
700 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
701 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
702 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
703 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
704
705 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
706 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
707 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
708 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
709 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
710 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
711
712 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
713 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
714 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
715 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
716 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
717 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
718
719 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
720 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
721 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
722
723 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
724 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
725 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
726 0, max98090_spk_tlv),
727
728 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
729 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
730 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
731
732 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
733 M98090_HPLM_SHIFT, 1, 1),
734 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
735 M98090_HPRM_SHIFT, 1, 1),
736
737 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
738 M98090_SPLM_SHIFT, 1, 1),
739 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
740 M98090_SPRM_SHIFT, 1, 1),
741
742 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
743 M98090_RCVLM_SHIFT, 1, 1),
744 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
745 M98090_RCVRM_SHIFT, 1, 1),
746
747 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
748 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
749 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
750 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
751 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
752 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
753
754 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
755 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
756 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
757 };
758
759 static const struct snd_kcontrol_new max98091_snd_controls[] = {
760
761 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
762 M98090_DMIC34_ZEROPAD_SHIFT,
763 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
764
765 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
766 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
767 M98090_FLT_DMIC34HPF_SHIFT,
768 M98090_FLT_DMIC34HPF_NUM - 1, 0),
769
770 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
771 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
772 max98090_avg_tlv),
773 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
774 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
775 max98090_avg_tlv),
776
777 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
778 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
779 max98090_av_tlv),
780 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
781 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
782 max98090_av_tlv),
783
784 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
785 M98090_REG_DMIC34_BIQUAD_BASE, 15),
786 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
787 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
788
789 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
790 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
791 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
792 };
793
794 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
795 struct snd_kcontrol *kcontrol, int event)
796 {
797 struct snd_soc_codec *codec = w->codec;
798 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
799
800 unsigned int val = snd_soc_read(codec, w->reg);
801
802 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
803 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
804 else
805 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
806
807
808 if (val >= 1) {
809 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
810 max98090->pa1en = val - 1; /* Update for volatile */
811 } else {
812 max98090->pa2en = val - 1; /* Update for volatile */
813 }
814 }
815
816 switch (event) {
817 case SND_SOC_DAPM_POST_PMU:
818 /* If turning on, set to most recently selected volume */
819 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
820 val = max98090->pa1en + 1;
821 else
822 val = max98090->pa2en + 1;
823 break;
824 case SND_SOC_DAPM_POST_PMD:
825 /* If turning off, turn off */
826 val = 0;
827 break;
828 default:
829 return -EINVAL;
830 }
831
832 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
833 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
834 val << M98090_MIC_PA1EN_SHIFT);
835 else
836 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
837 val << M98090_MIC_PA2EN_SHIFT);
838
839 return 0;
840 }
841
842 static const char *mic1_mux_text[] = { "IN12", "IN56" };
843
844 static const struct soc_enum mic1_mux_enum =
845 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT,
846 ARRAY_SIZE(mic1_mux_text), mic1_mux_text);
847
848 static const struct snd_kcontrol_new max98090_mic1_mux =
849 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
850
851 static const char *mic2_mux_text[] = { "IN34", "IN56" };
852
853 static const struct soc_enum mic2_mux_enum =
854 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT,
855 ARRAY_SIZE(mic2_mux_text), mic2_mux_text);
856
857 static const struct snd_kcontrol_new max98090_mic2_mux =
858 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
859
860 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
861
862 static const struct soc_enum dmic_mux_enum =
863 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dmic_mux_text), dmic_mux_text);
864
865 static const struct snd_kcontrol_new max98090_dmic_mux =
866 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum);
867
868 static const char *max98090_micpre_text[] = { "Off", "On" };
869
870 static const struct soc_enum max98090_pa1en_enum =
871 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
872 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
873
874 static const struct soc_enum max98090_pa2en_enum =
875 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
876 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
877
878 /* LINEA mixer switch */
879 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
880 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
881 M98090_IN1SEEN_SHIFT, 1, 0),
882 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
883 M98090_IN3SEEN_SHIFT, 1, 0),
884 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
885 M98090_IN5SEEN_SHIFT, 1, 0),
886 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
887 M98090_IN34DIFF_SHIFT, 1, 0),
888 };
889
890 /* LINEB mixer switch */
891 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
892 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
893 M98090_IN2SEEN_SHIFT, 1, 0),
894 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
895 M98090_IN4SEEN_SHIFT, 1, 0),
896 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
897 M98090_IN6SEEN_SHIFT, 1, 0),
898 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
899 M98090_IN56DIFF_SHIFT, 1, 0),
900 };
901
902 /* Left ADC mixer switch */
903 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
904 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
905 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
906 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
907 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
909 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
911 M98090_MIXADL_LINEA_SHIFT, 1, 0),
912 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
913 M98090_MIXADL_LINEB_SHIFT, 1, 0),
914 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
915 M98090_MIXADL_MIC1_SHIFT, 1, 0),
916 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
917 M98090_MIXADL_MIC2_SHIFT, 1, 0),
918 };
919
920 /* Right ADC mixer switch */
921 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
922 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
923 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
925 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
927 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
929 M98090_MIXADR_LINEA_SHIFT, 1, 0),
930 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
931 M98090_MIXADR_LINEB_SHIFT, 1, 0),
932 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
933 M98090_MIXADR_MIC1_SHIFT, 1, 0),
934 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
935 M98090_MIXADR_MIC2_SHIFT, 1, 0),
936 };
937
938 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
939
940 static const struct soc_enum ltenl_mux_enum =
941 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
942 ARRAY_SIZE(lten_mux_text), lten_mux_text);
943
944 static const struct soc_enum ltenr_mux_enum =
945 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
946 ARRAY_SIZE(lten_mux_text), lten_mux_text);
947
948 static const struct snd_kcontrol_new max98090_ltenl_mux =
949 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
950
951 static const struct snd_kcontrol_new max98090_ltenr_mux =
952 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
953
954 static const char *lben_mux_text[] = { "Normal", "Loopback" };
955
956 static const struct soc_enum lbenl_mux_enum =
957 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
958 ARRAY_SIZE(lben_mux_text), lben_mux_text);
959
960 static const struct soc_enum lbenr_mux_enum =
961 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
962 ARRAY_SIZE(lben_mux_text), lben_mux_text);
963
964 static const struct snd_kcontrol_new max98090_lbenl_mux =
965 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
966
967 static const struct snd_kcontrol_new max98090_lbenr_mux =
968 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
969
970 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
971
972 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
973
974 static const struct soc_enum stenl_mux_enum =
975 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT,
976 ARRAY_SIZE(stenl_mux_text), stenl_mux_text);
977
978 static const struct soc_enum stenr_mux_enum =
979 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT,
980 ARRAY_SIZE(stenr_mux_text), stenr_mux_text);
981
982 static const struct snd_kcontrol_new max98090_stenl_mux =
983 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
984
985 static const struct snd_kcontrol_new max98090_stenr_mux =
986 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
987
988 /* Left speaker mixer switch */
989 static const struct
990 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
991 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
992 M98090_MIXSPL_DACL_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
994 M98090_MIXSPL_DACR_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
996 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
997 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
998 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
999 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1000 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1001 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1002 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1003 };
1004
1005 /* Right speaker mixer switch */
1006 static const struct
1007 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1008 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1009 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1011 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1013 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1014 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1015 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1017 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1019 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1020 };
1021
1022 /* Left headphone mixer switch */
1023 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1024 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1025 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1027 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1029 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1030 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1031 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1032 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1033 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1034 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1035 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1036 };
1037
1038 /* Right headphone mixer switch */
1039 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1040 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1041 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1043 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1045 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1046 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1047 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1048 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1049 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1050 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1051 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1052 };
1053
1054 /* Left receiver mixer switch */
1055 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1056 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1057 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1058 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1059 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1060 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1061 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1062 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1063 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1064 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1065 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1066 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1067 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1068 };
1069
1070 /* Right receiver mixer switch */
1071 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1072 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1073 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1074 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1075 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1076 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1077 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1078 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1079 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1080 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1081 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1082 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1083 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1084 };
1085
1086 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1087
1088 static const struct soc_enum linmod_mux_enum =
1089 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT,
1090 ARRAY_SIZE(linmod_mux_text), linmod_mux_text);
1091
1092 static const struct snd_kcontrol_new max98090_linmod_mux =
1093 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1094
1095 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1096
1097 /*
1098 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1099 */
1100 static const struct soc_enum mixhplsel_mux_enum =
1101 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT,
1102 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1103
1104 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1105 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1106
1107 static const struct soc_enum mixhprsel_mux_enum =
1108 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT,
1109 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1110
1111 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1112 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1113
1114 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1115
1116 SND_SOC_DAPM_INPUT("MIC1"),
1117 SND_SOC_DAPM_INPUT("MIC2"),
1118 SND_SOC_DAPM_INPUT("DMICL"),
1119 SND_SOC_DAPM_INPUT("DMICR"),
1120 SND_SOC_DAPM_INPUT("IN1"),
1121 SND_SOC_DAPM_INPUT("IN2"),
1122 SND_SOC_DAPM_INPUT("IN3"),
1123 SND_SOC_DAPM_INPUT("IN4"),
1124 SND_SOC_DAPM_INPUT("IN5"),
1125 SND_SOC_DAPM_INPUT("IN6"),
1126 SND_SOC_DAPM_INPUT("IN12"),
1127 SND_SOC_DAPM_INPUT("IN34"),
1128 SND_SOC_DAPM_INPUT("IN56"),
1129
1130 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1131 M98090_MBEN_SHIFT, 0, NULL, 0),
1132 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1133 M98090_SHDNN_SHIFT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1135 M98090_SDIEN_SHIFT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1137 M98090_SDOEN_SHIFT, 0, NULL, 0),
1138 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1139 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1140 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1141 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1142 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1143 M98090_AHPF_SHIFT, 0, NULL, 0),
1144
1145 /*
1146 * Note: Sysclk and misc power supplies are taken care of by SHDN
1147 */
1148
1149 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1150 0, 0, &max98090_mic1_mux),
1151
1152 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1153 0, 0, &max98090_mic2_mux),
1154
1155 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM,
1156 0, 0, &max98090_dmic_mux),
1157
1158 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1159 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1160 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1161
1162 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1163 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1164 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1165
1166 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1167 &max98090_linea_mixer_controls[0],
1168 ARRAY_SIZE(max98090_linea_mixer_controls)),
1169
1170 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_lineb_mixer_controls[0],
1172 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1173
1174 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1175 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1176 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1177 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1178
1179 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1180 &max98090_left_adc_mixer_controls[0],
1181 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1182
1183 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1184 &max98090_right_adc_mixer_controls[0],
1185 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1186
1187 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1188 M98090_ADLEN_SHIFT, 0),
1189 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1190 M98090_ADREN_SHIFT, 0),
1191
1192 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1193 SND_SOC_NOPM, 0, 0),
1194 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1195 SND_SOC_NOPM, 0, 0),
1196
1197 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1198 0, 0, &max98090_lbenl_mux),
1199
1200 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1201 0, 0, &max98090_lbenr_mux),
1202
1203 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1204 0, 0, &max98090_ltenl_mux),
1205
1206 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1207 0, 0, &max98090_ltenr_mux),
1208
1209 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1210 0, 0, &max98090_stenl_mux),
1211
1212 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1213 0, 0, &max98090_stenr_mux),
1214
1215 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1216 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1217
1218 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1219 M98090_DALEN_SHIFT, 0),
1220 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1221 M98090_DAREN_SHIFT, 0),
1222
1223 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1224 &max98090_left_hp_mixer_controls[0],
1225 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1226
1227 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1228 &max98090_right_hp_mixer_controls[0],
1229 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1230
1231 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1232 &max98090_left_speaker_mixer_controls[0],
1233 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1234
1235 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1236 &max98090_right_speaker_mixer_controls[0],
1237 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1238
1239 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1240 &max98090_left_rcv_mixer_controls[0],
1241 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1242
1243 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1244 &max98090_right_rcv_mixer_controls[0],
1245 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1246
1247 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1248 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1249
1250 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1251 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1252
1253 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1254 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1255
1256 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1257 M98090_HPLEN_SHIFT, 0, NULL, 0),
1258 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1259 M98090_HPREN_SHIFT, 0, NULL, 0),
1260
1261 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1262 M98090_SPLEN_SHIFT, 0, NULL, 0),
1263 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1264 M98090_SPREN_SHIFT, 0, NULL, 0),
1265
1266 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1267 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1268 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1269 M98090_RCVREN_SHIFT, 0, NULL, 0),
1270
1271 SND_SOC_DAPM_OUTPUT("HPL"),
1272 SND_SOC_DAPM_OUTPUT("HPR"),
1273 SND_SOC_DAPM_OUTPUT("SPKL"),
1274 SND_SOC_DAPM_OUTPUT("SPKR"),
1275 SND_SOC_DAPM_OUTPUT("RCVL"),
1276 SND_SOC_DAPM_OUTPUT("RCVR"),
1277 };
1278
1279 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1280
1281 SND_SOC_DAPM_INPUT("DMIC3"),
1282 SND_SOC_DAPM_INPUT("DMIC4"),
1283
1284 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1285 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1286 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1287 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1288 };
1289
1290 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1291
1292 {"MIC1 Input", NULL, "MIC1"},
1293 {"MIC2 Input", NULL, "MIC2"},
1294
1295 {"DMICL", NULL, "DMICL_ENA"},
1296 {"DMICR", NULL, "DMICR_ENA"},
1297 {"DMICL", NULL, "AHPF"},
1298 {"DMICR", NULL, "AHPF"},
1299
1300 /* MIC1 input mux */
1301 {"MIC1 Mux", "IN12", "IN12"},
1302 {"MIC1 Mux", "IN56", "IN56"},
1303
1304 /* MIC2 input mux */
1305 {"MIC2 Mux", "IN34", "IN34"},
1306 {"MIC2 Mux", "IN56", "IN56"},
1307
1308 {"MIC1 Input", NULL, "MIC1 Mux"},
1309 {"MIC2 Input", NULL, "MIC2 Mux"},
1310
1311 /* Left ADC input mixer */
1312 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1313 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1314 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1315 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1316 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1317 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1318 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1319
1320 /* Right ADC input mixer */
1321 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1322 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1323 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1324 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1325 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1326 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1327 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1328
1329 /* Line A input mixer */
1330 {"LINEA Mixer", "IN1 Switch", "IN1"},
1331 {"LINEA Mixer", "IN3 Switch", "IN3"},
1332 {"LINEA Mixer", "IN5 Switch", "IN5"},
1333 {"LINEA Mixer", "IN34 Switch", "IN34"},
1334
1335 /* Line B input mixer */
1336 {"LINEB Mixer", "IN2 Switch", "IN2"},
1337 {"LINEB Mixer", "IN4 Switch", "IN4"},
1338 {"LINEB Mixer", "IN6 Switch", "IN6"},
1339 {"LINEB Mixer", "IN56 Switch", "IN56"},
1340
1341 {"LINEA Input", NULL, "LINEA Mixer"},
1342 {"LINEB Input", NULL, "LINEB Mixer"},
1343
1344 /* Inputs */
1345 {"ADCL", NULL, "Left ADC Mixer"},
1346 {"ADCR", NULL, "Right ADC Mixer"},
1347 {"ADCL", NULL, "SHDN"},
1348 {"ADCR", NULL, "SHDN"},
1349
1350 {"DMIC Mux", "ADC", "ADCL"},
1351 {"DMIC Mux", "ADC", "ADCR"},
1352 {"DMIC Mux", "DMIC", "DMICL"},
1353 {"DMIC Mux", "DMIC", "DMICR"},
1354
1355 {"LBENL Mux", "Normal", "DMIC Mux"},
1356 {"LBENL Mux", "Loopback", "LTENL Mux"},
1357 {"LBENR Mux", "Normal", "DMIC Mux"},
1358 {"LBENR Mux", "Loopback", "LTENR Mux"},
1359
1360 {"AIFOUTL", NULL, "LBENL Mux"},
1361 {"AIFOUTR", NULL, "LBENR Mux"},
1362 {"AIFOUTL", NULL, "SHDN"},
1363 {"AIFOUTR", NULL, "SHDN"},
1364 {"AIFOUTL", NULL, "SDOEN"},
1365 {"AIFOUTR", NULL, "SDOEN"},
1366
1367 {"LTENL Mux", "Normal", "AIFINL"},
1368 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1369 {"LTENR Mux", "Normal", "AIFINR"},
1370 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1371
1372 {"DACL", NULL, "LTENL Mux"},
1373 {"DACR", NULL, "LTENR Mux"},
1374
1375 {"STENL Mux", "Sidetone Left", "ADCL"},
1376 {"STENL Mux", "Sidetone Left", "DMICL"},
1377 {"STENR Mux", "Sidetone Right", "ADCR"},
1378 {"STENR Mux", "Sidetone Right", "DMICR"},
1379 {"DACL", "NULL", "STENL Mux"},
1380 {"DACR", "NULL", "STENL Mux"},
1381
1382 {"AIFINL", NULL, "SHDN"},
1383 {"AIFINR", NULL, "SHDN"},
1384 {"AIFINL", NULL, "SDIEN"},
1385 {"AIFINR", NULL, "SDIEN"},
1386 {"DACL", NULL, "SHDN"},
1387 {"DACR", NULL, "SHDN"},
1388
1389 /* Left headphone output mixer */
1390 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1391 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1392 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1393 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1394 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1395 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1396
1397 /* Right headphone output mixer */
1398 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1399 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1400 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1401 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1402 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1403 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1404
1405 /* Left speaker output mixer */
1406 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1407 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1408 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1409 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1410 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1411 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1412
1413 /* Right speaker output mixer */
1414 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1415 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1416 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1417 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1418 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1419 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1420
1421 /* Left Receiver output mixer */
1422 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1423 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1424 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1425 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1426 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1427 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1428
1429 /* Right Receiver output mixer */
1430 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1431 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1432 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1433 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1434 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1435 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1436
1437 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1438
1439 /*
1440 * Disable this for lowest power if bypassing
1441 * the DAC with an analog signal
1442 */
1443 {"HP Left Out", NULL, "DACL"},
1444 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1445
1446 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1447
1448 /*
1449 * Disable this for lowest power if bypassing
1450 * the DAC with an analog signal
1451 */
1452 {"HP Right Out", NULL, "DACR"},
1453 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1454
1455 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1456 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1457 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1458
1459 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1460 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1461 {"RCV Right Out", NULL, "LINMOD Mux"},
1462
1463 {"HPL", NULL, "HP Left Out"},
1464 {"HPR", NULL, "HP Right Out"},
1465 {"SPKL", NULL, "SPK Left Out"},
1466 {"SPKR", NULL, "SPK Right Out"},
1467 {"RCVL", NULL, "RCV Left Out"},
1468 {"RCVR", NULL, "RCV Right Out"},
1469
1470 };
1471
1472 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1473
1474 /* DMIC inputs */
1475 {"DMIC3", NULL, "DMIC3_ENA"},
1476 {"DMIC4", NULL, "DMIC4_ENA"},
1477 {"DMIC3", NULL, "AHPF"},
1478 {"DMIC4", NULL, "AHPF"},
1479
1480 };
1481
1482 static int max98090_add_widgets(struct snd_soc_codec *codec)
1483 {
1484 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1485 struct snd_soc_dapm_context *dapm = &codec->dapm;
1486
1487 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1488 ARRAY_SIZE(max98090_snd_controls));
1489
1490 if (max98090->devtype == MAX98091) {
1491 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1492 ARRAY_SIZE(max98091_snd_controls));
1493 }
1494
1495 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1496 ARRAY_SIZE(max98090_dapm_widgets));
1497
1498 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1499 ARRAY_SIZE(max98090_dapm_routes));
1500
1501 if (max98090->devtype == MAX98091) {
1502 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1503 ARRAY_SIZE(max98091_dapm_widgets));
1504
1505 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1506 ARRAY_SIZE(max98091_dapm_routes));
1507
1508 }
1509
1510 return 0;
1511 }
1512
1513 static const int pclk_rates[] = {
1514 12000000, 12000000, 13000000, 13000000,
1515 16000000, 16000000, 19200000, 19200000
1516 };
1517
1518 static const int lrclk_rates[] = {
1519 8000, 16000, 8000, 16000,
1520 8000, 16000, 8000, 16000
1521 };
1522
1523 static const int user_pclk_rates[] = {
1524 13000000, 13000000
1525 };
1526
1527 static const int user_lrclk_rates[] = {
1528 44100, 48000
1529 };
1530
1531 static const unsigned long long ni_value[] = {
1532 3528, 768
1533 };
1534
1535 static const unsigned long long mi_value[] = {
1536 8125, 1625
1537 };
1538
1539 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1540 {
1541 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1542 unsigned long long ni;
1543 int i;
1544
1545 if (!max98090->sysclk) {
1546 dev_err(codec->dev, "No SYSCLK configured\n");
1547 return;
1548 }
1549
1550 if (!max98090->bclk || !max98090->lrclk) {
1551 dev_err(codec->dev, "No audio clocks configured\n");
1552 return;
1553 }
1554
1555 /* Skip configuration when operating as slave */
1556 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1557 M98090_MAS_MASK)) {
1558 return;
1559 }
1560
1561 /* Check for supported PCLK to LRCLK ratios */
1562 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1563 if ((pclk_rates[i] == max98090->sysclk) &&
1564 (lrclk_rates[i] == max98090->lrclk)) {
1565 dev_dbg(codec->dev,
1566 "Found supported PCLK to LRCLK rates 0x%x\n",
1567 i + 0x8);
1568
1569 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1570 M98090_FREQ_MASK,
1571 (i + 0x8) << M98090_FREQ_SHIFT);
1572 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1573 M98090_USE_M1_MASK, 0);
1574 return;
1575 }
1576 }
1577
1578 /* Check for user calculated MI and NI ratios */
1579 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1580 if ((user_pclk_rates[i] == max98090->sysclk) &&
1581 (user_lrclk_rates[i] == max98090->lrclk)) {
1582 dev_dbg(codec->dev,
1583 "Found user supported PCLK to LRCLK rates\n");
1584 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1585 i, ni_value[i], mi_value[i]);
1586
1587 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1588 M98090_FREQ_MASK, 0);
1589 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1590 M98090_USE_M1_MASK,
1591 1 << M98090_USE_M1_SHIFT);
1592
1593 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1594 (ni_value[i] >> 8) & 0x7F);
1595 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1596 ni_value[i] & 0xFF);
1597 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1598 (mi_value[i] >> 8) & 0x7F);
1599 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1600 mi_value[i] & 0xFF);
1601
1602 return;
1603 }
1604 }
1605
1606 /*
1607 * Calculate based on MI = 65536 (not as good as either method above)
1608 */
1609 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1610 M98090_FREQ_MASK, 0);
1611 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1612 M98090_USE_M1_MASK, 0);
1613
1614 /*
1615 * Configure NI when operating as master
1616 * Note: There is a small, but significant audio quality improvement
1617 * by calculating ni and mi.
1618 */
1619 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1620 * (unsigned long long int)max98090->lrclk;
1621 do_div(ni, (unsigned long long int)max98090->sysclk);
1622 dev_info(codec->dev, "No better method found\n");
1623 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1624 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1625 (ni >> 8) & 0x7F);
1626 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1627 }
1628
1629 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1630 unsigned int fmt)
1631 {
1632 struct snd_soc_codec *codec = codec_dai->codec;
1633 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1634 struct max98090_cdata *cdata;
1635 u8 regval;
1636
1637 max98090->dai_fmt = fmt;
1638 cdata = &max98090->dai[0];
1639
1640 if (fmt != cdata->fmt) {
1641 cdata->fmt = fmt;
1642
1643 regval = 0;
1644 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1645 case SND_SOC_DAIFMT_CBS_CFS:
1646 /* Set to slave mode PLL - MAS mode off */
1647 snd_soc_write(codec,
1648 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1649 snd_soc_write(codec,
1650 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1651 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1652 M98090_USE_M1_MASK, 0);
1653 break;
1654 case SND_SOC_DAIFMT_CBM_CFM:
1655 /* Set to master mode */
1656 if (max98090->tdm_slots == 4) {
1657 /* TDM */
1658 regval |= M98090_MAS_MASK |
1659 M98090_BSEL_64;
1660 } else if (max98090->tdm_slots == 3) {
1661 /* TDM */
1662 regval |= M98090_MAS_MASK |
1663 M98090_BSEL_48;
1664 } else {
1665 /* Few TDM slots, or No TDM */
1666 regval |= M98090_MAS_MASK |
1667 M98090_BSEL_32;
1668 }
1669 break;
1670 case SND_SOC_DAIFMT_CBS_CFM:
1671 case SND_SOC_DAIFMT_CBM_CFS:
1672 default:
1673 dev_err(codec->dev, "DAI clock mode unsupported");
1674 return -EINVAL;
1675 }
1676 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1677
1678 regval = 0;
1679 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1680 case SND_SOC_DAIFMT_I2S:
1681 regval |= M98090_DLY_MASK;
1682 break;
1683 case SND_SOC_DAIFMT_LEFT_J:
1684 break;
1685 case SND_SOC_DAIFMT_RIGHT_J:
1686 regval |= M98090_RJ_MASK;
1687 break;
1688 case SND_SOC_DAIFMT_DSP_A:
1689 /* Not supported mode */
1690 default:
1691 dev_err(codec->dev, "DAI format unsupported");
1692 return -EINVAL;
1693 }
1694
1695 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1696 case SND_SOC_DAIFMT_NB_NF:
1697 break;
1698 case SND_SOC_DAIFMT_NB_IF:
1699 regval |= M98090_WCI_MASK;
1700 break;
1701 case SND_SOC_DAIFMT_IB_NF:
1702 regval |= M98090_BCI_MASK;
1703 break;
1704 case SND_SOC_DAIFMT_IB_IF:
1705 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1706 break;
1707 default:
1708 dev_err(codec->dev, "DAI invert mode unsupported");
1709 return -EINVAL;
1710 }
1711
1712 /*
1713 * This accommodates an inverted logic in the MAX98090 chip
1714 * for Bit Clock Invert (BCI). The inverted logic is only
1715 * seen for the case of TDM mode. The remaining cases have
1716 * normal logic.
1717 */
1718 if (max98090->tdm_slots > 1)
1719 regval ^= M98090_BCI_MASK;
1720
1721 snd_soc_write(codec,
1722 M98090_REG_INTERFACE_FORMAT, regval);
1723 }
1724
1725 return 0;
1726 }
1727
1728 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1729 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1730 {
1731 struct snd_soc_codec *codec = codec_dai->codec;
1732 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1733 struct max98090_cdata *cdata;
1734 cdata = &max98090->dai[0];
1735
1736 if (slots < 0 || slots > 4)
1737 return -EINVAL;
1738
1739 max98090->tdm_slots = slots;
1740 max98090->tdm_width = slot_width;
1741
1742 if (max98090->tdm_slots > 1) {
1743 /* SLOTL SLOTR SLOTDLY */
1744 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1745 0 << M98090_TDM_SLOTL_SHIFT |
1746 1 << M98090_TDM_SLOTR_SHIFT |
1747 0 << M98090_TDM_SLOTDLY_SHIFT);
1748
1749 /* FSW TDM */
1750 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1751 M98090_TDM_MASK,
1752 M98090_TDM_MASK);
1753 }
1754
1755 /*
1756 * Normally advisable to set TDM first, but this permits either order
1757 */
1758 cdata->fmt = 0;
1759 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1760
1761 return 0;
1762 }
1763
1764 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1765 enum snd_soc_bias_level level)
1766 {
1767 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1768 int ret;
1769
1770 switch (level) {
1771 case SND_SOC_BIAS_ON:
1772 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1773 ret = regcache_sync(max98090->regmap);
1774
1775 if (ret != 0) {
1776 dev_err(codec->dev,
1777 "Failed to sync cache: %d\n", ret);
1778 return ret;
1779 }
1780 }
1781
1782 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1783 /*
1784 * Set to normal bias level.
1785 */
1786 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1787 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1788 }
1789 break;
1790
1791 case SND_SOC_BIAS_PREPARE:
1792 break;
1793
1794 case SND_SOC_BIAS_STANDBY:
1795 case SND_SOC_BIAS_OFF:
1796 /* Set internal pull-up to lowest power mode */
1797 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1798 M98090_JDWK_MASK, M98090_JDWK_MASK);
1799 regcache_mark_dirty(max98090->regmap);
1800 break;
1801 }
1802 codec->dapm.bias_level = level;
1803 return 0;
1804 }
1805
1806 static const int comp_pclk_rates[] = {
1807 11289600, 12288000, 12000000, 13000000, 19200000
1808 };
1809
1810 static const int dmic_micclk[] = {
1811 2, 2, 2, 2, 4, 2
1812 };
1813
1814 static const int comp_lrclk_rates[] = {
1815 8000, 16000, 32000, 44100, 48000, 96000
1816 };
1817
1818 static const int dmic_comp[6][6] = {
1819 {7, 8, 3, 3, 3, 3},
1820 {7, 8, 3, 3, 3, 3},
1821 {7, 8, 3, 3, 3, 3},
1822 {7, 8, 3, 1, 1, 1},
1823 {7, 8, 3, 1, 2, 2},
1824 {7, 8, 3, 3, 3, 3}
1825 };
1826
1827 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1828 struct snd_pcm_hw_params *params,
1829 struct snd_soc_dai *dai)
1830 {
1831 struct snd_soc_codec *codec = dai->codec;
1832 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1833 struct max98090_cdata *cdata;
1834 int i, j;
1835
1836 cdata = &max98090->dai[0];
1837 max98090->bclk = snd_soc_params_to_bclk(params);
1838 if (params_channels(params) == 1)
1839 max98090->bclk *= 2;
1840
1841 max98090->lrclk = params_rate(params);
1842
1843 switch (params_format(params)) {
1844 case SNDRV_PCM_FORMAT_S16_LE:
1845 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1846 M98090_WS_MASK, 0);
1847 break;
1848 default:
1849 return -EINVAL;
1850 }
1851
1852 max98090_configure_bclk(codec);
1853
1854 cdata->rate = max98090->lrclk;
1855
1856 /* Update filter mode */
1857 if (max98090->lrclk < 24000)
1858 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1859 M98090_MODE_MASK, 0);
1860 else
1861 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1862 M98090_MODE_MASK, M98090_MODE_MASK);
1863
1864 /* Update sample rate mode */
1865 if (max98090->lrclk < 50000)
1866 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1867 M98090_DHF_MASK, 0);
1868 else
1869 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1870 M98090_DHF_MASK, M98090_DHF_MASK);
1871
1872 /* Check for supported PCLK to LRCLK ratios */
1873 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1874 if (comp_pclk_rates[j] == max98090->sysclk) {
1875 break;
1876 }
1877 }
1878
1879 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1880 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1881 comp_lrclk_rates[i + 1]) / 2) {
1882 break;
1883 }
1884 }
1885
1886 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1887 M98090_MICCLK_MASK,
1888 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1889
1890 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1891 M98090_DMIC_COMP_MASK,
1892 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1893
1894 return 0;
1895 }
1896
1897 /*
1898 * PLL / Sysclk
1899 */
1900 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1901 int clk_id, unsigned int freq, int dir)
1902 {
1903 struct snd_soc_codec *codec = dai->codec;
1904 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1905
1906 /* Requested clock frequency is already setup */
1907 if (freq == max98090->sysclk)
1908 return 0;
1909
1910 /* Setup clocks for slave mode, and using the PLL
1911 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1912 * 0x02 (when master clk is 20MHz to 40MHz)..
1913 * 0x03 (when master clk is 40MHz to 60MHz)..
1914 */
1915 if ((freq >= 10000000) && (freq < 20000000)) {
1916 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1917 M98090_PSCLK_DIV1);
1918 } else if ((freq >= 20000000) && (freq < 40000000)) {
1919 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1920 M98090_PSCLK_DIV2);
1921 } else if ((freq >= 40000000) && (freq < 60000000)) {
1922 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1923 M98090_PSCLK_DIV4);
1924 } else {
1925 dev_err(codec->dev, "Invalid master clock frequency\n");
1926 return -EINVAL;
1927 }
1928
1929 max98090->sysclk = freq;
1930
1931 max98090_configure_bclk(codec);
1932
1933 return 0;
1934 }
1935
1936 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1937 {
1938 struct snd_soc_codec *codec = codec_dai->codec;
1939 int regval;
1940
1941 regval = mute ? M98090_DVM_MASK : 0;
1942 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1943 M98090_DVM_MASK, regval);
1944
1945 return 0;
1946 }
1947
1948 static void max98090_jack_work(struct work_struct *work)
1949 {
1950 struct max98090_priv *max98090 = container_of(work,
1951 struct max98090_priv,
1952 jack_work.work);
1953 struct snd_soc_codec *codec = max98090->codec;
1954 struct snd_soc_dapm_context *dapm = &codec->dapm;
1955 int status = 0;
1956 int reg;
1957
1958 /* Read a second time */
1959 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1960
1961 /* Strong pull up allows mic detection */
1962 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1963 M98090_JDWK_MASK, 0);
1964
1965 msleep(50);
1966
1967 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1968
1969 /* Weak pull up allows only insertion detection */
1970 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1971 M98090_JDWK_MASK, M98090_JDWK_MASK);
1972 } else {
1973 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1974 }
1975
1976 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1977
1978 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
1979 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
1980 dev_dbg(codec->dev, "No Headset Detected\n");
1981
1982 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
1983
1984 status |= 0;
1985
1986 break;
1987
1988 case 0:
1989 if (max98090->jack_state ==
1990 M98090_JACK_STATE_HEADSET) {
1991
1992 dev_dbg(codec->dev,
1993 "Headset Button Down Detected\n");
1994
1995 /*
1996 * max98090_headset_button_event(codec)
1997 * could be defined, then called here.
1998 */
1999
2000 status |= SND_JACK_HEADSET;
2001 status |= SND_JACK_BTN_0;
2002
2003 break;
2004 }
2005
2006 /* Line is reported as Headphone */
2007 /* Nokia Headset is reported as Headphone */
2008 /* Mono Headphone is reported as Headphone */
2009 dev_dbg(codec->dev, "Headphone Detected\n");
2010
2011 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2012
2013 status |= SND_JACK_HEADPHONE;
2014
2015 break;
2016
2017 case M98090_JKSNS_MASK:
2018 dev_dbg(codec->dev, "Headset Detected\n");
2019
2020 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2021
2022 status |= SND_JACK_HEADSET;
2023
2024 break;
2025
2026 default:
2027 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2028 break;
2029 }
2030
2031 snd_soc_jack_report(max98090->jack, status,
2032 SND_JACK_HEADSET | SND_JACK_BTN_0);
2033
2034 snd_soc_dapm_sync(dapm);
2035 }
2036
2037 static irqreturn_t max98090_interrupt(int irq, void *data)
2038 {
2039 struct snd_soc_codec *codec = data;
2040 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2041 int ret;
2042 unsigned int mask;
2043 unsigned int active;
2044
2045 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2046
2047 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2048
2049 if (ret != 0) {
2050 dev_err(codec->dev,
2051 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2052 ret);
2053 return IRQ_NONE;
2054 }
2055
2056 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2057
2058 if (ret != 0) {
2059 dev_err(codec->dev,
2060 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2061 ret);
2062 return IRQ_NONE;
2063 }
2064
2065 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2066 active, mask, active & mask);
2067
2068 active &= mask;
2069
2070 if (!active)
2071 return IRQ_NONE;
2072
2073 if (active & M98090_CLD_MASK)
2074 dev_err(codec->dev, "M98090_CLD_MASK\n");
2075
2076 if (active & M98090_SLD_MASK)
2077 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2078
2079 if (active & M98090_ULK_MASK)
2080 dev_err(codec->dev, "M98090_ULK_MASK\n");
2081
2082 if (active & M98090_JDET_MASK) {
2083 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2084
2085 pm_wakeup_event(codec->dev, 100);
2086
2087 schedule_delayed_work(&max98090->jack_work,
2088 msecs_to_jiffies(100));
2089 }
2090
2091 if (active & M98090_DRCACT_MASK)
2092 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2093
2094 if (active & M98090_DRCCLP_MASK)
2095 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2096
2097 return IRQ_HANDLED;
2098 }
2099
2100 /**
2101 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2102 *
2103 * @codec: MAX98090 codec
2104 * @jack: jack to report detection events on
2105 *
2106 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2107 * being used to bring out signals to the processor then only platform
2108 * data configuration is needed for MAX98090 and processor GPIOs should
2109 * be configured using snd_soc_jack_add_gpios() instead.
2110 *
2111 * If no jack is supplied detection will be disabled.
2112 */
2113 int max98090_mic_detect(struct snd_soc_codec *codec,
2114 struct snd_soc_jack *jack)
2115 {
2116 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2117
2118 dev_dbg(codec->dev, "max98090_mic_detect\n");
2119
2120 max98090->jack = jack;
2121 if (jack) {
2122 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2123 M98090_IJDET_MASK,
2124 1 << M98090_IJDET_SHIFT);
2125 } else {
2126 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2127 M98090_IJDET_MASK,
2128 0);
2129 }
2130
2131 /* Send an initial empty report */
2132 snd_soc_jack_report(max98090->jack, 0,
2133 SND_JACK_HEADSET | SND_JACK_BTN_0);
2134
2135 schedule_delayed_work(&max98090->jack_work,
2136 msecs_to_jiffies(100));
2137
2138 return 0;
2139 }
2140 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2141
2142 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2143 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2144
2145 static struct snd_soc_dai_ops max98090_dai_ops = {
2146 .set_sysclk = max98090_dai_set_sysclk,
2147 .set_fmt = max98090_dai_set_fmt,
2148 .set_tdm_slot = max98090_set_tdm_slot,
2149 .hw_params = max98090_dai_hw_params,
2150 .digital_mute = max98090_dai_digital_mute,
2151 };
2152
2153 static struct snd_soc_dai_driver max98090_dai[] = {
2154 {
2155 .name = "HiFi",
2156 .playback = {
2157 .stream_name = "HiFi Playback",
2158 .channels_min = 2,
2159 .channels_max = 2,
2160 .rates = MAX98090_RATES,
2161 .formats = MAX98090_FORMATS,
2162 },
2163 .capture = {
2164 .stream_name = "HiFi Capture",
2165 .channels_min = 1,
2166 .channels_max = 2,
2167 .rates = MAX98090_RATES,
2168 .formats = MAX98090_FORMATS,
2169 },
2170 .ops = &max98090_dai_ops,
2171 }
2172 };
2173
2174 static void max98090_handle_pdata(struct snd_soc_codec *codec)
2175 {
2176 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2177 struct max98090_pdata *pdata = max98090->pdata;
2178
2179 if (!pdata) {
2180 dev_err(codec->dev, "No platform data\n");
2181 return;
2182 }
2183
2184 }
2185
2186 static int max98090_probe(struct snd_soc_codec *codec)
2187 {
2188 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2189 struct max98090_cdata *cdata;
2190 int ret = 0;
2191
2192 dev_dbg(codec->dev, "max98090_probe\n");
2193
2194 max98090->codec = codec;
2195
2196 codec->control_data = max98090->regmap;
2197
2198 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
2199 if (ret != 0) {
2200 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2201 return ret;
2202 }
2203
2204 /* Reset the codec, the DSP core, and disable all interrupts */
2205 max98090_reset(max98090);
2206
2207 /* Initialize private data */
2208
2209 max98090->sysclk = (unsigned)-1;
2210
2211 cdata = &max98090->dai[0];
2212 cdata->rate = (unsigned)-1;
2213 cdata->fmt = (unsigned)-1;
2214
2215 max98090->lin_state = 0;
2216 max98090->pa1en = 0;
2217 max98090->pa2en = 0;
2218 max98090->extmic_mux = 0;
2219
2220 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2221 if (ret < 0) {
2222 dev_err(codec->dev, "Failed to read device revision: %d\n",
2223 ret);
2224 goto err_access;
2225 }
2226
2227 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2228 max98090->devtype = MAX98090;
2229 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2230 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2231 max98090->devtype = MAX98091;
2232 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2233 } else {
2234 max98090->devtype = MAX98090;
2235 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2236 }
2237
2238 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2239
2240 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2241
2242 /* Enable jack detection */
2243 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2244 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2245
2246 /* Register for interrupts */
2247 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2248
2249 ret = request_threaded_irq(max98090->irq, NULL,
2250 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2251 "max98090_interrupt", codec);
2252 if (ret < 0) {
2253 dev_err(codec->dev, "request_irq failed: %d\n",
2254 ret);
2255 }
2256
2257 /*
2258 * Clear any old interrupts.
2259 * An old interrupt ocurring prior to installing the ISR
2260 * can keep a new interrupt from generating a trigger.
2261 */
2262 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2263
2264 /* High Performance is default */
2265 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2266 M98090_DACHP_MASK,
2267 1 << M98090_DACHP_SHIFT);
2268 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2269 M98090_PERFMODE_MASK,
2270 0 << M98090_PERFMODE_SHIFT);
2271 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2272 M98090_ADCHP_MASK,
2273 1 << M98090_ADCHP_SHIFT);
2274
2275 /* Turn on VCM bandgap reference */
2276 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2277 M98090_VCM_MODE_MASK);
2278
2279 max98090_handle_pdata(codec);
2280
2281 max98090_add_widgets(codec);
2282
2283 err_access:
2284 return ret;
2285 }
2286
2287 static int max98090_remove(struct snd_soc_codec *codec)
2288 {
2289 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2290
2291 cancel_delayed_work_sync(&max98090->jack_work);
2292
2293 return 0;
2294 }
2295
2296 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2297 .probe = max98090_probe,
2298 .remove = max98090_remove,
2299 .set_bias_level = max98090_set_bias_level,
2300 };
2301
2302 static const struct regmap_config max98090_regmap = {
2303 .reg_bits = 8,
2304 .val_bits = 8,
2305
2306 .max_register = MAX98090_MAX_REGISTER,
2307 .reg_defaults = max98090_reg,
2308 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2309 .volatile_reg = max98090_volatile_register,
2310 .readable_reg = max98090_readable_register,
2311 .cache_type = REGCACHE_RBTREE,
2312 };
2313
2314 static int max98090_i2c_probe(struct i2c_client *i2c,
2315 const struct i2c_device_id *id)
2316 {
2317 struct max98090_priv *max98090;
2318 int ret;
2319
2320 pr_debug("max98090_i2c_probe\n");
2321
2322 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2323 GFP_KERNEL);
2324 if (max98090 == NULL)
2325 return -ENOMEM;
2326
2327 max98090->devtype = id->driver_data;
2328 i2c_set_clientdata(i2c, max98090);
2329 max98090->control_data = i2c;
2330 max98090->pdata = i2c->dev.platform_data;
2331 max98090->irq = i2c->irq;
2332
2333 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2334 if (IS_ERR(max98090->regmap)) {
2335 ret = PTR_ERR(max98090->regmap);
2336 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2337 goto err_enable;
2338 }
2339
2340 ret = snd_soc_register_codec(&i2c->dev,
2341 &soc_codec_dev_max98090, max98090_dai,
2342 ARRAY_SIZE(max98090_dai));
2343 err_enable:
2344 return ret;
2345 }
2346
2347 static int max98090_i2c_remove(struct i2c_client *client)
2348 {
2349 snd_soc_unregister_codec(&client->dev);
2350 return 0;
2351 }
2352
2353 #ifdef CONFIG_PM_RUNTIME
2354 static int max98090_runtime_resume(struct device *dev)
2355 {
2356 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2357
2358 regcache_cache_only(max98090->regmap, false);
2359
2360 regcache_sync(max98090->regmap);
2361
2362 return 0;
2363 }
2364
2365 static int max98090_runtime_suspend(struct device *dev)
2366 {
2367 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2368
2369 regcache_cache_only(max98090->regmap, true);
2370
2371 return 0;
2372 }
2373 #endif
2374
2375 static const struct dev_pm_ops max98090_pm = {
2376 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2377 max98090_runtime_resume, NULL)
2378 };
2379
2380 static const struct i2c_device_id max98090_i2c_id[] = {
2381 { "max98090", MAX98090 },
2382 { }
2383 };
2384 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2385
2386 static struct i2c_driver max98090_i2c_driver = {
2387 .driver = {
2388 .name = "max98090",
2389 .owner = THIS_MODULE,
2390 .pm = &max98090_pm,
2391 },
2392 .probe = max98090_i2c_probe,
2393 .remove = max98090_i2c_remove,
2394 .id_table = max98090_i2c_id,
2395 };
2396
2397 module_i2c_driver(max98090_i2c_driver);
2398
2399 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2400 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2401 MODULE_LICENSE("GPL");
Linux with added FPC-III support