sound/soc/codecs/tlv320aic32x4.c

   1 /*
   2  * linux/sound/soc/codecs/tlv320aic32x4.c
   3  *
   4  * Copyright 2011 Vista Silicon S.L.
   5  *
   6  * Author: Javier Martin <javier.martin@vista-silicon.com>
   7  *
   8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  23  * MA 02110-1301, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/gpio.h>
  32 #include <linux/i2c.h>
  33 #include <linux/cdev.h>
  34 #include <linux/slab.h>
  35
  36 #include <sound/tlv320aic32x4.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/pcm_params.h>
  40 #include <sound/soc.h>
  41 #include <sound/soc-dapm.h>
  42 #include <sound/initval.h>
  43 #include <sound/tlv.h>
  44
  45 #include "tlv320aic32x4.h"
  46
  47 struct aic32x4_rate_divs {
  48         u32 mclk;
  49         u32 rate;
  50         u8 p_val;
  51         u8 pll_j;
  52         u16 pll_d;
  53         u16 dosr;
  54         u8 ndac;
  55         u8 mdac;
  56         u8 aosr;
  57         u8 nadc;
  58         u8 madc;
  59         u8 blck_N;
  60 };
  61
  62 struct aic32x4_priv {
  63         u32 sysclk;
  64         u8 page_no;
  65         void *control_data;
  66         u32 power_cfg;
  67         u32 micpga_routing;
  68         bool swapdacs;
  69         int rstn_gpio;
  70 };
  71
  72 /* 0dB min, 1dB steps */
  73 static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
  74 /* 0dB min, 0.5dB steps */
  75 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
  76
  77 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
  78         SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
  79                         AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
  80         SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
  81                         AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
  82         SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
  83                         AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
  84         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
  85                         AIC32X4_HPRGAIN, 6, 0x01, 1),
  86         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
  87                         AIC32X4_LORGAIN, 6, 0x01, 1),
  88         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
  89                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
  90
  91         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
  92         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
  93
  94         SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
  95                         AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
  96         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
  97                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
  98
  99         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
 100
 101         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 102         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 103         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 104                         4, 0x07, 0),
 105         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 106                         0, 0x03, 0),
 107         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 108                         6, 0x03, 0),
 109         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 110                         1, 0x1F, 0),
 111         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 112                         0, 0x7F, 0),
 113         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 114                         3, 0x1F, 0),
 115         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 116                         3, 0x1F, 0),
 117         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 118                         0, 0x1F, 0),
 119         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 120                         0, 0x0F, 0),
 121 };
 122
 123 static const struct aic32x4_rate_divs aic32x4_divs[] = {
 124         /* 8k rate */
 125         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
 126         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
 127         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
 128         /* 11.025k rate */
 129         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
 130         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
 131         /* 16k rate */
 132         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
 133         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
 134         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
 135         /* 22.05k rate */
 136         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
 137         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
 138         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
 139         /* 32k rate */
 140         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
 141         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
 142         /* 44.1k rate */
 143         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
 144         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
 145         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
 146         /* 48k rate */
 147         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
 148         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
 149         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
 150 };
 151
 152 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 153         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 154         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 155 };
 156
 157 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 158         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 159         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 160 };
 161
 162 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 163         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 164 };
 165
 166 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 167         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 168 };
 169
 170 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
 171         SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
 172         SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
 173         SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
 174 };
 175
 176 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
 177         SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
 178         SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
 179         SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
 180 };
 181
 182 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 183         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 184         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 185                            &hpl_output_mixer_controls[0],
 186                            ARRAY_SIZE(hpl_output_mixer_controls)),
 187         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 188
 189         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 190                            &lol_output_mixer_controls[0],
 191                            ARRAY_SIZE(lol_output_mixer_controls)),
 192         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 193
 194         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 195         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 196                            &hpr_output_mixer_controls[0],
 197                            ARRAY_SIZE(hpr_output_mixer_controls)),
 198         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 199         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 200                            &lor_output_mixer_controls[0],
 201                            ARRAY_SIZE(lor_output_mixer_controls)),
 202         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 203         SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
 204                            &left_input_mixer_controls[0],
 205                            ARRAY_SIZE(left_input_mixer_controls)),
 206         SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
 207                            &right_input_mixer_controls[0],
 208                            ARRAY_SIZE(right_input_mixer_controls)),
 209         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 210         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 211         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
 212
 213         SND_SOC_DAPM_OUTPUT("HPL"),
 214         SND_SOC_DAPM_OUTPUT("HPR"),
 215         SND_SOC_DAPM_OUTPUT("LOL"),
 216         SND_SOC_DAPM_OUTPUT("LOR"),
 217         SND_SOC_DAPM_INPUT("IN1_L"),
 218         SND_SOC_DAPM_INPUT("IN1_R"),
 219         SND_SOC_DAPM_INPUT("IN2_L"),
 220         SND_SOC_DAPM_INPUT("IN2_R"),
 221         SND_SOC_DAPM_INPUT("IN3_L"),
 222         SND_SOC_DAPM_INPUT("IN3_R"),
 223 };
 224
 225 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 226         /* Left Output */
 227         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 228         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 229
 230         {"HPL Power", NULL, "HPL Output Mixer"},
 231         {"HPL", NULL, "HPL Power"},
 232
 233         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 234
 235         {"LOL Power", NULL, "LOL Output Mixer"},
 236         {"LOL", NULL, "LOL Power"},
 237
 238         /* Right Output */
 239         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 240         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 241
 242         {"HPR Power", NULL, "HPR Output Mixer"},
 243         {"HPR", NULL, "HPR Power"},
 244
 245         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 246
 247         {"LOR Power", NULL, "LOR Output Mixer"},
 248         {"LOR", NULL, "LOR Power"},
 249
 250         /* Left input */
 251         {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
 252         {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
 253         {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
 254
 255         {"Left ADC", NULL, "Left Input Mixer"},
 256
 257         /* Right Input */
 258         {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
 259         {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
 260         {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
 261
 262         {"Right ADC", NULL, "Right Input Mixer"},
 263 };
 264
 265 static inline int aic32x4_change_page(struct snd_soc_codec *codec,
 266                                         unsigned int new_page)
 267 {
 268         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 269         u8 data[2];
 270         int ret;
 271
 272         data[0] = 0x00;
 273         data[1] = new_page & 0xff;
 274
 275         ret = codec->hw_write(codec->control_data, data, 2);
 276         if (ret == 2) {
 277                 aic32x4->page_no = new_page;
 278                 return 0;
 279         } else {
 280                 return ret;
 281         }
 282 }
 283
 284 static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg,
 285                                 unsigned int val)
 286 {
 287         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 288         unsigned int page = reg / 128;
 289         unsigned int fixed_reg = reg % 128;
 290         u8 data[2];
 291         int ret;
 292
 293         /* A write to AIC32X4_PSEL is really a non-explicit page change */
 294         if (reg == AIC32X4_PSEL)
 295                 return aic32x4_change_page(codec, val);
 296
 297         if (aic32x4->page_no != page) {
 298                 ret = aic32x4_change_page(codec, page);
 299                 if (ret != 0)
 300                         return ret;
 301         }
 302
 303         data[0] = fixed_reg & 0xff;
 304         data[1] = val & 0xff;
 305
 306         if (codec->hw_write(codec->control_data, data, 2) == 2)
 307                 return 0;
 308         else
 309                 return -EIO;
 310 }
 311
 312 static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg)
 313 {
 314         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 315         unsigned int page = reg / 128;
 316         unsigned int fixed_reg = reg % 128;
 317         int ret;
 318
 319         if (aic32x4->page_no != page) {
 320                 ret = aic32x4_change_page(codec, page);
 321                 if (ret != 0)
 322                         return ret;
 323         }
 324         return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff);
 325 }
 326
 327 static inline int aic32x4_get_divs(int mclk, int rate)
 328 {
 329         int i;
 330
 331         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 332                 if ((aic32x4_divs[i].rate == rate)
 333                     && (aic32x4_divs[i].mclk == mclk)) {
 334                         return i;
 335                 }
 336         }
 337         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
 338         return -EINVAL;
 339 }
 340
 341 static int aic32x4_add_widgets(struct snd_soc_codec *codec)
 342 {
 343         snd_soc_dapm_new_controls(&codec->dapm, aic32x4_dapm_widgets,
 344                                   ARRAY_SIZE(aic32x4_dapm_widgets));
 345
 346         snd_soc_dapm_add_routes(&codec->dapm, aic32x4_dapm_routes,
 347                                 ARRAY_SIZE(aic32x4_dapm_routes));
 348
 349         snd_soc_dapm_new_widgets(&codec->dapm);
 350         return 0;
 351 }
 352
 353 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 354                                   int clk_id, unsigned int freq, int dir)
 355 {
 356         struct snd_soc_codec *codec = codec_dai->codec;
 357         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 358
 359         switch (freq) {
 360         case AIC32X4_FREQ_12000000:
 361         case AIC32X4_FREQ_24000000:
 362         case AIC32X4_FREQ_25000000:
 363                 aic32x4->sysclk = freq;
 364                 return 0;
 365         }
 366         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
 367         return -EINVAL;
 368 }
 369
 370 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 371 {
 372         struct snd_soc_codec *codec = codec_dai->codec;
 373         u8 iface_reg_1;
 374         u8 iface_reg_2;
 375         u8 iface_reg_3;
 376
 377         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
 378         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
 379         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
 380         iface_reg_2 = 0;
 381         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
 382         iface_reg_3 = iface_reg_3 & ~(1 << 3);
 383
 384         /* set master/slave audio interface */
 385         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 386         case SND_SOC_DAIFMT_CBM_CFM:
 387                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 388                 break;
 389         case SND_SOC_DAIFMT_CBS_CFS:
 390                 break;
 391         default:
 392                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 393                 return -EINVAL;
 394         }
 395
 396         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 397         case SND_SOC_DAIFMT_I2S:
 398                 break;
 399         case SND_SOC_DAIFMT_DSP_A:
 400                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 401                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 402                 iface_reg_2 = 0x01; /* add offset 1 */
 403                 break;
 404         case SND_SOC_DAIFMT_DSP_B:
 405                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 406                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 407                 break;
 408         case SND_SOC_DAIFMT_RIGHT_J:
 409                 iface_reg_1 |=
 410                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 411                 break;
 412         case SND_SOC_DAIFMT_LEFT_J:
 413                 iface_reg_1 |=
 414                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 415                 break;
 416         default:
 417                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 418                 return -EINVAL;
 419         }
 420
 421         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
 422         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
 423         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
 424         return 0;
 425 }
 426
 427 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 428                              struct snd_pcm_hw_params *params,
 429                              struct snd_soc_dai *dai)
 430 {
 431         struct snd_soc_codec *codec = dai->codec;
 432         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 433         u8 data;
 434         int i;
 435
 436         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
 437         if (i < 0) {
 438                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
 439                 return i;
 440         }
 441
 442         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
 443         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
 444         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
 445
 446         /* We will fix R value to 1 and will make P & J=K.D as varialble */
 447         data = snd_soc_read(codec, AIC32X4_PLLPR);
 448         data &= ~(7 << 4);
 449         snd_soc_write(codec, AIC32X4_PLLPR,
 450                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
 451
 452         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 453
 454         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 455         snd_soc_write(codec, AIC32X4_PLLDLSB,
 456                       (aic32x4_divs[i].pll_d & 0xff));
 457
 458         /* NDAC divider value */
 459         data = snd_soc_read(codec, AIC32X4_NDAC);
 460         data &= ~(0x7f);
 461         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
 462
 463         /* MDAC divider value */
 464         data = snd_soc_read(codec, AIC32X4_MDAC);
 465         data &= ~(0x7f);
 466         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
 467
 468         /* DOSR MSB & LSB values */
 469         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 470         snd_soc_write(codec, AIC32X4_DOSRLSB,
 471                       (aic32x4_divs[i].dosr & 0xff));
 472
 473         /* NADC divider value */
 474         data = snd_soc_read(codec, AIC32X4_NADC);
 475         data &= ~(0x7f);
 476         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
 477
 478         /* MADC divider value */
 479         data = snd_soc_read(codec, AIC32X4_MADC);
 480         data &= ~(0x7f);
 481         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
 482
 483         /* AOSR value */
 484         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 485
 486         /* BCLK N divider */
 487         data = snd_soc_read(codec, AIC32X4_BCLKN);
 488         data &= ~(0x7f);
 489         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
 490
 491         data = snd_soc_read(codec, AIC32X4_IFACE1);
 492         data = data & ~(3 << 4);
 493         switch (params_format(params)) {
 494         case SNDRV_PCM_FORMAT_S16_LE:
 495                 break;
 496         case SNDRV_PCM_FORMAT_S20_3LE:
 497                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
 498                 break;
 499         case SNDRV_PCM_FORMAT_S24_LE:
 500                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
 501                 break;
 502         case SNDRV_PCM_FORMAT_S32_LE:
 503                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
 504                 break;
 505         }
 506         snd_soc_write(codec, AIC32X4_IFACE1, data);
 507
 508         return 0;
 509 }
 510
 511 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
 512 {
 513         struct snd_soc_codec *codec = dai->codec;
 514         u8 dac_reg;
 515
 516         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
 517         if (mute)
 518                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
 519         else
 520                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
 521         return 0;
 522 }
 523
 524 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 525                                   enum snd_soc_bias_level level)
 526 {
 527         switch (level) {
 528         case SND_SOC_BIAS_ON:
 529                 /* Switch on PLL */
 530                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 531                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
 532
 533                 /* Switch on NDAC Divider */
 534                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 535                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
 536
 537                 /* Switch on MDAC Divider */
 538                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 539                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
 540
 541                 /* Switch on NADC Divider */
 542                 snd_soc_update_bits(codec, AIC32X4_NADC,
 543                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
 544
 545                 /* Switch on MADC Divider */
 546                 snd_soc_update_bits(codec, AIC32X4_MADC,
 547                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
 548
 549                 /* Switch on BCLK_N Divider */
 550                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 551                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 552                 break;
 553         case SND_SOC_BIAS_PREPARE:
 554                 break;
 555         case SND_SOC_BIAS_STANDBY:
 556                 /* Switch off PLL */
 557                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 558                                     AIC32X4_PLLEN, 0);
 559
 560                 /* Switch off NDAC Divider */
 561                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 562                                     AIC32X4_NDACEN, 0);
 563
 564                 /* Switch off MDAC Divider */
 565                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 566                                     AIC32X4_MDACEN, 0);
 567
 568                 /* Switch off NADC Divider */
 569                 snd_soc_update_bits(codec, AIC32X4_NADC,
 570                                     AIC32X4_NADCEN, 0);
 571
 572                 /* Switch off MADC Divider */
 573                 snd_soc_update_bits(codec, AIC32X4_MADC,
 574                                     AIC32X4_MADCEN, 0);
 575
 576                 /* Switch off BCLK_N Divider */
 577                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 578                                     AIC32X4_BCLKEN, 0);
 579                 break;
 580         case SND_SOC_BIAS_OFF:
 581                 break;
 582         }
 583         codec->dapm.bias_level = level;
 584         return 0;
 585 }
 586
 587 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
 588 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 589                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 590
 591 static const struct snd_soc_dai_ops aic32x4_ops = {
 592         .hw_params = aic32x4_hw_params,
 593         .digital_mute = aic32x4_mute,
 594         .set_fmt = aic32x4_set_dai_fmt,
 595         .set_sysclk = aic32x4_set_dai_sysclk,
 596 };
 597
 598 static struct snd_soc_dai_driver aic32x4_dai = {
 599         .name = "tlv320aic32x4-hifi",
 600         .playback = {
 601                      .stream_name = "Playback",
 602                      .channels_min = 1,
 603                      .channels_max = 2,
 604                      .rates = AIC32X4_RATES,
 605                      .formats = AIC32X4_FORMATS,},
 606         .capture = {
 607                     .stream_name = "Capture",
 608                     .channels_min = 1,
 609                     .channels_max = 2,
 610                     .rates = AIC32X4_RATES,
 611                     .formats = AIC32X4_FORMATS,},
 612         .ops = &aic32x4_ops,
 613         .symmetric_rates = 1,
 614 };
 615
 616 static int aic32x4_suspend(struct snd_soc_codec *codec)
 617 {
 618         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 619         return 0;
 620 }
 621
 622 static int aic32x4_resume(struct snd_soc_codec *codec)
 623 {
 624         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 625         return 0;
 626 }
 627
 628 static int aic32x4_probe(struct snd_soc_codec *codec)
 629 {
 630         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 631         u32 tmp_reg;
 632         int ret;
 633
 634         codec->hw_write = (hw_write_t) i2c_master_send;
 635         codec->control_data = aic32x4->control_data;
 636
 637         if (aic32x4->rstn_gpio >= 0) {
 638                 ret = devm_gpio_request_one(codec->dev, aic32x4->rstn_gpio,
 639                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
 640                 if (ret != 0)
 641                         return ret;
 642                 ndelay(10);
 643                 gpio_set_value(aic32x4->rstn_gpio, 1);
 644         }
 645
 646         snd_soc_write(codec, AIC32X4_RESET, 0x01);
 647
 648         /* Power platform configuration */
 649         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 650                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 651                                                       AIC32X4_MICBIAS_2075V);
 652         }
 653         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
 654                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 655         }
 656
 657         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
 658                         AIC32X4_LDOCTLEN : 0;
 659         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
 660
 661         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
 662         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
 663                 tmp_reg |= AIC32X4_LDOIN_18_36;
 664         }
 665         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
 666                 tmp_reg |= AIC32X4_LDOIN2HP;
 667         }
 668         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 669
 670         /* Do DACs need to be swapped? */
 671         if (aic32x4->swapdacs) {
 672                 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN);
 673         } else {
 674                 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN);
 675         }
 676
 677         /* Mic PGA routing */
 678         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
 679                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
 680         }
 681         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
 682                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
 683         }
 684
 685         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 686         snd_soc_add_codec_controls(codec, aic32x4_snd_controls,
 687                              ARRAY_SIZE(aic32x4_snd_controls));
 688         aic32x4_add_widgets(codec);
 689
 690         /*
 691          * Workaround: for an unknown reason, the ADC needs to be powered up
 692          * and down for the first capture to work properly. It seems related to
 693          * a HW BUG or some kind of behavior not documented in the datasheet.
 694          */
 695         tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
 696         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
 697                                 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
 698         snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
 699
 700         return 0;
 701 }
 702
 703 static int aic32x4_remove(struct snd_soc_codec *codec)
 704 {
 705         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 706         return 0;
 707 }
 708
 709 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
 710         .read = aic32x4_read,
 711         .write = aic32x4_write,
 712         .probe = aic32x4_probe,
 713         .remove = aic32x4_remove,
 714         .suspend = aic32x4_suspend,
 715         .resume = aic32x4_resume,
 716         .set_bias_level = aic32x4_set_bias_level,
 717 };
 718
 719 static int aic32x4_i2c_probe(struct i2c_client *i2c,
 720                              const struct i2c_device_id *id)
 721 {
 722         struct aic32x4_pdata *pdata = i2c->dev.platform_data;
 723         struct aic32x4_priv *aic32x4;
 724         int ret;
 725
 726         aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
 727                                GFP_KERNEL);
 728         if (aic32x4 == NULL)
 729                 return -ENOMEM;
 730
 731         aic32x4->control_data = i2c;
 732         i2c_set_clientdata(i2c, aic32x4);
 733
 734         if (pdata) {
 735                 aic32x4->power_cfg = pdata->power_cfg;
 736                 aic32x4->swapdacs = pdata->swapdacs;
 737                 aic32x4->micpga_routing = pdata->micpga_routing;
 738                 aic32x4->rstn_gpio = pdata->rstn_gpio;
 739         } else {
 740                 aic32x4->power_cfg = 0;
 741                 aic32x4->swapdacs = false;
 742                 aic32x4->micpga_routing = 0;
 743                 aic32x4->rstn_gpio = -1;
 744         }
 745
 746         ret = snd_soc_register_codec(&i2c->dev,
 747                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
 748         return ret;
 749 }
 750
 751 static int aic32x4_i2c_remove(struct i2c_client *client)
 752 {
 753         snd_soc_unregister_codec(&client->dev);
 754         return 0;
 755 }
 756
 757 static const struct i2c_device_id aic32x4_i2c_id[] = {
 758         { "tlv320aic32x4", 0 },
 759         { }
 760 };
 761 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
 762
 763 static struct i2c_driver aic32x4_i2c_driver = {
 764         .driver = {
 765                 .name = "tlv320aic32x4",
 766                 .owner = THIS_MODULE,
 767         },
 768         .probe =    aic32x4_i2c_probe,
 769         .remove =   aic32x4_i2c_remove,
 770         .id_table = aic32x4_i2c_id,
 771 };
 772
 773 module_i2c_driver(aic32x4_i2c_driver);
 774
 775 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
 776 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
 777 MODULE_LICENSE("GPL");