drivers/scsi/aacraid/aacraid.h

   1 /*
   2  *      Adaptec AAC series RAID controller driver
   3  *      (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
   4  *
   5  * based on the old aacraid driver that is..
   6  * Adaptec aacraid device driver for Linux.
   7  *
   8  * Copyright (c) 2000-2010 Adaptec, Inc.
   9  *               2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
  10  *               2016-2017 Microsemi Corp. (aacraid@microsemi.com)
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; see the file COPYING.  If not, write to
  24  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Module Name:
  27  *  aacraid.h
  28  *
  29  * Abstract: Contains all routines for control of the aacraid driver
  30  *
  31  */
  32
  33 #ifndef _AACRAID_H_
  34 #define _AACRAID_H_
  35 #ifndef dprintk
  36 # define dprintk(x)
  37 #endif
  38 /* eg: if (nblank(dprintk(x))) */
  39 #define _nblank(x) #x
  40 #define nblank(x) _nblank(x)[0]
  41
  42 #include <linux/interrupt.h>
  43 #include <linux/completion.h>
  44 #include <linux/pci.h>
  45 #include <scsi/scsi_host.h>
  46
  47 /*------------------------------------------------------------------------------
  48  *              D E F I N E S
  49  *----------------------------------------------------------------------------*/
  50
  51 #define AAC_MAX_MSIX            32      /* vectors */
  52 #define AAC_PCI_MSI_ENABLE      0x8000
  53
  54 enum {
  55         AAC_ENABLE_INTERRUPT    = 0x0,
  56         AAC_DISABLE_INTERRUPT,
  57         AAC_ENABLE_MSIX,
  58         AAC_DISABLE_MSIX,
  59         AAC_CLEAR_AIF_BIT,
  60         AAC_CLEAR_SYNC_BIT,
  61         AAC_ENABLE_INTX
  62 };
  63
  64 #define AAC_INT_MODE_INTX               (1<<0)
  65 #define AAC_INT_MODE_MSI                (1<<1)
  66 #define AAC_INT_MODE_AIF                (1<<2)
  67 #define AAC_INT_MODE_SYNC               (1<<3)
  68 #define AAC_INT_MODE_MSIX               (1<<16)
  69
  70 #define AAC_INT_ENABLE_TYPE1_INTX       0xfffffffb
  71 #define AAC_INT_ENABLE_TYPE1_MSIX       0xfffffffa
  72 #define AAC_INT_DISABLE_ALL             0xffffffff
  73
  74 /* Bit definitions in IOA->Host Interrupt Register */
  75 #define PMC_TRANSITION_TO_OPERATIONAL   (1<<31)
  76 #define PMC_IOARCB_TRANSFER_FAILED      (1<<28)
  77 #define PMC_IOA_UNIT_CHECK              (1<<27)
  78 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
  79 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
  80 #define PMC_IOARRIN_LOST                (1<<4)
  81 #define PMC_SYSTEM_BUS_MMIO_ERROR       (1<<3)
  82 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
  83 #define PMC_HOST_RRQ_VALID              (1<<1)
  84 #define PMC_OPERATIONAL_STATUS          (1<<31)
  85 #define PMC_ALLOW_MSIX_VECTOR0          (1<<0)
  86
  87 #define PMC_IOA_ERROR_INTERRUPTS        (PMC_IOARCB_TRANSFER_FAILED | \
  88                                          PMC_IOA_UNIT_CHECK | \
  89                                          PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
  90                                          PMC_IOARRIN_LOST | \
  91                                          PMC_SYSTEM_BUS_MMIO_ERROR | \
  92                                          PMC_IOA_PROCESSOR_IN_ERROR_STATE)
  93
  94 #define PMC_ALL_INTERRUPT_BITS          (PMC_IOA_ERROR_INTERRUPTS | \
  95                                          PMC_HOST_RRQ_VALID | \
  96                                          PMC_TRANSITION_TO_OPERATIONAL | \
  97                                          PMC_ALLOW_MSIX_VECTOR0)
  98 #define PMC_GLOBAL_INT_BIT2             0x00000004
  99 #define PMC_GLOBAL_INT_BIT0             0x00000001
 100
 101 #ifndef AAC_DRIVER_BUILD
 102 # define AAC_DRIVER_BUILD 50877
 103 # define AAC_DRIVER_BRANCH "-custom"
 104 #endif
 105 #define MAXIMUM_NUM_CONTAINERS  32
 106
 107 #define AAC_NUM_MGT_FIB         8
 108 #define AAC_NUM_IO_FIB          (1024 - AAC_NUM_MGT_FIB)
 109 #define AAC_NUM_FIB             (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
 110
 111 #define AAC_MAX_LUN             256
 112
 113 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
 114 #define AAC_MAX_32BIT_SGBCOUNT  ((unsigned short)256)
 115
 116 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
 117
 118 #define AAC_MAX_NATIVE_TARGETS          1024
 119 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
 120 #define AAC_MAX_BUSES                   5
 121 #define AAC_MAX_TARGETS         256
 122 #define AAC_BUS_TARGET_LOOP             (AAC_MAX_BUSES * AAC_MAX_TARGETS)
 123 #define AAC_MAX_NATIVE_SIZE             2048
 124 #define FW_ERROR_BUFFER_SIZE            512
 125
 126 #define get_bus_number(x)       (x/AAC_MAX_TARGETS)
 127 #define get_target_number(x)    (x%AAC_MAX_TARGETS)
 128
 129 /* Thor AIF events */
 130 #define SA_AIF_HOTPLUG                  (1<<1)
 131 #define SA_AIF_HARDWARE         (1<<2)
 132 #define SA_AIF_PDEV_CHANGE              (1<<4)
 133 #define SA_AIF_LDEV_CHANGE              (1<<5)
 134 #define SA_AIF_BPSTAT_CHANGE            (1<<30)
 135 #define SA_AIF_BPCFG_CHANGE             (1<<31)
 136
 137 #define HBA_MAX_SG_EMBEDDED             28
 138 #define HBA_MAX_SG_SEPARATE             90
 139 #define HBA_SENSE_DATA_LEN_MAX          32
 140 #define HBA_REQUEST_TAG_ERROR_FLAG      0x00000002
 141 #define HBA_SGL_FLAGS_EXT               0x80000000UL
 142
 143 struct aac_hba_sgl {
 144         u32             addr_lo; /* Lower 32-bits of SGL element address */
 145         u32             addr_hi; /* Upper 32-bits of SGL element address */
 146         u32             len;    /* Length of SGL element in bytes */
 147         u32             flags;  /* SGL element flags */
 148 };
 149
 150 enum {
 151         HBA_IU_TYPE_SCSI_CMD_REQ                = 0x40,
 152         HBA_IU_TYPE_SCSI_TM_REQ                 = 0x41,
 153         HBA_IU_TYPE_SATA_REQ                    = 0x42,
 154         HBA_IU_TYPE_RESP                        = 0x60,
 155         HBA_IU_TYPE_COALESCED_RESP              = 0x61,
 156         HBA_IU_TYPE_INT_COALESCING_CFG_REQ      = 0x70
 157 };
 158
 159 enum {
 160         HBA_CMD_BYTE1_DATA_DIR_IN               = 0x1,
 161         HBA_CMD_BYTE1_DATA_DIR_OUT              = 0x2,
 162         HBA_CMD_BYTE1_DATA_TYPE_DDR             = 0x4,
 163         HBA_CMD_BYTE1_CRYPTO_ENABLE             = 0x8
 164 };
 165
 166 enum {
 167         HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN        = 0x0,
 168         HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
 169         HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
 170         HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
 171 };
 172
 173 enum {
 174         HBA_RESP_DATAPRES_NO_DATA               = 0x0,
 175         HBA_RESP_DATAPRES_RESPONSE_DATA,
 176         HBA_RESP_DATAPRES_SENSE_DATA
 177 };
 178
 179 enum {
 180         HBA_RESP_SVCRES_TASK_COMPLETE           = 0x0,
 181         HBA_RESP_SVCRES_FAILURE,
 182         HBA_RESP_SVCRES_TMF_COMPLETE,
 183         HBA_RESP_SVCRES_TMF_SUCCEEDED,
 184         HBA_RESP_SVCRES_TMF_REJECTED,
 185         HBA_RESP_SVCRES_TMF_LUN_INVALID
 186 };
 187
 188 enum {
 189         HBA_RESP_STAT_IO_ERROR                  = 0x1,
 190         HBA_RESP_STAT_IO_ABORTED,
 191         HBA_RESP_STAT_NO_PATH_TO_DEVICE,
 192         HBA_RESP_STAT_INVALID_DEVICE,
 193         HBA_RESP_STAT_HBAMODE_DISABLED          = 0xE,
 194         HBA_RESP_STAT_UNDERRUN                  = 0x51,
 195         HBA_RESP_STAT_OVERRUN                   = 0x75
 196 };
 197
 198 struct aac_hba_cmd_req {
 199         u8      iu_type;        /* HBA information unit type */
 200         /*
 201          * byte1:
 202          * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
 203          * [2]   TYPE - 0=PCI, 1=DDR
 204          * [3]   CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
 205          */
 206         u8      byte1;
 207         u8      reply_qid;      /* Host reply queue to post response to */
 208         u8      reserved1;
 209         __le32  it_nexus;       /* Device handle for the request */
 210         __le32  request_id;     /* Sender context */
 211         /* Lower 32-bits of tweak value for crypto enabled IOs */
 212         __le32  tweak_value_lo;
 213         u8      cdb[16];        /* SCSI CDB of the command */
 214         u8      lun[8];         /* SCSI LUN of the command */
 215
 216         /* Total data length in bytes to be read/written (if any) */
 217         __le32  data_length;
 218
 219         /* [2:0] Task Attribute, [6:3] Command Priority */
 220         u8      attr_prio;
 221
 222         /* Number of SGL elements embedded in the HBA req */
 223         u8      emb_data_desc_count;
 224
 225         __le16  dek_index;      /* DEK index for crypto enabled IOs */
 226
 227         /* Lower 32-bits of reserved error data target location on the host */
 228         __le32  error_ptr_lo;
 229
 230         /* Upper 32-bits of reserved error data target location on the host */
 231         __le32  error_ptr_hi;
 232
 233         /* Length of reserved error data area on the host in bytes */
 234         __le32  error_length;
 235
 236         /* Upper 32-bits of tweak value for crypto enabled IOs */
 237         __le32  tweak_value_hi;
 238
 239         struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
 240
 241         /*
 242          * structure must not exceed
 243          * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
 244          */
 245 };
 246
 247 /* Task Management Functions (TMF) */
 248 #define HBA_TMF_ABORT_TASK      0x01
 249 #define HBA_TMF_LUN_RESET       0x08
 250
 251 struct aac_hba_tm_req {
 252         u8      iu_type;        /* HBA information unit type */
 253         u8      reply_qid;      /* Host reply queue to post response to */
 254         u8      tmf;            /* Task management function */
 255         u8      reserved1;
 256
 257         __le32  it_nexus;       /* Device handle for the command */
 258
 259         u8      lun[8];         /* SCSI LUN */
 260
 261         /* Used to hold sender context. */
 262         __le32  request_id;     /* Sender context */
 263         __le32  reserved2;
 264
 265         /* Request identifier of managed task */
 266         __le32  managed_request_id;     /* Sender context being managed */
 267         __le32  reserved3;
 268
 269         /* Lower 32-bits of reserved error data target location on the host */
 270         __le32  error_ptr_lo;
 271         /* Upper 32-bits of reserved error data target location on the host */
 272         __le32  error_ptr_hi;
 273         /* Length of reserved error data area on the host in bytes */
 274         __le32  error_length;
 275 };
 276
 277 struct aac_hba_reset_req {
 278         u8      iu_type;        /* HBA information unit type */
 279         /* 0 - reset specified device, 1 - reset all devices */
 280         u8      reset_type;
 281         u8      reply_qid;      /* Host reply queue to post response to */
 282         u8      reserved1;
 283
 284         __le32  it_nexus;       /* Device handle for the command */
 285         __le32  request_id;     /* Sender context */
 286         /* Lower 32-bits of reserved error data target location on the host */
 287         __le32  error_ptr_lo;
 288         /* Upper 32-bits of reserved error data target location on the host */
 289         __le32  error_ptr_hi;
 290         /* Length of reserved error data area on the host in bytes */
 291         __le32  error_length;
 292 };
 293
 294 struct aac_hba_resp {
 295         u8      iu_type;                /* HBA information unit type */
 296         u8      reserved1[3];
 297         __le32  request_identifier;     /* sender context */
 298         __le32  reserved2;
 299         u8      service_response;       /* SCSI service response */
 300         u8      status;                 /* SCSI status */
 301         u8      datapres;       /* [1:0] - data present, [7:2] - reserved */
 302         u8      sense_response_data_len;        /* Sense/response data length */
 303         __le32  residual_count;         /* Residual data length in bytes */
 304         /* Sense/response data */
 305         u8      sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
 306 };
 307
 308 struct aac_native_hba {
 309         union {
 310                 struct aac_hba_cmd_req cmd;
 311                 struct aac_hba_tm_req tmr;
 312                 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
 313         } cmd;
 314         union {
 315                 struct aac_hba_resp err;
 316                 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
 317         } resp;
 318 };
 319
 320 #define CISS_REPORT_PHYSICAL_LUNS       0xc3
 321 #define WRITE_HOST_WELLNESS             0xa5
 322 #define CISS_IDENTIFY_PHYSICAL_DEVICE   0x15
 323 #define BMIC_IN                 0x26
 324 #define BMIC_OUT                        0x27
 325
 326 struct aac_ciss_phys_luns_resp {
 327         u8      list_length[4];         /* LUN list length (N-7, big endian) */
 328         u8      resp_flag;              /* extended response_flag */
 329         u8      reserved[3];
 330         struct _ciss_lun {
 331                 u8      tid[3];         /* Target ID */
 332                 u8      bus;            /* Bus, flag (bits 6,7) */
 333                 u8      level3[2];
 334                 u8      level2[2];
 335                 u8      node_ident[16]; /* phys. node identifier */
 336         } lun[1];                       /* List of phys. devices */
 337 };
 338
 339 /*
 340  * Interrupts
 341  */
 342 #define AAC_MAX_HRRQ            64
 343
 344 struct aac_ciss_identify_pd {
 345         u8 scsi_bus;                    /* SCSI Bus number on controller */
 346         u8 scsi_id;                     /* SCSI ID on this bus */
 347         u16 block_size;                 /* sector size in bytes */
 348         u32 total_blocks;               /* number for sectors on drive */
 349         u32 reserved_blocks;            /* controller reserved (RIS) */
 350         u8 model[40];                   /* Physical Drive Model */
 351         u8 serial_number[40];           /* Drive Serial Number */
 352         u8 firmware_revision[8];        /* drive firmware revision */
 353         u8 scsi_inquiry_bits;           /* inquiry byte 7 bits */
 354         u8 compaq_drive_stamp;          /* 0 means drive not stamped */
 355         u8 last_failure_reason;
 356
 357         u8  flags;
 358         u8  more_flags;
 359         u8  scsi_lun;                   /* SCSI LUN for phys drive */
 360         u8  yet_more_flags;
 361         u8  even_more_flags;
 362         u32 spi_speed_rules;            /* SPI Speed :Ultra disable diagnose */
 363         u8  phys_connector[2];          /* connector number on controller */
 364         u8  phys_box_on_bus;            /* phys enclosure this drive resides */
 365         u8  phys_bay_in_box;            /* phys drv bay this drive resides */
 366         u32 rpm;                        /* Drive rotational speed in rpm */
 367         u8  device_type;                /* type of drive */
 368         u8  sata_version;               /* only valid when drive_type is SATA */
 369         u64 big_total_block_count;
 370         u64 ris_starting_lba;
 371         u32 ris_size;
 372         u8  wwid[20];
 373         u8  controller_phy_map[32];
 374         u16 phy_count;
 375         u8  phy_connected_dev_type[256];
 376         u8  phy_to_drive_bay_num[256];
 377         u16 phy_to_attached_dev_index[256];
 378         u8  box_index;
 379         u8  spitfire_support;
 380         u16 extra_physical_drive_flags;
 381         u8  negotiated_link_rate[256];
 382         u8  phy_to_phy_map[256];
 383         u8  redundant_path_present_map;
 384         u8  redundant_path_failure_map;
 385         u8  active_path_number;
 386         u16 alternate_paths_phys_connector[8];
 387         u8  alternate_paths_phys_box_on_port[8];
 388         u8  multi_lun_device_lun_count;
 389         u8  minimum_good_fw_revision[8];
 390         u8  unique_inquiry_bytes[20];
 391         u8  current_temperature_degreesC;
 392         u8  temperature_threshold_degreesC;
 393         u8  max_temperature_degreesC;
 394         u8  logical_blocks_per_phys_block_exp;  /* phyblocksize = 512 * 2^exp */
 395         u16 current_queue_depth_limit;
 396         u8  switch_name[10];
 397         u16 switch_port;
 398         u8  alternate_paths_switch_name[40];
 399         u8  alternate_paths_switch_port[8];
 400         u16 power_on_hours;             /* valid only if gas gauge supported */
 401         u16 percent_endurance_used;     /* valid only if gas gauge supported. */
 402         u8  drive_authentication;
 403         u8  smart_carrier_authentication;
 404         u8  smart_carrier_app_fw_version;
 405         u8  smart_carrier_bootloader_fw_version;
 406         u8  SanitizeSecureEraseSupport;
 407         u8  DriveKeyFlags;
 408         u8  encryption_key_name[64];
 409         u32 misc_drive_flags;
 410         u16 dek_index;
 411         u16 drive_encryption_flags;
 412         u8  sanitize_maximum_time[6];
 413         u8  connector_info_mode;
 414         u8  connector_info_number[4];
 415         u8  long_connector_name[64];
 416         u8  device_unique_identifier[16];
 417         u8  padto_2K[17];
 418 } __packed;
 419
 420 /*
 421  * These macros convert from physical channels to virtual channels
 422  */
 423 #define CONTAINER_CHANNEL               (0)
 424 #define NATIVE_CHANNEL                  (1)
 425 #define CONTAINER_TO_CHANNEL(cont)      (CONTAINER_CHANNEL)
 426 #define CONTAINER_TO_ID(cont)           (cont)
 427 #define CONTAINER_TO_LUN(cont)          (0)
 428 #define ENCLOSURE_CHANNEL               (3)
 429
 430 #define PMC_DEVICE_S6   0x28b
 431 #define PMC_DEVICE_S7   0x28c
 432 #define PMC_DEVICE_S8   0x28d
 433
 434 #define aac_phys_to_logical(x)  ((x)+1)
 435 #define aac_logical_to_phys(x)  ((x)?(x)-1:0)
 436
 437 /*
 438  * These macros are for keeping track of
 439  * character device state.
 440  */
 441 #define AAC_CHARDEV_UNREGISTERED        (-1)
 442 #define AAC_CHARDEV_NEEDS_REINIT        (-2)
 443
 444 /* #define AAC_DETAILED_STATUS_INFO */
 445
 446 struct diskparm
 447 {
 448         int heads;
 449         int sectors;
 450         int cylinders;
 451 };
 452
 453
 454 /*
 455  *      Firmware constants
 456  */
 457
 458 #define         CT_NONE                 0
 459 #define         CT_OK                   218
 460 #define         FT_FILESYS      8       /* ADAPTEC's "FSA"(tm) filesystem */
 461 #define         FT_DRIVE        9       /* physical disk - addressable in scsi by bus/id/lun */
 462
 463 /*
 464  *      Host side memory scatter gather list
 465  *      Used by the adapter for read, write, and readdirplus operations
 466  *      We have separate 32 and 64 bit version because even
 467  *      on 64 bit systems not all cards support the 64 bit version
 468  */
 469 struct sgentry {
 470         __le32  addr;   /* 32-bit address. */
 471         __le32  count;  /* Length. */
 472 };
 473
 474 struct user_sgentry {
 475         u32     addr;   /* 32-bit address. */
 476         u32     count;  /* Length. */
 477 };
 478
 479 struct sgentry64 {
 480         __le32  addr[2];        /* 64-bit addr. 2 pieces for data alignment */
 481         __le32  count;  /* Length. */
 482 };
 483
 484 struct user_sgentry64 {
 485         u32     addr[2];        /* 64-bit addr. 2 pieces for data alignment */
 486         u32     count;  /* Length. */
 487 };
 488
 489 struct sgentryraw {
 490         __le32          next;   /* reserved for F/W use */
 491         __le32          prev;   /* reserved for F/W use */
 492         __le32          addr[2];
 493         __le32          count;
 494         __le32          flags;  /* reserved for F/W use */
 495 };
 496
 497 struct user_sgentryraw {
 498         u32             next;   /* reserved for F/W use */
 499         u32             prev;   /* reserved for F/W use */
 500         u32             addr[2];
 501         u32             count;
 502         u32             flags;  /* reserved for F/W use */
 503 };
 504
 505 struct sge_ieee1212 {
 506         u32     addrLow;
 507         u32     addrHigh;
 508         u32     length;
 509         u32     flags;
 510 };
 511
 512 /*
 513  *      SGMAP
 514  *
 515  *      This is the SGMAP structure for all commands that use
 516  *      32-bit addressing.
 517  */
 518
 519 struct sgmap {
 520         __le32          count;
 521         struct sgentry  sg[1];
 522 };
 523
 524 struct user_sgmap {
 525         u32             count;
 526         struct user_sgentry     sg[1];
 527 };
 528
 529 struct sgmap64 {
 530         __le32          count;
 531         struct sgentry64 sg[1];
 532 };
 533
 534 struct user_sgmap64 {
 535         u32             count;
 536         struct user_sgentry64 sg[1];
 537 };
 538
 539 struct sgmapraw {
 540         __le32            count;
 541         struct sgentryraw sg[1];
 542 };
 543
 544 struct user_sgmapraw {
 545         u32               count;
 546         struct user_sgentryraw sg[1];
 547 };
 548
 549 struct creation_info
 550 {
 551         u8              buildnum;               /* e.g., 588 */
 552         u8              usec;                   /* e.g., 588 */
 553         u8              via;                    /* e.g., 1 = FSU,
 554                                                  *       2 = API
 555                                                  */
 556         u8              year;                   /* e.g., 1997 = 97 */
 557         __le32          date;                   /*
 558                                                  * unsigned     Month           :4;     // 1 - 12
 559                                                  * unsigned     Day             :6;     // 1 - 32
 560                                                  * unsigned     Hour            :6;     // 0 - 23
 561                                                  * unsigned     Minute          :6;     // 0 - 60
 562                                                  * unsigned     Second          :6;     // 0 - 60
 563                                                  */
 564         __le32          serial[2];                      /* e.g., 0x1DEADB0BFAFAF001 */
 565 };
 566
 567
 568 /*
 569  *      Define all the constants needed for the communication interface
 570  */
 571
 572 /*
 573  *      Define how many queue entries each queue will have and the total
 574  *      number of entries for the entire communication interface. Also define
 575  *      how many queues we support.
 576  *
 577  *      This has to match the controller
 578  */
 579
 580 #define NUMBER_OF_COMM_QUEUES  8   // 4 command; 4 response
 581 #define HOST_HIGH_CMD_ENTRIES  4
 582 #define HOST_NORM_CMD_ENTRIES  8
 583 #define ADAP_HIGH_CMD_ENTRIES  4
 584 #define ADAP_NORM_CMD_ENTRIES  512
 585 #define HOST_HIGH_RESP_ENTRIES 4
 586 #define HOST_NORM_RESP_ENTRIES 512
 587 #define ADAP_HIGH_RESP_ENTRIES 4
 588 #define ADAP_NORM_RESP_ENTRIES 8
 589
 590 #define TOTAL_QUEUE_ENTRIES  \
 591     (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
 592             HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
 593
 594
 595 /*
 596  *      Set the queues on a 16 byte alignment
 597  */
 598
 599 #define QUEUE_ALIGNMENT         16
 600
 601 /*
 602  *      The queue headers define the Communication Region queues. These
 603  *      are physically contiguous and accessible by both the adapter and the
 604  *      host. Even though all queue headers are in the same contiguous block
 605  *      they will be represented as individual units in the data structures.
 606  */
 607
 608 struct aac_entry {
 609         __le32 size; /* Size in bytes of Fib which this QE points to */
 610         __le32 addr; /* Receiver address of the FIB */
 611 };
 612
 613 /*
 614  *      The adapter assumes the ProducerIndex and ConsumerIndex are grouped
 615  *      adjacently and in that order.
 616  */
 617
 618 struct aac_qhdr {
 619         __le64 header_addr;/* Address to hand the adapter to access
 620                               to this queue head */
 621         __le32 *producer; /* The producer index for this queue (host address) */
 622         __le32 *consumer; /* The consumer index for this queue (host address) */
 623 };
 624
 625 /*
 626  *      Define all the events which the adapter would like to notify
 627  *      the host of.
 628  */
 629
 630 #define         HostNormCmdQue          1       /* Change in host normal priority command queue */
 631 #define         HostHighCmdQue          2       /* Change in host high priority command queue */
 632 #define         HostNormRespQue         3       /* Change in host normal priority response queue */
 633 #define         HostHighRespQue         4       /* Change in host high priority response queue */
 634 #define         AdapNormRespNotFull     5
 635 #define         AdapHighRespNotFull     6
 636 #define         AdapNormCmdNotFull      7
 637 #define         AdapHighCmdNotFull      8
 638 #define         SynchCommandComplete    9
 639 #define         AdapInternalError       0xfe    /* The adapter detected an internal error shutting down */
 640
 641 /*
 642  *      Define all the events the host wishes to notify the
 643  *      adapter of. The first four values much match the Qid the
 644  *      corresponding queue.
 645  */
 646
 647 #define         AdapNormCmdQue          2
 648 #define         AdapHighCmdQue          3
 649 #define         AdapNormRespQue         6
 650 #define         AdapHighRespQue         7
 651 #define         HostShutdown            8
 652 #define         HostPowerFail           9
 653 #define         FatalCommError          10
 654 #define         HostNormRespNotFull     11
 655 #define         HostHighRespNotFull     12
 656 #define         HostNormCmdNotFull      13
 657 #define         HostHighCmdNotFull      14
 658 #define         FastIo                  15
 659 #define         AdapPrintfDone          16
 660
 661 /*
 662  *      Define all the queues that the adapter and host use to communicate
 663  *      Number them to match the physical queue layout.
 664  */
 665
 666 enum aac_queue_types {
 667         HostNormCmdQueue = 0,   /* Adapter to host normal priority command traffic */
 668         HostHighCmdQueue,       /* Adapter to host high priority command traffic */
 669         AdapNormCmdQueue,       /* Host to adapter normal priority command traffic */
 670         AdapHighCmdQueue,       /* Host to adapter high priority command traffic */
 671         HostNormRespQueue,      /* Adapter to host normal priority response traffic */
 672         HostHighRespQueue,      /* Adapter to host high priority response traffic */
 673         AdapNormRespQueue,      /* Host to adapter normal priority response traffic */
 674         AdapHighRespQueue       /* Host to adapter high priority response traffic */
 675 };
 676
 677 /*
 678  *      Assign type values to the FSA communication data structures
 679  */
 680
 681 #define         FIB_MAGIC       0x0001
 682 #define         FIB_MAGIC2      0x0004
 683 #define         FIB_MAGIC2_64   0x0005
 684
 685 /*
 686  *      Define the priority levels the FSA communication routines support.
 687  */
 688
 689 #define         FsaNormal       1
 690
 691 /* transport FIB header (PMC) */
 692 struct aac_fib_xporthdr {
 693         __le64  HostAddress;    /* FIB host address w/o xport header */
 694         __le32  Size;           /* FIB size excluding xport header */
 695         __le32  Handle;         /* driver handle to reference the FIB */
 696         __le64  Reserved[2];
 697 };
 698
 699 #define         ALIGN32         32
 700
 701 /*
 702  * Define the FIB. The FIB is the where all the requested data and
 703  * command information are put to the application on the FSA adapter.
 704  */
 705
 706 struct aac_fibhdr {
 707         __le32 XferState;       /* Current transfer state for this CCB */
 708         __le16 Command;         /* Routing information for the destination */
 709         u8 StructType;          /* Type FIB */
 710         u8 Unused;              /* Unused */
 711         __le16 Size;            /* Size of this FIB in bytes */
 712         __le16 SenderSize;      /* Size of the FIB in the sender
 713                                    (for response sizing) */
 714         __le32 SenderFibAddress;  /* Host defined data in the FIB */
 715         union {
 716                 __le32 ReceiverFibAddress;/* Logical address of this FIB for
 717                                      the adapter (old) */
 718                 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
 719                 __le32 TimeStamp;       /* otherwise timestamp for FW internal use */
 720         } u;
 721         __le32 Handle;          /* FIB handle used for MSGU commnunication */
 722         u32 Previous;           /* FW internal use */
 723         u32 Next;               /* FW internal use */
 724 };
 725
 726 struct hw_fib {
 727         struct aac_fibhdr header;
 728         u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
 729 };
 730
 731 /*
 732  *      FIB commands
 733  */
 734
 735 #define         TestCommandResponse             1
 736 #define         TestAdapterCommand              2
 737 /*
 738  *      Lowlevel and comm commands
 739  */
 740 #define         LastTestCommand                 100
 741 #define         ReinitHostNormCommandQueue      101
 742 #define         ReinitHostHighCommandQueue      102
 743 #define         ReinitHostHighRespQueue         103
 744 #define         ReinitHostNormRespQueue         104
 745 #define         ReinitAdapNormCommandQueue      105
 746 #define         ReinitAdapHighCommandQueue      107
 747 #define         ReinitAdapHighRespQueue         108
 748 #define         ReinitAdapNormRespQueue         109
 749 #define         InterfaceShutdown               110
 750 #define         DmaCommandFib                   120
 751 #define         StartProfile                    121
 752 #define         TermProfile                     122
 753 #define         SpeedTest                       123
 754 #define         TakeABreakPt                    124
 755 #define         RequestPerfData                 125
 756 #define         SetInterruptDefTimer            126
 757 #define         SetInterruptDefCount            127
 758 #define         GetInterruptDefStatus           128
 759 #define         LastCommCommand                 129
 760 /*
 761  *      Filesystem commands
 762  */
 763 #define         NuFileSystem                    300
 764 #define         UFS                             301
 765 #define         HostFileSystem                  302
 766 #define         LastFileSystemCommand           303
 767 /*
 768  *      Container Commands
 769  */
 770 #define         ContainerCommand                500
 771 #define         ContainerCommand64              501
 772 #define         ContainerRawIo                  502
 773 #define         ContainerRawIo2                 503
 774 /*
 775  *      Scsi Port commands (scsi passthrough)
 776  */
 777 #define         ScsiPortCommand                 600
 778 #define         ScsiPortCommand64               601
 779 /*
 780  *      Misc house keeping and generic adapter initiated commands
 781  */
 782 #define         AifRequest                      700
 783 #define         CheckRevision                   701
 784 #define         FsaHostShutdown                 702
 785 #define         RequestAdapterInfo              703
 786 #define         IsAdapterPaused                 704
 787 #define         SendHostTime                    705
 788 #define         RequestSupplementAdapterInfo    706
 789 #define         LastMiscCommand                 707
 790
 791 /*
 792  * Commands that will target the failover level on the FSA adapter
 793  */
 794
 795 enum fib_xfer_state {
 796         HostOwned                       = (1<<0),
 797         AdapterOwned                    = (1<<1),
 798         FibInitialized                  = (1<<2),
 799         FibEmpty                        = (1<<3),
 800         AllocatedFromPool               = (1<<4),
 801         SentFromHost                    = (1<<5),
 802         SentFromAdapter                 = (1<<6),
 803         ResponseExpected                = (1<<7),
 804         NoResponseExpected              = (1<<8),
 805         AdapterProcessed                = (1<<9),
 806         HostProcessed                   = (1<<10),
 807         HighPriority                    = (1<<11),
 808         NormalPriority                  = (1<<12),
 809         Async                           = (1<<13),
 810         AsyncIo                         = (1<<13),      // rpbfix: remove with new regime
 811         PageFileIo                      = (1<<14),      // rpbfix: remove with new regime
 812         ShutdownRequest                 = (1<<15),
 813         LazyWrite                       = (1<<16),      // rpbfix: remove with new regime
 814         AdapterMicroFib                 = (1<<17),
 815         BIOSFibPath                     = (1<<18),
 816         FastResponseCapable             = (1<<19),
 817         ApiFib                          = (1<<20),      /* Its an API Fib */
 818         /* PMC NEW COMM: There is no more AIF data pending */
 819         NoMoreAifDataAvailable          = (1<<21)
 820 };
 821
 822 /*
 823  *      The following defines needs to be updated any time there is an
 824  *      incompatible change made to the aac_init structure.
 825  */
 826
 827 #define ADAPTER_INIT_STRUCT_REVISION            3
 828 #define ADAPTER_INIT_STRUCT_REVISION_4          4 // rocket science
 829 #define ADAPTER_INIT_STRUCT_REVISION_6          6 /* PMC src */
 830 #define ADAPTER_INIT_STRUCT_REVISION_7          7 /* Denali */
 831 #define ADAPTER_INIT_STRUCT_REVISION_8          8 // Thor
 832
 833 union aac_init
 834 {
 835         struct _r7 {
 836                 __le32  init_struct_revision;
 837                 __le32  no_of_msix_vectors;
 838                 __le32  fsrev;
 839                 __le32  comm_header_address;
 840                 __le32  fast_io_comm_area_address;
 841                 __le32  adapter_fibs_physical_address;
 842                 __le32  adapter_fibs_virtual_address;
 843                 __le32  adapter_fibs_size;
 844                 __le32  adapter_fib_align;
 845                 __le32  printfbuf;
 846                 __le32  printfbufsiz;
 847                 /* number of 4k pages of host phys. mem. */
 848                 __le32  host_phys_mem_pages;
 849                 /* number of seconds since 1970. */
 850                 __le32  host_elapsed_seconds;
 851                 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
 852                 __le32  init_flags;     /* flags for supported features */
 853 #define INITFLAGS_NEW_COMM_SUPPORTED    0x00000001
 854 #define INITFLAGS_DRIVER_USES_UTC_TIME  0x00000010
 855 #define INITFLAGS_DRIVER_SUPPORTS_PM    0x00000020
 856 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED      0x00000040
 857 #define INITFLAGS_FAST_JBOD_SUPPORTED   0x00000080
 858 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED      0x00000100
 859 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE  0x00000400
 860                 __le32  max_io_commands;        /* max outstanding commands */
 861                 __le32  max_io_size;    /* largest I/O command */
 862                 __le32  max_fib_size;   /* largest FIB to adapter */
 863                 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
 864                 __le32  max_num_aif;    /* max number of aif */
 865                 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
 866                 /* Host RRQ (response queue) for SRC */
 867                 __le32  host_rrq_addr_low;
 868                 __le32  host_rrq_addr_high;
 869         } r7;
 870         struct _r8 {
 871                 /* ADAPTER_INIT_STRUCT_REVISION_8 */
 872                 __le32  init_struct_revision;
 873                 __le32  rr_queue_count;
 874                 __le32  host_elapsed_seconds; /* number of secs since 1970. */
 875                 __le32  init_flags;
 876                 __le32  max_io_size;    /* largest I/O command */
 877                 __le32  max_num_aif;    /* max number of aif */
 878                 __le32  reserved1;
 879                 __le32  reserved2;
 880                 struct _rrq {
 881                         __le32  host_addr_low;
 882                         __le32  host_addr_high;
 883                         __le16  msix_id;
 884                         __le16  element_count;
 885                         __le16  comp_thresh;
 886                         __le16  unused;
 887                 } rrq[1];               /* up to 64 RRQ addresses */
 888         } r8;
 889 };
 890
 891 enum aac_log_level {
 892         LOG_AAC_INIT                    = 10,
 893         LOG_AAC_INFORMATIONAL           = 20,
 894         LOG_AAC_WARNING                 = 30,
 895         LOG_AAC_LOW_ERROR               = 40,
 896         LOG_AAC_MEDIUM_ERROR            = 50,
 897         LOG_AAC_HIGH_ERROR              = 60,
 898         LOG_AAC_PANIC                   = 70,
 899         LOG_AAC_DEBUG                   = 80,
 900         LOG_AAC_WINDBG_PRINT            = 90
 901 };
 902
 903 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT       0x030b
 904 #define FSAFS_NTC_FIB_CONTEXT                   0x030c
 905
 906 struct aac_dev;
 907 struct fib;
 908 struct scsi_cmnd;
 909
 910 struct adapter_ops
 911 {
 912         /* Low level operations */
 913         void (*adapter_interrupt)(struct aac_dev *dev);
 914         void (*adapter_notify)(struct aac_dev *dev, u32 event);
 915         void (*adapter_disable_int)(struct aac_dev *dev);
 916         void (*adapter_enable_int)(struct aac_dev *dev);
 917         int  (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
 918         int  (*adapter_check_health)(struct aac_dev *dev);
 919         int  (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
 920         void (*adapter_start)(struct aac_dev *dev);
 921         /* Transport operations */
 922         int  (*adapter_ioremap)(struct aac_dev * dev, u32 size);
 923         irq_handler_t adapter_intr;
 924         /* Packet operations */
 925         int  (*adapter_deliver)(struct fib * fib);
 926         int  (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
 927         int  (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
 928         int  (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
 929         int  (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
 930         /* Administrative operations */
 931         int  (*adapter_comm)(struct aac_dev * dev, int comm);
 932 };
 933
 934 /*
 935  *      Define which interrupt handler needs to be installed
 936  */
 937
 938 struct aac_driver_ident
 939 {
 940         int     (*init)(struct aac_dev *dev);
 941         char *  name;
 942         char *  vname;
 943         char *  model;
 944         u16     channels;
 945         int     quirks;
 946 };
 947 /*
 948  * Some adapter firmware needs communication memory
 949  * below 2gig. This tells the init function to set the
 950  * dma mask such that fib memory will be allocated where the
 951  * adapter firmware can get to it.
 952  */
 953 #define AAC_QUIRK_31BIT 0x0001
 954
 955 /*
 956  * Some adapter firmware, when the raid card's cache is turned off, can not
 957  * split up scatter gathers in order to deal with the limits of the
 958  * underlying CHIM. This limit is 34 scatter gather elements.
 959  */
 960 #define AAC_QUIRK_34SG  0x0002
 961
 962 /*
 963  * This adapter is a slave (no Firmware)
 964  */
 965 #define AAC_QUIRK_SLAVE 0x0004
 966
 967 /*
 968  * This adapter is a master.
 969  */
 970 #define AAC_QUIRK_MASTER 0x0008
 971
 972 /*
 973  * Some adapter firmware perform poorly when it must split up scatter gathers
 974  * in order to deal with the limits of the underlying CHIM. This limit in this
 975  * class of adapters is 17 scatter gather elements.
 976  */
 977 #define AAC_QUIRK_17SG  0x0010
 978
 979 /*
 980  *      Some adapter firmware does not support 64 bit scsi passthrough
 981  * commands.
 982  */
 983 #define AAC_QUIRK_SCSI_32       0x0020
 984
 985 /*
 986  * SRC based adapters support the AifReqEvent functions
 987  */
 988 #define AAC_QUIRK_SRC 0x0040
 989
 990 /*
 991  *      The adapter interface specs all queues to be located in the same
 992  *      physically contiguous block. The host structure that defines the
 993  *      commuication queues will assume they are each a separate physically
 994  *      contiguous memory region that will support them all being one big
 995  *      contiguous block.
 996  *      There is a command and response queue for each level and direction of
 997  *      commuication. These regions are accessed by both the host and adapter.
 998  */
 999
1000 struct aac_queue {
1001         u64                     logical;        /*address we give the adapter */
1002         struct aac_entry        *base;          /*system virtual address */
1003         struct aac_qhdr         headers;        /*producer,consumer q headers*/
1004         u32                     entries;        /*Number of queue entries */
1005         wait_queue_head_t       qfull;          /*Event to wait on if q full */
1006         wait_queue_head_t       cmdready;       /*Cmd ready from the adapter */
1007                 /* This is only valid for adapter to host command queues. */
1008         spinlock_t              *lock;          /* Spinlock for this queue must take this lock before accessing the lock */
1009         spinlock_t              lockdata;       /* Actual lock (used only on one side of the lock) */
1010         struct list_head        cmdq;           /* A queue of FIBs which need to be prcessed by the FS thread. This is */
1011                                                 /* only valid for command queues which receive entries from the adapter. */
1012         /* Number of entries on outstanding queue. */
1013         atomic_t                numpending;
1014         struct aac_dev *        dev;            /* Back pointer to adapter structure */
1015 };
1016
1017 /*
1018  *      Message queues. The order here is important, see also the
1019  *      queue type ordering
1020  */
1021
1022 struct aac_queue_block
1023 {
1024         struct aac_queue queue[8];
1025 };
1026
1027 /*
1028  *      SaP1 Message Unit Registers
1029  */
1030
1031 struct sa_drawbridge_CSR {
1032                                 /*      Offset  |  Name */
1033         __le32  reserved[10];   /*      00h-27h |  Reserved */
1034         u8      LUT_Offset;     /*      28h     |  Lookup Table Offset */
1035         u8      reserved1[3];   /*      29h-2bh |  Reserved */
1036         __le32  LUT_Data;       /*      2ch     |  Looup Table Data */
1037         __le32  reserved2[26];  /*      30h-97h |  Reserved */
1038         __le16  PRICLEARIRQ;    /*      98h     |  Primary Clear Irq */
1039         __le16  SECCLEARIRQ;    /*      9ah     |  Secondary Clear Irq */
1040         __le16  PRISETIRQ;      /*      9ch     |  Primary Set Irq */
1041         __le16  SECSETIRQ;      /*      9eh     |  Secondary Set Irq */
1042         __le16  PRICLEARIRQMASK;/*      a0h     |  Primary Clear Irq Mask */
1043         __le16  SECCLEARIRQMASK;/*      a2h     |  Secondary Clear Irq Mask */
1044         __le16  PRISETIRQMASK;  /*      a4h     |  Primary Set Irq Mask */
1045         __le16  SECSETIRQMASK;  /*      a6h     |  Secondary Set Irq Mask */
1046         __le32  MAILBOX0;       /*      a8h     |  Scratchpad 0 */
1047         __le32  MAILBOX1;       /*      ach     |  Scratchpad 1 */
1048         __le32  MAILBOX2;       /*      b0h     |  Scratchpad 2 */
1049         __le32  MAILBOX3;       /*      b4h     |  Scratchpad 3 */
1050         __le32  MAILBOX4;       /*      b8h     |  Scratchpad 4 */
1051         __le32  MAILBOX5;       /*      bch     |  Scratchpad 5 */
1052         __le32  MAILBOX6;       /*      c0h     |  Scratchpad 6 */
1053         __le32  MAILBOX7;       /*      c4h     |  Scratchpad 7 */
1054         __le32  ROM_Setup_Data; /*      c8h     |  Rom Setup and Data */
1055         __le32  ROM_Control_Addr;/*     cch     |  Rom Control and Address */
1056         __le32  reserved3[12];  /*      d0h-ffh |  reserved */
1057         __le32  LUT[64];        /*    100h-1ffh |  Lookup Table Entries */
1058 };
1059
1060 #define Mailbox0        SaDbCSR.MAILBOX0
1061 #define Mailbox1        SaDbCSR.MAILBOX1
1062 #define Mailbox2        SaDbCSR.MAILBOX2
1063 #define Mailbox3        SaDbCSR.MAILBOX3
1064 #define Mailbox4        SaDbCSR.MAILBOX4
1065 #define Mailbox5        SaDbCSR.MAILBOX5
1066 #define Mailbox6        SaDbCSR.MAILBOX6
1067 #define Mailbox7        SaDbCSR.MAILBOX7
1068
1069 #define DoorbellReg_p SaDbCSR.PRISETIRQ
1070 #define DoorbellReg_s SaDbCSR.SECSETIRQ
1071 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1072
1073
1074 #define DOORBELL_0      0x0001
1075 #define DOORBELL_1      0x0002
1076 #define DOORBELL_2      0x0004
1077 #define DOORBELL_3      0x0008
1078 #define DOORBELL_4      0x0010
1079 #define DOORBELL_5      0x0020
1080 #define DOORBELL_6      0x0040
1081
1082
1083 #define PrintfReady     DOORBELL_5
1084 #define PrintfDone      DOORBELL_5
1085
1086 struct sa_registers {
1087         struct sa_drawbridge_CSR        SaDbCSR;                        /* 98h - c4h */
1088 };
1089
1090
1091 #define SA_INIT_NUM_MSIXVECTORS         1
1092 #define SA_MINIPORT_REVISION            SA_INIT_NUM_MSIXVECTORS
1093
1094 #define sa_readw(AEP, CSR)              readl(&((AEP)->regs.sa->CSR))
1095 #define sa_readl(AEP, CSR)              readl(&((AEP)->regs.sa->CSR))
1096 #define sa_writew(AEP, CSR, value)      writew(value, &((AEP)->regs.sa->CSR))
1097 #define sa_writel(AEP, CSR, value)      writel(value, &((AEP)->regs.sa->CSR))
1098
1099 /*
1100  *      Rx Message Unit Registers
1101  */
1102
1103 struct rx_mu_registers {
1104                             /*  Local  | PCI*| Name */
1105         __le32  ARSR;       /*  1300h  | 00h | APIC Register Select Register */
1106         __le32  reserved0;  /*  1304h  | 04h | Reserved */
1107         __le32  AWR;        /*  1308h  | 08h | APIC Window Register */
1108         __le32  reserved1;  /*  130Ch  | 0Ch | Reserved */
1109         __le32  IMRx[2];    /*  1310h  | 10h | Inbound Message Registers */
1110         __le32  OMRx[2];    /*  1318h  | 18h | Outbound Message Registers */
1111         __le32  IDR;        /*  1320h  | 20h | Inbound Doorbell Register */
1112         __le32  IISR;       /*  1324h  | 24h | Inbound Interrupt
1113                                                 Status Register */
1114         __le32  IIMR;       /*  1328h  | 28h | Inbound Interrupt
1115                                                 Mask Register */
1116         __le32  ODR;        /*  132Ch  | 2Ch | Outbound Doorbell Register */
1117         __le32  OISR;       /*  1330h  | 30h | Outbound Interrupt
1118                                                 Status Register */
1119         __le32  OIMR;       /*  1334h  | 34h | Outbound Interrupt
1120                                                 Mask Register */
1121         __le32  reserved2;  /*  1338h  | 38h | Reserved */
1122         __le32  reserved3;  /*  133Ch  | 3Ch | Reserved */
1123         __le32  InboundQueue;/* 1340h  | 40h | Inbound Queue Port relative to firmware */
1124         __le32  OutboundQueue;/*1344h  | 44h | Outbound Queue Port relative to firmware */
1125                             /* * Must access through ATU Inbound
1126                                  Translation Window */
1127 };
1128
1129 struct rx_inbound {
1130         __le32  Mailbox[8];
1131 };
1132
1133 #define INBOUNDDOORBELL_0       0x00000001
1134 #define INBOUNDDOORBELL_1       0x00000002
1135 #define INBOUNDDOORBELL_2       0x00000004
1136 #define INBOUNDDOORBELL_3       0x00000008
1137 #define INBOUNDDOORBELL_4       0x00000010
1138 #define INBOUNDDOORBELL_5       0x00000020
1139 #define INBOUNDDOORBELL_6       0x00000040
1140
1141 #define OUTBOUNDDOORBELL_0      0x00000001
1142 #define OUTBOUNDDOORBELL_1      0x00000002
1143 #define OUTBOUNDDOORBELL_2      0x00000004
1144 #define OUTBOUNDDOORBELL_3      0x00000008
1145 #define OUTBOUNDDOORBELL_4      0x00000010
1146
1147 #define InboundDoorbellReg      MUnit.IDR
1148 #define OutboundDoorbellReg     MUnit.ODR
1149
1150 struct rx_registers {
1151         struct rx_mu_registers          MUnit;          /* 1300h - 1347h */
1152         __le32                          reserved1[2];   /* 1348h - 134ch */
1153         struct rx_inbound               IndexRegs;
1154 };
1155
1156 #define rx_readb(AEP, CSR)              readb(&((AEP)->regs.rx->CSR))
1157 #define rx_readl(AEP, CSR)              readl(&((AEP)->regs.rx->CSR))
1158 #define rx_writeb(AEP, CSR, value)      writeb(value, &((AEP)->regs.rx->CSR))
1159 #define rx_writel(AEP, CSR, value)      writel(value, &((AEP)->regs.rx->CSR))
1160
1161 /*
1162  *      Rkt Message Unit Registers (same as Rx, except a larger reserve region)
1163  */
1164
1165 #define rkt_mu_registers rx_mu_registers
1166 #define rkt_inbound rx_inbound
1167
1168 struct rkt_registers {
1169         struct rkt_mu_registers         MUnit;           /* 1300h - 1347h */
1170         __le32                          reserved1[1006]; /* 1348h - 22fch */
1171         struct rkt_inbound              IndexRegs;       /* 2300h - */
1172 };
1173
1174 #define rkt_readb(AEP, CSR)             readb(&((AEP)->regs.rkt->CSR))
1175 #define rkt_readl(AEP, CSR)             readl(&((AEP)->regs.rkt->CSR))
1176 #define rkt_writeb(AEP, CSR, value)     writeb(value, &((AEP)->regs.rkt->CSR))
1177 #define rkt_writel(AEP, CSR, value)     writel(value, &((AEP)->regs.rkt->CSR))
1178
1179 /*
1180  * PMC SRC message unit registers
1181  */
1182
1183 #define src_inbound rx_inbound
1184
1185 struct src_mu_registers {
1186                                 /*  PCI*| Name */
1187         __le32  reserved0[6];   /*  00h | Reserved */
1188         __le32  IOAR[2];        /*  18h | IOA->host interrupt register */
1189         __le32  IDR;            /*  20h | Inbound Doorbell Register */
1190         __le32  IISR;           /*  24h | Inbound Int. Status Register */
1191         __le32  reserved1[3];   /*  28h | Reserved */
1192         __le32  OIMR;           /*  34h | Outbound Int. Mask Register */
1193         __le32  reserved2[25];  /*  38h | Reserved */
1194         __le32  ODR_R;          /*  9ch | Outbound Doorbell Read */
1195         __le32  ODR_C;          /*  a0h | Outbound Doorbell Clear */
1196         __le32  reserved3[3];   /*  a4h | Reserved */
1197         __le32  SCR0;           /*  b0h | Scratchpad 0 */
1198         __le32  reserved4[2];   /*  b4h | Reserved */
1199         __le32  OMR;            /*  bch | Outbound Message Register */
1200         __le32  IQ_L;           /*  c0h | Inbound Queue (Low address) */
1201         __le32  IQ_H;           /*  c4h | Inbound Queue (High address) */
1202         __le32  ODR_MSI;        /*  c8h | MSI register for sync./AIF */
1203         __le32  reserved5;      /*  cch | Reserved */
1204         __le32  IQN_L;          /*  d0h | Inbound (native cmd) low  */
1205         __le32  IQN_H;          /*  d4h | Inbound (native cmd) high */
1206 };
1207
1208 struct src_registers {
1209         struct src_mu_registers MUnit;  /* 00h - cbh */
1210         union {
1211                 struct {
1212                         __le32 reserved1[130786];       /* d8h - 7fc5fh */
1213                         struct src_inbound IndexRegs;   /* 7fc60h */
1214                 } tupelo;
1215                 struct {
1216                         __le32 reserved1[970];          /* d8h - fffh */
1217                         struct src_inbound IndexRegs;   /* 1000h */
1218                 } denali;
1219         } u;
1220 };
1221
1222 #define src_readb(AEP, CSR)             readb(&((AEP)->regs.src.bar0->CSR))
1223 #define src_readl(AEP, CSR)             readl(&((AEP)->regs.src.bar0->CSR))
1224 #define src_writeb(AEP, CSR, value)     writeb(value, \
1225                                                 &((AEP)->regs.src.bar0->CSR))
1226 #define src_writel(AEP, CSR, value)     writel(value, \
1227                                                 &((AEP)->regs.src.bar0->CSR))
1228 #if defined(writeq)
1229 #define src_writeq(AEP, CSR, value)     writeq(value, \
1230                                                 &((AEP)->regs.src.bar0->CSR))
1231 #endif
1232
1233 #define SRC_ODR_SHIFT           12
1234 #define SRC_IDR_SHIFT           9
1235 #define SRC_MSI_READ_MASK       0x1000
1236
1237 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1238
1239 struct aac_fib_context {
1240         s16                     type;           // used for verification of structure
1241         s16                     size;
1242         u32                     unique;         // unique value representing this context
1243         ulong                   jiffies;        // used for cleanup - dmb changed to ulong
1244         struct list_head        next;           // used to link context's into a linked list
1245         struct completion       completion;     // this is used to wait for the next fib to arrive.
1246         int                     wait;           // Set to true when thread is in WaitForSingleObject
1247         unsigned long           count;          // total number of FIBs on FibList
1248         struct list_head        fib_list;       // this holds fibs and their attachd hw_fibs
1249 };
1250
1251 struct sense_data {
1252         u8 error_code;          /* 70h (current errors), 71h(deferred errors) */
1253         u8 valid:1;             /* A valid bit of one indicates that the information  */
1254                                 /* field contains valid information as defined in the
1255                                  * SCSI-2 Standard.
1256                                  */
1257         u8 segment_number;      /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1258         u8 sense_key:4;         /* Sense Key */
1259         u8 reserved:1;
1260         u8 ILI:1;               /* Incorrect Length Indicator */
1261         u8 EOM:1;               /* End Of Medium - reserved for random access devices */
1262         u8 filemark:1;          /* Filemark - reserved for random access devices */
1263
1264         u8 information[4];      /* for direct-access devices, contains the unsigned
1265                                  * logical block address or residue associated with
1266                                  * the sense key
1267                                  */
1268         u8 add_sense_len;       /* number of additional sense bytes to follow this field */
1269         u8 cmnd_info[4];        /* not used */
1270         u8 ASC;                 /* Additional Sense Code */
1271         u8 ASCQ;                /* Additional Sense Code Qualifier */
1272         u8 FRUC;                /* Field Replaceable Unit Code - not used */
1273         u8 bit_ptr:3;           /* indicates which byte of the CDB or parameter data
1274                                  * was in error
1275                                  */
1276         u8 BPV:1;               /* bit pointer valid (BPV): 1- indicates that
1277                                  * the bit_ptr field has valid value
1278                                  */
1279         u8 reserved2:2;
1280         u8 CD:1;                /* command data bit: 1- illegal parameter in CDB.
1281                                  * 0- illegal parameter in data.
1282                                  */
1283         u8 SKSV:1;
1284         u8 field_ptr[2];        /* byte of the CDB or parameter data in error */
1285 };
1286
1287 struct fsa_dev_info {
1288         u64             last;
1289         u64             size;
1290         u32             type;
1291         u32             config_waiting_on;
1292         unsigned long   config_waiting_stamp;
1293         u16             queue_depth;
1294         u8              config_needed;
1295         u8              valid;
1296         u8              ro;
1297         u8              locked;
1298         u8              deleted;
1299         char            devname[8];
1300         struct sense_data sense_data;
1301         u32             block_size;
1302         u8              identifier[16];
1303 };
1304
1305 struct fib {
1306         void                    *next;  /* this is used by the allocator */
1307         s16                     type;
1308         s16                     size;
1309         /*
1310          *      The Adapter that this I/O is destined for.
1311          */
1312         struct aac_dev          *dev;
1313         /*
1314          *      This is the event the sendfib routine will wait on if the
1315          *      caller did not pass one and this is synch io.
1316          */
1317         struct completion       event_wait;
1318         spinlock_t              event_lock;
1319
1320         u32                     done;   /* gets set to 1 when fib is complete */
1321         fib_callback            callback;
1322         void                    *callback_data;
1323         u32                     flags; // u32 dmb was ulong
1324         /*
1325          *      And for the internal issue/reply queues (we may be able
1326          *      to merge these two)
1327          */
1328         struct list_head        fiblink;
1329         void                    *data;
1330         u32                     vector_no;
1331         struct hw_fib           *hw_fib_va;     /* also used for native */
1332         dma_addr_t              hw_fib_pa;      /* physical address of hw_fib*/
1333         dma_addr_t              hw_sgl_pa;      /* extra sgl for native */
1334         dma_addr_t              hw_error_pa;    /* error buffer for native */
1335         u32                     hbacmd_size;    /* cmd size for native */
1336 };
1337
1338 #define AAC_INIT                        0
1339 #define AAC_RESCAN                      1
1340
1341 #define AAC_DEVTYPE_RAID_MEMBER 1
1342 #define AAC_DEVTYPE_ARC_RAW             2
1343 #define AAC_DEVTYPE_NATIVE_RAW          3
1344
1345 #define AAC_SAFW_RESCAN_DELAY           (10 * HZ)
1346
1347 struct aac_hba_map_info {
1348         __le32  rmw_nexus;              /* nexus for native HBA devices */
1349         u8              devtype;        /* device type */
1350         s8              reset_state;    /* 0 - no reset, 1..x - */
1351                                         /* after xth TM LUN reset */
1352         u16             qd_limit;
1353         u32             scan_counter;
1354         struct aac_ciss_identify_pd  *safw_identify_resp;
1355 };
1356
1357 /*
1358  *      Adapter Information Block
1359  *
1360  *      This is returned by the RequestAdapterInfo block
1361  */
1362
1363 struct aac_adapter_info
1364 {
1365         __le32  platform;
1366         __le32  cpu;
1367         __le32  subcpu;
1368         __le32  clock;
1369         __le32  execmem;
1370         __le32  buffermem;
1371         __le32  totalmem;
1372         __le32  kernelrev;
1373         __le32  kernelbuild;
1374         __le32  monitorrev;
1375         __le32  monitorbuild;
1376         __le32  hwrev;
1377         __le32  hwbuild;
1378         __le32  biosrev;
1379         __le32  biosbuild;
1380         __le32  cluster;
1381         __le32  clusterchannelmask;
1382         __le32  serial[2];
1383         __le32  battery;
1384         __le32  options;
1385         __le32  OEM;
1386 };
1387
1388 struct aac_supplement_adapter_info
1389 {
1390         u8      adapter_type_text[17+1];
1391         u8      pad[2];
1392         __le32  flash_memory_byte_size;
1393         __le32  flash_image_id;
1394         __le32  max_number_ports;
1395         __le32  version;
1396         __le32  feature_bits;
1397         u8      slot_number;
1398         u8      reserved_pad0[3];
1399         u8      build_date[12];
1400         __le32  current_number_ports;
1401         struct {
1402                 u8      assembly_pn[8];
1403                 u8      fru_pn[8];
1404                 u8      battery_fru_pn[8];
1405                 u8      ec_version_string[8];
1406                 u8      tsid[12];
1407         }       vpd_info;
1408         __le32  flash_firmware_revision;
1409         __le32  flash_firmware_build;
1410         __le32  raid_type_morph_options;
1411         __le32  flash_firmware_boot_revision;
1412         __le32  flash_firmware_boot_build;
1413         u8      mfg_pcba_serial_no[12];
1414         u8      mfg_wwn_name[8];
1415         __le32  supported_options2;
1416         __le32  struct_expansion;
1417         /* StructExpansion == 1 */
1418         __le32  feature_bits3;
1419         __le32  supported_performance_modes;
1420         u8      host_bus_type;          /* uses HOST_BUS_TYPE_xxx defines */
1421         u8      host_bus_width;         /* actual width in bits or links */
1422         u16     host_bus_speed;         /* actual bus speed/link rate in MHz */
1423         u8      max_rrc_drives;         /* max. number of ITP-RRC drives/pool */
1424         u8      max_disk_xtasks;        /* max. possible num of DiskX Tasks */
1425
1426         u8      cpld_ver_loaded;
1427         u8      cpld_ver_in_flash;
1428
1429         __le64  max_rrc_capacity;
1430         __le32  compiled_max_hist_log_level;
1431         u8      custom_board_name[12];
1432         u16     supported_cntlr_mode;   /* identify supported controller mode */
1433         u16     reserved_for_future16;
1434         __le32  supported_options3;     /* reserved for future options */
1435
1436         __le16  virt_device_bus;                /* virt. SCSI device for Thor */
1437         __le16  virt_device_target;
1438         __le16  virt_device_lun;
1439         __le16  unused;
1440         __le32  reserved_for_future_growth[68];
1441
1442 };
1443 #define AAC_FEATURE_FALCON      cpu_to_le32(0x00000010)
1444 #define AAC_FEATURE_JBOD        cpu_to_le32(0x08000000)
1445 /* SupportedOptions2 */
1446 #define AAC_OPTION_MU_RESET             cpu_to_le32(0x00000001)
1447 #define AAC_OPTION_IGNORE_RESET         cpu_to_le32(0x00000002)
1448 #define AAC_OPTION_POWER_MANAGEMENT     cpu_to_le32(0x00000004)
1449 #define AAC_OPTION_DOORBELL_RESET       cpu_to_le32(0x00004000)
1450 /* 4KB sector size */
1451 #define AAC_OPTION_VARIABLE_BLOCK_SIZE  cpu_to_le32(0x00040000)
1452 /* 240 simple volume support */
1453 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1454 /*
1455  * Supports FIB dump sync command send prior to IOP_RESET
1456  */
1457 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP        cpu_to_le32(0x00004000)
1458 #define AAC_SIS_VERSION_V3      3
1459 #define AAC_SIS_SLOT_UNKNOWN    0xFF
1460
1461 #define GetBusInfo 0x00000009
1462 struct aac_bus_info {
1463         __le32  Command;        /* VM_Ioctl */
1464         __le32  ObjType;        /* FT_DRIVE */
1465         __le32  MethodId;       /* 1 = SCSI Layer */
1466         __le32  ObjectId;       /* Handle */
1467         __le32  CtlCmd;         /* GetBusInfo */
1468 };
1469
1470 struct aac_bus_info_response {
1471         __le32  Status;         /* ST_OK */
1472         __le32  ObjType;
1473         __le32  MethodId;       /* unused */
1474         __le32  ObjectId;       /* unused */
1475         __le32  CtlCmd;         /* unused */
1476         __le32  ProbeComplete;
1477         __le32  BusCount;
1478         __le32  TargetsPerBus;
1479         u8      InitiatorBusId[10];
1480         u8      BusValid[10];
1481 };
1482
1483 /*
1484  * Battery platforms
1485  */
1486 #define AAC_BAT_REQ_PRESENT     (1)
1487 #define AAC_BAT_REQ_NOTPRESENT  (2)
1488 #define AAC_BAT_OPT_PRESENT     (3)
1489 #define AAC_BAT_OPT_NOTPRESENT  (4)
1490 #define AAC_BAT_NOT_SUPPORTED   (5)
1491 /*
1492  * cpu types
1493  */
1494 #define AAC_CPU_SIMULATOR       (1)
1495 #define AAC_CPU_I960            (2)
1496 #define AAC_CPU_STRONGARM       (3)
1497
1498 /*
1499  * Supported Options
1500  */
1501 #define AAC_OPT_SNAPSHOT                cpu_to_le32(1)
1502 #define AAC_OPT_CLUSTERS                cpu_to_le32(1<<1)
1503 #define AAC_OPT_WRITE_CACHE             cpu_to_le32(1<<2)
1504 #define AAC_OPT_64BIT_DATA              cpu_to_le32(1<<3)
1505 #define AAC_OPT_HOST_TIME_FIB           cpu_to_le32(1<<4)
1506 #define AAC_OPT_RAID50                  cpu_to_le32(1<<5)
1507 #define AAC_OPT_4GB_WINDOW              cpu_to_le32(1<<6)
1508 #define AAC_OPT_SCSI_UPGRADEABLE        cpu_to_le32(1<<7)
1509 #define AAC_OPT_SOFT_ERR_REPORT         cpu_to_le32(1<<8)
1510 #define AAC_OPT_SUPPORTED_RECONDITION   cpu_to_le32(1<<9)
1511 #define AAC_OPT_SGMAP_HOST64            cpu_to_le32(1<<10)
1512 #define AAC_OPT_ALARM                   cpu_to_le32(1<<11)
1513 #define AAC_OPT_NONDASD                 cpu_to_le32(1<<12)
1514 #define AAC_OPT_SCSI_MANAGED            cpu_to_le32(1<<13)
1515 #define AAC_OPT_RAID_SCSI_MODE          cpu_to_le32(1<<14)
1516 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1517 #define AAC_OPT_NEW_COMM                cpu_to_le32(1<<17)
1518 #define AAC_OPT_NEW_COMM_64             cpu_to_le32(1<<18)
1519 #define AAC_OPT_EXTENDED                cpu_to_le32(1<<23)
1520 #define AAC_OPT_NATIVE_HBA              cpu_to_le32(1<<25)
1521 #define AAC_OPT_NEW_COMM_TYPE1          cpu_to_le32(1<<28)
1522 #define AAC_OPT_NEW_COMM_TYPE2          cpu_to_le32(1<<29)
1523 #define AAC_OPT_NEW_COMM_TYPE3          cpu_to_le32(1<<30)
1524 #define AAC_OPT_NEW_COMM_TYPE4          cpu_to_le32(1<<31)
1525
1526 #define AAC_COMM_PRODUCER               0
1527 #define AAC_COMM_MESSAGE                1
1528 #define AAC_COMM_MESSAGE_TYPE1          3
1529 #define AAC_COMM_MESSAGE_TYPE2          4
1530 #define AAC_COMM_MESSAGE_TYPE3          5
1531
1532 #define AAC_EXTOPT_SA_FIRMWARE          cpu_to_le32(1<<1)
1533 #define AAC_EXTOPT_SOFT_RESET           cpu_to_le32(1<<16)
1534
1535 /* MSIX context */
1536 struct aac_msix_ctx {
1537         int             vector_no;
1538         struct aac_dev  *dev;
1539 };
1540
1541 struct aac_dev
1542 {
1543         struct list_head        entry;
1544         const char              *name;
1545         int                     id;
1546
1547         /*
1548          *      negotiated FIB settings
1549          */
1550         unsigned int            max_fib_size;
1551         unsigned int            sg_tablesize;
1552         unsigned int            max_num_aif;
1553
1554         unsigned int            max_cmd_size;   /* max_fib_size or MAX_NATIVE */
1555
1556         /*
1557          *      Map for 128 fib objects (64k)
1558          */
1559         dma_addr_t              hw_fib_pa;      /* also used for native cmd */
1560         struct hw_fib           *hw_fib_va;     /* also used for native cmd */
1561         struct hw_fib           *aif_base_va;
1562         /*
1563          *      Fib Headers
1564          */
1565         struct fib              *fibs;
1566
1567         struct fib              *free_fib;
1568         spinlock_t              fib_lock;
1569
1570         struct mutex            ioctl_mutex;
1571         struct mutex            scan_mutex;
1572         struct aac_queue_block *queues;
1573         /*
1574          *      The user API will use an IOCTL to register itself to receive
1575          *      FIBs from the adapter.  The following list is used to keep
1576          *      track of all the threads that have requested these FIBs.  The
1577          *      mutex is used to synchronize access to all data associated
1578          *      with the adapter fibs.
1579          */
1580         struct list_head        fib_list;
1581
1582         struct adapter_ops      a_ops;
1583         unsigned long           fsrev;          /* Main driver's revision number */
1584
1585         resource_size_t         base_start;     /* main IO base */
1586         resource_size_t         dbg_base;       /* address of UART
1587                                                  * debug buffer */
1588
1589         resource_size_t         base_size, dbg_size;    /* Size of
1590                                                          *  mapped in region */
1591         /*
1592          * Holds initialization info
1593          * to communicate with adapter
1594          */
1595         union aac_init          *init;
1596         dma_addr_t              init_pa;        /* Holds physical address of the init struct */
1597         /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1598         __le32                  *host_rrq;
1599         dma_addr_t              host_rrq_pa;    /* phys. address */
1600         /* index into rrq buffer */
1601         u32                     host_rrq_idx[AAC_MAX_MSIX];
1602         atomic_t                rrq_outstanding[AAC_MAX_MSIX];
1603         u32                     fibs_pushed_no;
1604         struct pci_dev          *pdev;          /* Our PCI interface */
1605         /* pointer to buffer used for printf's from the adapter */
1606         void                    *printfbuf;
1607         void                    *comm_addr;     /* Base address of Comm area */
1608         dma_addr_t              comm_phys;      /* Physical Address of Comm area */
1609         size_t                  comm_size;
1610
1611         struct Scsi_Host        *scsi_host_ptr;
1612         int                     maximum_num_containers;
1613         int                     maximum_num_physicals;
1614         int                     maximum_num_channels;
1615         struct fsa_dev_info     *fsa_dev;
1616         struct task_struct      *thread;
1617         struct delayed_work     safw_rescan_work;
1618         int                     cardtype;
1619         /*
1620          *This lock will protect the two 32-bit
1621          *writes to the Inbound Queue
1622          */
1623         spinlock_t              iq_lock;
1624
1625         /*
1626          *      The following is the device specific extension.
1627          */
1628 #ifndef AAC_MIN_FOOTPRINT_SIZE
1629 #       define AAC_MIN_FOOTPRINT_SIZE 8192
1630 #       define AAC_MIN_SRC_BAR0_SIZE 0x400000
1631 #       define AAC_MIN_SRC_BAR1_SIZE 0x800
1632 #       define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1633 #       define AAC_MIN_SRCV_BAR1_SIZE 0x400
1634 #endif
1635         union
1636         {
1637                 struct sa_registers __iomem *sa;
1638                 struct rx_registers __iomem *rx;
1639                 struct rkt_registers __iomem *rkt;
1640                 struct {
1641                         struct src_registers __iomem *bar0;
1642                         char __iomem *bar1;
1643                 } src;
1644         } regs;
1645         volatile void __iomem *base, *dbg_base_mapped;
1646         volatile struct rx_inbound __iomem *IndexRegs;
1647         u32                     OIMR; /* Mask Register Cache */
1648         /*
1649          *      AIF thread states
1650          */
1651         u32                     aif_thread;
1652         struct aac_adapter_info adapter_info;
1653         struct aac_supplement_adapter_info supplement_adapter_info;
1654         /* These are in adapter info but they are in the io flow so
1655          * lets break them out so we don't have to do an AND to check them
1656          */
1657         u8                      nondasd_support;
1658         u8                      jbod;
1659         u8                      cache_protected;
1660         u8                      dac_support;
1661         u8                      needs_dac;
1662         u8                      raid_scsi_mode;
1663         u8                      comm_interface;
1664         u8                      raw_io_interface;
1665         u8                      raw_io_64;
1666         u8                      printf_enabled;
1667         u8                      in_reset;
1668         u8                      in_soft_reset;
1669         u8                      msi;
1670         u8                      sa_firmware;
1671         int                     management_fib_count;
1672         spinlock_t              manage_lock;
1673         spinlock_t              sync_lock;
1674         int                     sync_mode;
1675         struct fib              *sync_fib;
1676         struct list_head        sync_fib_list;
1677         u32                     doorbell_mask;
1678         u32                     max_msix;       /* max. MSI-X vectors */
1679         u32                     vector_cap;     /* MSI-X vector capab.*/
1680         int                     msi_enabled;    /* MSI/MSI-X enabled */
1681         atomic_t                msix_counter;
1682         u32                     scan_counter;
1683         struct msix_entry       msixentry[AAC_MAX_MSIX];
1684         struct aac_msix_ctx     aac_msix[AAC_MAX_MSIX]; /* context */
1685         struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1686         struct aac_ciss_phys_luns_resp *safw_phys_luns;
1687         u8                      adapter_shutdown;
1688         u32                     handle_pci_error;
1689         bool                    init_reset;
1690 };
1691
1692 #define aac_adapter_interrupt(dev) \
1693         (dev)->a_ops.adapter_interrupt(dev)
1694
1695 #define aac_adapter_notify(dev, event) \
1696         (dev)->a_ops.adapter_notify(dev, event)
1697
1698 #define aac_adapter_disable_int(dev) \
1699         (dev)->a_ops.adapter_disable_int(dev)
1700
1701 #define aac_adapter_enable_int(dev) \
1702         (dev)->a_ops.adapter_enable_int(dev)
1703
1704 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1705         (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1706
1707 #define aac_adapter_restart(dev, bled, reset_type) \
1708         ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1709
1710 #define aac_adapter_start(dev) \
1711         ((dev)->a_ops.adapter_start(dev))
1712
1713 #define aac_adapter_ioremap(dev, size) \
1714         (dev)->a_ops.adapter_ioremap(dev, size)
1715
1716 #define aac_adapter_deliver(fib) \
1717         ((fib)->dev)->a_ops.adapter_deliver(fib)
1718
1719 #define aac_adapter_bounds(dev,cmd,lba) \
1720         dev->a_ops.adapter_bounds(dev,cmd,lba)
1721
1722 #define aac_adapter_read(fib,cmd,lba,count) \
1723         ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1724
1725 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1726         ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1727
1728 #define aac_adapter_scsi(fib,cmd) \
1729         ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1730
1731 #define aac_adapter_comm(dev,comm) \
1732         (dev)->a_ops.adapter_comm(dev, comm)
1733
1734 #define FIB_CONTEXT_FLAG_TIMED_OUT              (0x00000001)
1735 #define FIB_CONTEXT_FLAG                        (0x00000002)
1736 #define FIB_CONTEXT_FLAG_WAIT                   (0x00000004)
1737 #define FIB_CONTEXT_FLAG_FASTRESP               (0x00000008)
1738 #define FIB_CONTEXT_FLAG_NATIVE_HBA             (0x00000010)
1739 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1740 #define FIB_CONTEXT_FLAG_SCSI_CMD       (0x00000040)
1741 #define FIB_CONTEXT_FLAG_EH_RESET       (0x00000080)
1742
1743 /*
1744  *      Define the command values
1745  */
1746
1747 #define         Null                    0
1748 #define         GetAttributes           1
1749 #define         SetAttributes           2
1750 #define         Lookup                  3
1751 #define         ReadLink                4
1752 #define         Read                    5
1753 #define         Write                   6
1754 #define         Create                  7
1755 #define         MakeDirectory           8
1756 #define         SymbolicLink            9
1757 #define         MakeNode                10
1758 #define         Removex                 11
1759 #define         RemoveDirectoryx        12
1760 #define         Rename                  13
1761 #define         Link                    14
1762 #define         ReadDirectory           15
1763 #define         ReadDirectoryPlus       16
1764 #define         FileSystemStatus        17
1765 #define         FileSystemInfo          18
1766 #define         PathConfigure           19
1767 #define         Commit                  20
1768 #define         Mount                   21
1769 #define         UnMount                 22
1770 #define         Newfs                   23
1771 #define         FsCheck                 24
1772 #define         FsSync                  25
1773 #define         SimReadWrite            26
1774 #define         SetFileSystemStatus     27
1775 #define         BlockRead               28
1776 #define         BlockWrite              29
1777 #define         NvramIoctl              30
1778 #define         FsSyncWait              31
1779 #define         ClearArchiveBit         32
1780 #define         SetAcl                  33
1781 #define         GetAcl                  34
1782 #define         AssignAcl               35
1783 #define         FaultInsertion          36      /* Fault Insertion Command */
1784 #define         CrazyCache              37      /* Crazycache */
1785
1786 #define         MAX_FSACOMMAND_NUM      38
1787
1788
1789 /*
1790  *      Define the status returns. These are very unixlike although
1791  *      most are not in fact used
1792  */
1793
1794 #define         ST_OK           0
1795 #define         ST_PERM         1
1796 #define         ST_NOENT        2
1797 #define         ST_IO           5
1798 #define         ST_NXIO         6
1799 #define         ST_E2BIG        7
1800 #define         ST_MEDERR       8
1801 #define         ST_ACCES        13
1802 #define         ST_EXIST        17
1803 #define         ST_XDEV         18
1804 #define         ST_NODEV        19
1805 #define         ST_NOTDIR       20
1806 #define         ST_ISDIR        21
1807 #define         ST_INVAL        22
1808 #define         ST_FBIG         27
1809 #define         ST_NOSPC        28
1810 #define         ST_ROFS         30
1811 #define         ST_MLINK        31
1812 #define         ST_WOULDBLOCK   35
1813 #define         ST_NAMETOOLONG  63
1814 #define         ST_NOTEMPTY     66
1815 #define         ST_DQUOT        69
1816 #define         ST_STALE        70
1817 #define         ST_REMOTE       71
1818 #define         ST_NOT_READY    72
1819 #define         ST_BADHANDLE    10001
1820 #define         ST_NOT_SYNC     10002
1821 #define         ST_BAD_COOKIE   10003
1822 #define         ST_NOTSUPP      10004
1823 #define         ST_TOOSMALL     10005
1824 #define         ST_SERVERFAULT  10006
1825 #define         ST_BADTYPE      10007
1826 #define         ST_JUKEBOX      10008
1827 #define         ST_NOTMOUNTED   10009
1828 #define         ST_MAINTMODE    10010
1829 #define         ST_STALEACL     10011
1830
1831 /*
1832  *      On writes how does the client want the data written.
1833  */
1834
1835 #define CACHE_CSTABLE           1
1836 #define CACHE_UNSTABLE          2
1837
1838 /*
1839  *      Lets the client know at which level the data was committed on
1840  *      a write request
1841  */
1842
1843 #define CMFILE_SYNCH_NVRAM      1
1844 #define CMDATA_SYNCH_NVRAM      2
1845 #define CMFILE_SYNCH            3
1846 #define CMDATA_SYNCH            4
1847 #define CMUNSTABLE              5
1848
1849 #define RIO_TYPE_WRITE                  0x0000
1850 #define RIO_TYPE_READ                   0x0001
1851 #define RIO_SUREWRITE                   0x0008
1852
1853 #define RIO2_IO_TYPE                    0x0003
1854 #define RIO2_IO_TYPE_WRITE              0x0000
1855 #define RIO2_IO_TYPE_READ               0x0001
1856 #define RIO2_IO_TYPE_VERIFY             0x0002
1857 #define RIO2_IO_ERROR                   0x0004
1858 #define RIO2_IO_SUREWRITE               0x0008
1859 #define RIO2_SGL_CONFORMANT             0x0010
1860 #define RIO2_SG_FORMAT                  0xF000
1861 #define RIO2_SG_FORMAT_ARC              0x0000
1862 #define RIO2_SG_FORMAT_SRL              0x1000
1863 #define RIO2_SG_FORMAT_IEEE1212         0x2000
1864
1865 struct aac_read
1866 {
1867         __le32          command;
1868         __le32          cid;
1869         __le32          block;
1870         __le32          count;
1871         struct sgmap    sg;     // Must be last in struct because it is variable
1872 };
1873
1874 struct aac_read64
1875 {
1876         __le32          command;
1877         __le16          cid;
1878         __le16          sector_count;
1879         __le32          block;
1880         __le16          pad;
1881         __le16          flags;
1882         struct sgmap64  sg;     // Must be last in struct because it is variable
1883 };
1884
1885 struct aac_read_reply
1886 {
1887         __le32          status;
1888         __le32          count;
1889 };
1890
1891 struct aac_write
1892 {
1893         __le32          command;
1894         __le32          cid;
1895         __le32          block;
1896         __le32          count;
1897         __le32          stable; // Not used
1898         struct sgmap    sg;     // Must be last in struct because it is variable
1899 };
1900
1901 struct aac_write64
1902 {
1903         __le32          command;
1904         __le16          cid;
1905         __le16          sector_count;
1906         __le32          block;
1907         __le16          pad;
1908         __le16          flags;
1909         struct sgmap64  sg;     // Must be last in struct because it is variable
1910 };
1911 struct aac_write_reply
1912 {
1913         __le32          status;
1914         __le32          count;
1915         __le32          committed;
1916 };
1917
1918 struct aac_raw_io
1919 {
1920         __le32          block[2];
1921         __le32          count;
1922         __le16          cid;
1923         __le16          flags;          /* 00 W, 01 R */
1924         __le16          bpTotal;        /* reserved for F/W use */
1925         __le16          bpComplete;     /* reserved for F/W use */
1926         struct sgmapraw sg;
1927 };
1928
1929 struct aac_raw_io2 {
1930         __le32          blockLow;
1931         __le32          blockHigh;
1932         __le32          byteCount;
1933         __le16          cid;
1934         __le16          flags;          /* RIO2 flags */
1935         __le32          sgeFirstSize;   /* size of first sge el. */
1936         __le32          sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1937         u8              sgeCnt;         /* only 8 bits required */
1938         u8              bpTotal;        /* reserved for F/W use */
1939         u8              bpComplete;     /* reserved for F/W use */
1940         u8              sgeFirstIndex;  /* reserved for F/W use */
1941         u8              unused[4];
1942         struct sge_ieee1212     sge[1];
1943 };
1944
1945 #define CT_FLUSH_CACHE 129
1946 struct aac_synchronize {
1947         __le32          command;        /* VM_ContainerConfig */
1948         __le32          type;           /* CT_FLUSH_CACHE */
1949         __le32          cid;
1950         __le32          parm1;
1951         __le32          parm2;
1952         __le32          parm3;
1953         __le32          parm4;
1954         __le32          count;  /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1955 };
1956
1957 struct aac_synchronize_reply {
1958         __le32          dummy0;
1959         __le32          dummy1;
1960         __le32          status; /* CT_OK */
1961         __le32          parm1;
1962         __le32          parm2;
1963         __le32          parm3;
1964         __le32          parm4;
1965         __le32          parm5;
1966         u8              data[16];
1967 };
1968
1969 #define CT_POWER_MANAGEMENT     245
1970 #define CT_PM_START_UNIT        2
1971 #define CT_PM_STOP_UNIT         3
1972 #define CT_PM_UNIT_IMMEDIATE    1
1973 struct aac_power_management {
1974         __le32          command;        /* VM_ContainerConfig */
1975         __le32          type;           /* CT_POWER_MANAGEMENT */
1976         __le32          sub;            /* CT_PM_* */
1977         __le32          cid;
1978         __le32          parm;           /* CT_PM_sub_* */
1979 };
1980
1981 #define CT_PAUSE_IO    65
1982 #define CT_RELEASE_IO  66
1983 struct aac_pause {
1984         __le32          command;        /* VM_ContainerConfig */
1985         __le32          type;           /* CT_PAUSE_IO */
1986         __le32          timeout;        /* 10ms ticks */
1987         __le32          min;
1988         __le32          noRescan;
1989         __le32          parm3;
1990         __le32          parm4;
1991         __le32          count;  /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1992 };
1993
1994 struct aac_srb
1995 {
1996         __le32          function;
1997         __le32          channel;
1998         __le32          id;
1999         __le32          lun;
2000         __le32          timeout;
2001         __le32          flags;
2002         __le32          count;          // Data xfer size
2003         __le32          retry_limit;
2004         __le32          cdb_size;
2005         u8              cdb[16];
2006         struct  sgmap   sg;
2007 };
2008
2009 /*
2010  * This and associated data structs are used by the
2011  * ioctl caller and are in cpu order.
2012  */
2013 struct user_aac_srb
2014 {
2015         u32             function;
2016         u32             channel;
2017         u32             id;
2018         u32             lun;
2019         u32             timeout;
2020         u32             flags;
2021         u32             count;          // Data xfer size
2022         u32             retry_limit;
2023         u32             cdb_size;
2024         u8              cdb[16];
2025         struct  user_sgmap      sg;
2026 };
2027
2028 #define         AAC_SENSE_BUFFERSIZE     30
2029
2030 struct aac_srb_reply
2031 {
2032         __le32          status;
2033         __le32          srb_status;
2034         __le32          scsi_status;
2035         __le32          data_xfer_length;
2036         __le32          sense_data_size;
2037         u8              sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
2038 };
2039
2040 struct aac_srb_unit {
2041         struct aac_srb          srb;
2042         struct aac_srb_reply    srb_reply;
2043 };
2044
2045 /*
2046  * SRB Flags
2047  */
2048 #define         SRB_NoDataXfer           0x0000
2049 #define         SRB_DisableDisconnect    0x0004
2050 #define         SRB_DisableSynchTransfer 0x0008
2051 #define         SRB_BypassFrozenQueue    0x0010
2052 #define         SRB_DisableAutosense     0x0020
2053 #define         SRB_DataIn               0x0040
2054 #define         SRB_DataOut              0x0080
2055
2056 /*
2057  * SRB Functions - set in aac_srb->function
2058  */
2059 #define SRBF_ExecuteScsi        0x0000
2060 #define SRBF_ClaimDevice        0x0001
2061 #define SRBF_IO_Control         0x0002
2062 #define SRBF_ReceiveEvent       0x0003
2063 #define SRBF_ReleaseQueue       0x0004
2064 #define SRBF_AttachDevice       0x0005
2065 #define SRBF_ReleaseDevice      0x0006
2066 #define SRBF_Shutdown           0x0007
2067 #define SRBF_Flush              0x0008
2068 #define SRBF_AbortCommand       0x0010
2069 #define SRBF_ReleaseRecovery    0x0011
2070 #define SRBF_ResetBus           0x0012
2071 #define SRBF_ResetDevice        0x0013
2072 #define SRBF_TerminateIO        0x0014
2073 #define SRBF_FlushQueue         0x0015
2074 #define SRBF_RemoveDevice       0x0016
2075 #define SRBF_DomainValidation   0x0017
2076
2077 /*
2078  * SRB SCSI Status - set in aac_srb->scsi_status
2079  */
2080 #define SRB_STATUS_PENDING                  0x00
2081 #define SRB_STATUS_SUCCESS                  0x01
2082 #define SRB_STATUS_ABORTED                  0x02
2083 #define SRB_STATUS_ABORT_FAILED             0x03
2084 #define SRB_STATUS_ERROR                    0x04
2085 #define SRB_STATUS_BUSY                     0x05
2086 #define SRB_STATUS_INVALID_REQUEST          0x06
2087 #define SRB_STATUS_INVALID_PATH_ID          0x07
2088 #define SRB_STATUS_NO_DEVICE                0x08
2089 #define SRB_STATUS_TIMEOUT                  0x09
2090 #define SRB_STATUS_SELECTION_TIMEOUT        0x0A
2091 #define SRB_STATUS_COMMAND_TIMEOUT          0x0B
2092 #define SRB_STATUS_MESSAGE_REJECTED         0x0D
2093 #define SRB_STATUS_BUS_RESET                0x0E
2094 #define SRB_STATUS_PARITY_ERROR             0x0F
2095 #define SRB_STATUS_REQUEST_SENSE_FAILED     0x10
2096 #define SRB_STATUS_NO_HBA                   0x11
2097 #define SRB_STATUS_DATA_OVERRUN             0x12
2098 #define SRB_STATUS_UNEXPECTED_BUS_FREE      0x13
2099 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE   0x14
2100 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH     0x15
2101 #define SRB_STATUS_REQUEST_FLUSHED          0x16
2102 #define SRB_STATUS_DELAYED_RETRY            0x17
2103 #define SRB_STATUS_INVALID_LUN              0x20
2104 #define SRB_STATUS_INVALID_TARGET_ID        0x21
2105 #define SRB_STATUS_BAD_FUNCTION             0x22
2106 #define SRB_STATUS_ERROR_RECOVERY           0x23
2107 #define SRB_STATUS_NOT_STARTED              0x24
2108 #define SRB_STATUS_NOT_IN_USE               0x30
2109 #define SRB_STATUS_FORCE_ABORT              0x31
2110 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL   0x32
2111
2112 /*
2113  * Object-Server / Volume-Manager Dispatch Classes
2114  */
2115
2116 #define         VM_Null                 0
2117 #define         VM_NameServe            1
2118 #define         VM_ContainerConfig      2
2119 #define         VM_Ioctl                3
2120 #define         VM_FilesystemIoctl      4
2121 #define         VM_CloseAll             5
2122 #define         VM_CtBlockRead          6
2123 #define         VM_CtBlockWrite         7
2124 #define         VM_SliceBlockRead       8       /* raw access to configured "storage objects" */
2125 #define         VM_SliceBlockWrite      9
2126 #define         VM_DriveBlockRead       10      /* raw access to physical devices */
2127 #define         VM_DriveBlockWrite      11
2128 #define         VM_EnclosureMgt         12      /* enclosure management */
2129 #define         VM_Unused               13      /* used to be diskset management */
2130 #define         VM_CtBlockVerify        14
2131 #define         VM_CtPerf               15      /* performance test */
2132 #define         VM_CtBlockRead64        16
2133 #define         VM_CtBlockWrite64       17
2134 #define         VM_CtBlockVerify64      18
2135 #define         VM_CtHostRead64         19
2136 #define         VM_CtHostWrite64        20
2137 #define         VM_DrvErrTblLog         21
2138 #define         VM_NameServe64          22
2139 #define         VM_NameServeAllBlk      30
2140
2141 #define         MAX_VMCOMMAND_NUM       23      /* used for sizing stats array - leave last */
2142
2143 /*
2144  *      Descriptive information (eg, vital stats)
2145  *      that a content manager might report.  The
2146  *      FileArray filesystem component is one example
2147  *      of a content manager.  Raw mode might be
2148  *      another.
2149  */
2150
2151 struct aac_fsinfo {
2152         __le32  fsTotalSize;    /* Consumed by fs, incl. metadata */
2153         __le32  fsBlockSize;
2154         __le32  fsFragSize;
2155         __le32  fsMaxExtendSize;
2156         __le32  fsSpaceUnits;
2157         __le32  fsMaxNumFiles;
2158         __le32  fsNumFreeFiles;
2159         __le32  fsInodeDensity;
2160 };      /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
2161
2162 struct  aac_blockdevinfo {
2163         __le32  block_size;
2164         __le32  logical_phys_map;
2165         u8      identifier[16];
2166 };
2167
2168 union aac_contentinfo {
2169         struct  aac_fsinfo              filesys;
2170         struct  aac_blockdevinfo        bdevinfo;
2171 };
2172
2173 /*
2174  *      Query for Container Configuration Status
2175  */
2176
2177 #define CT_GET_CONFIG_STATUS 147
2178 struct aac_get_config_status {
2179         __le32          command;        /* VM_ContainerConfig */
2180         __le32          type;           /* CT_GET_CONFIG_STATUS */
2181         __le32          parm1;
2182         __le32          parm2;
2183         __le32          parm3;
2184         __le32          parm4;
2185         __le32          parm5;
2186         __le32          count;  /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2187 };
2188
2189 #define CFACT_CONTINUE 0
2190 #define CFACT_PAUSE    1
2191 #define CFACT_ABORT    2
2192 struct aac_get_config_status_resp {
2193         __le32          response; /* ST_OK */
2194         __le32          dummy0;
2195         __le32          status; /* CT_OK */
2196         __le32          parm1;
2197         __le32          parm2;
2198         __le32          parm3;
2199         __le32          parm4;
2200         __le32          parm5;
2201         struct {
2202                 __le32  action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
2203                 __le16  flags;
2204                 __le16  count;
2205         }               data;
2206 };
2207
2208 /*
2209  *      Accept the configuration as-is
2210  */
2211
2212 #define CT_COMMIT_CONFIG 152
2213
2214 struct aac_commit_config {
2215         __le32          command;        /* VM_ContainerConfig */
2216         __le32          type;           /* CT_COMMIT_CONFIG */
2217 };
2218
2219 /*
2220  *      Query for Container Configuration Status
2221  */
2222
2223 #define CT_GET_CONTAINER_COUNT 4
2224 struct aac_get_container_count {
2225         __le32          command;        /* VM_ContainerConfig */
2226         __le32          type;           /* CT_GET_CONTAINER_COUNT */
2227 };
2228
2229 struct aac_get_container_count_resp {
2230         __le32          response; /* ST_OK */
2231         __le32          dummy0;
2232         __le32          MaxContainers;
2233         __le32          ContainerSwitchEntries;
2234         __le32          MaxPartitions;
2235         __le32          MaxSimpleVolumes;
2236 };
2237
2238
2239 /*
2240  *      Query for "mountable" objects, ie, objects that are typically
2241  *      associated with a drive letter on the client (host) side.
2242  */
2243
2244 struct aac_mntent {
2245         __le32                  oid;
2246         u8                      name[16];       /* if applicable */
2247         struct creation_info    create_info;    /* if applicable */
2248         __le32                  capacity;
2249         __le32                  vol;            /* substrate structure */
2250         __le32                  obj;            /* FT_FILESYS, etc. */
2251         __le32                  state;          /* unready for mounting,
2252                                                    readonly, etc. */
2253         union aac_contentinfo   fileinfo;       /* Info specific to content
2254                                                    manager (eg, filesystem) */
2255         __le32                  altoid;         /* != oid <==> snapshot or
2256                                                    broken mirror exists */
2257         __le32                  capacityhigh;
2258 };
2259
2260 #define FSCS_NOTCLEAN   0x0001  /* fsck is necessary before mounting */
2261 #define FSCS_READONLY   0x0002  /* possible result of broken mirror */
2262 #define FSCS_HIDDEN     0x0004  /* should be ignored - set during a clear */
2263 #define FSCS_NOT_READY  0x0008  /* Array spinning up to fulfil request */
2264
2265 struct aac_query_mount {
2266         __le32          command;
2267         __le32          type;
2268         __le32          count;
2269 };
2270
2271 struct aac_mount {
2272         __le32          status;
2273         __le32          type;           /* should be same as that requested */
2274         __le32          count;
2275         struct aac_mntent mnt[1];
2276 };
2277
2278 #define CT_READ_NAME 130
2279 struct aac_get_name {
2280         __le32          command;        /* VM_ContainerConfig */
2281         __le32          type;           /* CT_READ_NAME */
2282         __le32          cid;
2283         __le32          parm1;
2284         __le32          parm2;
2285         __le32          parm3;
2286         __le32          parm4;
2287         __le32          count;  /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2288 };
2289
2290 struct aac_get_name_resp {
2291         __le32          dummy0;
2292         __le32          dummy1;
2293         __le32          status; /* CT_OK */
2294         __le32          parm1;
2295         __le32          parm2;
2296         __le32          parm3;
2297         __le32          parm4;
2298         __le32          parm5;
2299         u8              data[17];
2300 };
2301
2302 #define CT_CID_TO_32BITS_UID 165
2303 struct aac_get_serial {
2304         __le32          command;        /* VM_ContainerConfig */
2305         __le32          type;           /* CT_CID_TO_32BITS_UID */
2306         __le32          cid;
2307 };
2308
2309 struct aac_get_serial_resp {
2310         __le32          dummy0;
2311         __le32          dummy1;
2312         __le32          status; /* CT_OK */
2313         __le32          uid;
2314 };
2315
2316 /*
2317  * The following command is sent to shut down each container.
2318  */
2319
2320 struct aac_close {
2321         __le32  command;
2322         __le32  cid;
2323 };
2324
2325 struct aac_query_disk
2326 {
2327         s32     cnum;
2328         s32     bus;
2329         s32     id;
2330         s32     lun;
2331         u32     valid;
2332         u32     locked;
2333         u32     deleted;
2334         s32     instance;
2335         s8      name[10];
2336         u32     unmapped;
2337 };
2338
2339 struct aac_delete_disk {
2340         u32     disknum;
2341         u32     cnum;
2342 };
2343
2344 struct fib_ioctl
2345 {
2346         u32     fibctx;
2347         s32     wait;
2348         char    __user *fib;
2349 };
2350
2351 struct revision
2352 {
2353         u32 compat;
2354         __le32 version;
2355         __le32 build;
2356 };
2357
2358
2359 /*
2360  *      Ugly - non Linux like ioctl coding for back compat.
2361  */
2362
2363 #define CTL_CODE(function, method) (                 \
2364     (4<< 16) | ((function) << 2) | (method) \
2365 )
2366
2367 /*
2368  *      Define the method codes for how buffers are passed for I/O and FS
2369  *      controls
2370  */
2371
2372 #define METHOD_BUFFERED                 0
2373 #define METHOD_NEITHER                  3
2374
2375 /*
2376  *      Filesystem ioctls
2377  */
2378
2379 #define FSACTL_SENDFIB                          CTL_CODE(2050, METHOD_BUFFERED)
2380 #define FSACTL_SEND_RAW_SRB                     CTL_CODE(2067, METHOD_BUFFERED)
2381 #define FSACTL_DELETE_DISK                      0x163
2382 #define FSACTL_QUERY_DISK                       0x173
2383 #define FSACTL_OPEN_GET_ADAPTER_FIB             CTL_CODE(2100, METHOD_BUFFERED)
2384 #define FSACTL_GET_NEXT_ADAPTER_FIB             CTL_CODE(2101, METHOD_BUFFERED)
2385 #define FSACTL_CLOSE_GET_ADAPTER_FIB            CTL_CODE(2102, METHOD_BUFFERED)
2386 #define FSACTL_MINIPORT_REV_CHECK               CTL_CODE(2107, METHOD_BUFFERED)
2387 #define FSACTL_GET_PCI_INFO                     CTL_CODE(2119, METHOD_BUFFERED)
2388 #define FSACTL_FORCE_DELETE_DISK                CTL_CODE(2120, METHOD_NEITHER)
2389 #define FSACTL_GET_CONTAINERS                   2131
2390 #define FSACTL_SEND_LARGE_FIB                   CTL_CODE(2138, METHOD_BUFFERED)
2391 #define FSACTL_RESET_IOP                        CTL_CODE(2140, METHOD_BUFFERED)
2392 #define FSACTL_GET_HBA_INFO                     CTL_CODE(2150, METHOD_BUFFERED)
2393 /* flags defined for IOP & HW SOFT RESET */
2394 #define HW_IOP_RESET                            0x01
2395 #define HW_SOFT_RESET                           0x02
2396 #define IOP_HWSOFT_RESET                        (HW_IOP_RESET | HW_SOFT_RESET)
2397 /* HW Soft Reset register offset */
2398 #define IBW_SWR_OFFSET                          0x4000
2399 #define SOFT_RESET_TIME                 60
2400
2401
2402
2403 struct aac_common
2404 {
2405         /*
2406          *      If this value is set to 1 then interrupt moderation will occur
2407          *      in the base commuication support.
2408          */
2409         u32 irq_mod;
2410         u32 peak_fibs;
2411         u32 zero_fibs;
2412         u32 fib_timeouts;
2413         /*
2414          *      Statistical counters in debug mode
2415          */
2416 #ifdef DBG
2417         u32 FibsSent;
2418         u32 FibRecved;
2419         u32 NativeSent;
2420         u32 NativeRecved;
2421         u32 NoResponseSent;
2422         u32 NoResponseRecved;
2423         u32 AsyncSent;
2424         u32 AsyncRecved;
2425         u32 NormalSent;
2426         u32 NormalRecved;
2427 #endif
2428 };
2429
2430 extern struct aac_common aac_config;
2431
2432 /*
2433  * This is for management ioctl purpose only.
2434  */
2435 struct aac_hba_info {
2436
2437         u8      driver_name[50];
2438         u8      adapter_number;
2439         u8      system_io_bus_number;
2440         u8      device_number;
2441         u32     function_number;
2442         u32     vendor_id;
2443         u32     device_id;
2444         u32     sub_vendor_id;
2445         u32     sub_system_id;
2446         u32     mapped_base_address_size;
2447         u32     base_physical_address_high_part;
2448         u32     base_physical_address_low_part;
2449
2450         u32     max_command_size;
2451         u32     max_fib_size;
2452         u32     max_scatter_gather_from_os;
2453         u32     max_scatter_gather_to_fw;
2454         u32     max_outstanding_fibs;
2455
2456         u32     queue_start_threshold;
2457         u32     queue_dump_threshold;
2458         u32     max_io_size_queued;
2459         u32     outstanding_io;
2460
2461         u32     firmware_build_number;
2462         u32     bios_build_number;
2463         u32     driver_build_number;
2464         u32     serial_number_high_part;
2465         u32     serial_number_low_part;
2466         u32     supported_options;
2467         u32     feature_bits;
2468         u32     currentnumber_ports;
2469
2470         u8      new_comm_interface:1;
2471         u8      new_commands_supported:1;
2472         u8      disable_passthrough:1;
2473         u8      expose_non_dasd:1;
2474         u8      queue_allowed:1;
2475         u8      bled_check_enabled:1;
2476         u8      reserved1:1;
2477         u8      reserted2:1;
2478
2479         u32     reserved3[10];
2480
2481 };
2482
2483 /*
2484  *      The following macro is used when sending and receiving FIBs. It is
2485  *      only used for debugging.
2486  */
2487
2488 #ifdef DBG
2489 #define FIB_COUNTER_INCREMENT(counter)          (counter)++
2490 #else
2491 #define FIB_COUNTER_INCREMENT(counter)
2492 #endif
2493
2494 /*
2495  *      Adapter direct commands
2496  *      Monitor/Kernel API
2497  */
2498
2499 #define BREAKPOINT_REQUEST              0x00000004
2500 #define INIT_STRUCT_BASE_ADDRESS        0x00000005
2501 #define READ_PERMANENT_PARAMETERS       0x0000000a
2502 #define WRITE_PERMANENT_PARAMETERS      0x0000000b
2503 #define HOST_CRASHING                   0x0000000d
2504 #define SEND_SYNCHRONOUS_FIB            0x0000000c
2505 #define COMMAND_POST_RESULTS            0x00000014
2506 #define GET_ADAPTER_PROPERTIES          0x00000019
2507 #define GET_DRIVER_BUFFER_PROPERTIES    0x00000023
2508 #define RCV_TEMP_READINGS               0x00000025
2509 #define GET_COMM_PREFERRED_SETTINGS     0x00000026
2510 #define IOP_RESET_FW_FIB_DUMP           0x00000034
2511 #define DROP_IO                 0x00000035
2512 #define IOP_RESET                       0x00001000
2513 #define IOP_RESET_ALWAYS                0x00001001
2514 #define RE_INIT_ADAPTER         0x000000ee
2515
2516 #define IOP_SRC_RESET_MASK              0x00000100
2517
2518 /*
2519  *      Adapter Status Register
2520  *
2521  *  Phase Staus mailbox is 32bits:
2522  *      <31:16> = Phase Status
2523  *      <15:0>  = Phase
2524  *
2525  *      The adapter reports is present state through the phase.  Only
2526  *      a single phase should be ever be set.  Each phase can have multiple
2527  *      phase status bits to provide more detailed information about the
2528  *      state of the board.  Care should be taken to ensure that any phase
2529  *      status bits that are set when changing the phase are also valid
2530  *      for the new phase or be cleared out.  Adapter software (monitor,
2531  *      iflash, kernel) is responsible for properly maintining the phase
2532  *      status mailbox when it is running.
2533  *
2534  *      MONKER_API Phases
2535  *
2536  *      Phases are bit oriented.  It is NOT valid  to have multiple bits set
2537  */
2538
2539 #define SELF_TEST_FAILED                0x00000004
2540 #define MONITOR_PANIC                   0x00000020
2541 #define KERNEL_BOOTING                  0x00000040
2542 #define KERNEL_UP_AND_RUNNING           0x00000080
2543 #define KERNEL_PANIC                    0x00000100
2544 #define FLASH_UPD_PENDING               0x00002000
2545 #define FLASH_UPD_SUCCESS               0x00004000
2546 #define FLASH_UPD_FAILED                0x00008000
2547 #define INVALID_OMR                     0xffffffff
2548 #define FWUPD_TIMEOUT                   (5 * 60)
2549
2550 /*
2551  *      Doorbell bit defines
2552  */
2553
2554 #define DoorBellSyncCmdAvailable        (1<<0)  /* Host -> Adapter */
2555 #define DoorBellPrintfDone              (1<<5)  /* Host -> Adapter */
2556 #define DoorBellAdapterNormCmdReady     (1<<1)  /* Adapter -> Host */
2557 #define DoorBellAdapterNormRespReady    (1<<2)  /* Adapter -> Host */
2558 #define DoorBellAdapterNormCmdNotFull   (1<<3)  /* Adapter -> Host */
2559 #define DoorBellAdapterNormRespNotFull  (1<<4)  /* Adapter -> Host */
2560 #define DoorBellPrintfReady             (1<<5)  /* Adapter -> Host */
2561 #define DoorBellAifPending              (1<<6)  /* Adapter -> Host */
2562
2563 /* PMC specific outbound doorbell bits */
2564 #define PmDoorBellResponseSent          (1<<1)  /* Adapter -> Host */
2565
2566 /*
2567  *      For FIB communication, we need all of the following things
2568  *      to send back to the user.
2569  */
2570
2571 #define         AifCmdEventNotify       1       /* Notify of event */
2572 #define                 AifEnConfigChange       3       /* Adapter configuration change */
2573 #define                 AifEnContainerChange    4       /* Container configuration change */
2574 #define                 AifEnDeviceFailure      5       /* SCSI device failed */
2575 #define                 AifEnEnclosureManagement 13     /* EM_DRIVE_* */
2576 #define                         EM_DRIVE_INSERTION      31
2577 #define                         EM_DRIVE_REMOVAL        32
2578 #define                 EM_SES_DRIVE_INSERTION  33
2579 #define                 EM_SES_DRIVE_REMOVAL    26
2580 #define                 AifEnBatteryEvent       14      /* Change in Battery State */
2581 #define                 AifEnAddContainer       15      /* A new array was created */
2582 #define                 AifEnDeleteContainer    16      /* A container was deleted */
2583 #define                 AifEnExpEvent           23      /* Firmware Event Log */
2584 #define                 AifExeFirmwarePanic     3       /* Firmware Event Panic */
2585 #define                 AifHighPriority         3       /* Highest Priority Event */
2586 #define                 AifEnAddJBOD            30      /* JBOD created */
2587 #define                 AifEnDeleteJBOD         31      /* JBOD deleted */
2588
2589 #define                 AifBuManagerEvent               42 /* Bu management*/
2590 #define                 AifBuCacheDataLoss              10
2591 #define                 AifBuCacheDataRecover   11
2592
2593 #define         AifCmdJobProgress       2       /* Progress report */
2594 #define                 AifJobCtrZero   101     /* Array Zero progress */
2595 #define                 AifJobStsSuccess 1      /* Job completes */
2596 #define                 AifJobStsRunning 102    /* Job running */
2597 #define         AifCmdAPIReport         3       /* Report from other user of API */
2598 #define         AifCmdDriverNotify      4       /* Notify host driver of event */
2599 #define                 AifDenMorphComplete 200 /* A morph operation completed */
2600 #define                 AifDenVolumeExtendComplete 201 /* A volume extend completed */
2601 #define         AifReqJobList           100     /* Gets back complete job list */
2602 #define         AifReqJobsForCtr        101     /* Gets back jobs for specific container */
2603 #define         AifReqJobsForScsi       102     /* Gets back jobs for specific SCSI device */
2604 #define         AifReqJobReport         103     /* Gets back a specific job report or list of them */
2605 #define         AifReqTerminateJob      104     /* Terminates job */
2606 #define         AifReqSuspendJob        105     /* Suspends a job */
2607 #define         AifReqResumeJob         106     /* Resumes a job */
2608 #define         AifReqSendAPIReport     107     /* API generic report requests */
2609 #define         AifReqAPIJobStart       108     /* Start a job from the API */
2610 #define         AifReqAPIJobUpdate      109     /* Update a job report from the API */
2611 #define         AifReqAPIJobFinish      110     /* Finish a job from the API */
2612
2613 /* PMC NEW COMM: Request the event data */
2614 #define         AifReqEvent             200
2615 #define         AifRawDeviceRemove      203     /* RAW device deleted */
2616 #define         AifNativeDeviceAdd      204     /* native HBA device added */
2617 #define         AifNativeDeviceRemove   205     /* native HBA device removed */
2618
2619
2620 /*
2621  *      Adapter Initiated FIB command structures. Start with the adapter
2622  *      initiated FIBs that really come from the adapter, and get responded
2623  *      to by the host.
2624  */
2625
2626 struct aac_aifcmd {
2627         __le32 command;         /* Tell host what type of notify this is */
2628         __le32 seqnum;          /* To allow ordering of reports (if necessary) */
2629         u8 data[1];             /* Undefined length (from kernel viewpoint) */
2630 };
2631
2632 /**
2633  *      Convert capacity to cylinders
2634  *      accounting for the fact capacity could be a 64 bit value
2635  *
2636  */
2637 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2638 {
2639         sector_div(capacity, divisor);
2640         return capacity;
2641 }
2642
2643 static inline int aac_pci_offline(struct aac_dev *dev)
2644 {
2645         return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
2646 }
2647
2648 static inline int aac_adapter_check_health(struct aac_dev *dev)
2649 {
2650         if (unlikely(aac_pci_offline(dev)))
2651                 return -1;
2652
2653         return (dev)->a_ops.adapter_check_health(dev);
2654 }
2655
2656
2657 int aac_scan_host(struct aac_dev *dev);
2658
2659 static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2660 {
2661         schedule_delayed_work(&dev->safw_rescan_work, AAC_SAFW_RESCAN_DELAY);
2662 }
2663
2664 static inline void aac_safw_rescan_worker(struct work_struct *work)
2665 {
2666         struct aac_dev *dev = container_of(to_delayed_work(work),
2667                 struct aac_dev, safw_rescan_work);
2668
2669         wait_event(dev->scsi_host_ptr->host_wait,
2670                 !scsi_host_in_recovery(dev->scsi_host_ptr));
2671
2672         aac_scan_host(dev);
2673 }
2674
2675 static inline void aac_cancel_safw_rescan_worker(struct aac_dev *dev)
2676 {
2677         if (dev->sa_firmware)
2678                 cancel_delayed_work_sync(&dev->safw_rescan_work);
2679 }
2680
2681 /* SCp.phase values */
2682 #define AAC_OWNER_MIDLEVEL      0x101
2683 #define AAC_OWNER_LOWLEVEL      0x102
2684 #define AAC_OWNER_ERROR_HANDLER 0x103
2685 #define AAC_OWNER_FIRMWARE      0x106
2686
2687 void aac_safw_rescan_worker(struct work_struct *work);
2688 int aac_acquire_irq(struct aac_dev *dev);
2689 void aac_free_irq(struct aac_dev *dev);
2690 int aac_setup_safw_adapter(struct aac_dev *dev);
2691 const char *aac_driverinfo(struct Scsi_Host *);
2692 void aac_fib_vector_assign(struct aac_dev *dev);
2693 struct fib *aac_fib_alloc(struct aac_dev *dev);
2694 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2695 int aac_fib_setup(struct aac_dev *dev);
2696 void aac_fib_map_free(struct aac_dev *dev);
2697 void aac_fib_free(struct fib * context);
2698 void aac_fib_init(struct fib * context);
2699 void aac_printf(struct aac_dev *dev, u32 val);
2700 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2701 int aac_hba_send(u8 command, struct fib *context,
2702                 fib_callback callback, void *ctxt);
2703 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2704 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2705 int aac_fib_complete(struct fib * context);
2706 void aac_hba_callback(void *context, struct fib *fibptr);
2707 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2708 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2709 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2710 void aac_set_intx_mode(struct aac_dev *dev);
2711 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2712 int aac_get_containers(struct aac_dev *dev);
2713 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2714 int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2715 #ifndef shost_to_class
2716 #define shost_to_class(shost) &shost->shost_dev
2717 #endif
2718 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2719 int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2720 int aac_rx_init(struct aac_dev *dev);
2721 int aac_rkt_init(struct aac_dev *dev);
2722 int aac_nark_init(struct aac_dev *dev);
2723 int aac_sa_init(struct aac_dev *dev);
2724 int aac_src_init(struct aac_dev *dev);
2725 int aac_srcv_init(struct aac_dev *dev);
2726 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2727 void aac_define_int_mode(struct aac_dev *dev);
2728 unsigned int aac_response_normal(struct aac_queue * q);
2729 unsigned int aac_command_normal(struct aac_queue * q);
2730 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2731                         int isAif, int isFastResponse,
2732                         struct hw_fib *aif_fib);
2733 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2734 int aac_check_health(struct aac_dev * dev);
2735 int aac_command_thread(void *data);
2736 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2737 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2738 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2739 int aac_get_adapter_info(struct aac_dev* dev);
2740 int aac_send_shutdown(struct aac_dev *dev);
2741 int aac_probe_container(struct aac_dev *dev, int cid);
2742 int _aac_rx_init(struct aac_dev *dev);
2743 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2744 int aac_rx_deliver_producer(struct fib * fib);
2745
2746 static inline int aac_is_src(struct aac_dev *dev)
2747 {
2748         u16 device = dev->pdev->device;
2749
2750         if (device == PMC_DEVICE_S6 ||
2751                 device == PMC_DEVICE_S7 ||
2752                 device == PMC_DEVICE_S8)
2753                 return 1;
2754         return 0;
2755 }
2756
2757 static inline int aac_supports_2T(struct aac_dev *dev)
2758 {
2759         return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2760 }
2761
2762 char * get_container_type(unsigned type);
2763 extern int numacb;
2764 extern char aac_driver_version[];
2765 extern int startup_timeout;
2766 extern int aif_timeout;
2767 extern int expose_physicals;
2768 extern int aac_reset_devices;
2769 extern int aac_msi;
2770 extern int aac_commit;
2771 extern int update_interval;
2772 extern int check_interval;
2773 extern int aac_check_reset;
2774 extern int aac_fib_dump;
2775 #endif