include/kvm/arm_vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_H
  17 #define __KVM_ARM_VGIC_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/kvm.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/static_key.h>
  24 #include <linux/types.h>
  25 #include <kvm/iodev.h>
  26 #include <linux/list.h>
  27 #include <linux/jump_label.h>
  28
  29 #include <linux/irqchip/arm-gic-v4.h>
  30
  31 #define VGIC_V3_MAX_CPUS        255
  32 #define VGIC_V2_MAX_CPUS        8
  33 #define VGIC_NR_IRQS_LEGACY     256
  34 #define VGIC_NR_SGIS            16
  35 #define VGIC_NR_PPIS            16
  36 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
  37 #define VGIC_MAX_PRIVATE        (VGIC_NR_PRIVATE_IRQS - 1)
  38 #define VGIC_MAX_SPI            1019
  39 #define VGIC_MAX_RESERVED       1023
  40 #define VGIC_MIN_LPI            8192
  41 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
  42
  43 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
  44 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
  45                          (irq) <= VGIC_MAX_SPI)
  46
  47 enum vgic_type {
  48         VGIC_V2,                /* Good ol' GICv2 */
  49         VGIC_V3,                /* New fancy GICv3 */
  50 };
  51
  52 /* same for all guests, as depending only on the _host's_ GIC model */
  53 struct vgic_global {
  54         /* type of the host GIC */
  55         enum vgic_type          type;
  56
  57         /* Physical address of vgic virtual cpu interface */
  58         phys_addr_t             vcpu_base;
  59
  60         /* GICV mapping */
  61         void __iomem            *vcpu_base_va;
  62
  63         /* virtual control interface mapping */
  64         void __iomem            *vctrl_base;
  65
  66         /* Number of implemented list registers */
  67         int                     nr_lr;
  68
  69         /* Maintenance IRQ number */
  70         unsigned int            maint_irq;
  71
  72         /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
  73         int                     max_gic_vcpus;
  74
  75         /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  76         bool                    can_emulate_gicv2;
  77
  78         /* Hardware has GICv4? */
  79         bool                    has_gicv4;
  80
  81         /* GIC system register CPU interface */
  82         struct static_key_false gicv3_cpuif;
  83
  84         u32                     ich_vtr_el2;
  85 };
  86
  87 extern struct vgic_global kvm_vgic_global_state;
  88
  89 #define VGIC_V2_MAX_LRS         (1 << 6)
  90 #define VGIC_V3_MAX_LRS         16
  91 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
  92
  93 enum vgic_irq_config {
  94         VGIC_CONFIG_EDGE = 0,
  95         VGIC_CONFIG_LEVEL
  96 };
  97
  98 struct vgic_irq {
  99         spinlock_t irq_lock;            /* Protects the content of the struct */
 100         struct list_head lpi_list;      /* Used to link all LPIs together */
 101         struct list_head ap_list;
 102
 103         struct kvm_vcpu *vcpu;          /* SGIs and PPIs: The VCPU
 104                                          * SPIs and LPIs: The VCPU whose ap_list
 105                                          * this is queued on.
 106                                          */
 107
 108         struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
 109                                          * be sent to, as a result of the
 110                                          * targets reg (v2) or the
 111                                          * affinity reg (v3).
 112                                          */
 113
 114         u32 intid;                      /* Guest visible INTID */
 115         bool line_level;                /* Level only */
 116         bool pending_latch;             /* The pending latch state used to calculate
 117                                          * the pending state for both level
 118                                          * and edge triggered IRQs. */
 119         bool active;                    /* not used for LPIs */
 120         bool enabled;
 121         bool hw;                        /* Tied to HW IRQ */
 122         struct kref refcount;           /* Used for LPIs */
 123         u32 hwintid;                    /* HW INTID number */
 124         unsigned int host_irq;          /* linux irq corresponding to hwintid */
 125         union {
 126                 u8 targets;                     /* GICv2 target VCPUs mask */
 127                 u32 mpidr;                      /* GICv3 target VCPU */
 128         };
 129         u8 source;                      /* GICv2 SGIs only */
 130         u8 priority;
 131         enum vgic_irq_config config;    /* Level or edge */
 132
 133         /*
 134          * Callback function pointer to in-kernel devices that can tell us the
 135          * state of the input level of mapped level-triggered IRQ faster than
 136          * peaking into the physical GIC.
 137          *
 138          * Always called in non-preemptible section and the functions can use
 139          * kvm_arm_get_running_vcpu() to get the vcpu pointer for private
 140          * IRQs.
 141          */
 142         bool (*get_input_level)(int vintid);
 143
 144         void *owner;                    /* Opaque pointer to reserve an interrupt
 145                                            for in-kernel devices. */
 146 };
 147
 148 struct vgic_register_region;
 149 struct vgic_its;
 150
 151 enum iodev_type {
 152         IODEV_CPUIF,
 153         IODEV_DIST,
 154         IODEV_REDIST,
 155         IODEV_ITS
 156 };
 157
 158 struct vgic_io_device {
 159         gpa_t base_addr;
 160         union {
 161                 struct kvm_vcpu *redist_vcpu;
 162                 struct vgic_its *its;
 163         };
 164         const struct vgic_register_region *regions;
 165         enum iodev_type iodev_type;
 166         int nr_regions;
 167         struct kvm_io_device dev;
 168 };
 169
 170 struct vgic_its {
 171         /* The base address of the ITS control register frame */
 172         gpa_t                   vgic_its_base;
 173
 174         bool                    enabled;
 175         struct vgic_io_device   iodev;
 176         struct kvm_device       *dev;
 177
 178         /* These registers correspond to GITS_BASER{0,1} */
 179         u64                     baser_device_table;
 180         u64                     baser_coll_table;
 181
 182         /* Protects the command queue */
 183         struct mutex            cmd_lock;
 184         u64                     cbaser;
 185         u32                     creadr;
 186         u32                     cwriter;
 187
 188         /* migration ABI revision in use */
 189         u32                     abi_rev;
 190
 191         /* Protects the device and collection lists */
 192         struct mutex            its_lock;
 193         struct list_head        device_list;
 194         struct list_head        collection_list;
 195 };
 196
 197 struct vgic_state_iter;
 198
 199 struct vgic_dist {
 200         bool                    in_kernel;
 201         bool                    ready;
 202         bool                    initialized;
 203
 204         /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
 205         u32                     vgic_model;
 206
 207         /* Do injected MSIs require an additional device ID? */
 208         bool                    msis_require_devid;
 209
 210         int                     nr_spis;
 211
 212         /* TODO: Consider moving to global state */
 213         /* Virtual control interface mapping */
 214         void __iomem            *vctrl_base;
 215
 216         /* base addresses in guest physical address space: */
 217         gpa_t                   vgic_dist_base;         /* distributor */
 218         union {
 219                 /* either a GICv2 CPU interface */
 220                 gpa_t                   vgic_cpu_base;
 221                 /* or a number of GICv3 redistributor regions */
 222                 struct {
 223                         gpa_t           vgic_redist_base;
 224                         gpa_t           vgic_redist_free_offset;
 225                 };
 226         };
 227
 228         /* distributor enabled */
 229         bool                    enabled;
 230
 231         struct vgic_irq         *spis;
 232
 233         struct vgic_io_device   dist_iodev;
 234
 235         bool                    has_its;
 236
 237         /*
 238          * Contains the attributes and gpa of the LPI configuration table.
 239          * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
 240          * one address across all redistributors.
 241          * GICv3 spec: 6.1.2 "LPI Configuration tables"
 242          */
 243         u64                     propbaser;
 244
 245         /* Protects the lpi_list and the count value below. */
 246         spinlock_t              lpi_list_lock;
 247         struct list_head        lpi_list_head;
 248         int                     lpi_list_count;
 249
 250         /* used by vgic-debug */
 251         struct vgic_state_iter *iter;
 252
 253         /*
 254          * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
 255          * array, the property table pointer as well as allocation
 256          * data. This essentially ties the Linux IRQ core and ITS
 257          * together, and avoids leaking KVM's data structures anywhere
 258          * else.
 259          */
 260         struct its_vm           its_vm;
 261 };
 262
 263 struct vgic_v2_cpu_if {
 264         u32             vgic_hcr;
 265         u32             vgic_vmcr;
 266         u64             vgic_elrsr;     /* Saved only */
 267         u32             vgic_apr;
 268         u32             vgic_lr[VGIC_V2_MAX_LRS];
 269 };
 270
 271 struct vgic_v3_cpu_if {
 272         u32             vgic_hcr;
 273         u32             vgic_vmcr;
 274         u32             vgic_sre;       /* Restored only, change ignored */
 275         u32             vgic_elrsr;     /* Saved only */
 276         u32             vgic_ap0r[4];
 277         u32             vgic_ap1r[4];
 278         u64             vgic_lr[VGIC_V3_MAX_LRS];
 279
 280         /*
 281          * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
 282          * pending table pointer, the its_vm pointer and a few other
 283          * HW specific things. As for the its_vm structure, this is
 284          * linking the Linux IRQ subsystem and the ITS together.
 285          */
 286         struct its_vpe  its_vpe;
 287 };
 288
 289 struct vgic_cpu {
 290         /* CPU vif control registers for world switch */
 291         union {
 292                 struct vgic_v2_cpu_if   vgic_v2;
 293                 struct vgic_v3_cpu_if   vgic_v3;
 294         };
 295
 296         unsigned int used_lrs;
 297         struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
 298
 299         spinlock_t ap_list_lock;        /* Protects the ap_list */
 300
 301         /*
 302          * List of IRQs that this VCPU should consider because they are either
 303          * Active or Pending (hence the name; AP list), or because they recently
 304          * were one of the two and need to be migrated off this list to another
 305          * VCPU.
 306          */
 307         struct list_head ap_list_head;
 308
 309         /*
 310          * Members below are used with GICv3 emulation only and represent
 311          * parts of the redistributor.
 312          */
 313         struct vgic_io_device   rd_iodev;
 314         struct vgic_io_device   sgi_iodev;
 315
 316         /* Contains the attributes and gpa of the LPI pending tables. */
 317         u64 pendbaser;
 318
 319         bool lpis_enabled;
 320
 321         /* Cache guest priority bits */
 322         u32 num_pri_bits;
 323
 324         /* Cache guest interrupt ID bits */
 325         u32 num_id_bits;
 326 };
 327
 328 extern struct static_key_false vgic_v2_cpuif_trap;
 329 extern struct static_key_false vgic_v3_cpuif_trap;
 330
 331 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
 332 void kvm_vgic_early_init(struct kvm *kvm);
 333 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
 334 int kvm_vgic_create(struct kvm *kvm, u32 type);
 335 void kvm_vgic_destroy(struct kvm *kvm);
 336 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
 337 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
 338 int kvm_vgic_map_resources(struct kvm *kvm);
 339 int kvm_vgic_hyp_init(void);
 340 void kvm_vgic_init_cpu_hardware(void);
 341
 342 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 343                         bool level, void *owner);
 344 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
 345                           u32 vintid, bool (*get_input_level)(int vindid));
 346 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
 347 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
 348
 349 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
 350
 351 void kvm_vgic_load(struct kvm_vcpu *vcpu);
 352 void kvm_vgic_put(struct kvm_vcpu *vcpu);
 353
 354 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
 355 #define vgic_initialized(k)     ((k)->arch.vgic.initialized)
 356 #define vgic_ready(k)           ((k)->arch.vgic.ready)
 357 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
 358                         ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 359
 360 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
 361 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
 362 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
 363
 364 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
 365
 366 /**
 367  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 368  *
 369  * The host's GIC naturally limits the maximum amount of VCPUs a guest
 370  * can use.
 371  */
 372 static inline int kvm_vgic_get_max_vcpus(void)
 373 {
 374         return kvm_vgic_global_state.max_gic_vcpus;
 375 }
 376
 377 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);
 378
 379 /**
 380  * kvm_vgic_setup_default_irq_routing:
 381  * Setup a default flat gsi routing table mapping all SPIs
 382  */
 383 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
 384
 385 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
 386
 387 struct kvm_kernel_irq_routing_entry;
 388
 389 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
 390                                struct kvm_kernel_irq_routing_entry *irq_entry);
 391
 392 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
 393                                  struct kvm_kernel_irq_routing_entry *irq_entry);
 394
 395 void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
 396 void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
 397
 398 #endif /* __KVM_ARM_VGIC_H */