net/mlx4_en: Move filters cleanup to a proper location
[linux/fpc-iii.git] / drivers / net / wireless / intel / iwlwifi / iwl-csr.h
blobb52913448c4acab76bc5e70c37acade0add76094
1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * GPL LICENSE SUMMARY
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
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29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
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65 *****************************************************************************/
66 #ifndef __iwl_csr_h__
67 #define __iwl_csr_h__
69 * CSR (control and status registers)
71 * CSR registers are mapped directly into PCI bus space, and are accessible
72 * whenever platform supplies power to device, even when device is in
73 * low power states due to driver-invoked device resets
74 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
76 * Use iwl_write32() and iwl_read32() family to access these registers;
77 * these provide simple PCI bus access, without waking up the MAC.
78 * Do not use iwl_write_direct32() family for these registers;
79 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
80 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
81 * the CSR registers.
83 * NOTE: Device does need to be awake in order to read this memory
84 * via CSR_EEPROM and CSR_OTP registers
86 #define CSR_BASE (0x000)
88 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
89 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
90 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
91 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
92 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
93 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
94 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
95 #define CSR_GP_CNTRL (CSR_BASE+0x024)
97 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
98 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
101 * Hardware revision info
102 * Bit fields:
103 * 31-16: Reserved
104 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
105 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
106 * 1-0: "Dash" (-) value, as in A-1, etc.
108 #define CSR_HW_REV (CSR_BASE+0x028)
111 * RF ID revision info
112 * Bit fields:
113 * 31:24: Reserved (set to 0x0)
114 * 23:12: Type
115 * 11:8: Step (A - 0x0, B - 0x1, etc)
116 * 7:4: Dash
117 * 3:0: Flavor
119 #define CSR_HW_RF_ID (CSR_BASE+0x09c)
122 * EEPROM and OTP (one-time-programmable) memory reads
124 * NOTE: Device must be awake, initialized via apm_ops.init(),
125 * in order to read.
127 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
128 #define CSR_EEPROM_GP (CSR_BASE+0x030)
129 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
131 #define CSR_GIO_REG (CSR_BASE+0x03C)
132 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
133 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
136 * UCODE-DRIVER GP (general purpose) mailbox registers.
137 * SET/CLR registers set/clear bit(s) if "1" is written.
139 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
140 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
141 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
142 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
144 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
146 #define CSR_LED_REG (CSR_BASE+0x094)
147 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
148 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
151 /* GIO Chicken Bits (PCI Express bus link power management) */
152 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
154 /* Analog phase-lock-loop configuration */
155 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
158 * CSR HW resources monitor registers
160 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
161 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
162 #define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
165 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
166 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
167 * See also CSR_HW_REV register.
168 * Bit fields:
169 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
170 * 1-0: "Dash" (-) value, as in C-1, etc.
172 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
174 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
175 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
177 /* Bits for CSR_HW_IF_CONFIG_REG */
178 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
179 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
180 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
181 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
182 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
183 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
184 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
185 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
187 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
188 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
189 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
190 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
191 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
192 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
194 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
195 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
196 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
197 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
198 #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
199 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
200 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
202 #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
204 #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
205 #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
207 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
208 * acknowledged (reset) by host writing "1" to flagged bits. */
209 #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
210 #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
211 #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
212 #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
213 #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
214 #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
215 #define CSR_INT_BIT_PAGING (1 << 24) /* SDIO PAGING */
216 #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
217 #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
218 #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
219 #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
220 #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
222 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
223 CSR_INT_BIT_HW_ERR | \
224 CSR_INT_BIT_FH_TX | \
225 CSR_INT_BIT_SW_ERR | \
226 CSR_INT_BIT_PAGING | \
227 CSR_INT_BIT_RF_KILL | \
228 CSR_INT_BIT_SW_RX | \
229 CSR_INT_BIT_WAKEUP | \
230 CSR_INT_BIT_ALIVE | \
231 CSR_INT_BIT_RX_PERIODIC)
233 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
234 #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
235 #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
236 #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
237 #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
238 #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
239 #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
241 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
242 CSR_FH_INT_BIT_RX_CHNL1 | \
243 CSR_FH_INT_BIT_RX_CHNL0)
245 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
246 CSR_FH_INT_BIT_TX_CHNL0)
248 /* GPIO */
249 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
250 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
251 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
253 /* RESET */
254 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
255 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
256 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
257 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
258 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
259 #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
262 * GP (general purpose) CONTROL REGISTER
263 * Bit fields:
264 * 27: HW_RF_KILL_SW
265 * Indicates state of (platform's) hardware RF-Kill switch
266 * 26-24: POWER_SAVE_TYPE
267 * Indicates current power-saving mode:
268 * 000 -- No power saving
269 * 001 -- MAC power-down
270 * 010 -- PHY (radio) power-down
271 * 011 -- Error
272 * 10: XTAL ON request
273 * 9-6: SYS_CONFIG
274 * Indicates current system configuration, reflecting pins on chip
275 * as forced high/low by device circuit board.
276 * 4: GOING_TO_SLEEP
277 * Indicates MAC is entering a power-saving sleep power-down.
278 * Not a good time to access device-internal resources.
279 * 3: MAC_ACCESS_REQ
280 * Host sets this to request and maintain MAC wakeup, to allow host
281 * access to device-internal resources. Host must wait for
282 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
283 * device registers.
284 * 2: INIT_DONE
285 * Host sets this to put device into fully operational D0 power mode.
286 * Host resets this after SW_RESET to put device into low power mode.
287 * 0: MAC_CLOCK_READY
288 * Indicates MAC (ucode processor, etc.) is powered up and can run.
289 * Internal resources are accessible.
290 * NOTE: This does not indicate that the processor is actually running.
291 * NOTE: This does not indicate that device has completed
292 * init or post-power-down restore of internal SRAM memory.
293 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
294 * SRAM is restored and uCode is in normal operation mode.
295 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
296 * do not need to save/restore it.
297 * NOTE: After device reset, this bit remains "0" until host sets
298 * INIT_DONE
300 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
301 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
302 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
303 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
304 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
306 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
308 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
309 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
310 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
313 /* HW REV */
314 #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
315 #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
319 * hw_rev values
321 enum {
322 SILICON_A_STEP = 0,
323 SILICON_B_STEP,
324 SILICON_C_STEP,
328 #define CSR_HW_REV_TYPE_MSK (0x000FFF0)
329 #define CSR_HW_REV_TYPE_5300 (0x0000020)
330 #define CSR_HW_REV_TYPE_5350 (0x0000030)
331 #define CSR_HW_REV_TYPE_5100 (0x0000050)
332 #define CSR_HW_REV_TYPE_5150 (0x0000040)
333 #define CSR_HW_REV_TYPE_1000 (0x0000060)
334 #define CSR_HW_REV_TYPE_6x00 (0x0000070)
335 #define CSR_HW_REV_TYPE_6x50 (0x0000080)
336 #define CSR_HW_REV_TYPE_6150 (0x0000084)
337 #define CSR_HW_REV_TYPE_6x05 (0x00000B0)
338 #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
339 #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
340 #define CSR_HW_REV_TYPE_2x30 (0x00000C0)
341 #define CSR_HW_REV_TYPE_2x00 (0x0000100)
342 #define CSR_HW_REV_TYPE_105 (0x0000110)
343 #define CSR_HW_REV_TYPE_135 (0x0000120)
344 #define CSR_HW_REV_TYPE_7265D (0x0000210)
345 #define CSR_HW_REV_TYPE_NONE (0x00001F0)
347 /* RF_ID value */
348 #define CSR_HW_RF_ID_TYPE_JF (0x00105000)
349 #define CSR_HW_RF_ID_TYPE_LC (0x00101000)
351 /* EEPROM REG */
352 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
353 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
354 #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
355 #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
357 /* EEPROM GP */
358 #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
359 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
360 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
361 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
362 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
363 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
365 /* One-time-programmable memory general purpose reg */
366 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
367 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
368 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
369 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
371 /* GP REG */
372 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
373 #define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
374 #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
375 #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
376 #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
379 /* CSR GIO */
380 #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
383 * UCODE-DRIVER GP (general purpose) mailbox register 1
384 * Host driver and uCode write and/or read this register to communicate with
385 * each other.
386 * Bit fields:
387 * 4: UCODE_DISABLE
388 * Host sets this to request permanent halt of uCode, same as
389 * sending CARD_STATE command with "halt" bit set.
390 * 3: CT_KILL_EXIT
391 * Host sets this to request exit from CT_KILL state, i.e. host thinks
392 * device temperature is low enough to continue normal operation.
393 * 2: CMD_BLOCKED
394 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
395 * to release uCode to clear all Tx and command queues, enter
396 * unassociated mode, and power down.
397 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
398 * 1: SW_BIT_RFKILL
399 * Host sets this when issuing CARD_STATE command to request
400 * device sleep.
401 * 0: MAC_SLEEP
402 * uCode sets this when preparing a power-saving power-down.
403 * uCode resets this when power-up is complete and SRAM is sane.
404 * NOTE: device saves internal SRAM data to host when powering down,
405 * and must restore this data after powering back up.
406 * MAC_SLEEP is the best indication that restore is complete.
407 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
408 * do not need to save/restore it.
410 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
411 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
412 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
413 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
414 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
416 /* GP Driver */
417 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
418 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
419 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
420 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
421 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
422 #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
424 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
426 /* GIO Chicken Bits (PCI Express bus link power management) */
427 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
428 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
430 /* LED */
431 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
432 #define CSR_LED_REG_TURN_ON (0x60)
433 #define CSR_LED_REG_TURN_OFF (0x20)
435 /* ANA_PLL */
436 #define CSR50_ANA_PLL_CFG_VAL (0x00880300)
438 /* HPET MEM debug */
439 #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
441 /* DRAM INT TABLE */
442 #define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
443 #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
444 #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
447 * SHR target access (Shared block memory space)
449 * Shared internal registers can be accessed directly from PCI bus through SHR
450 * arbiter without need for the MAC HW to be powered up. This is possible due to
451 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
452 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
454 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
455 * need not be powered up so no "grab inc access" is required.
459 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
460 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
461 * first, write to the control register:
462 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
463 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
464 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
466 * To write the register, first, write to the data register
467 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
468 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
469 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
471 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
472 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
475 * HBUS (Host-side Bus)
477 * HBUS registers are mapped directly into PCI bus space, but are used
478 * to indirectly access device's internal memory or registers that
479 * may be powered-down.
481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
484 * internal resources.
486 * Do not use iwl_write32()/iwl_read32() family to access these registers;
487 * these provide only simple PCI bus access, without waking up the MAC.
489 #define HBUS_BASE (0x400)
492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
493 * structures, error log, event log, verifying uCode load).
494 * First write to address register, then read from or write to data register
495 * to complete the job. Once the address register is set up, accesses to
496 * data registers auto-increment the address by one dword.
497 * Bit usage for address registers (read or write):
498 * 0-31: memory address within device
500 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
501 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
502 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
503 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
505 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
506 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
507 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
510 * Registers for accessing device's internal peripheral registers
511 * (e.g. SCD, BSM, etc.). First write to address register,
512 * then read from or write to data register to complete the job.
513 * Bit usage for address registers (read or write):
514 * 0-15: register address (offset) within device
515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
517 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
518 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
519 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
520 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
522 /* Used to enable DBGM */
523 #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
526 * Per-Tx-queue write pointer (index, really!)
527 * Indicates index to next TFD that driver will fill (1 past latest filled).
528 * Bit usage:
529 * 0-7: queue write index
530 * 11-8: queue selector
532 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
534 /**********************************************************
535 * CSR values
536 **********************************************************/
538 * host interrupt timeout value
539 * used with setting interrupt coalescing timer
540 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
542 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
544 #define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
545 #define IWL_HOST_INT_TIMEOUT_DEF (0x40)
546 #define IWL_HOST_INT_TIMEOUT_MIN (0x0)
547 #define IWL_HOST_INT_OPER_MODE BIT(31)
549 /*****************************************************************************
550 * 7000/3000 series SHR DTS addresses *
551 *****************************************************************************/
553 /* Diode Results Register Structure: */
554 enum dtd_diode_reg {
555 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
556 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
557 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
558 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
559 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
560 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
561 /* Those are the masks INSIDE the flags bit-field: */
562 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
563 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
564 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
565 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
568 /*****************************************************************************
569 * MSIX related registers *
570 *****************************************************************************/
572 #define CSR_MSIX_BASE (0x2000)
573 #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
574 #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
575 #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
576 #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
577 #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
578 #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
579 #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
580 #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
581 #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
582 #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
584 #define MSIX_FH_INT_CAUSES_Q(q) (q)
587 * Causes for the FH register interrupts
589 enum msix_fh_int_causes {
590 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
591 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
592 MSIX_FH_INT_CAUSES_S2D = BIT(19),
593 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
597 * Causes for the HW register interrupts
599 enum msix_hw_int_causes {
600 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
601 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
602 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
603 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
604 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
605 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
606 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
607 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
608 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
609 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
612 #define MSIX_MIN_INTERRUPT_VECTORS 2
613 #define MSIX_AUTO_CLEAR_CAUSE 0
614 #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
616 /*****************************************************************************
617 * HW address related registers *
618 *****************************************************************************/
620 #define CSR_ADDR_BASE (0x380)
621 #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
622 #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
623 #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
624 #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
626 #endif /* !__iwl_csr_h__ */