drivers/net/wireless/intel/iwlwifi/mvm/fw-api-rx.h

   1 /******************************************************************************
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   6  * GPL LICENSE SUMMARY
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   8  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
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  12  * This program is free software; you can redistribute it and/or modify
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  30  *  Intel Linux Wireless <linuxwifi@intel.com>
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  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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  66  *****************************************************************************/
  67
  68 #ifndef __fw_api_rx_h__
  69 #define __fw_api_rx_h__
  70
  71 /* API for pre-9000 hardware */
  72
  73 #define IWL_RX_INFO_PHY_CNT 8
  74 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
  75 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
  76 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
  77 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
  78 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
  79 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
  80 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
  81
  82 enum iwl_mac_context_info {
  83         MAC_CONTEXT_INFO_NONE,
  84         MAC_CONTEXT_INFO_GSCAN,
  85 };
  86
  87 /**
  88  * struct iwl_rx_phy_info - phy info
  89  * (REPLY_RX_PHY_CMD = 0xc0)
  90  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
  91  * @cfg_phy_cnt: configurable DSP phy data byte count
  92  * @stat_id: configurable DSP phy data set ID
  93  * @reserved1:
  94  * @system_timestamp: GP2  at on air rise
  95  * @timestamp: TSF at on air rise
  96  * @beacon_time_stamp: beacon at on-air rise
  97  * @phy_flags: general phy flags: band, modulation, ...
  98  * @channel: channel number
  99  * @non_cfg_phy_buf: for various implementations of non_cfg_phy
 100  * @rate_n_flags: RATE_MCS_*
 101  * @byte_count: frame's byte-count
 102  * @frame_time: frame's time on the air, based on byte count and frame rate
 103  *      calculation
 104  * @mac_active_msk: what MACs were active when the frame was received
 105  * @mac_context_info: additional info on the context in which the frame was
 106  *      received as defined in &enum iwl_mac_context_info
 107  *
 108  * Before each Rx, the device sends this data. It contains PHY information
 109  * about the reception of the packet.
 110  */
 111 struct iwl_rx_phy_info {
 112         u8 non_cfg_phy_cnt;
 113         u8 cfg_phy_cnt;
 114         u8 stat_id;
 115         u8 reserved1;
 116         __le32 system_timestamp;
 117         __le64 timestamp;
 118         __le32 beacon_time_stamp;
 119         __le16 phy_flags;
 120         __le16 channel;
 121         __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
 122         __le32 rate_n_flags;
 123         __le32 byte_count;
 124         u8 mac_active_msk;
 125         u8 mac_context_info;
 126         __le16 frame_time;
 127 } __packed;
 128
 129 /*
 130  * TCP offload Rx assist info
 131  *
 132  * bits 0:3 - reserved
 133  * bits 4:7 - MIC CRC length
 134  * bits 8:12 - MAC header length
 135  * bit 13 - Padding indication
 136  * bit 14 - A-AMSDU indication
 137  * bit 15 - Offload enabled
 138  */
 139 enum iwl_csum_rx_assist_info {
 140         CSUM_RXA_RESERVED_MASK  = 0x000f,
 141         CSUM_RXA_MICSIZE_MASK   = 0x00f0,
 142         CSUM_RXA_HEADERLEN_MASK = 0x1f00,
 143         CSUM_RXA_PADD           = BIT(13),
 144         CSUM_RXA_AMSDU          = BIT(14),
 145         CSUM_RXA_ENA            = BIT(15)
 146 };
 147
 148 /**
 149  * struct iwl_rx_mpdu_res_start - phy info
 150  * @assist: see CSUM_RX_ASSIST_ above
 151  */
 152 struct iwl_rx_mpdu_res_start {
 153         __le16 byte_count;
 154         __le16 assist;
 155 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
 156
 157 /**
 158  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
 159  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
 160  * @RX_RES_PHY_FLAGS_MOD_CCK:
 161  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
 162  * @RX_RES_PHY_FLAGS_NARROW_BAND:
 163  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
 164  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
 165  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
 166  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
 167  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
 168  */
 169 enum iwl_rx_phy_flags {
 170         RX_RES_PHY_FLAGS_BAND_24        = BIT(0),
 171         RX_RES_PHY_FLAGS_MOD_CCK        = BIT(1),
 172         RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
 173         RX_RES_PHY_FLAGS_NARROW_BAND    = BIT(3),
 174         RX_RES_PHY_FLAGS_ANTENNA        = (0x7 << 4),
 175         RX_RES_PHY_FLAGS_ANTENNA_POS    = 4,
 176         RX_RES_PHY_FLAGS_AGG            = BIT(7),
 177         RX_RES_PHY_FLAGS_OFDM_HT        = BIT(8),
 178         RX_RES_PHY_FLAGS_OFDM_GF        = BIT(9),
 179         RX_RES_PHY_FLAGS_OFDM_VHT       = BIT(10),
 180 };
 181
 182 /**
 183  * enum iwl_mvm_rx_status - written by fw for each Rx packet
 184  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
 185  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
 186  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
 187  * @RX_MPDU_RES_STATUS_KEY_VALID:
 188  * @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
 189  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
 190  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
 191  *      in the driver.
 192  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
 193  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
 194  *      alg = CCM only. Checks replay attack for 11w frames. Relevant only if
 195  *      %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
 196  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
 197  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
 198  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
 199  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
 200  * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
 201  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
 202  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
 203  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
 204  * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
 205  * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
 206  * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
 207  * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
 208  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
 209  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
 210  * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
 211  * @RX_MPDU_RES_STATUS_STA_ID_MSK:
 212  * @RX_MPDU_RES_STATUS_RRF_KILL:
 213  * @RX_MPDU_RES_STATUS_FILTERING_MSK:
 214  * @RX_MPDU_RES_STATUS2_FILTERING_MSK:
 215  */
 216 enum iwl_mvm_rx_status {
 217         RX_MPDU_RES_STATUS_CRC_OK                       = BIT(0),
 218         RX_MPDU_RES_STATUS_OVERRUN_OK                   = BIT(1),
 219         RX_MPDU_RES_STATUS_SRC_STA_FOUND                = BIT(2),
 220         RX_MPDU_RES_STATUS_KEY_VALID                    = BIT(3),
 221         RX_MPDU_RES_STATUS_KEY_PARAM_OK                 = BIT(4),
 222         RX_MPDU_RES_STATUS_ICV_OK                       = BIT(5),
 223         RX_MPDU_RES_STATUS_MIC_OK                       = BIT(6),
 224         RX_MPDU_RES_STATUS_TTAK_OK                      = BIT(7),
 225         RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR         = BIT(7),
 226         RX_MPDU_RES_STATUS_SEC_NO_ENC                   = (0 << 8),
 227         RX_MPDU_RES_STATUS_SEC_WEP_ENC                  = (1 << 8),
 228         RX_MPDU_RES_STATUS_SEC_CCM_ENC                  = (2 << 8),
 229         RX_MPDU_RES_STATUS_SEC_TKIP_ENC                 = (3 << 8),
 230         RX_MPDU_RES_STATUS_SEC_EXT_ENC                  = (4 << 8),
 231         RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC             = (6 << 8),
 232         RX_MPDU_RES_STATUS_SEC_ENC_ERR                  = (7 << 8),
 233         RX_MPDU_RES_STATUS_SEC_ENC_MSK                  = (7 << 8),
 234         RX_MPDU_RES_STATUS_DEC_DONE                     = BIT(11),
 235         RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP        = BIT(12),
 236         RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP               = BIT(13),
 237         RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT               = BIT(14),
 238         RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME             = BIT(15),
 239         RX_MPDU_RES_STATUS_CSUM_DONE                    = BIT(16),
 240         RX_MPDU_RES_STATUS_CSUM_OK                      = BIT(17),
 241         RX_MPDU_RES_STATUS_HASH_INDEX_MSK               = (0x3F0000),
 242         RX_MDPU_RES_STATUS_STA_ID_SHIFT                 = 24,
 243         RX_MPDU_RES_STATUS_STA_ID_MSK                   = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
 244         RX_MPDU_RES_STATUS_RRF_KILL                     = BIT(29),
 245         RX_MPDU_RES_STATUS_FILTERING_MSK                = (0xc00000),
 246         RX_MPDU_RES_STATUS2_FILTERING_MSK               = (0xc0000000),
 247 };
 248
 249 /* 9000 series API */
 250 enum iwl_rx_mpdu_mac_flags1 {
 251         IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK         = 0x03,
 252         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK      = 0xf0,
 253         /* shift should be 4, but the length is measured in 2-byte
 254          * words, so shifting only by 3 gives a byte result
 255          */
 256         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT     = 3,
 257 };
 258
 259 enum iwl_rx_mpdu_mac_flags2 {
 260         /* in 2-byte words */
 261         IWL_RX_MPDU_MFLG2_HDR_LEN_MASK          = 0x1f,
 262         IWL_RX_MPDU_MFLG2_PAD                   = 0x20,
 263         IWL_RX_MPDU_MFLG2_AMSDU                 = 0x40,
 264 };
 265
 266 enum iwl_rx_mpdu_amsdu_info {
 267         IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK     = 0x7f,
 268         IWL_RX_MPDU_AMSDU_LAST_SUBFRAME         = 0x80,
 269 };
 270
 271 enum iwl_rx_l3_proto_values {
 272         IWL_RX_L3_TYPE_NONE,
 273         IWL_RX_L3_TYPE_IPV4,
 274         IWL_RX_L3_TYPE_IPV4_FRAG,
 275         IWL_RX_L3_TYPE_IPV6_FRAG,
 276         IWL_RX_L3_TYPE_IPV6,
 277         IWL_RX_L3_TYPE_IPV6_IN_IPV4,
 278         IWL_RX_L3_TYPE_ARP,
 279         IWL_RX_L3_TYPE_EAPOL,
 280 };
 281
 282 #define IWL_RX_L3_PROTO_POS 4
 283
 284 enum iwl_rx_l3l4_flags {
 285         IWL_RX_L3L4_IP_HDR_CSUM_OK              = BIT(0),
 286         IWL_RX_L3L4_TCP_UDP_CSUM_OK             = BIT(1),
 287         IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH         = BIT(2),
 288         IWL_RX_L3L4_TCP_ACK                     = BIT(3),
 289         IWL_RX_L3L4_L3_PROTO_MASK               = 0xf << IWL_RX_L3_PROTO_POS,
 290         IWL_RX_L3L4_L4_PROTO_MASK               = 0xf << 8,
 291         IWL_RX_L3L4_RSS_HASH_MASK               = 0xf << 12,
 292 };
 293
 294 enum iwl_rx_mpdu_status {
 295         IWL_RX_MPDU_STATUS_CRC_OK               = BIT(0),
 296         IWL_RX_MPDU_STATUS_OVERRUN_OK           = BIT(1),
 297         IWL_RX_MPDU_STATUS_SRC_STA_FOUND        = BIT(2),
 298         IWL_RX_MPDU_STATUS_KEY_VALID            = BIT(3),
 299         IWL_RX_MPDU_STATUS_KEY_ERROR            = BIT(4),
 300         IWL_RX_MPDU_STATUS_ICV_OK               = BIT(5),
 301         IWL_RX_MPDU_STATUS_MIC_OK               = BIT(6),
 302         IWL_RX_MPDU_RES_STATUS_TTAK_OK          = BIT(7),
 303         IWL_RX_MPDU_STATUS_SEC_MASK             = 0x7 << 8,
 304         IWL_RX_MPDU_STATUS_SEC_NONE             = 0x0 << 8,
 305         IWL_RX_MPDU_STATUS_SEC_WEP              = 0x1 << 8,
 306         IWL_RX_MPDU_STATUS_SEC_CCM              = 0x2 << 8,
 307         IWL_RX_MPDU_STATUS_SEC_TKIP             = 0x3 << 8,
 308         IWL_RX_MPDU_STATUS_SEC_EXT_ENC          = 0x4 << 8,
 309         IWL_RX_MPDU_STATUS_SEC_GCM              = 0x5 << 8,
 310         IWL_RX_MPDU_STATUS_DECRYPTED            = BIT(11),
 311         IWL_RX_MPDU_STATUS_WEP_MATCH            = BIT(12),
 312         IWL_RX_MPDU_STATUS_EXT_IV_MATCH         = BIT(13),
 313         IWL_RX_MPDU_STATUS_KEY_ID_MATCH         = BIT(14),
 314         IWL_RX_MPDU_STATUS_KEY_COLOR            = BIT(15),
 315 };
 316
 317 enum iwl_rx_mpdu_hash_filter {
 318         IWL_RX_MPDU_HF_A1_HASH_MASK             = 0x3f,
 319         IWL_RX_MPDU_HF_FILTER_STATUS_MASK       = 0xc0,
 320 };
 321
 322 enum iwl_rx_mpdu_sta_id_flags {
 323         IWL_RX_MPDU_SIF_STA_ID_MASK             = 0x1f,
 324         IWL_RX_MPDU_SIF_RRF_ABORT               = 0x20,
 325         IWL_RX_MPDU_SIF_FILTER_STATUS_MASK      = 0xc0,
 326 };
 327
 328 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
 329
 330 enum iwl_rx_mpdu_reorder_data {
 331         IWL_RX_MPDU_REORDER_NSSN_MASK           = 0x00000fff,
 332         IWL_RX_MPDU_REORDER_SN_MASK             = 0x00fff000,
 333         IWL_RX_MPDU_REORDER_SN_SHIFT            = 12,
 334         IWL_RX_MPDU_REORDER_BAID_MASK           = 0x7f000000,
 335         IWL_RX_MPDU_REORDER_BAID_SHIFT          = 24,
 336         IWL_RX_MPDU_REORDER_BA_OLD_SN           = 0x80000000,
 337 };
 338
 339 struct iwl_rx_mpdu_desc {
 340         /* DW2 */
 341         __le16 mpdu_len;
 342         u8 mac_flags1;
 343         u8 mac_flags2;
 344         /* DW3 */
 345         u8 amsdu_info;
 346         __le16 reserved_for_software;
 347         u8 mac_phy_idx;
 348         /* DW4 */
 349         __le16 raw_csum; /* alledgedly unreliable */
 350         __le16 l3l4_flags;
 351         /* DW5 */
 352         __le16 status;
 353         u8 hash_filter;
 354         u8 sta_id_flags;
 355         /* DW6 */
 356         __le32 reorder_data;
 357         /* DW7 */
 358         __le32 rss_hash;
 359         /* DW8 */
 360         __le32 filter_match;
 361         /* DW9 */
 362         __le32 rate_n_flags;
 363         /* DW10 */
 364         u8 energy_a, energy_b, channel, reserved;
 365         /* DW11 */
 366         __le32 gp2_on_air_rise;
 367         /* DW12 & DW13 */
 368         __le64 tsf_on_air_rise;
 369 } __packed;
 370
 371 struct iwl_frame_release {
 372         u8 baid;
 373         u8 reserved;
 374         __le16 nssn;
 375 };
 376
 377 enum iwl_rss_hash_func_en {
 378         IWL_RSS_HASH_TYPE_IPV4_TCP,
 379         IWL_RSS_HASH_TYPE_IPV4_UDP,
 380         IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
 381         IWL_RSS_HASH_TYPE_IPV6_TCP,
 382         IWL_RSS_HASH_TYPE_IPV6_UDP,
 383         IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
 384 };
 385
 386 #define IWL_RSS_HASH_KEY_CNT 10
 387 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
 388 #define IWL_RSS_ENABLE 1
 389
 390 /**
 391  * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
 392  *
 393  * @flags: 1 - enable, 0 - disable
 394  * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
 395  * @secret_key: 320 bit input of random key configuration from driver
 396  * @indirection_table: indirection table
 397  */
 398 struct iwl_rss_config_cmd {
 399         __le32 flags;
 400         u8 hash_mask;
 401         u8 reserved[3];
 402         __le32 secret_key[IWL_RSS_HASH_KEY_CNT];
 403         u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
 404 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
 405
 406 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128
 407 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
 408 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
 409
 410 /**
 411  * struct iwl_rxq_sync_cmd - RXQ notification trigger
 412  *
 413  * @flags: flags of the notification. bit 0:3 are the sender queue
 414  * @rxq_mask: rx queues to send the notification on
 415  * @count: number of bytes in payload, should be DWORD aligned
 416  * @payload: data to send to rx queues
 417  */
 418 struct iwl_rxq_sync_cmd {
 419         __le32 flags;
 420         __le32 rxq_mask;
 421         __le32 count;
 422         u8 payload[];
 423 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 424
 425 /**
 426  * struct iwl_rxq_sync_notification - Notification triggered by RXQ
 427  * sync command
 428  *
 429  * @count: number of bytes in payload
 430  * @payload: data to send to rx queues
 431  */
 432 struct iwl_rxq_sync_notification {
 433         __le32 count;
 434         u8 payload[];
 435 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 436
 437 /**
 438 * Internal message identifier
 439 *
 440 * @IWL_MVM_RXQ_EMPTY: empty sync notification
 441 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
 442 */
 443 enum iwl_mvm_rxq_notif_type {
 444         IWL_MVM_RXQ_EMPTY,
 445         IWL_MVM_RXQ_NOTIF_DEL_BA,
 446 };
 447
 448 /**
 449 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
 450 * in &iwl_rxq_sync_cmd. Should be DWORD aligned.
 451 * FW is agnostic to the payload, so there are no endianity requirements.
 452 *
 453 * @type: value from &iwl_mvm_rxq_notif_type
 454 * @sync: ctrl path is waiting for all notifications to be received
 455 * @cookie: internal cookie to identify old notifications
 456 * @data: payload
 457 */
 458 struct iwl_mvm_internal_rxq_notif {
 459         u16 type;
 460         u16 sync;
 461         u32 cookie;
 462         u8 data[];
 463 } __packed;
 464
 465 #endif /* __fw_api_rx_h__ */