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net/mlx4_en: Move filters cleanup to a proper location
[linux/fpc-iii.git] / drivers / net / wireless / intel / iwlwifi / mvm / fw-dbg.c
blobe1b6b2c665eb61b63be7297a5dc55b14dec40ca6
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program;
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <linuxwifi@intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
34 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
35 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/devcoredump.h>
66
67 #include "fw-dbg.h"
68 #include "iwl-io.h"
69 #include "mvm.h"
70 #include "iwl-prph.h"
71 #include "iwl-csr.h"
72
73 static ssize_t iwl_mvm_read_coredump(char *buffer, loff_t offset, size_t count,
74 void *data, size_t datalen)
75 {
76 const struct iwl_mvm_dump_ptrs *dump_ptrs = data;
77 ssize_t bytes_read;
78 ssize_t bytes_read_trans;
79
80 if (offset < dump_ptrs->op_mode_len) {
81 bytes_read = min_t(ssize_t, count,
82 dump_ptrs->op_mode_len - offset);
83 memcpy(buffer, (u8 *)dump_ptrs->op_mode_ptr + offset,
84 bytes_read);
85 offset += bytes_read;
86 count -= bytes_read;
87
88 if (count == 0)
89 return bytes_read;
90 } else {
91 bytes_read = 0;
92 }
93
94 if (!dump_ptrs->trans_ptr)
95 return bytes_read;
96
97 offset -= dump_ptrs->op_mode_len;
98 bytes_read_trans = min_t(ssize_t, count,
99 dump_ptrs->trans_ptr->len - offset);
100 memcpy(buffer + bytes_read,
101 (u8 *)dump_ptrs->trans_ptr->data + offset,
102 bytes_read_trans);
103
104 return bytes_read + bytes_read_trans;
105 }
106
107 static void iwl_mvm_free_coredump(void *data)
108 {
109 const struct iwl_mvm_dump_ptrs *fw_error_dump = data;
110
111 vfree(fw_error_dump->op_mode_ptr);
112 vfree(fw_error_dump->trans_ptr);
113 kfree(fw_error_dump);
114 }
115
116 #define RADIO_REG_MAX_READ 0x2ad
117 static void iwl_mvm_read_radio_reg(struct iwl_mvm *mvm,
118 struct iwl_fw_error_dump_data **dump_data)
119 {
120 u8 *pos = (void *)(*dump_data)->data;
121 unsigned long flags;
122 int i;
123
124 if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
125 return;
126
127 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
128 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
129
130 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
131 u32 rd_cmd = RADIO_RSP_RD_CMD;
132
133 rd_cmd |= i << RADIO_RSP_ADDR_POS;
134 iwl_write_prph_no_grab(mvm->trans, RSP_RADIO_CMD, rd_cmd);
135 *pos = (u8)iwl_read_prph_no_grab(mvm->trans, RSP_RADIO_RDDAT);
136
137 pos++;
138 }
139
140 *dump_data = iwl_fw_error_next_data(*dump_data);
141
142 iwl_trans_release_nic_access(mvm->trans, &flags);
143 }
144
145 static void iwl_mvm_dump_fifos(struct iwl_mvm *mvm,
146 struct iwl_fw_error_dump_data **dump_data)
147 {
148 struct iwl_fw_error_dump_fifo *fifo_hdr;
149 u32 *fifo_data;
150 u32 fifo_len;
151 unsigned long flags;
152 int i, j;
153
154 if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
155 return;
156
157 /* Pull RXF data from all RXFs */
158 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) {
159 /*
160 * Keep aside the additional offset that might be needed for
161 * next RXF
162 */
163 u32 offset_diff = RXF_DIFF_FROM_PREV * i;
164
165 fifo_hdr = (void *)(*dump_data)->data;
166 fifo_data = (void *)fifo_hdr->data;
167 fifo_len = mvm->shared_mem_cfg.rxfifo_size[i];
168
169 /* No need to try to read the data if the length is 0 */
170 if (fifo_len == 0)
171 continue;
172
173 /* Add a TLV for the RXF */
174 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
175 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
176
177 fifo_hdr->fifo_num = cpu_to_le32(i);
178 fifo_hdr->available_bytes =
179 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
180 RXF_RD_D_SPACE +
181 offset_diff));
182 fifo_hdr->wr_ptr =
183 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
184 RXF_RD_WR_PTR +
185 offset_diff));
186 fifo_hdr->rd_ptr =
187 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
188 RXF_RD_RD_PTR +
189 offset_diff));
190 fifo_hdr->fence_ptr =
191 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
192 RXF_RD_FENCE_PTR +
193 offset_diff));
194 fifo_hdr->fence_mode =
195 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
196 RXF_SET_FENCE_MODE +
197 offset_diff));
198
199 /* Lock fence */
200 iwl_trans_write_prph(mvm->trans,
201 RXF_SET_FENCE_MODE + offset_diff, 0x1);
202 /* Set fence pointer to the same place like WR pointer */
203 iwl_trans_write_prph(mvm->trans,
204 RXF_LD_WR2FENCE + offset_diff, 0x1);
205 /* Set fence offset */
206 iwl_trans_write_prph(mvm->trans,
207 RXF_LD_FENCE_OFFSET_ADDR + offset_diff,
208 0x0);
209
210 /* Read FIFO */
211 fifo_len /= sizeof(u32); /* Size in DWORDS */
212 for (j = 0; j < fifo_len; j++)
213 fifo_data[j] = iwl_trans_read_prph(mvm->trans,
214 RXF_FIFO_RD_FENCE_INC +
215 offset_diff);
216 *dump_data = iwl_fw_error_next_data(*dump_data);
217 }
218
219 /* Pull TXF data from all TXFs */
220 for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) {
221 /* Mark the number of TXF we're pulling now */
222 iwl_trans_write_prph(mvm->trans, TXF_LARC_NUM, i);
223
224 fifo_hdr = (void *)(*dump_data)->data;
225 fifo_data = (void *)fifo_hdr->data;
226 fifo_len = mvm->shared_mem_cfg.txfifo_size[i];
227
228 /* No need to try to read the data if the length is 0 */
229 if (fifo_len == 0)
230 continue;
231
232 /* Add a TLV for the FIFO */
233 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
234 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
235
236 fifo_hdr->fifo_num = cpu_to_le32(i);
237 fifo_hdr->available_bytes =
238 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
239 TXF_FIFO_ITEM_CNT));
240 fifo_hdr->wr_ptr =
241 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
242 TXF_WR_PTR));
243 fifo_hdr->rd_ptr =
244 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
245 TXF_RD_PTR));
246 fifo_hdr->fence_ptr =
247 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
248 TXF_FENCE_PTR));
249 fifo_hdr->fence_mode =
250 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
251 TXF_LOCK_FENCE));
252
253 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
254 iwl_trans_write_prph(mvm->trans, TXF_READ_MODIFY_ADDR,
255 TXF_WR_PTR);
256
257 /* Dummy-read to advance the read pointer to the head */
258 iwl_trans_read_prph(mvm->trans, TXF_READ_MODIFY_DATA);
259
260 /* Read FIFO */
261 fifo_len /= sizeof(u32); /* Size in DWORDS */
262 for (j = 0; j < fifo_len; j++)
263 fifo_data[j] = iwl_trans_read_prph(mvm->trans,
264 TXF_READ_MODIFY_DATA);
265 *dump_data = iwl_fw_error_next_data(*dump_data);
266 }
267
268 if (fw_has_capa(&mvm->fw->ucode_capa,
269 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
270 /* Pull UMAC internal TXF data from all TXFs */
271 for (i = 0;
272 i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
273 i++) {
274 fifo_hdr = (void *)(*dump_data)->data;
275 fifo_data = (void *)fifo_hdr->data;
276 fifo_len = mvm->shared_mem_cfg.internal_txfifo_size[i];
277
278 /* No need to try to read the data if the length is 0 */
279 if (fifo_len == 0)
280 continue;
281
282 /* Add a TLV for the internal FIFOs */
283 (*dump_data)->type =
284 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
285 (*dump_data)->len =
286 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
287
288 fifo_hdr->fifo_num = cpu_to_le32(i);
289
290 /* Mark the number of TXF we're pulling now */
291 iwl_trans_write_prph(mvm->trans, TXF_CPU2_NUM, i);
292
293 fifo_hdr->available_bytes =
294 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
295 TXF_CPU2_FIFO_ITEM_CNT));
296 fifo_hdr->wr_ptr =
297 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
298 TXF_CPU2_WR_PTR));
299 fifo_hdr->rd_ptr =
300 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
301 TXF_CPU2_RD_PTR));
302 fifo_hdr->fence_ptr =
303 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
304 TXF_CPU2_FENCE_PTR));
305 fifo_hdr->fence_mode =
306 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
307 TXF_CPU2_LOCK_FENCE));
308
309 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
310 iwl_trans_write_prph(mvm->trans,
311 TXF_CPU2_READ_MODIFY_ADDR,
312 TXF_CPU2_WR_PTR);
313
314 /* Dummy-read to advance the read pointer to head */
315 iwl_trans_read_prph(mvm->trans,
316 TXF_CPU2_READ_MODIFY_DATA);
317
318 /* Read FIFO */
319 fifo_len /= sizeof(u32); /* Size in DWORDS */
320 for (j = 0; j < fifo_len; j++)
321 fifo_data[j] =
322 iwl_trans_read_prph(mvm->trans,
323 TXF_CPU2_READ_MODIFY_DATA);
324 *dump_data = iwl_fw_error_next_data(*dump_data);
325 }
326 }
327
328 iwl_trans_release_nic_access(mvm->trans, &flags);
329 }
330
331 void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm)
332 {
333 if (mvm->fw_dump_desc == &iwl_mvm_dump_desc_assert)
334 return;
335
336 kfree(mvm->fw_dump_desc);
337 mvm->fw_dump_desc = NULL;
338 }
339
340 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
341 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
342
343 struct iwl_prph_range {
344 u32 start, end;
345 };
346
347 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
348 { .start = 0x00a00000, .end = 0x00a00000 },
349 { .start = 0x00a0000c, .end = 0x00a00024 },
350 { .start = 0x00a0002c, .end = 0x00a0003c },
351 { .start = 0x00a00410, .end = 0x00a00418 },
352 { .start = 0x00a00420, .end = 0x00a00420 },
353 { .start = 0x00a00428, .end = 0x00a00428 },
354 { .start = 0x00a00430, .end = 0x00a0043c },
355 { .start = 0x00a00444, .end = 0x00a00444 },
356 { .start = 0x00a004c0, .end = 0x00a004cc },
357 { .start = 0x00a004d8, .end = 0x00a004d8 },
358 { .start = 0x00a004e0, .end = 0x00a004f0 },
359 { .start = 0x00a00840, .end = 0x00a00840 },
360 { .start = 0x00a00850, .end = 0x00a00858 },
361 { .start = 0x00a01004, .end = 0x00a01008 },
362 { .start = 0x00a01010, .end = 0x00a01010 },
363 { .start = 0x00a01018, .end = 0x00a01018 },
364 { .start = 0x00a01024, .end = 0x00a01024 },
365 { .start = 0x00a0102c, .end = 0x00a01034 },
366 { .start = 0x00a0103c, .end = 0x00a01040 },
367 { .start = 0x00a01048, .end = 0x00a01094 },
368 { .start = 0x00a01c00, .end = 0x00a01c20 },
369 { .start = 0x00a01c58, .end = 0x00a01c58 },
370 { .start = 0x00a01c7c, .end = 0x00a01c7c },
371 { .start = 0x00a01c28, .end = 0x00a01c54 },
372 { .start = 0x00a01c5c, .end = 0x00a01c5c },
373 { .start = 0x00a01c60, .end = 0x00a01cdc },
374 { .start = 0x00a01ce0, .end = 0x00a01d0c },
375 { .start = 0x00a01d18, .end = 0x00a01d20 },
376 { .start = 0x00a01d2c, .end = 0x00a01d30 },
377 { .start = 0x00a01d40, .end = 0x00a01d5c },
378 { .start = 0x00a01d80, .end = 0x00a01d80 },
379 { .start = 0x00a01d98, .end = 0x00a01d9c },
380 { .start = 0x00a01da8, .end = 0x00a01da8 },
381 { .start = 0x00a01db8, .end = 0x00a01df4 },
382 { .start = 0x00a01dc0, .end = 0x00a01dfc },
383 { .start = 0x00a01e00, .end = 0x00a01e2c },
384 { .start = 0x00a01e40, .end = 0x00a01e60 },
385 { .start = 0x00a01e68, .end = 0x00a01e6c },
386 { .start = 0x00a01e74, .end = 0x00a01e74 },
387 { .start = 0x00a01e84, .end = 0x00a01e90 },
388 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
389 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
390 { .start = 0x00a01f00, .end = 0x00a01f1c },
391 { .start = 0x00a01f44, .end = 0x00a01ffc },
392 { .start = 0x00a02000, .end = 0x00a02048 },
393 { .start = 0x00a02068, .end = 0x00a020f0 },
394 { .start = 0x00a02100, .end = 0x00a02118 },
395 { .start = 0x00a02140, .end = 0x00a0214c },
396 { .start = 0x00a02168, .end = 0x00a0218c },
397 { .start = 0x00a021c0, .end = 0x00a021c0 },
398 { .start = 0x00a02400, .end = 0x00a02410 },
399 { .start = 0x00a02418, .end = 0x00a02420 },
400 { .start = 0x00a02428, .end = 0x00a0242c },
401 { .start = 0x00a02434, .end = 0x00a02434 },
402 { .start = 0x00a02440, .end = 0x00a02460 },
403 { .start = 0x00a02468, .end = 0x00a024b0 },
404 { .start = 0x00a024c8, .end = 0x00a024cc },
405 { .start = 0x00a02500, .end = 0x00a02504 },
406 { .start = 0x00a0250c, .end = 0x00a02510 },
407 { .start = 0x00a02540, .end = 0x00a02554 },
408 { .start = 0x00a02580, .end = 0x00a025f4 },
409 { .start = 0x00a02600, .end = 0x00a0260c },
410 { .start = 0x00a02648, .end = 0x00a02650 },
411 { .start = 0x00a02680, .end = 0x00a02680 },
412 { .start = 0x00a026c0, .end = 0x00a026d0 },
413 { .start = 0x00a02700, .end = 0x00a0270c },
414 { .start = 0x00a02804, .end = 0x00a02804 },
415 { .start = 0x00a02818, .end = 0x00a0281c },
416 { .start = 0x00a02c00, .end = 0x00a02db4 },
417 { .start = 0x00a02df4, .end = 0x00a02fb0 },
418 { .start = 0x00a03000, .end = 0x00a03014 },
419 { .start = 0x00a0301c, .end = 0x00a0302c },
420 { .start = 0x00a03034, .end = 0x00a03038 },
421 { .start = 0x00a03040, .end = 0x00a03048 },
422 { .start = 0x00a03060, .end = 0x00a03068 },
423 { .start = 0x00a03070, .end = 0x00a03074 },
424 { .start = 0x00a0307c, .end = 0x00a0307c },
425 { .start = 0x00a03080, .end = 0x00a03084 },
426 { .start = 0x00a0308c, .end = 0x00a03090 },
427 { .start = 0x00a03098, .end = 0x00a03098 },
428 { .start = 0x00a030a0, .end = 0x00a030a0 },
429 { .start = 0x00a030a8, .end = 0x00a030b4 },
430 { .start = 0x00a030bc, .end = 0x00a030bc },
431 { .start = 0x00a030c0, .end = 0x00a0312c },
432 { .start = 0x00a03c00, .end = 0x00a03c5c },
433 { .start = 0x00a04400, .end = 0x00a04454 },
434 { .start = 0x00a04460, .end = 0x00a04474 },
435 { .start = 0x00a044c0, .end = 0x00a044ec },
436 { .start = 0x00a04500, .end = 0x00a04504 },
437 { .start = 0x00a04510, .end = 0x00a04538 },
438 { .start = 0x00a04540, .end = 0x00a04548 },
439 { .start = 0x00a04560, .end = 0x00a0457c },
440 { .start = 0x00a04590, .end = 0x00a04598 },
441 { .start = 0x00a045c0, .end = 0x00a045f4 },
442 { .start = 0x00a44000, .end = 0x00a7bf80 },
443 };
444
445 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
446 { .start = 0x00a05c00, .end = 0x00a05c18 },
447 { .start = 0x00a05400, .end = 0x00a056e8 },
448 { .start = 0x00a08000, .end = 0x00a098bc },
449 { .start = 0x00adfc00, .end = 0x00adfd1c },
450 { .start = 0x00a02400, .end = 0x00a02758 },
451 };
452
453 static u32 iwl_dump_prph(struct iwl_trans *trans,
454 struct iwl_fw_error_dump_data **data,
455 const struct iwl_prph_range *iwl_prph_dump_addr,
456 u32 range_len)
457 {
458 struct iwl_fw_error_dump_prph *prph;
459 unsigned long flags;
460 u32 prph_len = 0, i;
461
462 if (!iwl_trans_grab_nic_access(trans, &flags))
463 return 0;
464
465 for (i = 0; i < range_len; i++) {
466 /* The range includes both boundaries */
467 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
468 iwl_prph_dump_addr[i].start + 4;
469 int reg;
470 __le32 *val;
471
472 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
473
474 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
475 (*data)->len = cpu_to_le32(sizeof(*prph) +
476 num_bytes_in_chunk);
477 prph = (void *)(*data)->data;
478 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
479 val = (void *)prph->data;
480
481 for (reg = iwl_prph_dump_addr[i].start;
482 reg <= iwl_prph_dump_addr[i].end;
483 reg += 4)
484 *val++ = cpu_to_le32(iwl_read_prph_no_grab(trans,
485 reg));
486
487 *data = iwl_fw_error_next_data(*data);
488 }
489
490 iwl_trans_release_nic_access(trans, &flags);
491
492 return prph_len;
493 }
494
495 void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
496 {
497 struct iwl_fw_error_dump_file *dump_file;
498 struct iwl_fw_error_dump_data *dump_data;
499 struct iwl_fw_error_dump_info *dump_info;
500 struct iwl_fw_error_dump_mem *dump_mem;
501 struct iwl_fw_error_dump_trigger_desc *dump_trig;
502 struct iwl_mvm_dump_ptrs *fw_error_dump;
503 u32 sram_len, sram_ofs;
504 struct iwl_fw_dbg_mem_seg_tlv * const *fw_dbg_mem =
505 mvm->fw->dbg_mem_tlv;
506 u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0;
507 u32 smem_len = mvm->fw->dbg_dynamic_mem ? 0 : mvm->cfg->smem_len;
508 u32 sram2_len = mvm->fw->dbg_dynamic_mem ? 0 : mvm->cfg->dccm2_len;
509 bool monitor_dump_only = false;
510 int i;
511
512 if (!IWL_MVM_COLLECT_FW_ERR_DUMP &&
513 !mvm->trans->dbg_dest_tlv)
514 return;
515
516 lockdep_assert_held(&mvm->mutex);
517
518 /* there's no point in fw dump if the bus is dead */
519 if (test_bit(STATUS_TRANS_DEAD, &mvm->trans->status)) {
520 IWL_ERR(mvm, "Skip fw error dump since bus is dead\n");
521 goto out;
522 }
523
524 if (mvm->fw_dump_trig &&
525 mvm->fw_dump_trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)
526 monitor_dump_only = true;
527
528 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL);
529 if (!fw_error_dump)
530 goto out;
531
532 /* SRAM - include stack CCM if driver knows the values for it */
533 if (!mvm->cfg->dccm_offset || !mvm->cfg->dccm_len) {
534 const struct fw_img *img;
535
536 img = &mvm->fw->img[mvm->cur_ucode];
537 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
538 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
539 } else {
540 sram_ofs = mvm->cfg->dccm_offset;
541 sram_len = mvm->cfg->dccm_len;
542 }
543
544 /* reading RXF/TXF sizes */
545 if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
546 struct iwl_mvm_shared_mem_cfg *mem_cfg = &mvm->shared_mem_cfg;
547
548 fifo_data_len = 0;
549
550 /* Count RXF size */
551 for (i = 0; i < ARRAY_SIZE(mem_cfg->rxfifo_size); i++) {
552 if (!mem_cfg->rxfifo_size[i])
553 continue;
554
555 /* Add header info */
556 fifo_data_len += mem_cfg->rxfifo_size[i] +
557 sizeof(*dump_data) +
558 sizeof(struct iwl_fw_error_dump_fifo);
559 }
560
561 for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++) {
562 if (!mem_cfg->txfifo_size[i])
563 continue;
564
565 /* Add header info */
566 fifo_data_len += mem_cfg->txfifo_size[i] +
567 sizeof(*dump_data) +
568 sizeof(struct iwl_fw_error_dump_fifo);
569 }
570
571 if (fw_has_capa(&mvm->fw->ucode_capa,
572 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
573 for (i = 0;
574 i < ARRAY_SIZE(mem_cfg->internal_txfifo_size);
575 i++) {
576 if (!mem_cfg->internal_txfifo_size[i])
577 continue;
578
579 /* Add header info */
580 fifo_data_len +=
581 mem_cfg->internal_txfifo_size[i] +
582 sizeof(*dump_data) +
583 sizeof(struct iwl_fw_error_dump_fifo);
584 }
585 }
586
587 /* Make room for PRPH registers */
588 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr_comm); i++) {
589 /* The range includes both boundaries */
590 int num_bytes_in_chunk =
591 iwl_prph_dump_addr_comm[i].end -
592 iwl_prph_dump_addr_comm[i].start + 4;
593
594 prph_len += sizeof(*dump_data) +
595 sizeof(struct iwl_fw_error_dump_prph) +
596 num_bytes_in_chunk;
597 }
598
599 if (mvm->cfg->mq_rx_supported) {
600 for (i = 0; i <
601 ARRAY_SIZE(iwl_prph_dump_addr_9000); i++) {
602 /* The range includes both boundaries */
603 int num_bytes_in_chunk =
604 iwl_prph_dump_addr_9000[i].end -
605 iwl_prph_dump_addr_9000[i].start + 4;
606
607 prph_len += sizeof(*dump_data) +
608 sizeof(struct iwl_fw_error_dump_prph) +
609 num_bytes_in_chunk;
610 }
611 }
612
613 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
614 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
615 }
616
617 file_len = sizeof(*dump_file) +
618 sizeof(*dump_data) * 2 +
619 fifo_data_len +
620 prph_len +
621 radio_len +
622 sizeof(*dump_info);
623
624 /* Make room for the SMEM, if it exists */
625 if (smem_len)
626 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len;
627
628 /* Make room for the secondary SRAM, if it exists */
629 if (sram2_len)
630 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len;
631
632 /* Make room for MEM segments */
633 for (i = 0; i < ARRAY_SIZE(mvm->fw->dbg_mem_tlv); i++) {
634 if (fw_dbg_mem[i])
635 file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
636 le32_to_cpu(fw_dbg_mem[i]->len);
637 }
638
639 /* Make room for fw's virtual image pages, if it exists */
640 if (mvm->fw->img[mvm->cur_ucode].paging_mem_size &&
641 mvm->fw_paging_db[0].fw_paging_block)
642 file_len += mvm->num_of_paging_blk *
643 (sizeof(*dump_data) +
644 sizeof(struct iwl_fw_error_dump_paging) +
645 PAGING_BLOCK_SIZE);
646
647 /* If we only want a monitor dump, reset the file length */
648 if (monitor_dump_only) {
649 file_len = sizeof(*dump_file) + sizeof(*dump_data) +
650 sizeof(*dump_info);
651 }
652
653 /*
654 * In 8000 HW family B-step include the ICCM (which resides separately)
655 */
656 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
657 CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP)
658 file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
659 IWL8260_ICCM_LEN;
660
661 if (mvm->fw_dump_desc)
662 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
663 mvm->fw_dump_desc->len;
664
665 if (!mvm->fw->dbg_dynamic_mem)
666 file_len += sram_len + sizeof(*dump_mem);
667
668 dump_file = vzalloc(file_len);
669 if (!dump_file) {
670 kfree(fw_error_dump);
671 goto out;
672 }
673
674 fw_error_dump->op_mode_ptr = dump_file;
675
676 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
677 dump_data = (void *)dump_file->data;
678
679 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
680 dump_data->len = cpu_to_le32(sizeof(*dump_info));
681 dump_info = (void *)dump_data->data;
682 dump_info->device_family =
683 mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000 ?
684 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) :
685 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8);
686 dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(mvm->trans->hw_rev));
687 memcpy(dump_info->fw_human_readable, mvm->fw->human_readable,
688 sizeof(dump_info->fw_human_readable));
689 strncpy(dump_info->dev_human_readable, mvm->cfg->name,
690 sizeof(dump_info->dev_human_readable));
691 strncpy(dump_info->bus_human_readable, mvm->dev->bus->name,
692 sizeof(dump_info->bus_human_readable));
693
694 dump_data = iwl_fw_error_next_data(dump_data);
695 /* We only dump the FIFOs if the FW is in error state */
696 if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
697 iwl_mvm_dump_fifos(mvm, &dump_data);
698 if (radio_len)
699 iwl_mvm_read_radio_reg(mvm, &dump_data);
700 }
701
702 if (mvm->fw_dump_desc) {
703 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
704 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
705 mvm->fw_dump_desc->len);
706 dump_trig = (void *)dump_data->data;
707 memcpy(dump_trig, &mvm->fw_dump_desc->trig_desc,
708 sizeof(*dump_trig) + mvm->fw_dump_desc->len);
709
710 dump_data = iwl_fw_error_next_data(dump_data);
711 }
712
713 /* In case we only want monitor dump, skip to dump trasport data */
714 if (monitor_dump_only)
715 goto dump_trans_data;
716
717 if (!mvm->fw->dbg_dynamic_mem) {
718 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
719 dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem));
720 dump_mem = (void *)dump_data->data;
721 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
722 dump_mem->offset = cpu_to_le32(sram_ofs);
723 iwl_trans_read_mem_bytes(mvm->trans, sram_ofs, dump_mem->data,
724 sram_len);
725 dump_data = iwl_fw_error_next_data(dump_data);
726 }
727
728 for (i = 0; i < ARRAY_SIZE(mvm->fw->dbg_mem_tlv); i++) {
729 if (fw_dbg_mem[i]) {
730 u32 len = le32_to_cpu(fw_dbg_mem[i]->len);
731 u32 ofs = le32_to_cpu(fw_dbg_mem[i]->ofs);
732
733 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
734 dump_data->len = cpu_to_le32(len +
735 sizeof(*dump_mem));
736 dump_mem = (void *)dump_data->data;
737 dump_mem->type = fw_dbg_mem[i]->data_type;
738 dump_mem->offset = cpu_to_le32(ofs);
739 iwl_trans_read_mem_bytes(mvm->trans, ofs,
740 dump_mem->data,
741 len);
742 dump_data = iwl_fw_error_next_data(dump_data);
743 }
744 }
745
746 if (smem_len) {
747 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
748 dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem));
749 dump_mem = (void *)dump_data->data;
750 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM);
751 dump_mem->offset = cpu_to_le32(mvm->cfg->smem_offset);
752 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->smem_offset,
753 dump_mem->data, smem_len);
754 dump_data = iwl_fw_error_next_data(dump_data);
755 }
756
757 if (sram2_len) {
758 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
759 dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem));
760 dump_mem = (void *)dump_data->data;
761 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
762 dump_mem->offset = cpu_to_le32(mvm->cfg->dccm2_offset);
763 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->dccm2_offset,
764 dump_mem->data, sram2_len);
765 dump_data = iwl_fw_error_next_data(dump_data);
766 }
767
768 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
769 CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP) {
770 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
771 dump_data->len = cpu_to_le32(IWL8260_ICCM_LEN +
772 sizeof(*dump_mem));
773 dump_mem = (void *)dump_data->data;
774 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
775 dump_mem->offset = cpu_to_le32(IWL8260_ICCM_OFFSET);
776 iwl_trans_read_mem_bytes(mvm->trans, IWL8260_ICCM_OFFSET,
777 dump_mem->data, IWL8260_ICCM_LEN);
778 dump_data = iwl_fw_error_next_data(dump_data);
779 }
780
781 /* Dump fw's virtual image */
782 if (mvm->fw->img[mvm->cur_ucode].paging_mem_size &&
783 mvm->fw_paging_db[0].fw_paging_block) {
784 for (i = 1; i < mvm->num_of_paging_blk + 1; i++) {
785 struct iwl_fw_error_dump_paging *paging;
786 struct page *pages =
787 mvm->fw_paging_db[i].fw_paging_block;
788
789 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
790 dump_data->len = cpu_to_le32(sizeof(*paging) +
791 PAGING_BLOCK_SIZE);
792 paging = (void *)dump_data->data;
793 paging->index = cpu_to_le32(i);
794 memcpy(paging->data, page_address(pages),
795 PAGING_BLOCK_SIZE);
796 dump_data = iwl_fw_error_next_data(dump_data);
797 }
798 }
799
800 if (prph_len) {
801 iwl_dump_prph(mvm->trans, &dump_data,
802 iwl_prph_dump_addr_comm,
803 ARRAY_SIZE(iwl_prph_dump_addr_comm));
804
805 if (mvm->cfg->mq_rx_supported)
806 iwl_dump_prph(mvm->trans, &dump_data,
807 iwl_prph_dump_addr_9000,
808 ARRAY_SIZE(iwl_prph_dump_addr_9000));
809 }
810
811 dump_trans_data:
812 fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans,
813 mvm->fw_dump_trig);
814 fw_error_dump->op_mode_len = file_len;
815 if (fw_error_dump->trans_ptr)
816 file_len += fw_error_dump->trans_ptr->len;
817 dump_file->file_len = cpu_to_le32(file_len);
818
819 dev_coredumpm(mvm->trans->dev, THIS_MODULE, fw_error_dump, 0,
820 GFP_KERNEL, iwl_mvm_read_coredump, iwl_mvm_free_coredump);
821
822 out:
823 iwl_mvm_free_fw_dump_desc(mvm);
824 mvm->fw_dump_trig = NULL;
825 clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status);
826 }
827
828 const struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert = {
829 .trig_desc = {
830 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
831 },
832 };
833
834 int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
835 const struct iwl_mvm_dump_desc *desc,
836 const struct iwl_fw_dbg_trigger_tlv *trigger)
837 {
838 unsigned int delay = 0;
839
840 if (trigger)
841 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
842
843 if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
844 return -EBUSY;
845
846 if (WARN_ON(mvm->fw_dump_desc))
847 iwl_mvm_free_fw_dump_desc(mvm);
848
849 IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
850 le32_to_cpu(desc->trig_desc.type));
851
852 mvm->fw_dump_desc = desc;
853 mvm->fw_dump_trig = trigger;
854
855 queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
856
857 return 0;
858 }
859
860 int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
861 const char *str, size_t len,
862 const struct iwl_fw_dbg_trigger_tlv *trigger)
863 {
864 struct iwl_mvm_dump_desc *desc;
865
866 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
867 if (!desc)
868 return -ENOMEM;
869
870 desc->len = len;
871 desc->trig_desc.type = cpu_to_le32(trig);
872 memcpy(desc->trig_desc.data, str, len);
873
874 return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
875 }
876
877 int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
878 struct iwl_fw_dbg_trigger_tlv *trigger,
879 const char *fmt, ...)
880 {
881 u16 occurrences = le16_to_cpu(trigger->occurrences);
882 int ret, len = 0;
883 char buf[64];
884
885 if (!occurrences)
886 return 0;
887
888 if (fmt) {
889 va_list ap;
890
891 buf[sizeof(buf) - 1] = '\0';
892
893 va_start(ap, fmt);
894 vsnprintf(buf, sizeof(buf), fmt, ap);
895 va_end(ap);
896
897 /* check for truncation */
898 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
899 buf[sizeof(buf) - 1] = '\0';
900
901 len = strlen(buf) + 1;
902 }
903
904 ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
905 trigger);
906
907 if (ret)
908 return ret;
909
910 trigger->occurrences = cpu_to_le16(occurrences - 1);
911 return 0;
912 }
913
914 static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
915 {
916 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
917 iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
918 else
919 iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
920 }
921
922 int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
923 {
924 u8 *ptr;
925 int ret;
926 int i;
927
928 if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
929 "Invalid configuration %d\n", conf_id))
930 return -EINVAL;
931
932 /* EARLY START - firmware's configuration is hard coded */
933 if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
934 !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
935 conf_id == FW_DBG_START_FROM_ALIVE) {
936 iwl_mvm_restart_early_start(mvm);
937 return 0;
938 }
939
940 if (!mvm->fw->dbg_conf_tlv[conf_id])
941 return -EINVAL;
942
943 if (mvm->fw_dbg_conf != FW_DBG_INVALID)
944 IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
945 mvm->fw_dbg_conf);
946
947 /* Send all HCMDs for configuring the FW debug */
948 ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
949 for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
950 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
951
952 ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
953 le16_to_cpu(cmd->len), cmd->data);
954 if (ret)
955 return ret;
956
957 ptr += sizeof(*cmd);
958 ptr += le16_to_cpu(cmd->len);
959 }
960
961 mvm->fw_dbg_conf = conf_id;
962 return ret;
963 }
Linux with added FPC-III support