2 * sh73a0 Core CPG Clocks
4 * Copyright (C) 2014 Ulrich Hecht
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/shmobile.h>
14 #include <linux/init.h>
15 #include <linux/kernel.h>
17 #include <linux/of_address.h>
18 #include <linux/spinlock.h>
21 struct clk_onecell_data data
;
26 #define CPG_FRQCRA 0x00
27 #define CPG_FRQCRB 0x04
28 #define CPG_SD0CKCR 0x74
29 #define CPG_SD1CKCR 0x78
30 #define CPG_SD2CKCR 0x7c
31 #define CPG_PLLECR 0xd0
32 #define CPG_PLL0CR 0xd8
33 #define CPG_PLL1CR 0x28
34 #define CPG_PLL2CR 0x2c
35 #define CPG_PLL3CR 0xdc
36 #define CPG_CKSCR 0xc0
37 #define CPG_DSI0PHYCR 0x6c
38 #define CPG_DSI1PHYCR 0x70
40 #define CLK_ENABLE_ON_INIT BIT(0)
49 static struct div4_clk div4_clks
[] = {
50 { "zg", "pll0", CPG_FRQCRA
, 16 },
51 { "m3", "pll1", CPG_FRQCRA
, 12 },
52 { "b", "pll1", CPG_FRQCRA
, 8 },
53 { "m1", "pll1", CPG_FRQCRA
, 4 },
54 { "m2", "pll1", CPG_FRQCRA
, 0 },
55 { "zx", "pll1", CPG_FRQCRB
, 12 },
56 { "hp", "pll1", CPG_FRQCRB
, 4 },
60 static const struct clk_div_table div4_div_table
[] = {
61 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
62 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
66 static const struct clk_div_table z_div_table
[] = {
68 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
69 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
70 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
72 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
73 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
76 static struct clk
* __init
77 sh73a0_cpg_register_clock(struct device_node
*np
, struct sh73a0_cpg
*cpg
,
80 const struct clk_div_table
*table
= NULL
;
81 unsigned int shift
, reg
, width
;
82 const char *parent_name
;
83 unsigned int mult
= 1;
86 if (!strcmp(name
, "main")) {
87 /* extal1, extal1_div2, extal2, extal2_div2 */
88 u32 parent_idx
= (clk_readl(cpg
->reg
+ CPG_CKSCR
) >> 28) & 3;
90 parent_name
= of_clk_get_parent_name(np
, parent_idx
>> 1);
91 div
= (parent_idx
& 1) + 1;
92 } else if (!strncmp(name
, "pll", 3)) {
93 void __iomem
*enable_reg
= cpg
->reg
;
94 u32 enable_bit
= name
[3] - '0';
99 enable_reg
+= CPG_PLL0CR
;
102 enable_reg
+= CPG_PLL1CR
;
105 enable_reg
+= CPG_PLL2CR
;
108 enable_reg
+= CPG_PLL3CR
;
111 return ERR_PTR(-EINVAL
);
113 if (clk_readl(cpg
->reg
+ CPG_PLLECR
) & BIT(enable_bit
)) {
114 mult
= ((clk_readl(enable_reg
) >> 24) & 0x3f) + 1;
115 /* handle CFG bit for PLL1 and PLL2 */
116 if (enable_bit
== 1 || enable_bit
== 2)
117 if (clk_readl(enable_reg
) & BIT(20))
120 } else if (!strcmp(name
, "dsi0phy") || !strcmp(name
, "dsi1phy")) {
121 u32 phy_no
= name
[3] - '0';
122 void __iomem
*dsi_reg
= cpg
->reg
+
123 (phy_no
? CPG_DSI1PHYCR
: CPG_DSI0PHYCR
);
125 parent_name
= phy_no
? "dsi1pck" : "dsi0pck";
126 mult
= __raw_readl(dsi_reg
);
127 if (!(mult
& 0x8000))
130 mult
= (mult
& 0x3f) + 1;
131 } else if (!strcmp(name
, "z")) {
132 parent_name
= "pll0";
140 for (c
= div4_clks
; c
->name
; c
++) {
141 if (!strcmp(name
, c
->name
)) {
142 parent_name
= c
->parent
;
143 table
= div4_div_table
;
151 return ERR_PTR(-EINVAL
);
155 return clk_register_fixed_factor(NULL
, name
, parent_name
, 0,
158 return clk_register_divider_table(NULL
, name
, parent_name
, 0,
159 cpg
->reg
+ reg
, shift
, width
, 0,
164 static void __init
sh73a0_cpg_clocks_init(struct device_node
*np
)
166 struct sh73a0_cpg
*cpg
;
171 num_clks
= of_property_count_strings(np
, "clock-output-names");
173 pr_err("%s: failed to count clocks\n", __func__
);
177 cpg
= kzalloc(sizeof(*cpg
), GFP_KERNEL
);
178 clks
= kcalloc(num_clks
, sizeof(*clks
), GFP_KERNEL
);
179 if (cpg
== NULL
|| clks
== NULL
) {
180 /* We're leaking memory on purpose, there's no point in cleaning
181 * up as the system won't boot anyway.
186 spin_lock_init(&cpg
->lock
);
188 cpg
->data
.clks
= clks
;
189 cpg
->data
.clk_num
= num_clks
;
191 cpg
->reg
= of_iomap(np
, 0);
192 if (WARN_ON(cpg
->reg
== NULL
))
195 /* Set SDHI clocks to a known state */
196 clk_writel(0x108, cpg
->reg
+ CPG_SD0CKCR
);
197 clk_writel(0x108, cpg
->reg
+ CPG_SD1CKCR
);
198 clk_writel(0x108, cpg
->reg
+ CPG_SD2CKCR
);
200 for (i
= 0; i
< num_clks
; ++i
) {
204 of_property_read_string_index(np
, "clock-output-names", i
,
207 clk
= sh73a0_cpg_register_clock(np
, cpg
, name
);
209 pr_err("%s: failed to register %s %s clock (%ld)\n",
210 __func__
, np
->name
, name
, PTR_ERR(clk
));
212 cpg
->data
.clks
[i
] = clk
;
215 of_clk_add_provider(np
, of_clk_src_onecell_get
, &cpg
->data
);
217 CLK_OF_DECLARE(sh73a0_cpg_clks
, "renesas,sh73a0-cpg-clocks",
218 sh73a0_cpg_clocks_init
);