arch/i386/kernel/cpu/mcheck/p4.c

   1 /*
   2  * P4 specific Machine Check Exception Reporting
   3  */
   4
   5 #include <linux/init.h>
   6 #include <linux/types.h>
   7 #include <linux/kernel.h>
   8 #include <linux/config.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/smp.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/system.h>
  14 #include <asm/msr.h>
  15 #include <asm/apic.h>
  16
  17 #include "mce.h"
  18
  19 /* as supported by the P4/Xeon family */
  20 struct intel_mce_extended_msrs {
  21         u32 eax;
  22         u32 ebx;
  23         u32 ecx;
  24         u32 edx;
  25         u32 esi;
  26         u32 edi;
  27         u32 ebp;
  28         u32 esp;
  29         u32 eflags;
  30         u32 eip;
  31         /* u32 *reserved[]; */
  32 };
  33
  34 static int mce_num_extended_msrs = 0;
  35
  36
  37 #ifdef CONFIG_X86_MCE_P4THERMAL
  38 static void unexpected_thermal_interrupt(struct pt_regs *regs)
  39 {
  40         printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
  41                         smp_processor_id());
  42         add_taint(TAINT_MACHINE_CHECK);
  43 }
  44
  45 /* P4/Xeon Thermal transition interrupt handler */
  46 static void intel_thermal_interrupt(struct pt_regs *regs)
  47 {
  48         u32 l, h;
  49         unsigned int cpu = smp_processor_id();
  50         static unsigned long next[NR_CPUS];
  51
  52         ack_APIC_irq();
  53
  54         if (time_after(next[cpu], jiffies))
  55                 return;
  56
  57         next[cpu] = jiffies + HZ*5;
  58         rdmsr(MSR_IA32_THERM_STATUS, l, h);
  59         if (l & 0x1) {
  60                 printk(KERN_EMERG "CPU%d: Temperature above threshold\n", cpu);
  61                 printk(KERN_EMERG "CPU%d: Running in modulated clock mode\n",
  62                                 cpu);
  63                 add_taint(TAINT_MACHINE_CHECK);
  64         } else {
  65                 printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
  66         }
  67 }
  68
  69 /* Thermal interrupt handler for this CPU setup */
  70 static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
  71
  72 fastcall void smp_thermal_interrupt(struct pt_regs *regs)
  73 {
  74         irq_enter();
  75         vendor_thermal_interrupt(regs);
  76         irq_exit();
  77 }
  78
  79 /* P4/Xeon Thermal regulation detect and init */
  80 static void intel_init_thermal(struct cpuinfo_x86 *c)
  81 {
  82         u32 l, h;
  83         unsigned int cpu = smp_processor_id();
  84
  85         /* Thermal monitoring */
  86         if (!cpu_has(c, X86_FEATURE_ACPI))
  87                 return; /* -ENODEV */
  88
  89         /* Clock modulation */
  90         if (!cpu_has(c, X86_FEATURE_ACC))
  91                 return; /* -ENODEV */
  92
  93         /* first check if its enabled already, in which case there might
  94          * be some SMM goo which handles it, so we can't even put a handler
  95          * since it might be delivered via SMI already -zwanem.
  96          */
  97         rdmsr (MSR_IA32_MISC_ENABLE, l, h);
  98         h = apic_read(APIC_LVTTHMR);
  99         if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
 100                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
 101                                 cpu);
 102                 return; /* -EBUSY */
 103         }
 104
 105         /* check whether a vector already exists, temporarily masked? */
 106         if (h & APIC_VECTOR_MASK) {
 107                 printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
 108                                 "installed\n",
 109                         cpu, (h & APIC_VECTOR_MASK));
 110                 return; /* -EBUSY */
 111         }
 112
 113         /* The temperature transition interrupt handler setup */
 114         h = THERMAL_APIC_VECTOR;                /* our delivery vector */
 115         h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
 116         apic_write_around(APIC_LVTTHMR, h);
 117
 118         rdmsr (MSR_IA32_THERM_INTERRUPT, l, h);
 119         wrmsr (MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
 120
 121         /* ok we're good to go... */
 122         vendor_thermal_interrupt = intel_thermal_interrupt;
 123
 124         rdmsr (MSR_IA32_MISC_ENABLE, l, h);
 125         wrmsr (MSR_IA32_MISC_ENABLE, l | (1<<3), h);
 126
 127         l = apic_read (APIC_LVTTHMR);
 128         apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
 129         printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
 130         return;
 131 }
 132 #endif /* CONFIG_X86_MCE_P4THERMAL */
 133
 134
 135 /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
 136 static inline int intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
 137 {
 138         u32 h;
 139
 140         if (mce_num_extended_msrs == 0)
 141                 goto done;
 142
 143         rdmsr (MSR_IA32_MCG_EAX, r->eax, h);
 144         rdmsr (MSR_IA32_MCG_EBX, r->ebx, h);
 145         rdmsr (MSR_IA32_MCG_ECX, r->ecx, h);
 146         rdmsr (MSR_IA32_MCG_EDX, r->edx, h);
 147         rdmsr (MSR_IA32_MCG_ESI, r->esi, h);
 148         rdmsr (MSR_IA32_MCG_EDI, r->edi, h);
 149         rdmsr (MSR_IA32_MCG_EBP, r->ebp, h);
 150         rdmsr (MSR_IA32_MCG_ESP, r->esp, h);
 151         rdmsr (MSR_IA32_MCG_EFLAGS, r->eflags, h);
 152         rdmsr (MSR_IA32_MCG_EIP, r->eip, h);
 153
 154         /* can we rely on kmalloc to do a dynamic
 155          * allocation for the reserved registers?
 156          */
 157 done:
 158         return mce_num_extended_msrs;
 159 }
 160
 161 static fastcall void intel_machine_check(struct pt_regs * regs, long error_code)
 162 {
 163         int recover=1;
 164         u32 alow, ahigh, high, low;
 165         u32 mcgstl, mcgsth;
 166         int i;
 167         struct intel_mce_extended_msrs dbg;
 168
 169         rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 170         if (mcgstl & (1<<0))    /* Recoverable ? */
 171                 recover=0;
 172
 173         printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
 174                 smp_processor_id(), mcgsth, mcgstl);
 175
 176         if (intel_get_extended_msrs(&dbg)) {
 177                 printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
 178                         smp_processor_id(), dbg.eip, dbg.eflags);
 179                 printk (KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
 180                         dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
 181                 printk (KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
 182                         dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
 183         }
 184
 185         for (i=0; i<nr_mce_banks; i++) {
 186                 rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
 187                 if (high & (1<<31)) {
 188                         if (high & (1<<29))
 189                                 recover |= 1;
 190                         if (high & (1<<25))
 191                                 recover |= 2;
 192                         printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
 193                         high &= ~(1<<31);
 194                         if (high & (1<<27)) {
 195                                 rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
 196                                 printk ("[%08x%08x]", ahigh, alow);
 197                         }
 198                         if (high & (1<<26)) {
 199                                 rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
 200                                 printk (" at %08x%08x", ahigh, alow);
 201                         }
 202                         printk ("\n");
 203                 }
 204         }
 205
 206         if (recover & 2)
 207                 panic ("CPU context corrupt");
 208         if (recover & 1)
 209                 panic ("Unable to continue");
 210
 211         printk(KERN_EMERG "Attempting to continue.\n");
 212         /*
 213          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
 214          * recoverable/continuable.This will allow BIOS to look at the MSRs
 215          * for errors if the OS could not log the error.
 216          */
 217         for (i=0; i<nr_mce_banks; i++) {
 218                 u32 msr;
 219                 msr = MSR_IA32_MC0_STATUS+i*4;
 220                 rdmsr (msr, low, high);
 221                 if (high&(1<<31)) {
 222                         /* Clear it */
 223                         wrmsr(msr, 0UL, 0UL);
 224                         /* Serialize */
 225                         wmb();
 226                         add_taint(TAINT_MACHINE_CHECK);
 227                 }
 228         }
 229         mcgstl &= ~(1<<2);
 230         wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
 231 }
 232
 233
 234 void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 235 {
 236         u32 l, h;
 237         int i;
 238
 239         machine_check_vector = intel_machine_check;
 240         wmb();
 241
 242         printk (KERN_INFO "Intel machine check architecture supported.\n");
 243         rdmsr (MSR_IA32_MCG_CAP, l, h);
 244         if (l & (1<<8)) /* Control register present ? */
 245                 wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 246         nr_mce_banks = l & 0xff;
 247
 248         for (i=0; i<nr_mce_banks; i++) {
 249                 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 250                 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 251         }
 252
 253         set_in_cr4 (X86_CR4_MCE);
 254         printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 255                 smp_processor_id());
 256
 257         /* Check for P4/Xeon extended MCE MSRs */
 258         rdmsr (MSR_IA32_MCG_CAP, l, h);
 259         if (l & (1<<9)) {/* MCG_EXT_P */
 260                 mce_num_extended_msrs = (l >> 16) & 0xff;
 261                 printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
 262                                 " available\n",
 263                         smp_processor_id(), mce_num_extended_msrs);
 264
 265 #ifdef CONFIG_X86_MCE_P4THERMAL
 266                 /* Check for P4/Xeon Thermal monitor */
 267                 intel_init_thermal(c);
 268 #endif
 269         }
 270 }