drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui <ray.huang@amd.com>
  23  *
  24  */
  25
  26 #ifndef _ICELAND_SMUMGR_H_
  27 #define _ICELAND_SMUMGR_H_
  28
  29
  30 #include "smu7_smumgr.h"
  31 #include "pp_endian.h"
  32 #include "smu71_discrete.h"
  33
  34 struct iceland_pt_defaults {
  35         uint8_t   svi_load_line_en;
  36         uint8_t   svi_load_line_vddc;
  37         uint8_t   tdc_vddc_throttle_release_limit_perc;
  38         uint8_t   tdc_mawt;
  39         uint8_t   tdc_waterfall_ctl;
  40         uint8_t   dte_ambient_temp_base;
  41         uint32_t  display_cac;
  42         uint32_t  bamp_temp_gradient;
  43         uint16_t  bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
  44         uint16_t  bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
  45 };
  46
  47 struct iceland_mc_reg_entry {
  48         uint32_t mclk_max;
  49         uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
  50 };
  51
  52 struct iceland_mc_reg_table {
  53         uint8_t   last;               /* number of registers*/
  54         uint8_t   num_entries;        /* number of entries in mc_reg_table_entry used*/
  55         uint16_t  validflag;          /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
  56         struct iceland_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
  57         SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
  58 };
  59
  60 struct iceland_smumgr {
  61         struct smu7_smumgr smu7_data;
  62         struct SMU71_Discrete_DpmTable       smc_state_table;
  63         struct SMU71_Discrete_PmFuses  power_tune_table;
  64         struct SMU71_Discrete_Ulv            ulv_setting;
  65         const struct iceland_pt_defaults  *power_tune_defaults;
  66         SMU71_Discrete_MCRegisters      mc_regs;
  67         struct iceland_mc_reg_table mc_reg_table;
  68         uint32_t        activity_target[SMU71_MAX_LEVELS_GRAPHICS];
  69 };
  70
  71 #endif