drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_encoder.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_dp_dual_mode_helper.h>
  38 #include <drm/drm_dp_mst_helper.h>
  39 #include <drm/drm_rect.h>
  40 #include <drm/drm_atomic.h>
  41
  42 /**
  43  * _wait_for - magic (register) wait macro
  44  *
  45  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46  * contexts. Note that it's important that we check the condition again after
  47  * having timed out, since the timeout could be due to preemption or similar and
  48  * we've never had a chance to check the condition before the timeout.
  49  *
  50  * TODO: When modesetting has fully transitioned to atomic, the below
  51  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  52  * added.
  53  */
  54 #define _wait_for(COND, US, W) ({ \
  55         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  56         int ret__;                                                      \
  57         for (;;) {                                                      \
  58                 bool expired__ = time_after(jiffies, timeout__);        \
  59                 if (COND) {                                             \
  60                         ret__ = 0;                                      \
  61                         break;                                          \
  62                 }                                                       \
  63                 if (expired__) {                                        \
  64                         ret__ = -ETIMEDOUT;                             \
  65                         break;                                          \
  66                 }                                                       \
  67                 if ((W) && drm_can_sleep()) {                           \
  68                         usleep_range((W), (W)*2);                       \
  69                 } else {                                                \
  70                         cpu_relax();                                    \
  71                 }                                                       \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  77
  78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  81 #else
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  83 #endif
  84
  85 #define _wait_for_atomic(COND, US, ATOMIC) \
  86 ({ \
  87         int cpu, ret, timeout = (US) * 1000; \
  88         u64 base; \
  89         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  90         BUILD_BUG_ON((US) > 50000); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 133 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 134
 135 #define KHz(x) (1000 * (x))
 136 #define MHz(x) KHz(1000 * (x))
 137
 138 /*
 139  * Display related stuff
 140  */
 141
 142 /* store information about an Ixxx DVO */
 143 /* The i830->i865 use multiple DVOs with multiple i2cs */
 144 /* the i915, i945 have a single sDVO i2c bus - which is different */
 145 #define MAX_OUTPUTS 6
 146 /* maximum connectors per crtcs in the mode set */
 147
 148 /* Maximum cursor sizes */
 149 #define GEN2_CURSOR_WIDTH 64
 150 #define GEN2_CURSOR_HEIGHT 64
 151 #define MAX_CURSOR_WIDTH 256
 152 #define MAX_CURSOR_HEIGHT 256
 153
 154 #define INTEL_I2C_BUS_DVO 1
 155 #define INTEL_I2C_BUS_SDVO 2
 156
 157 /* these are outputs from the chip - integrated only
 158    external chips are via DVO or SDVO output */
 159 enum intel_output_type {
 160         INTEL_OUTPUT_UNUSED = 0,
 161         INTEL_OUTPUT_ANALOG = 1,
 162         INTEL_OUTPUT_DVO = 2,
 163         INTEL_OUTPUT_SDVO = 3,
 164         INTEL_OUTPUT_LVDS = 4,
 165         INTEL_OUTPUT_TVOUT = 5,
 166         INTEL_OUTPUT_HDMI = 6,
 167         INTEL_OUTPUT_DP = 7,
 168         INTEL_OUTPUT_EDP = 8,
 169         INTEL_OUTPUT_DSI = 9,
 170         INTEL_OUTPUT_UNKNOWN = 10,
 171         INTEL_OUTPUT_DP_MST = 11,
 172 };
 173
 174 #define INTEL_DVO_CHIP_NONE 0
 175 #define INTEL_DVO_CHIP_LVDS 1
 176 #define INTEL_DVO_CHIP_TMDS 2
 177 #define INTEL_DVO_CHIP_TVOUT 4
 178
 179 #define INTEL_DSI_VIDEO_MODE    0
 180 #define INTEL_DSI_COMMAND_MODE  1
 181
 182 struct intel_framebuffer {
 183         struct drm_framebuffer base;
 184         struct drm_i915_gem_object *obj;
 185         struct intel_rotation_info rot_info;
 186
 187         /* for each plane in the normal GTT view */
 188         struct {
 189                 unsigned int x, y;
 190         } normal[2];
 191         /* for each plane in the rotated GTT view */
 192         struct {
 193                 unsigned int x, y;
 194                 unsigned int pitch; /* pixels */
 195         } rotated[2];
 196 };
 197
 198 struct intel_fbdev {
 199         struct drm_fb_helper helper;
 200         struct intel_framebuffer *fb;
 201         struct i915_vma *vma;
 202         async_cookie_t cookie;
 203         int preferred_bpp;
 204 };
 205
 206 struct intel_encoder {
 207         struct drm_encoder base;
 208
 209         enum intel_output_type type;
 210         enum port port;
 211         unsigned int cloneable;
 212         void (*hot_plug)(struct intel_encoder *);
 213         bool (*compute_config)(struct intel_encoder *,
 214                                struct intel_crtc_state *,
 215                                struct drm_connector_state *);
 216         void (*pre_pll_enable)(struct intel_encoder *,
 217                                struct intel_crtc_state *,
 218                                struct drm_connector_state *);
 219         void (*pre_enable)(struct intel_encoder *,
 220                            struct intel_crtc_state *,
 221                            struct drm_connector_state *);
 222         void (*enable)(struct intel_encoder *,
 223                        struct intel_crtc_state *,
 224                        struct drm_connector_state *);
 225         void (*disable)(struct intel_encoder *,
 226                         struct intel_crtc_state *,
 227                         struct drm_connector_state *);
 228         void (*post_disable)(struct intel_encoder *,
 229                              struct intel_crtc_state *,
 230                              struct drm_connector_state *);
 231         void (*post_pll_disable)(struct intel_encoder *,
 232                                  struct intel_crtc_state *,
 233                                  struct drm_connector_state *);
 234         /* Read out the current hw state of this connector, returning true if
 235          * the encoder is active. If the encoder is enabled it also set the pipe
 236          * it is connected to in the pipe parameter. */
 237         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 238         /* Reconstructs the equivalent mode flags for the current hardware
 239          * state. This must be called _after_ display->get_pipe_config has
 240          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 241          * be set correctly before calling this function. */
 242         void (*get_config)(struct intel_encoder *,
 243                            struct intel_crtc_state *pipe_config);
 244         /*
 245          * Called during system suspend after all pending requests for the
 246          * encoder are flushed (for example for DP AUX transactions) and
 247          * device interrupts are disabled.
 248          */
 249         void (*suspend)(struct intel_encoder *);
 250         int crtc_mask;
 251         enum hpd_pin hpd_pin;
 252         /* for communication with audio component; protected by av_mutex */
 253         const struct drm_connector *audio_connector;
 254 };
 255
 256 struct intel_panel {
 257         struct drm_display_mode *fixed_mode;
 258         struct drm_display_mode *downclock_mode;
 259         int fitting_mode;
 260
 261         /* backlight */
 262         struct {
 263                 bool present;
 264                 u32 level;
 265                 u32 min;
 266                 u32 max;
 267                 bool enabled;
 268                 bool combination_mode;  /* gen 2/4 only */
 269                 bool active_low_pwm;
 270                 bool alternate_pwm_increment;   /* lpt+ */
 271
 272                 /* PWM chip */
 273                 bool util_pin_active_low;       /* bxt+ */
 274                 u8 controller;          /* bxt+ only */
 275                 struct pwm_device *pwm;
 276
 277                 struct backlight_device *device;
 278
 279                 /* Connector and platform specific backlight functions */
 280                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 281                 uint32_t (*get)(struct intel_connector *connector);
 282                 void (*set)(struct intel_connector *connector, uint32_t level);
 283                 void (*disable)(struct intel_connector *connector);
 284                 void (*enable)(struct intel_connector *connector);
 285                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 286                                       uint32_t hz);
 287                 void (*power)(struct intel_connector *, bool enable);
 288         } backlight;
 289 };
 290
 291 struct intel_connector {
 292         struct drm_connector base;
 293         /*
 294          * The fixed encoder this connector is connected to.
 295          */
 296         struct intel_encoder *encoder;
 297
 298         /* ACPI device id for ACPI and driver cooperation */
 299         u32 acpi_device_id;
 300
 301         /* Reads out the current hw, returning true if the connector is enabled
 302          * and active (i.e. dpms ON state). */
 303         bool (*get_hw_state)(struct intel_connector *);
 304
 305         /* Panel info for eDP and LVDS */
 306         struct intel_panel panel;
 307
 308         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 309         struct edid *edid;
 310         struct edid *detect_edid;
 311
 312         /* since POLL and HPD connectors may use the same HPD line keep the native
 313            state of connector->polled in case hotplug storm detection changes it */
 314         u8 polled;
 315
 316         void *port; /* store this opaque as its illegal to dereference it */
 317
 318         struct intel_dp *mst_port;
 319 };
 320
 321 struct dpll {
 322         /* given values */
 323         int n;
 324         int m1, m2;
 325         int p1, p2;
 326         /* derived values */
 327         int     dot;
 328         int     vco;
 329         int     m;
 330         int     p;
 331 };
 332
 333 struct intel_atomic_state {
 334         struct drm_atomic_state base;
 335
 336         unsigned int cdclk;
 337
 338         /*
 339          * Calculated device cdclk, can be different from cdclk
 340          * only when all crtc's are DPMS off.
 341          */
 342         unsigned int dev_cdclk;
 343
 344         bool dpll_set, modeset;
 345
 346         /*
 347          * Does this transaction change the pipes that are active?  This mask
 348          * tracks which CRTC's have changed their active state at the end of
 349          * the transaction (not counting the temporary disable during modesets).
 350          * This mask should only be non-zero when intel_state->modeset is true,
 351          * but the converse is not necessarily true; simply changing a mode may
 352          * not flip the final active status of any CRTC's
 353          */
 354         unsigned int active_pipe_changes;
 355
 356         unsigned int active_crtcs;
 357         unsigned int min_pixclk[I915_MAX_PIPES];
 358
 359         /* SKL/KBL Only */
 360         unsigned int cdclk_pll_vco;
 361
 362         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 363
 364         /*
 365          * Current watermarks can't be trusted during hardware readout, so
 366          * don't bother calculating intermediate watermarks.
 367          */
 368         bool skip_intermediate_wm;
 369
 370         /* Gen9+ only */
 371         struct skl_wm_values wm_results;
 372
 373         struct i915_sw_fence commit_ready;
 374 };
 375
 376 struct intel_plane_state {
 377         struct drm_plane_state base;
 378         struct drm_rect clip;
 379         struct i915_vma *vma;
 380
 381         struct {
 382                 u32 offset;
 383                 int x, y;
 384         } main;
 385         struct {
 386                 u32 offset;
 387                 int x, y;
 388         } aux;
 389
 390         /*
 391          * scaler_id
 392          *    = -1 : not using a scaler
 393          *    >=  0 : using a scalers
 394          *
 395          * plane requiring a scaler:
 396          *   - During check_plane, its bit is set in
 397          *     crtc_state->scaler_state.scaler_users by calling helper function
 398          *     update_scaler_plane.
 399          *   - scaler_id indicates the scaler it got assigned.
 400          *
 401          * plane doesn't require a scaler:
 402          *   - this can happen when scaling is no more required or plane simply
 403          *     got disabled.
 404          *   - During check_plane, corresponding bit is reset in
 405          *     crtc_state->scaler_state.scaler_users by calling helper function
 406          *     update_scaler_plane.
 407          */
 408         int scaler_id;
 409
 410         struct drm_intel_sprite_colorkey ckey;
 411 };
 412
 413 struct intel_initial_plane_config {
 414         struct intel_framebuffer *fb;
 415         unsigned int tiling;
 416         int size;
 417         u32 base;
 418 };
 419
 420 #define SKL_MIN_SRC_W 8
 421 #define SKL_MAX_SRC_W 4096
 422 #define SKL_MIN_SRC_H 8
 423 #define SKL_MAX_SRC_H 4096
 424 #define SKL_MIN_DST_W 8
 425 #define SKL_MAX_DST_W 4096
 426 #define SKL_MIN_DST_H 8
 427 #define SKL_MAX_DST_H 4096
 428
 429 struct intel_scaler {
 430         int in_use;
 431         uint32_t mode;
 432 };
 433
 434 struct intel_crtc_scaler_state {
 435 #define SKL_NUM_SCALERS 2
 436         struct intel_scaler scalers[SKL_NUM_SCALERS];
 437
 438         /*
 439          * scaler_users: keeps track of users requesting scalers on this crtc.
 440          *
 441          *     If a bit is set, a user is using a scaler.
 442          *     Here user can be a plane or crtc as defined below:
 443          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 444          *       bit 31    - crtc
 445          *
 446          * Instead of creating a new index to cover planes and crtc, using
 447          * existing drm_plane_index for planes which is well less than 31
 448          * planes and bit 31 for crtc. This should be fine to cover all
 449          * our platforms.
 450          *
 451          * intel_atomic_setup_scalers will setup available scalers to users
 452          * requesting scalers. It will gracefully fail if request exceeds
 453          * avilability.
 454          */
 455 #define SKL_CRTC_INDEX 31
 456         unsigned scaler_users;
 457
 458         /* scaler used by crtc for panel fitting purpose */
 459         int scaler_id;
 460 };
 461
 462 /* drm_mode->private_flags */
 463 #define I915_MODE_FLAG_INHERITED 1
 464
 465 struct intel_pipe_wm {
 466         struct intel_wm_level wm[5];
 467         struct intel_wm_level raw_wm[5];
 468         uint32_t linetime;
 469         bool fbc_wm_enabled;
 470         bool pipe_enabled;
 471         bool sprites_enabled;
 472         bool sprites_scaled;
 473 };
 474
 475 struct skl_plane_wm {
 476         struct skl_wm_level wm[8];
 477         struct skl_wm_level trans_wm;
 478 };
 479
 480 struct skl_pipe_wm {
 481         struct skl_plane_wm planes[I915_MAX_PLANES];
 482         uint32_t linetime;
 483 };
 484
 485 struct intel_crtc_wm_state {
 486         union {
 487                 struct {
 488                         /*
 489                          * Intermediate watermarks; these can be
 490                          * programmed immediately since they satisfy
 491                          * both the current configuration we're
 492                          * switching away from and the new
 493                          * configuration we're switching to.
 494                          */
 495                         struct intel_pipe_wm intermediate;
 496
 497                         /*
 498                          * Optimal watermarks, programmed post-vblank
 499                          * when this state is committed.
 500                          */
 501                         struct intel_pipe_wm optimal;
 502                 } ilk;
 503
 504                 struct {
 505                         /* gen9+ only needs 1-step wm programming */
 506                         struct skl_pipe_wm optimal;
 507                         struct skl_ddb_entry ddb;
 508                 } skl;
 509         };
 510
 511         /*
 512          * Platforms with two-step watermark programming will need to
 513          * update watermark programming post-vblank to switch from the
 514          * safe intermediate watermarks to the optimal final
 515          * watermarks.
 516          */
 517         bool need_postvbl_update;
 518 };
 519
 520 struct intel_crtc_state {
 521         struct drm_crtc_state base;
 522
 523         /**
 524          * quirks - bitfield with hw state readout quirks
 525          *
 526          * For various reasons the hw state readout code might not be able to
 527          * completely faithfully read out the current state. These cases are
 528          * tracked with quirk flags so that fastboot and state checker can act
 529          * accordingly.
 530          */
 531 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 532         unsigned long quirks;
 533
 534         unsigned fb_bits; /* framebuffers to flip */
 535         bool update_pipe; /* can a fast modeset be performed? */
 536         bool disable_cxsr;
 537         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 538         bool fb_changed; /* fb on any of the planes is changed */
 539
 540         /* Pipe source size (ie. panel fitter input size)
 541          * All planes will be positioned inside this space,
 542          * and get clipped at the edges. */
 543         int pipe_src_w, pipe_src_h;
 544
 545         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 546          * between pch encoders and cpu encoders. */
 547         bool has_pch_encoder;
 548
 549         /* Are we sending infoframes on the attached port */
 550         bool has_infoframe;
 551
 552         /* CPU Transcoder for the pipe. Currently this can only differ from the
 553          * pipe on Haswell and later (where we have a special eDP transcoder)
 554          * and Broxton (where we have special DSI transcoders). */
 555         enum transcoder cpu_transcoder;
 556
 557         /*
 558          * Use reduced/limited/broadcast rbg range, compressing from the full
 559          * range fed into the crtcs.
 560          */
 561         bool limited_color_range;
 562
 563         /* Bitmask of encoder types (enum intel_output_type)
 564          * driven by the pipe.
 565          */
 566         unsigned int output_types;
 567
 568         /* Whether we should send NULL infoframes. Required for audio. */
 569         bool has_hdmi_sink;
 570
 571         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 572          * has_dp_encoder is set. */
 573         bool has_audio;
 574
 575         /*
 576          * Enable dithering, used when the selected pipe bpp doesn't match the
 577          * plane bpp.
 578          */
 579         bool dither;
 580
 581         /* Controls for the clock computation, to override various stages. */
 582         bool clock_set;
 583
 584         /* SDVO TV has a bunch of special case. To make multifunction encoders
 585          * work correctly, we need to track this at runtime.*/
 586         bool sdvo_tv_clock;
 587
 588         /*
 589          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 590          * required. This is set in the 2nd loop of calling encoder's
 591          * ->compute_config if the first pick doesn't work out.
 592          */
 593         bool bw_constrained;
 594
 595         /* Settings for the intel dpll used on pretty much everything but
 596          * haswell. */
 597         struct dpll dpll;
 598
 599         /* Selected dpll when shared or NULL. */
 600         struct intel_shared_dpll *shared_dpll;
 601
 602         /* Actual register state of the dpll, for shared dpll cross-checking. */
 603         struct intel_dpll_hw_state dpll_hw_state;
 604
 605         /* DSI PLL registers */
 606         struct {
 607                 u32 ctrl, div;
 608         } dsi_pll;
 609
 610         int pipe_bpp;
 611         struct intel_link_m_n dp_m_n;
 612
 613         /* m2_n2 for eDP downclock */
 614         struct intel_link_m_n dp_m2_n2;
 615         bool has_drrs;
 616
 617         /*
 618          * Frequence the dpll for the port should run at. Differs from the
 619          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 620          * already multiplied by pixel_multiplier.
 621          */
 622         int port_clock;
 623
 624         /* Used by SDVO (and if we ever fix it, HDMI). */
 625         unsigned pixel_multiplier;
 626
 627         uint8_t lane_count;
 628
 629         /*
 630          * Used by platforms having DP/HDMI PHY with programmable lane
 631          * latency optimization.
 632          */
 633         uint8_t lane_lat_optim_mask;
 634
 635         /* Panel fitter controls for gen2-gen4 + VLV */
 636         struct {
 637                 u32 control;
 638                 u32 pgm_ratios;
 639                 u32 lvds_border_bits;
 640         } gmch_pfit;
 641
 642         /* Panel fitter placement and size for Ironlake+ */
 643         struct {
 644                 u32 pos;
 645                 u32 size;
 646                 bool enabled;
 647                 bool force_thru;
 648         } pch_pfit;
 649
 650         /* FDI configuration, only valid if has_pch_encoder is set. */
 651         int fdi_lanes;
 652         struct intel_link_m_n fdi_m_n;
 653
 654         bool ips_enabled;
 655
 656         bool enable_fbc;
 657
 658         bool double_wide;
 659
 660         int pbn;
 661
 662         struct intel_crtc_scaler_state scaler_state;
 663
 664         /* w/a for waiting 2 vblanks during crtc enable */
 665         enum pipe hsw_workaround_pipe;
 666
 667         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 668         bool disable_lp_wm;
 669
 670         struct intel_crtc_wm_state wm;
 671
 672         /* Gamma mode programmed on the pipe */
 673         uint32_t gamma_mode;
 674 };
 675
 676 struct vlv_wm_state {
 677         struct vlv_pipe_wm wm[3];
 678         struct vlv_sr_wm sr[3];
 679         uint8_t num_active_planes;
 680         uint8_t num_levels;
 681         uint8_t level;
 682         bool cxsr;
 683 };
 684
 685 struct intel_crtc {
 686         struct drm_crtc base;
 687         enum pipe pipe;
 688         enum plane plane;
 689         u8 lut_r[256], lut_g[256], lut_b[256];
 690         /*
 691          * Whether the crtc and the connected output pipeline is active. Implies
 692          * that crtc->enabled is set, i.e. the current mode configuration has
 693          * some outputs connected to this crtc.
 694          */
 695         bool active;
 696         bool lowfreq_avail;
 697         u8 plane_ids_mask;
 698         unsigned long enabled_power_domains;
 699         struct intel_overlay *overlay;
 700         struct intel_flip_work *flip_work;
 701
 702         atomic_t unpin_work_count;
 703
 704         /* Display surface base address adjustement for pageflips. Note that on
 705          * gen4+ this only adjusts up to a tile, offsets within a tile are
 706          * handled in the hw itself (with the TILEOFF register). */
 707         u32 dspaddr_offset;
 708         int adjusted_x;
 709         int adjusted_y;
 710
 711         uint32_t cursor_addr;
 712         uint32_t cursor_cntl;
 713         uint32_t cursor_size;
 714         uint32_t cursor_base;
 715
 716         struct intel_crtc_state *config;
 717
 718         /* global reset count when the last flip was submitted */
 719         unsigned int reset_count;
 720
 721         /* Access to these should be protected by dev_priv->irq_lock. */
 722         bool cpu_fifo_underrun_disabled;
 723         bool pch_fifo_underrun_disabled;
 724
 725         /* per-pipe watermark state */
 726         struct {
 727                 /* watermarks currently being used  */
 728                 union {
 729                         struct intel_pipe_wm ilk;
 730                 } active;
 731
 732                 /* allow CxSR on this pipe */
 733                 bool cxsr_allowed;
 734         } wm;
 735
 736         int scanline_offset;
 737
 738         struct {
 739                 unsigned start_vbl_count;
 740                 ktime_t start_vbl_time;
 741                 int min_vbl, max_vbl;
 742                 int scanline_start;
 743         } debug;
 744
 745         /* scalers available on this crtc */
 746         int num_scalers;
 747
 748         struct vlv_wm_state wm_state;
 749 };
 750
 751 struct intel_plane_wm_parameters {
 752         uint32_t horiz_pixels;
 753         uint32_t vert_pixels;
 754         /*
 755          *   For packed pixel formats:
 756          *     bytes_per_pixel - holds bytes per pixel
 757          *   For planar pixel formats:
 758          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 759          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 760          */
 761         uint8_t bytes_per_pixel;
 762         uint8_t y_bytes_per_pixel;
 763         bool enabled;
 764         bool scaled;
 765         u64 tiling;
 766         unsigned int rotation;
 767         uint16_t fifo_size;
 768 };
 769
 770 struct intel_plane {
 771         struct drm_plane base;
 772         u8 plane;
 773         enum plane_id id;
 774         enum pipe pipe;
 775         bool can_scale;
 776         int max_downscale;
 777         uint32_t frontbuffer_bit;
 778
 779         /* Since we need to change the watermarks before/after
 780          * enabling/disabling the planes, we need to store the parameters here
 781          * as the other pieces of the struct may not reflect the values we want
 782          * for the watermark calculations. Currently only Haswell uses this.
 783          */
 784         struct intel_plane_wm_parameters wm;
 785
 786         /*
 787          * NOTE: Do not place new plane state fields here (e.g., when adding
 788          * new plane properties).  New runtime state should now be placed in
 789          * the intel_plane_state structure and accessed via plane_state.
 790          */
 791
 792         void (*update_plane)(struct drm_plane *plane,
 793                              const struct intel_crtc_state *crtc_state,
 794                              const struct intel_plane_state *plane_state);
 795         void (*disable_plane)(struct drm_plane *plane,
 796                               struct drm_crtc *crtc);
 797         int (*check_plane)(struct drm_plane *plane,
 798                            struct intel_crtc_state *crtc_state,
 799                            struct intel_plane_state *state);
 800 };
 801
 802 struct intel_watermark_params {
 803         u16 fifo_size;
 804         u16 max_wm;
 805         u8 default_wm;
 806         u8 guard_size;
 807         u8 cacheline_size;
 808 };
 809
 810 struct cxsr_latency {
 811         bool is_desktop : 1;
 812         bool is_ddr3 : 1;
 813         u16 fsb_freq;
 814         u16 mem_freq;
 815         u16 display_sr;
 816         u16 display_hpll_disable;
 817         u16 cursor_sr;
 818         u16 cursor_hpll_disable;
 819 };
 820
 821 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 822 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 823 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 824 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 825 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 826 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 827 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 828 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 829 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 830
 831 struct intel_hdmi {
 832         i915_reg_t hdmi_reg;
 833         int ddc_bus;
 834         struct {
 835                 enum drm_dp_dual_mode_type type;
 836                 int max_tmds_clock;
 837         } dp_dual_mode;
 838         bool limited_color_range;
 839         bool color_range_auto;
 840         bool has_hdmi_sink;
 841         bool has_audio;
 842         enum hdmi_force_audio force_audio;
 843         bool rgb_quant_range_selectable;
 844         enum hdmi_picture_aspect aspect_ratio;
 845         struct intel_connector *attached_connector;
 846         void (*write_infoframe)(struct drm_encoder *encoder,
 847                                 const struct intel_crtc_state *crtc_state,
 848                                 enum hdmi_infoframe_type type,
 849                                 const void *frame, ssize_t len);
 850         void (*set_infoframes)(struct drm_encoder *encoder,
 851                                bool enable,
 852                                const struct intel_crtc_state *crtc_state,
 853                                const struct drm_connector_state *conn_state);
 854         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 855                                   const struct intel_crtc_state *pipe_config);
 856 };
 857
 858 struct intel_dp_mst_encoder;
 859 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 860
 861 /*
 862  * enum link_m_n_set:
 863  *      When platform provides two set of M_N registers for dp, we can
 864  *      program them and switch between them incase of DRRS.
 865  *      But When only one such register is provided, we have to program the
 866  *      required divider value on that registers itself based on the DRRS state.
 867  *
 868  * M1_N1        : Program dp_m_n on M1_N1 registers
 869  *                        dp_m2_n2 on M2_N2 registers (If supported)
 870  *
 871  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 872  *                        M2_N2 registers are not supported
 873  */
 874
 875 enum link_m_n_set {
 876         /* Sets the m1_n1 and m2_n2 */
 877         M1_N1 = 0,
 878         M2_N2
 879 };
 880
 881 struct intel_dp_desc {
 882         u8 oui[3];
 883         u8 device_id[6];
 884         u8 hw_rev;
 885         u8 sw_major_rev;
 886         u8 sw_minor_rev;
 887 } __packed;
 888
 889 struct intel_dp_compliance_data {
 890         unsigned long edid;
 891 };
 892
 893 struct intel_dp_compliance {
 894         unsigned long test_type;
 895         struct intel_dp_compliance_data test_data;
 896         bool test_active;
 897 };
 898
 899 struct intel_dp {
 900         i915_reg_t output_reg;
 901         i915_reg_t aux_ch_ctl_reg;
 902         i915_reg_t aux_ch_data_reg[5];
 903         uint32_t DP;
 904         int link_rate;
 905         uint8_t lane_count;
 906         uint8_t sink_count;
 907         bool link_mst;
 908         bool has_audio;
 909         bool detect_done;
 910         bool channel_eq_status;
 911         enum hdmi_force_audio force_audio;
 912         bool limited_color_range;
 913         bool color_range_auto;
 914         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 915         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 916         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 917         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 918         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 919         uint8_t num_sink_rates;
 920         int sink_rates[DP_MAX_SUPPORTED_RATES];
 921         /* Max lane count for the sink as per DPCD registers */
 922         uint8_t max_sink_lane_count;
 923         /* Max link BW for the sink as per DPCD registers */
 924         int max_sink_link_bw;
 925         /* sink or branch descriptor */
 926         struct intel_dp_desc desc;
 927         struct drm_dp_aux aux;
 928         uint8_t train_set[4];
 929         int panel_power_up_delay;
 930         int panel_power_down_delay;
 931         int panel_power_cycle_delay;
 932         int backlight_on_delay;
 933         int backlight_off_delay;
 934         struct delayed_work panel_vdd_work;
 935         bool want_panel_vdd;
 936         unsigned long last_power_on;
 937         unsigned long last_backlight_off;
 938         ktime_t panel_power_off_time;
 939
 940         struct notifier_block edp_notifier;
 941
 942         /*
 943          * Pipe whose power sequencer is currently locked into
 944          * this port. Only relevant on VLV/CHV.
 945          */
 946         enum pipe pps_pipe;
 947         /*
 948          * Pipe currently driving the port. Used for preventing
 949          * the use of the PPS for any pipe currentrly driving
 950          * external DP as that will mess things up on VLV.
 951          */
 952         enum pipe active_pipe;
 953         /*
 954          * Set if the sequencer may be reset due to a power transition,
 955          * requiring a reinitialization. Only relevant on BXT.
 956          */
 957         bool pps_reset;
 958         struct edp_power_seq pps_delays;
 959
 960         bool can_mst; /* this port supports mst */
 961         bool is_mst;
 962         int active_mst_links;
 963         /* connector directly attached - won't be use for modeset in mst world */
 964         struct intel_connector *attached_connector;
 965
 966         /* mst connector list */
 967         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 968         struct drm_dp_mst_topology_mgr mst_mgr;
 969
 970         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 971         /*
 972          * This function returns the value we have to program the AUX_CTL
 973          * register with to kick off an AUX transaction.
 974          */
 975         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 976                                      bool has_aux_irq,
 977                                      int send_bytes,
 978                                      uint32_t aux_clock_divider);
 979
 980         /* This is called before a link training is starterd */
 981         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 982
 983         /* Displayport compliance testing */
 984         struct intel_dp_compliance compliance;
 985 };
 986
 987 struct intel_lspcon {
 988         bool active;
 989         enum drm_lspcon_mode mode;
 990         bool desc_valid;
 991 };
 992
 993 struct intel_digital_port {
 994         struct intel_encoder base;
 995         enum port port;
 996         u32 saved_port_bits;
 997         struct intel_dp dp;
 998         struct intel_hdmi hdmi;
 999         struct intel_lspcon lspcon;
1000         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1001         bool release_cl2_override;
1002         uint8_t max_lanes;
1003 };
1004
1005 struct intel_dp_mst_encoder {
1006         struct intel_encoder base;
1007         enum pipe pipe;
1008         struct intel_digital_port *primary;
1009         struct intel_connector *connector;
1010 };
1011
1012 static inline enum dpio_channel
1013 vlv_dport_to_channel(struct intel_digital_port *dport)
1014 {
1015         switch (dport->port) {
1016         case PORT_B:
1017         case PORT_D:
1018                 return DPIO_CH0;
1019         case PORT_C:
1020                 return DPIO_CH1;
1021         default:
1022                 BUG();
1023         }
1024 }
1025
1026 static inline enum dpio_phy
1027 vlv_dport_to_phy(struct intel_digital_port *dport)
1028 {
1029         switch (dport->port) {
1030         case PORT_B:
1031         case PORT_C:
1032                 return DPIO_PHY0;
1033         case PORT_D:
1034                 return DPIO_PHY1;
1035         default:
1036                 BUG();
1037         }
1038 }
1039
1040 static inline enum dpio_channel
1041 vlv_pipe_to_channel(enum pipe pipe)
1042 {
1043         switch (pipe) {
1044         case PIPE_A:
1045         case PIPE_C:
1046                 return DPIO_CH0;
1047         case PIPE_B:
1048                 return DPIO_CH1;
1049         default:
1050                 BUG();
1051         }
1052 }
1053
1054 static inline struct intel_crtc *
1055 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1056 {
1057         return dev_priv->pipe_to_crtc_mapping[pipe];
1058 }
1059
1060 static inline struct intel_crtc *
1061 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1062 {
1063         return dev_priv->plane_to_crtc_mapping[plane];
1064 }
1065
1066 struct intel_flip_work {
1067         struct work_struct unpin_work;
1068         struct work_struct mmio_work;
1069
1070         struct drm_crtc *crtc;
1071         struct i915_vma *old_vma;
1072         struct drm_framebuffer *old_fb;
1073         struct drm_i915_gem_object *pending_flip_obj;
1074         struct drm_pending_vblank_event *event;
1075         atomic_t pending;
1076         u32 flip_count;
1077         u32 gtt_offset;
1078         struct drm_i915_gem_request *flip_queued_req;
1079         u32 flip_queued_vblank;
1080         u32 flip_ready_vblank;
1081         unsigned int rotation;
1082 };
1083
1084 struct intel_load_detect_pipe {
1085         struct drm_atomic_state *restore_state;
1086 };
1087
1088 static inline struct intel_encoder *
1089 intel_attached_encoder(struct drm_connector *connector)
1090 {
1091         return to_intel_connector(connector)->encoder;
1092 }
1093
1094 static inline struct intel_digital_port *
1095 enc_to_dig_port(struct drm_encoder *encoder)
1096 {
1097         return container_of(encoder, struct intel_digital_port, base.base);
1098 }
1099
1100 static inline struct intel_dp_mst_encoder *
1101 enc_to_mst(struct drm_encoder *encoder)
1102 {
1103         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1104 }
1105
1106 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1107 {
1108         return &enc_to_dig_port(encoder)->dp;
1109 }
1110
1111 static inline struct intel_digital_port *
1112 dp_to_dig_port(struct intel_dp *intel_dp)
1113 {
1114         return container_of(intel_dp, struct intel_digital_port, dp);
1115 }
1116
1117 static inline struct intel_lspcon *
1118 dp_to_lspcon(struct intel_dp *intel_dp)
1119 {
1120         return &dp_to_dig_port(intel_dp)->lspcon;
1121 }
1122
1123 static inline struct intel_digital_port *
1124 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1125 {
1126         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1127 }
1128
1129 /* intel_fifo_underrun.c */
1130 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1131                                            enum pipe pipe, bool enable);
1132 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1133                                            enum transcoder pch_transcoder,
1134                                            bool enable);
1135 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1136                                          enum pipe pipe);
1137 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1138                                          enum transcoder pch_transcoder);
1139 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1140 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1141
1142 /* i915_irq.c */
1143 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1144 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1145 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1146 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1147 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1148 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1149 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1150 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1151 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1152 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1153 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1154 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1155 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1156 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1157 {
1158         /*
1159          * We only use drm_irq_uninstall() at unload and VT switch, so
1160          * this is the only thing we need to check.
1161          */
1162         return dev_priv->pm.irqs_enabled;
1163 }
1164
1165 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1166 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1167                                      unsigned int pipe_mask);
1168 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1169                                      unsigned int pipe_mask);
1170 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1171 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1172 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1173
1174 /* intel_crt.c */
1175 void intel_crt_init(struct drm_i915_private *dev_priv);
1176 void intel_crt_reset(struct drm_encoder *encoder);
1177
1178 /* intel_ddi.c */
1179 void intel_ddi_clk_select(struct intel_encoder *encoder,
1180                           struct intel_shared_dpll *pll);
1181 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1182                                 struct intel_crtc_state *old_crtc_state,
1183                                 struct drm_connector_state *old_conn_state);
1184 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1185 void hsw_fdi_link_train(struct drm_crtc *crtc);
1186 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1187 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1188 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1189 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1190 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1191                                        enum transcoder cpu_transcoder);
1192 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1193 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1194 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1195                           struct intel_crtc_state *crtc_state);
1196 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1197 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1198 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1199 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1200                                  struct intel_crtc *intel_crtc);
1201 void intel_ddi_get_config(struct intel_encoder *encoder,
1202                           struct intel_crtc_state *pipe_config);
1203 struct intel_encoder *
1204 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1205
1206 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1207 void intel_ddi_clock_get(struct intel_encoder *encoder,
1208                          struct intel_crtc_state *pipe_config);
1209 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1210 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1211 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1212                                                   int clock);
1213 unsigned int intel_fb_align_height(struct drm_device *dev,
1214                                    unsigned int height,
1215                                    uint32_t pixel_format,
1216                                    uint64_t fb_format_modifier);
1217 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1218                               uint64_t fb_modifier, uint32_t pixel_format);
1219
1220 /* intel_audio.c */
1221 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1222 void intel_audio_codec_enable(struct intel_encoder *encoder,
1223                               const struct intel_crtc_state *crtc_state,
1224                               const struct drm_connector_state *conn_state);
1225 void intel_audio_codec_disable(struct intel_encoder *encoder);
1226 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1227 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1228
1229 /* intel_display.c */
1230 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1231 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1232 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1233 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1234                       const char *name, u32 reg, int ref_freq);
1235 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1236 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1237 extern const struct drm_plane_funcs intel_plane_funcs;
1238 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1239 unsigned int intel_fb_xy_to_linear(int x, int y,
1240                                    const struct intel_plane_state *state,
1241                                    int plane);
1242 void intel_add_fb_offsets(int *x, int *y,
1243                           const struct intel_plane_state *state, int plane);
1244 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1245 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1246 void intel_mark_busy(struct drm_i915_private *dev_priv);
1247 void intel_mark_idle(struct drm_i915_private *dev_priv);
1248 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1249 int intel_display_suspend(struct drm_device *dev);
1250 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1251 void intel_encoder_destroy(struct drm_encoder *encoder);
1252 int intel_connector_init(struct intel_connector *);
1253 struct intel_connector *intel_connector_alloc(void);
1254 bool intel_connector_get_hw_state(struct intel_connector *connector);
1255 void intel_connector_attach_encoder(struct intel_connector *connector,
1256                                     struct intel_encoder *encoder);
1257 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1258                                              struct drm_crtc *crtc);
1259 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1260 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1261                                 struct drm_file *file_priv);
1262 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1263                                              enum pipe pipe);
1264 static inline bool
1265 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1266                     enum intel_output_type type)
1267 {
1268         return crtc_state->output_types & (1 << type);
1269 }
1270 static inline bool
1271 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1272 {
1273         return crtc_state->output_types &
1274                 ((1 << INTEL_OUTPUT_DP) |
1275                  (1 << INTEL_OUTPUT_DP_MST) |
1276                  (1 << INTEL_OUTPUT_EDP));
1277 }
1278 static inline void
1279 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1280 {
1281         drm_wait_one_vblank(&dev_priv->drm, pipe);
1282 }
1283 static inline void
1284 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1285 {
1286         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1287
1288         if (crtc->active)
1289                 intel_wait_for_vblank(dev_priv, pipe);
1290 }
1291
1292 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1293
1294 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1295 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1296                          struct intel_digital_port *dport,
1297                          unsigned int expected_mask);
1298 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1299                                 struct drm_display_mode *mode,
1300                                 struct intel_load_detect_pipe *old,
1301                                 struct drm_modeset_acquire_ctx *ctx);
1302 void intel_release_load_detect_pipe(struct drm_connector *connector,
1303                                     struct intel_load_detect_pipe *old,
1304                                     struct drm_modeset_acquire_ctx *ctx);
1305 struct i915_vma *
1306 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1307 void intel_unpin_fb_vma(struct i915_vma *vma);
1308 struct drm_framebuffer *
1309 __intel_framebuffer_create(struct drm_device *dev,
1310                            struct drm_mode_fb_cmd2 *mode_cmd,
1311                            struct drm_i915_gem_object *obj);
1312 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1313 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1314 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1315 int intel_prepare_plane_fb(struct drm_plane *plane,
1316                            struct drm_plane_state *new_state);
1317 void intel_cleanup_plane_fb(struct drm_plane *plane,
1318                             struct drm_plane_state *old_state);
1319 int intel_plane_atomic_get_property(struct drm_plane *plane,
1320                                     const struct drm_plane_state *state,
1321                                     struct drm_property *property,
1322                                     uint64_t *val);
1323 int intel_plane_atomic_set_property(struct drm_plane *plane,
1324                                     struct drm_plane_state *state,
1325                                     struct drm_property *property,
1326                                     uint64_t val);
1327 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1328                                     struct drm_plane_state *plane_state);
1329
1330 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1331                                uint64_t fb_modifier, unsigned int cpp);
1332
1333 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1334                                     enum pipe pipe);
1335
1336 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1337                      const struct dpll *dpll);
1338 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1339 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1340
1341 /* modesetting asserts */
1342 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1343                            enum pipe pipe);
1344 void assert_pll(struct drm_i915_private *dev_priv,
1345                 enum pipe pipe, bool state);
1346 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1347 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1348 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1349 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1350 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1351 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1352                        enum pipe pipe, bool state);
1353 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1354 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1355 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1356 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1357 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1358 u32 intel_compute_tile_offset(int *x, int *y,
1359                               const struct intel_plane_state *state, int plane);
1360 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1361 void intel_finish_reset(struct drm_i915_private *dev_priv);
1362 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1363 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1364 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1365 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1366 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1367 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1368 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1369 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1370 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1371 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1372 unsigned int skl_cdclk_get_vco(unsigned int freq);
1373 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1374 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1375 void intel_dp_get_m_n(struct intel_crtc *crtc,
1376                       struct intel_crtc_state *pipe_config);
1377 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1378 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1379 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1380                         struct dpll *best_clock);
1381 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1382
1383 bool intel_crtc_active(struct intel_crtc *crtc);
1384 void hsw_enable_ips(struct intel_crtc *crtc);
1385 void hsw_disable_ips(struct intel_crtc *crtc);
1386 enum intel_display_power_domain
1387 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1388 enum intel_display_power_domain
1389 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1390 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1391                                  struct intel_crtc_state *pipe_config);
1392
1393 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1394 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1395
1396 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1397 {
1398         return i915_ggtt_offset(state->vma);
1399 }
1400
1401 u32 skl_plane_ctl_format(uint32_t pixel_format);
1402 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1403 u32 skl_plane_ctl_rotation(unsigned int rotation);
1404 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1405                      unsigned int rotation);
1406 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1407
1408 /* intel_csr.c */
1409 void intel_csr_ucode_init(struct drm_i915_private *);
1410 void intel_csr_load_program(struct drm_i915_private *);
1411 void intel_csr_ucode_fini(struct drm_i915_private *);
1412 void intel_csr_ucode_suspend(struct drm_i915_private *);
1413 void intel_csr_ucode_resume(struct drm_i915_private *);
1414
1415 /* intel_dp.c */
1416 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1417                    enum port port);
1418 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1419                              struct intel_connector *intel_connector);
1420 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1421                               int link_rate, uint8_t lane_count,
1422                               bool link_mst);
1423 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1424                                             int link_rate, uint8_t lane_count);
1425 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1426 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1427 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1428 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1429 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1430 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1431 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1432 bool intel_dp_compute_config(struct intel_encoder *encoder,
1433                              struct intel_crtc_state *pipe_config,
1434                              struct drm_connector_state *conn_state);
1435 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1436 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1437                                   bool long_hpd);
1438 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1439 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1440 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1441 void intel_edp_panel_on(struct intel_dp *intel_dp);
1442 void intel_edp_panel_off(struct intel_dp *intel_dp);
1443 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1444 void intel_dp_mst_suspend(struct drm_device *dev);
1445 void intel_dp_mst_resume(struct drm_device *dev);
1446 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1447 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1448 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1449 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1450 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1451 void intel_plane_destroy(struct drm_plane *plane);
1452 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1453                            struct intel_crtc_state *crtc_state);
1454 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1455                            struct intel_crtc_state *crtc_state);
1456 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1457                                unsigned int frontbuffer_bits);
1458 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1459                           unsigned int frontbuffer_bits);
1460
1461 void
1462 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1463                                        uint8_t dp_train_pat);
1464 void
1465 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1466 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1467 uint8_t
1468 intel_dp_voltage_max(struct intel_dp *intel_dp);
1469 uint8_t
1470 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1471 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1472                            uint8_t *link_bw, uint8_t *rate_select);
1473 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1474 bool
1475 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1476
1477 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1478 {
1479         return ~((1 << lane_count) - 1) & 0xf;
1480 }
1481
1482 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1483 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1484                           struct intel_dp_desc *desc);
1485 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1486 int intel_dp_link_required(int pixel_clock, int bpp);
1487 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1488
1489 /* intel_dp_aux_backlight.c */
1490 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1491
1492 /* intel_dp_mst.c */
1493 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1494 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1495 /* intel_dsi.c */
1496 void intel_dsi_init(struct drm_i915_private *dev_priv);
1497
1498 /* intel_dsi_dcs_backlight.c */
1499 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1500
1501 /* intel_dvo.c */
1502 void intel_dvo_init(struct drm_i915_private *dev_priv);
1503 /* intel_hotplug.c */
1504 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1505
1506
1507 /* legacy fbdev emulation in intel_fbdev.c */
1508 #ifdef CONFIG_DRM_FBDEV_EMULATION
1509 extern int intel_fbdev_init(struct drm_device *dev);
1510 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1511 extern void intel_fbdev_fini(struct drm_device *dev);
1512 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1513 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1514 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1515 #else
1516 static inline int intel_fbdev_init(struct drm_device *dev)
1517 {
1518         return 0;
1519 }
1520
1521 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1522 {
1523 }
1524
1525 static inline void intel_fbdev_fini(struct drm_device *dev)
1526 {
1527 }
1528
1529 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1530 {
1531 }
1532
1533 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1534 {
1535 }
1536
1537 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1538 {
1539 }
1540 #endif
1541
1542 /* intel_fbc.c */
1543 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1544                            struct drm_atomic_state *state);
1545 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1546 void intel_fbc_pre_update(struct intel_crtc *crtc,
1547                           struct intel_crtc_state *crtc_state,
1548                           struct intel_plane_state *plane_state);
1549 void intel_fbc_post_update(struct intel_crtc *crtc);
1550 void intel_fbc_init(struct drm_i915_private *dev_priv);
1551 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1552 void intel_fbc_enable(struct intel_crtc *crtc,
1553                       struct intel_crtc_state *crtc_state,
1554                       struct intel_plane_state *plane_state);
1555 void intel_fbc_disable(struct intel_crtc *crtc);
1556 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1557 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1558                           unsigned int frontbuffer_bits,
1559                           enum fb_op_origin origin);
1560 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1561                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1562 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1563 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1564
1565 /* intel_hdmi.c */
1566 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1567                      enum port port);
1568 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1569                                struct intel_connector *intel_connector);
1570 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1571 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1572                                struct intel_crtc_state *pipe_config,
1573                                struct drm_connector_state *conn_state);
1574 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1575
1576
1577 /* intel_lvds.c */
1578 void intel_lvds_init(struct drm_i915_private *dev_priv);
1579 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1580 bool intel_is_dual_link_lvds(struct drm_device *dev);
1581
1582
1583 /* intel_modes.c */
1584 int intel_connector_update_modes(struct drm_connector *connector,
1585                                  struct edid *edid);
1586 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1587 void intel_attach_force_audio_property(struct drm_connector *connector);
1588 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1589 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1590
1591
1592 /* intel_overlay.c */
1593 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1594 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1595 int intel_overlay_switch_off(struct intel_overlay *overlay);
1596 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1597                                   struct drm_file *file_priv);
1598 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1599                               struct drm_file *file_priv);
1600 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1601
1602
1603 /* intel_panel.c */
1604 int intel_panel_init(struct intel_panel *panel,
1605                      struct drm_display_mode *fixed_mode,
1606                      struct drm_display_mode *downclock_mode);
1607 void intel_panel_fini(struct intel_panel *panel);
1608 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1609                             struct drm_display_mode *adjusted_mode);
1610 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1611                              struct intel_crtc_state *pipe_config,
1612                              int fitting_mode);
1613 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1614                               struct intel_crtc_state *pipe_config,
1615                               int fitting_mode);
1616 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1617                                     u32 level, u32 max);
1618 int intel_panel_setup_backlight(struct drm_connector *connector,
1619                                 enum pipe pipe);
1620 void intel_panel_enable_backlight(struct intel_connector *connector);
1621 void intel_panel_disable_backlight(struct intel_connector *connector);
1622 void intel_panel_destroy_backlight(struct drm_connector *connector);
1623 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1624 extern struct drm_display_mode *intel_find_panel_downclock(
1625                                 struct drm_i915_private *dev_priv,
1626                                 struct drm_display_mode *fixed_mode,
1627                                 struct drm_connector *connector);
1628
1629 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1630 int intel_backlight_device_register(struct intel_connector *connector);
1631 void intel_backlight_device_unregister(struct intel_connector *connector);
1632 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1633 static int intel_backlight_device_register(struct intel_connector *connector)
1634 {
1635         return 0;
1636 }
1637 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1638 {
1639 }
1640 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1641
1642
1643 /* intel_psr.c */
1644 void intel_psr_enable(struct intel_dp *intel_dp);
1645 void intel_psr_disable(struct intel_dp *intel_dp);
1646 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1647                           unsigned frontbuffer_bits);
1648 void intel_psr_flush(struct drm_i915_private *dev_priv,
1649                      unsigned frontbuffer_bits,
1650                      enum fb_op_origin origin);
1651 void intel_psr_init(struct drm_i915_private *dev_priv);
1652 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1653                                    unsigned frontbuffer_bits);
1654
1655 /* intel_runtime_pm.c */
1656 int intel_power_domains_init(struct drm_i915_private *);
1657 void intel_power_domains_fini(struct drm_i915_private *);
1658 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1659 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1660 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1661 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1662 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1663 const char *
1664 intel_display_power_domain_str(enum intel_display_power_domain domain);
1665
1666 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1667                                     enum intel_display_power_domain domain);
1668 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1669                                       enum intel_display_power_domain domain);
1670 void intel_display_power_get(struct drm_i915_private *dev_priv,
1671                              enum intel_display_power_domain domain);
1672 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1673                                         enum intel_display_power_domain domain);
1674 void intel_display_power_put(struct drm_i915_private *dev_priv,
1675                              enum intel_display_power_domain domain);
1676
1677 static inline void
1678 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1679 {
1680         WARN_ONCE(dev_priv->pm.suspended,
1681                   "Device suspended during HW access\n");
1682 }
1683
1684 static inline void
1685 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1686 {
1687         assert_rpm_device_not_suspended(dev_priv);
1688         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1689          * too much noise. */
1690         if (!atomic_read(&dev_priv->pm.wakeref_count))
1691                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1692 }
1693
1694 /**
1695  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1696  * @dev_priv: i915 device instance
1697  *
1698  * This function disable asserts that check if we hold an RPM wakelock
1699  * reference, while keeping the device-not-suspended checks still enabled.
1700  * It's meant to be used only in special circumstances where our rule about
1701  * the wakelock refcount wrt. the device power state doesn't hold. According
1702  * to this rule at any point where we access the HW or want to keep the HW in
1703  * an active state we must hold an RPM wakelock reference acquired via one of
1704  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1705  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1706  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1707  * users should avoid using this function.
1708  *
1709  * Any calls to this function must have a symmetric call to
1710  * enable_rpm_wakeref_asserts().
1711  */
1712 static inline void
1713 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1714 {
1715         atomic_inc(&dev_priv->pm.wakeref_count);
1716 }
1717
1718 /**
1719  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1720  * @dev_priv: i915 device instance
1721  *
1722  * This function re-enables the RPM assert checks after disabling them with
1723  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1724  * circumstances otherwise its use should be avoided.
1725  *
1726  * Any calls to this function must have a symmetric call to
1727  * disable_rpm_wakeref_asserts().
1728  */
1729 static inline void
1730 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1731 {
1732         atomic_dec(&dev_priv->pm.wakeref_count);
1733 }
1734
1735 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1736 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1737 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1738 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1739
1740 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1741
1742 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1743                              bool override, unsigned int mask);
1744 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1745                           enum dpio_channel ch, bool override);
1746
1747
1748 /* intel_pm.c */
1749 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1750 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1751 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1752 void intel_update_watermarks(struct intel_crtc *crtc);
1753 void intel_init_pm(struct drm_i915_private *dev_priv);
1754 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1755 void intel_pm_setup(struct drm_i915_private *dev_priv);
1756 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1757 void intel_gpu_ips_teardown(void);
1758 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1759 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1760 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1761 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1762 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1763 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1764 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1765 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1766 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1767 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1768 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1769                     struct intel_rps_client *rps,
1770                     unsigned long submitted);
1771 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1772 void vlv_wm_get_hw_state(struct drm_device *dev);
1773 void ilk_wm_get_hw_state(struct drm_device *dev);
1774 void skl_wm_get_hw_state(struct drm_device *dev);
1775 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1776                           struct skl_ddb_allocation *ddb /* out */);
1777 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1778                               struct skl_pipe_wm *out);
1779 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1780 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1781 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1782 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1783                          const struct skl_wm_level *l2);
1784 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1785                                  const struct skl_ddb_entry *ddb,
1786                                  int ignore);
1787 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1788 bool ilk_disable_lp_wm(struct drm_device *dev);
1789 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1790 static inline int intel_enable_rc6(void)
1791 {
1792         return i915.enable_rc6;
1793 }
1794
1795 /* intel_sdvo.c */
1796 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1797                      i915_reg_t reg, enum port port);
1798
1799
1800 /* intel_sprite.c */
1801 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1802                              int usecs);
1803 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1804                                               enum pipe pipe, int plane);
1805 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1806                               struct drm_file *file_priv);
1807 void intel_pipe_update_start(struct intel_crtc *crtc);
1808 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1809
1810 /* intel_tv.c */
1811 void intel_tv_init(struct drm_i915_private *dev_priv);
1812
1813 /* intel_atomic.c */
1814 int intel_connector_atomic_get_property(struct drm_connector *connector,
1815                                         const struct drm_connector_state *state,
1816                                         struct drm_property *property,
1817                                         uint64_t *val);
1818 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1819 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1820                                struct drm_crtc_state *state);
1821 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1822 void intel_atomic_state_clear(struct drm_atomic_state *);
1823
1824 static inline struct intel_crtc_state *
1825 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1826                             struct intel_crtc *crtc)
1827 {
1828         struct drm_crtc_state *crtc_state;
1829         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1830         if (IS_ERR(crtc_state))
1831                 return ERR_CAST(crtc_state);
1832
1833         return to_intel_crtc_state(crtc_state);
1834 }
1835
1836 static inline struct intel_crtc_state *
1837 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1838                                      struct intel_crtc *crtc)
1839 {
1840         struct drm_crtc_state *crtc_state;
1841
1842         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1843
1844         if (crtc_state)
1845                 return to_intel_crtc_state(crtc_state);
1846         else
1847                 return NULL;
1848 }
1849
1850 static inline struct intel_plane_state *
1851 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1852                                       struct intel_plane *plane)
1853 {
1854         struct drm_plane_state *plane_state;
1855
1856         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1857
1858         return to_intel_plane_state(plane_state);
1859 }
1860
1861 int intel_atomic_setup_scalers(struct drm_device *dev,
1862         struct intel_crtc *intel_crtc,
1863         struct intel_crtc_state *crtc_state);
1864
1865 /* intel_atomic_plane.c */
1866 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1867 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1868 void intel_plane_destroy_state(struct drm_plane *plane,
1869                                struct drm_plane_state *state);
1870 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1871 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1872                                         struct intel_plane_state *intel_state);
1873
1874 /* intel_color.c */
1875 void intel_color_init(struct drm_crtc *crtc);
1876 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1877 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1878 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1879
1880 /* intel_lspcon.c */
1881 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1882 void lspcon_resume(struct intel_lspcon *lspcon);
1883 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1884
1885 /* intel_pipe_crc.c */
1886 int intel_pipe_crc_create(struct drm_minor *minor);
1887 void intel_pipe_crc_cleanup(struct drm_minor *minor);
1888 #ifdef CONFIG_DEBUG_FS
1889 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1890                               size_t *values_cnt);
1891 #else
1892 #define intel_crtc_set_crc_source NULL
1893 #endif
1894 extern const struct file_operations i915_display_crc_ctl_fops;
1895 #endif /* __INTEL_DRV_H__ */