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drm/exynos: Stop using drm_framebuffer_unregister_private
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_pipe_crc.c
blobc0b1f99da37b34c914fe180c856bec51dc4c333f
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
24 *
25 */
26
27 #include <linux/seq_file.h>
28 #include <linux/circ_buf.h>
29 #include <linux/ctype.h>
30 #include <linux/debugfs.h>
31 #include "intel_drv.h"
32
33 struct pipe_crc_info {
34 const char *name;
35 struct drm_i915_private *dev_priv;
36 enum pipe pipe;
37 };
38
39 /* As the drm_debugfs_init() routines are called before dev->dev_private is
40 * allocated we need to hook into the minor for release.
41 */
42 static int drm_add_fake_info_node(struct drm_minor *minor,
43 struct dentry *ent, const void *key)
44 {
45 struct drm_info_node *node;
46
47 node = kmalloc(sizeof(*node), GFP_KERNEL);
48 if (node == NULL) {
49 debugfs_remove(ent);
50 return -ENOMEM;
51 }
52
53 node->minor = minor;
54 node->dent = ent;
55 node->info_ent = (void *) key;
56
57 mutex_lock(&minor->debugfs_lock);
58 list_add(&node->list, &minor->debugfs_list);
59 mutex_unlock(&minor->debugfs_lock);
60
61 return 0;
62 }
63
64 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
65 {
66 struct pipe_crc_info *info = inode->i_private;
67 struct drm_i915_private *dev_priv = info->dev_priv;
68 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
69
70 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
71 return -ENODEV;
72
73 spin_lock_irq(&pipe_crc->lock);
74
75 if (pipe_crc->opened) {
76 spin_unlock_irq(&pipe_crc->lock);
77 return -EBUSY; /* already open */
78 }
79
80 pipe_crc->opened = true;
81 filep->private_data = inode->i_private;
82
83 spin_unlock_irq(&pipe_crc->lock);
84
85 return 0;
86 }
87
88 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
89 {
90 struct pipe_crc_info *info = inode->i_private;
91 struct drm_i915_private *dev_priv = info->dev_priv;
92 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
93
94 spin_lock_irq(&pipe_crc->lock);
95 pipe_crc->opened = false;
96 spin_unlock_irq(&pipe_crc->lock);
97
98 return 0;
99 }
100
101 /* (6 fields, 8 chars each, space separated (5) + '\n') */
102 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
103 /* account for \'0' */
104 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
105
106 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
107 {
108 assert_spin_locked(&pipe_crc->lock);
109 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
110 INTEL_PIPE_CRC_ENTRIES_NR);
111 }
112
113 static ssize_t
114 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
115 loff_t *pos)
116 {
117 struct pipe_crc_info *info = filep->private_data;
118 struct drm_i915_private *dev_priv = info->dev_priv;
119 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
120 char buf[PIPE_CRC_BUFFER_LEN];
121 int n_entries;
122 ssize_t bytes_read;
123
124 /*
125 * Don't allow user space to provide buffers not big enough to hold
126 * a line of data.
127 */
128 if (count < PIPE_CRC_LINE_LEN)
129 return -EINVAL;
130
131 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
132 return 0;
133
134 /* nothing to read */
135 spin_lock_irq(&pipe_crc->lock);
136 while (pipe_crc_data_count(pipe_crc) == 0) {
137 int ret;
138
139 if (filep->f_flags & O_NONBLOCK) {
140 spin_unlock_irq(&pipe_crc->lock);
141 return -EAGAIN;
142 }
143
144 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
145 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
146 if (ret) {
147 spin_unlock_irq(&pipe_crc->lock);
148 return ret;
149 }
150 }
151
152 /* We now have one or more entries to read */
153 n_entries = count / PIPE_CRC_LINE_LEN;
154
155 bytes_read = 0;
156 while (n_entries > 0) {
157 struct intel_pipe_crc_entry *entry =
158 &pipe_crc->entries[pipe_crc->tail];
159
160 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
161 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
162 break;
163
164 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
165 pipe_crc->tail = (pipe_crc->tail + 1) &
166 (INTEL_PIPE_CRC_ENTRIES_NR - 1);
167
168 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
169 "%8u %8x %8x %8x %8x %8x\n",
170 entry->frame, entry->crc[0],
171 entry->crc[1], entry->crc[2],
172 entry->crc[3], entry->crc[4]);
173
174 spin_unlock_irq(&pipe_crc->lock);
175
176 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
177 return -EFAULT;
178
179 user_buf += PIPE_CRC_LINE_LEN;
180 n_entries--;
181
182 spin_lock_irq(&pipe_crc->lock);
183 }
184
185 spin_unlock_irq(&pipe_crc->lock);
186
187 return bytes_read;
188 }
189
190 static const struct file_operations i915_pipe_crc_fops = {
191 .owner = THIS_MODULE,
192 .open = i915_pipe_crc_open,
193 .read = i915_pipe_crc_read,
194 .release = i915_pipe_crc_release,
195 };
196
197 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
198 {
199 .name = "i915_pipe_A_crc",
200 .pipe = PIPE_A,
201 },
202 {
203 .name = "i915_pipe_B_crc",
204 .pipe = PIPE_B,
205 },
206 {
207 .name = "i915_pipe_C_crc",
208 .pipe = PIPE_C,
209 },
210 };
211
212 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
213 enum pipe pipe)
214 {
215 struct drm_i915_private *dev_priv = to_i915(minor->dev);
216 struct dentry *ent;
217 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
218
219 info->dev_priv = dev_priv;
220 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
221 &i915_pipe_crc_fops);
222 if (!ent)
223 return -ENOMEM;
224
225 return drm_add_fake_info_node(minor, ent, info);
226 }
227
228 static const char * const pipe_crc_sources[] = {
229 "none",
230 "plane1",
231 "plane2",
232 "pf",
233 "pipe",
234 "TV",
235 "DP-B",
236 "DP-C",
237 "DP-D",
238 "auto",
239 };
240
241 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
242 {
243 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
244 return pipe_crc_sources[source];
245 }
246
247 static int display_crc_ctl_show(struct seq_file *m, void *data)
248 {
249 struct drm_i915_private *dev_priv = m->private;
250 int i;
251
252 for (i = 0; i < I915_MAX_PIPES; i++)
253 seq_printf(m, "%c %s\n", pipe_name(i),
254 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
255
256 return 0;
257 }
258
259 static int display_crc_ctl_open(struct inode *inode, struct file *file)
260 {
261 return single_open(file, display_crc_ctl_show, inode->i_private);
262 }
263
264 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
265 uint32_t *val)
266 {
267 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
268 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
269
270 switch (*source) {
271 case INTEL_PIPE_CRC_SOURCE_PIPE:
272 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
273 break;
274 case INTEL_PIPE_CRC_SOURCE_NONE:
275 *val = 0;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 return 0;
282 }
283
284 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
285 enum pipe pipe,
286 enum intel_pipe_crc_source *source)
287 {
288 struct drm_device *dev = &dev_priv->drm;
289 struct intel_encoder *encoder;
290 struct intel_crtc *crtc;
291 struct intel_digital_port *dig_port;
292 int ret = 0;
293
294 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
295
296 drm_modeset_lock_all(dev);
297 for_each_intel_encoder(dev, encoder) {
298 if (!encoder->base.crtc)
299 continue;
300
301 crtc = to_intel_crtc(encoder->base.crtc);
302
303 if (crtc->pipe != pipe)
304 continue;
305
306 switch (encoder->type) {
307 case INTEL_OUTPUT_TVOUT:
308 *source = INTEL_PIPE_CRC_SOURCE_TV;
309 break;
310 case INTEL_OUTPUT_DP:
311 case INTEL_OUTPUT_EDP:
312 dig_port = enc_to_dig_port(&encoder->base);
313 switch (dig_port->port) {
314 case PORT_B:
315 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
316 break;
317 case PORT_C:
318 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
319 break;
320 case PORT_D:
321 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
322 break;
323 default:
324 WARN(1, "nonexisting DP port %c\n",
325 port_name(dig_port->port));
326 break;
327 }
328 break;
329 default:
330 break;
331 }
332 }
333 drm_modeset_unlock_all(dev);
334
335 return ret;
336 }
337
338 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
339 enum pipe pipe,
340 enum intel_pipe_crc_source *source,
341 uint32_t *val)
342 {
343 bool need_stable_symbols = false;
344
345 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
346 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
347 if (ret)
348 return ret;
349 }
350
351 switch (*source) {
352 case INTEL_PIPE_CRC_SOURCE_PIPE:
353 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
354 break;
355 case INTEL_PIPE_CRC_SOURCE_DP_B:
356 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
357 need_stable_symbols = true;
358 break;
359 case INTEL_PIPE_CRC_SOURCE_DP_C:
360 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
361 need_stable_symbols = true;
362 break;
363 case INTEL_PIPE_CRC_SOURCE_DP_D:
364 if (!IS_CHERRYVIEW(dev_priv))
365 return -EINVAL;
366 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
367 need_stable_symbols = true;
368 break;
369 case INTEL_PIPE_CRC_SOURCE_NONE:
370 *val = 0;
371 break;
372 default:
373 return -EINVAL;
374 }
375
376 /*
377 * When the pipe CRC tap point is after the transcoders we need
378 * to tweak symbol-level features to produce a deterministic series of
379 * symbols for a given frame. We need to reset those features only once
380 * a frame (instead of every nth symbol):
381 * - DC-balance: used to ensure a better clock recovery from the data
382 * link (SDVO)
383 * - DisplayPort scrambling: used for EMI reduction
384 */
385 if (need_stable_symbols) {
386 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
387
388 tmp |= DC_BALANCE_RESET_VLV;
389 switch (pipe) {
390 case PIPE_A:
391 tmp |= PIPE_A_SCRAMBLE_RESET;
392 break;
393 case PIPE_B:
394 tmp |= PIPE_B_SCRAMBLE_RESET;
395 break;
396 case PIPE_C:
397 tmp |= PIPE_C_SCRAMBLE_RESET;
398 break;
399 default:
400 return -EINVAL;
401 }
402 I915_WRITE(PORT_DFT2_G4X, tmp);
403 }
404
405 return 0;
406 }
407
408 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
409 enum pipe pipe,
410 enum intel_pipe_crc_source *source,
411 uint32_t *val)
412 {
413 bool need_stable_symbols = false;
414
415 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
416 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
417 if (ret)
418 return ret;
419 }
420
421 switch (*source) {
422 case INTEL_PIPE_CRC_SOURCE_PIPE:
423 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
424 break;
425 case INTEL_PIPE_CRC_SOURCE_TV:
426 if (!SUPPORTS_TV(dev_priv))
427 return -EINVAL;
428 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
429 break;
430 case INTEL_PIPE_CRC_SOURCE_DP_B:
431 if (!IS_G4X(dev_priv))
432 return -EINVAL;
433 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
434 need_stable_symbols = true;
435 break;
436 case INTEL_PIPE_CRC_SOURCE_DP_C:
437 if (!IS_G4X(dev_priv))
438 return -EINVAL;
439 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
440 need_stable_symbols = true;
441 break;
442 case INTEL_PIPE_CRC_SOURCE_DP_D:
443 if (!IS_G4X(dev_priv))
444 return -EINVAL;
445 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
446 need_stable_symbols = true;
447 break;
448 case INTEL_PIPE_CRC_SOURCE_NONE:
449 *val = 0;
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 /*
456 * When the pipe CRC tap point is after the transcoders we need
457 * to tweak symbol-level features to produce a deterministic series of
458 * symbols for a given frame. We need to reset those features only once
459 * a frame (instead of every nth symbol):
460 * - DC-balance: used to ensure a better clock recovery from the data
461 * link (SDVO)
462 * - DisplayPort scrambling: used for EMI reduction
463 */
464 if (need_stable_symbols) {
465 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
466
467 WARN_ON(!IS_G4X(dev_priv));
468
469 I915_WRITE(PORT_DFT_I9XX,
470 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
471
472 if (pipe == PIPE_A)
473 tmp |= PIPE_A_SCRAMBLE_RESET;
474 else
475 tmp |= PIPE_B_SCRAMBLE_RESET;
476
477 I915_WRITE(PORT_DFT2_G4X, tmp);
478 }
479
480 return 0;
481 }
482
483 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
484 enum pipe pipe)
485 {
486 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
487
488 switch (pipe) {
489 case PIPE_A:
490 tmp &= ~PIPE_A_SCRAMBLE_RESET;
491 break;
492 case PIPE_B:
493 tmp &= ~PIPE_B_SCRAMBLE_RESET;
494 break;
495 case PIPE_C:
496 tmp &= ~PIPE_C_SCRAMBLE_RESET;
497 break;
498 default:
499 return;
500 }
501 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
502 tmp &= ~DC_BALANCE_RESET_VLV;
503 I915_WRITE(PORT_DFT2_G4X, tmp);
504
505 }
506
507 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
508 enum pipe pipe)
509 {
510 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
511
512 if (pipe == PIPE_A)
513 tmp &= ~PIPE_A_SCRAMBLE_RESET;
514 else
515 tmp &= ~PIPE_B_SCRAMBLE_RESET;
516 I915_WRITE(PORT_DFT2_G4X, tmp);
517
518 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
519 I915_WRITE(PORT_DFT_I9XX,
520 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
521 }
522 }
523
524 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
525 uint32_t *val)
526 {
527 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
528 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
529
530 switch (*source) {
531 case INTEL_PIPE_CRC_SOURCE_PLANE1:
532 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
533 break;
534 case INTEL_PIPE_CRC_SOURCE_PLANE2:
535 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
536 break;
537 case INTEL_PIPE_CRC_SOURCE_PIPE:
538 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
539 break;
540 case INTEL_PIPE_CRC_SOURCE_NONE:
541 *val = 0;
542 break;
543 default:
544 return -EINVAL;
545 }
546
547 return 0;
548 }
549
550 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
551 bool enable)
552 {
553 struct drm_device *dev = &dev_priv->drm;
554 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
555 struct intel_crtc_state *pipe_config;
556 struct drm_atomic_state *state;
557 int ret = 0;
558
559 drm_modeset_lock_all(dev);
560 state = drm_atomic_state_alloc(dev);
561 if (!state) {
562 ret = -ENOMEM;
563 goto unlock;
564 }
565
566 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
567 pipe_config = intel_atomic_get_crtc_state(state, crtc);
568 if (IS_ERR(pipe_config)) {
569 ret = PTR_ERR(pipe_config);
570 goto put_state;
571 }
572
573 pipe_config->pch_pfit.force_thru = enable;
574 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
575 pipe_config->pch_pfit.enabled != enable)
576 pipe_config->base.connectors_changed = true;
577
578 ret = drm_atomic_commit(state);
579
580 put_state:
581 drm_atomic_state_put(state);
582 unlock:
583 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
584 drm_modeset_unlock_all(dev);
585 }
586
587 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
588 enum pipe pipe,
589 enum intel_pipe_crc_source *source,
590 uint32_t *val)
591 {
592 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
593 *source = INTEL_PIPE_CRC_SOURCE_PF;
594
595 switch (*source) {
596 case INTEL_PIPE_CRC_SOURCE_PLANE1:
597 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
598 break;
599 case INTEL_PIPE_CRC_SOURCE_PLANE2:
600 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
601 break;
602 case INTEL_PIPE_CRC_SOURCE_PF:
603 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
604 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
605
606 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
607 break;
608 case INTEL_PIPE_CRC_SOURCE_NONE:
609 *val = 0;
610 break;
611 default:
612 return -EINVAL;
613 }
614
615 return 0;
616 }
617
618 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
619 enum pipe pipe,
620 enum intel_pipe_crc_source *source, u32 *val)
621 {
622 if (IS_GEN2(dev_priv))
623 return i8xx_pipe_crc_ctl_reg(source, val);
624 else if (INTEL_GEN(dev_priv) < 5)
625 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
626 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
627 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
628 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
629 return ilk_pipe_crc_ctl_reg(source, val);
630 else
631 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
632 }
633
634 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
635 enum pipe pipe,
636 enum intel_pipe_crc_source source)
637 {
638 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
639 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
640 enum intel_display_power_domain power_domain;
641 u32 val = 0; /* shut up gcc */
642 int ret;
643
644 if (pipe_crc->source == source)
645 return 0;
646
647 /* forbid changing the source without going back to 'none' */
648 if (pipe_crc->source && source)
649 return -EINVAL;
650
651 power_domain = POWER_DOMAIN_PIPE(pipe);
652 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
653 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
654 return -EIO;
655 }
656
657 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
658 if (ret != 0)
659 goto out;
660
661 /* none -> real source transition */
662 if (source) {
663 struct intel_pipe_crc_entry *entries;
664
665 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
666 pipe_name(pipe), pipe_crc_source_name(source));
667
668 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
669 sizeof(pipe_crc->entries[0]),
670 GFP_KERNEL);
671 if (!entries) {
672 ret = -ENOMEM;
673 goto out;
674 }
675
676 /*
677 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
678 * enabled and disabled dynamically based on package C states,
679 * user space can't make reliable use of the CRCs, so let's just
680 * completely disable it.
681 */
682 hsw_disable_ips(crtc);
683
684 spin_lock_irq(&pipe_crc->lock);
685 kfree(pipe_crc->entries);
686 pipe_crc->entries = entries;
687 pipe_crc->head = 0;
688 pipe_crc->tail = 0;
689 spin_unlock_irq(&pipe_crc->lock);
690 }
691
692 pipe_crc->source = source;
693
694 I915_WRITE(PIPE_CRC_CTL(pipe), val);
695 POSTING_READ(PIPE_CRC_CTL(pipe));
696
697 /* real source -> none transition */
698 if (!source) {
699 struct intel_pipe_crc_entry *entries;
700 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
701 pipe);
702
703 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
704 pipe_name(pipe));
705
706 drm_modeset_lock(&crtc->base.mutex, NULL);
707 if (crtc->base.state->active)
708 intel_wait_for_vblank(dev_priv, pipe);
709 drm_modeset_unlock(&crtc->base.mutex);
710
711 spin_lock_irq(&pipe_crc->lock);
712 entries = pipe_crc->entries;
713 pipe_crc->entries = NULL;
714 pipe_crc->head = 0;
715 pipe_crc->tail = 0;
716 spin_unlock_irq(&pipe_crc->lock);
717
718 kfree(entries);
719
720 if (IS_G4X(dev_priv))
721 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
722 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
723 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
724 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
725 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
726
727 hsw_enable_ips(crtc);
728 }
729
730 ret = 0;
731
732 out:
733 intel_display_power_put(dev_priv, power_domain);
734
735 return ret;
736 }
737
738 /*
739 * Parse pipe CRC command strings:
740 * command: wsp* object wsp+ name wsp+ source wsp*
741 * object: 'pipe'
742 * name: (A | B | C)
743 * source: (none | plane1 | plane2 | pf)
744 * wsp: (#0x20 | #0x9 | #0xA)+
745 *
746 * eg.:
747 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
748 * "pipe A none" -> Stop CRC
749 */
750 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
751 {
752 int n_words = 0;
753
754 while (*buf) {
755 char *end;
756
757 /* skip leading white space */
758 buf = skip_spaces(buf);
759 if (!*buf)
760 break; /* end of buffer */
761
762 /* find end of word */
763 for (end = buf; *end && !isspace(*end); end++)
764 ;
765
766 if (n_words == max_words) {
767 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
768 max_words);
769 return -EINVAL; /* ran out of words[] before bytes */
770 }
771
772 if (*end)
773 *end++ = '\0';
774 words[n_words++] = buf;
775 buf = end;
776 }
777
778 return n_words;
779 }
780
781 enum intel_pipe_crc_object {
782 PIPE_CRC_OBJECT_PIPE,
783 };
784
785 static const char * const pipe_crc_objects[] = {
786 "pipe",
787 };
788
789 static int
790 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
791 {
792 int i;
793
794 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
795 if (!strcmp(buf, pipe_crc_objects[i])) {
796 *o = i;
797 return 0;
798 }
799
800 return -EINVAL;
801 }
802
803 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
804 {
805 const char name = buf[0];
806
807 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
808 return -EINVAL;
809
810 *pipe = name - 'A';
811
812 return 0;
813 }
814
815 static int
816 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
817 {
818 int i;
819
820 if (!buf) {
821 *s = INTEL_PIPE_CRC_SOURCE_NONE;
822 return 0;
823 }
824
825 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
826 if (!strcmp(buf, pipe_crc_sources[i])) {
827 *s = i;
828 return 0;
829 }
830
831 return -EINVAL;
832 }
833
834 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
835 char *buf, size_t len)
836 {
837 #define N_WORDS 3
838 int n_words;
839 char *words[N_WORDS];
840 enum pipe pipe;
841 enum intel_pipe_crc_object object;
842 enum intel_pipe_crc_source source;
843
844 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
845 if (n_words != N_WORDS) {
846 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
847 N_WORDS);
848 return -EINVAL;
849 }
850
851 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
852 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
853 return -EINVAL;
854 }
855
856 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
857 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
858 return -EINVAL;
859 }
860
861 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
862 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
863 return -EINVAL;
864 }
865
866 return pipe_crc_set_source(dev_priv, pipe, source);
867 }
868
869 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
870 size_t len, loff_t *offp)
871 {
872 struct seq_file *m = file->private_data;
873 struct drm_i915_private *dev_priv = m->private;
874 char *tmpbuf;
875 int ret;
876
877 if (len == 0)
878 return 0;
879
880 if (len > PAGE_SIZE - 1) {
881 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
882 PAGE_SIZE);
883 return -E2BIG;
884 }
885
886 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
887 if (!tmpbuf)
888 return -ENOMEM;
889
890 if (copy_from_user(tmpbuf, ubuf, len)) {
891 ret = -EFAULT;
892 goto out;
893 }
894 tmpbuf[len] = '\0';
895
896 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
897
898 out:
899 kfree(tmpbuf);
900 if (ret < 0)
901 return ret;
902
903 *offp += len;
904 return len;
905 }
906
907 const struct file_operations i915_display_crc_ctl_fops = {
908 .owner = THIS_MODULE,
909 .open = display_crc_ctl_open,
910 .read = seq_read,
911 .llseek = seq_lseek,
912 .release = single_release,
913 .write = display_crc_ctl_write
914 };
915
916 void intel_display_crc_init(struct drm_i915_private *dev_priv)
917 {
918 enum pipe pipe;
919
920 for_each_pipe(dev_priv, pipe) {
921 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
922
923 pipe_crc->opened = false;
924 spin_lock_init(&pipe_crc->lock);
925 init_waitqueue_head(&pipe_crc->wq);
926 }
927 }
928
929 int intel_pipe_crc_create(struct drm_minor *minor)
930 {
931 int ret, i;
932
933 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
934 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
935 if (ret)
936 return ret;
937 }
938
939 return 0;
940 }
941
942 void intel_pipe_crc_cleanup(struct drm_minor *minor)
943 {
944 int i;
945
946 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
947 struct drm_info_list *info_list =
948 (struct drm_info_list *)&i915_pipe_crc_data[i];
949
950 drm_debugfs_remove_files(info_list, 1, minor);
951 }
952 }
953
954 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
955 size_t *values_cnt)
956 {
957 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
958 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
960 enum intel_display_power_domain power_domain;
961 enum intel_pipe_crc_source source;
962 u32 val = 0; /* shut up gcc */
963 int ret = 0;
964
965 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
966 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
967 return -EINVAL;
968 }
969
970 power_domain = POWER_DOMAIN_PIPE(crtc->index);
971 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
972 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
973 return -EIO;
974 }
975
976 ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
977 if (ret != 0)
978 goto out;
979
980 if (source) {
981 /*
982 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
983 * enabled and disabled dynamically based on package C states,
984 * user space can't make reliable use of the CRCs, so let's just
985 * completely disable it.
986 */
987 hsw_disable_ips(intel_crtc);
988 }
989
990 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
991 POSTING_READ(PIPE_CRC_CTL(crtc->index));
992
993 if (!source) {
994 if (IS_G4X(dev_priv))
995 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
996 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
997 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
998 else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A)
999 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
1000
1001 hsw_enable_ips(intel_crtc);
1002 }
1003
1004 pipe_crc->skipped = 0;
1005 *values_cnt = 5;
1006
1007 out:
1008 intel_display_power_put(dev_priv, power_domain);
1009
1010 return ret;
1011 }
Linux with added FPC-III support