drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #endif /* CONFIG_PPC_PMAC */
  38
  39 /* from radeon_legacy_encoder.c */
  40 extern void
  41 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  42                           uint32_t supported_device);
  43
  44 /* old legacy ATI BIOS routines */
  45
  46 /* COMBIOS table offsets */
  47 enum radeon_combios_table_offset {
  48         /* absolute offset tables */
  49         COMBIOS_ASIC_INIT_1_TABLE,
  50         COMBIOS_BIOS_SUPPORT_TABLE,
  51         COMBIOS_DAC_PROGRAMMING_TABLE,
  52         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  53         COMBIOS_CRTC_INFO_TABLE,
  54         COMBIOS_PLL_INFO_TABLE,
  55         COMBIOS_TV_INFO_TABLE,
  56         COMBIOS_DFP_INFO_TABLE,
  57         COMBIOS_HW_CONFIG_INFO_TABLE,
  58         COMBIOS_MULTIMEDIA_INFO_TABLE,
  59         COMBIOS_TV_STD_PATCH_TABLE,
  60         COMBIOS_LCD_INFO_TABLE,
  61         COMBIOS_MOBILE_INFO_TABLE,
  62         COMBIOS_PLL_INIT_TABLE,
  63         COMBIOS_MEM_CONFIG_TABLE,
  64         COMBIOS_SAVE_MASK_TABLE,
  65         COMBIOS_HARDCODED_EDID_TABLE,
  66         COMBIOS_ASIC_INIT_2_TABLE,
  67         COMBIOS_CONNECTOR_INFO_TABLE,
  68         COMBIOS_DYN_CLK_1_TABLE,
  69         COMBIOS_RESERVED_MEM_TABLE,
  70         COMBIOS_EXT_TMDS_INFO_TABLE,
  71         COMBIOS_MEM_CLK_INFO_TABLE,
  72         COMBIOS_EXT_DAC_INFO_TABLE,
  73         COMBIOS_MISC_INFO_TABLE,
  74         COMBIOS_CRT_INFO_TABLE,
  75         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  76         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  77         COMBIOS_FAN_SPEED_INFO_TABLE,
  78         COMBIOS_OVERDRIVE_INFO_TABLE,
  79         COMBIOS_OEM_INFO_TABLE,
  80         COMBIOS_DYN_CLK_2_TABLE,
  81         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  82         COMBIOS_I2C_INFO_TABLE,
  83         /* relative offset tables */
  84         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  85         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  86         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
  87         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  88         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  89         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
  90         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  91         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  92         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  93         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  94         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  95 };
  96
  97 enum radeon_combios_ddc {
  98         DDC_NONE_DETECTED,
  99         DDC_MONID,
 100         DDC_DVI,
 101         DDC_VGA,
 102         DDC_CRT2,
 103         DDC_LCD,
 104         DDC_GPIO,
 105 };
 106
 107 enum radeon_combios_connector {
 108         CONNECTOR_NONE_LEGACY,
 109         CONNECTOR_PROPRIETARY_LEGACY,
 110         CONNECTOR_CRT_LEGACY,
 111         CONNECTOR_DVI_I_LEGACY,
 112         CONNECTOR_DVI_D_LEGACY,
 113         CONNECTOR_CTV_LEGACY,
 114         CONNECTOR_STV_LEGACY,
 115         CONNECTOR_UNSUPPORTED_LEGACY
 116 };
 117
 118 static const int legacy_connector_convert[] = {
 119         DRM_MODE_CONNECTOR_Unknown,
 120         DRM_MODE_CONNECTOR_DVID,
 121         DRM_MODE_CONNECTOR_VGA,
 122         DRM_MODE_CONNECTOR_DVII,
 123         DRM_MODE_CONNECTOR_DVID,
 124         DRM_MODE_CONNECTOR_Composite,
 125         DRM_MODE_CONNECTOR_SVIDEO,
 126         DRM_MODE_CONNECTOR_Unknown,
 127 };
 128
 129 static uint16_t combios_get_table_offset(struct drm_device *dev,
 130                                          enum radeon_combios_table_offset table)
 131 {
 132         struct radeon_device *rdev = dev->dev_private;
 133         int rev, size;
 134         uint16_t offset = 0, check_offset;
 135
 136         if (!rdev->bios)
 137                 return 0;
 138
 139         switch (table) {
 140                 /* absolute offset tables */
 141         case COMBIOS_ASIC_INIT_1_TABLE:
 142                 check_offset = 0xc;
 143                 break;
 144         case COMBIOS_BIOS_SUPPORT_TABLE:
 145                 check_offset = 0x14;
 146                 break;
 147         case COMBIOS_DAC_PROGRAMMING_TABLE:
 148                 check_offset = 0x2a;
 149                 break;
 150         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 151                 check_offset = 0x2c;
 152                 break;
 153         case COMBIOS_CRTC_INFO_TABLE:
 154                 check_offset = 0x2e;
 155                 break;
 156         case COMBIOS_PLL_INFO_TABLE:
 157                 check_offset = 0x30;
 158                 break;
 159         case COMBIOS_TV_INFO_TABLE:
 160                 check_offset = 0x32;
 161                 break;
 162         case COMBIOS_DFP_INFO_TABLE:
 163                 check_offset = 0x34;
 164                 break;
 165         case COMBIOS_HW_CONFIG_INFO_TABLE:
 166                 check_offset = 0x36;
 167                 break;
 168         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 169                 check_offset = 0x38;
 170                 break;
 171         case COMBIOS_TV_STD_PATCH_TABLE:
 172                 check_offset = 0x3e;
 173                 break;
 174         case COMBIOS_LCD_INFO_TABLE:
 175                 check_offset = 0x40;
 176                 break;
 177         case COMBIOS_MOBILE_INFO_TABLE:
 178                 check_offset = 0x42;
 179                 break;
 180         case COMBIOS_PLL_INIT_TABLE:
 181                 check_offset = 0x46;
 182                 break;
 183         case COMBIOS_MEM_CONFIG_TABLE:
 184                 check_offset = 0x48;
 185                 break;
 186         case COMBIOS_SAVE_MASK_TABLE:
 187                 check_offset = 0x4a;
 188                 break;
 189         case COMBIOS_HARDCODED_EDID_TABLE:
 190                 check_offset = 0x4c;
 191                 break;
 192         case COMBIOS_ASIC_INIT_2_TABLE:
 193                 check_offset = 0x4e;
 194                 break;
 195         case COMBIOS_CONNECTOR_INFO_TABLE:
 196                 check_offset = 0x50;
 197                 break;
 198         case COMBIOS_DYN_CLK_1_TABLE:
 199                 check_offset = 0x52;
 200                 break;
 201         case COMBIOS_RESERVED_MEM_TABLE:
 202                 check_offset = 0x54;
 203                 break;
 204         case COMBIOS_EXT_TMDS_INFO_TABLE:
 205                 check_offset = 0x58;
 206                 break;
 207         case COMBIOS_MEM_CLK_INFO_TABLE:
 208                 check_offset = 0x5a;
 209                 break;
 210         case COMBIOS_EXT_DAC_INFO_TABLE:
 211                 check_offset = 0x5c;
 212                 break;
 213         case COMBIOS_MISC_INFO_TABLE:
 214                 check_offset = 0x5e;
 215                 break;
 216         case COMBIOS_CRT_INFO_TABLE:
 217                 check_offset = 0x60;
 218                 break;
 219         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 220                 check_offset = 0x62;
 221                 break;
 222         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 223                 check_offset = 0x64;
 224                 break;
 225         case COMBIOS_FAN_SPEED_INFO_TABLE:
 226                 check_offset = 0x66;
 227                 break;
 228         case COMBIOS_OVERDRIVE_INFO_TABLE:
 229                 check_offset = 0x68;
 230                 break;
 231         case COMBIOS_OEM_INFO_TABLE:
 232                 check_offset = 0x6a;
 233                 break;
 234         case COMBIOS_DYN_CLK_2_TABLE:
 235                 check_offset = 0x6c;
 236                 break;
 237         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 238                 check_offset = 0x6e;
 239                 break;
 240         case COMBIOS_I2C_INFO_TABLE:
 241                 check_offset = 0x70;
 242                 break;
 243                 /* relative offset tables */
 244         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 245                 check_offset =
 246                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 247                 if (check_offset) {
 248                         rev = RBIOS8(check_offset);
 249                         if (rev > 0) {
 250                                 check_offset = RBIOS16(check_offset + 0x3);
 251                                 if (check_offset)
 252                                         offset = check_offset;
 253                         }
 254                 }
 255                 break;
 256         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 257                 check_offset =
 258                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 259                 if (check_offset) {
 260                         rev = RBIOS8(check_offset);
 261                         if (rev > 0) {
 262                                 check_offset = RBIOS16(check_offset + 0x5);
 263                                 if (check_offset)
 264                                         offset = check_offset;
 265                         }
 266                 }
 267                 break;
 268         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 269                 check_offset =
 270                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 271                 if (check_offset) {
 272                         rev = RBIOS8(check_offset);
 273                         if (rev > 0) {
 274                                 check_offset = RBIOS16(check_offset + 0x7);
 275                                 if (check_offset)
 276                                         offset = check_offset;
 277                         }
 278                 }
 279                 break;
 280         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 281                 check_offset =
 282                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 283                 if (check_offset) {
 284                         rev = RBIOS8(check_offset);
 285                         if (rev == 2) {
 286                                 check_offset = RBIOS16(check_offset + 0x9);
 287                                 if (check_offset)
 288                                         offset = check_offset;
 289                         }
 290                 }
 291                 break;
 292         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 293                 check_offset =
 294                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 295                 if (check_offset) {
 296                         while (RBIOS8(check_offset++));
 297                         check_offset += 2;
 298                         if (check_offset)
 299                                 offset = check_offset;
 300                 }
 301                 break;
 302         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 303                 check_offset =
 304                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 305                 if (check_offset) {
 306                         check_offset = RBIOS16(check_offset + 0x11);
 307                         if (check_offset)
 308                                 offset = check_offset;
 309                 }
 310                 break;
 311         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 312                 check_offset =
 313                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 314                 if (check_offset) {
 315                         check_offset = RBIOS16(check_offset + 0x13);
 316                         if (check_offset)
 317                                 offset = check_offset;
 318                 }
 319                 break;
 320         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 321                 check_offset =
 322                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 323                 if (check_offset) {
 324                         check_offset = RBIOS16(check_offset + 0x15);
 325                         if (check_offset)
 326                                 offset = check_offset;
 327                 }
 328                 break;
 329         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 332                 if (check_offset) {
 333                         check_offset = RBIOS16(check_offset + 0x17);
 334                         if (check_offset)
 335                                 offset = check_offset;
 336                 }
 337                 break;
 338         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 339                 check_offset =
 340                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 341                 if (check_offset) {
 342                         check_offset = RBIOS16(check_offset + 0x2);
 343                         if (check_offset)
 344                                 offset = check_offset;
 345                 }
 346                 break;
 347         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 348                 check_offset =
 349                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 350                 if (check_offset) {
 351                         check_offset = RBIOS16(check_offset + 0x4);
 352                         if (check_offset)
 353                                 offset = check_offset;
 354                 }
 355                 break;
 356         default:
 357                 check_offset = 0;
 358                 break;
 359         }
 360
 361         size = RBIOS8(rdev->bios_header_start + 0x6);
 362         /* check absolute offset tables */
 363         if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
 364                 offset = RBIOS16(rdev->bios_header_start + check_offset);
 365
 366         return offset;
 367 }
 368
 369 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 370 {
 371         int edid_info, size;
 372         struct edid *edid;
 373         unsigned char *raw;
 374         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 375         if (!edid_info)
 376                 return false;
 377
 378         raw = rdev->bios + edid_info;
 379         size = EDID_LENGTH * (raw[0x7e] + 1);
 380         edid = kmalloc(size, GFP_KERNEL);
 381         if (edid == NULL)
 382                 return false;
 383
 384         memcpy((unsigned char *)edid, raw, size);
 385
 386         if (!drm_edid_is_valid(edid)) {
 387                 kfree(edid);
 388                 return false;
 389         }
 390
 391         rdev->mode_info.bios_hardcoded_edid = edid;
 392         rdev->mode_info.bios_hardcoded_edid_size = size;
 393         return true;
 394 }
 395
 396 /* this is used for atom LCDs as well */
 397 struct edid *
 398 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 399 {
 400         struct edid *edid;
 401
 402         if (rdev->mode_info.bios_hardcoded_edid) {
 403                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 404                 if (edid) {
 405                         memcpy((unsigned char *)edid,
 406                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 407                                rdev->mode_info.bios_hardcoded_edid_size);
 408                         return edid;
 409                 }
 410         }
 411         return NULL;
 412 }
 413
 414 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 415                                                        enum radeon_combios_ddc ddc,
 416                                                        u32 clk_mask,
 417                                                        u32 data_mask)
 418 {
 419         struct radeon_i2c_bus_rec i2c;
 420         int ddc_line = 0;
 421
 422         /* ddc id            = mask reg
 423          * DDC_NONE_DETECTED = none
 424          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 425          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 426          * DDC_LCD           = RADEON_GPIOPAD_MASK
 427          * DDC_GPIO          = RADEON_MDGPIO_MASK
 428          * r1xx
 429          * DDC_MONID         = RADEON_GPIO_MONID
 430          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 431          * r200
 432          * DDC_MONID         = RADEON_GPIO_MONID
 433          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 434          * r300/r350
 435          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 436          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 437          * rv2xx/rv3xx
 438          * DDC_MONID         = RADEON_GPIO_MONID
 439          * DDC_CRT2          = RADEON_GPIO_MONID
 440          * rs3xx/rs4xx
 441          * DDC_MONID         = RADEON_GPIOPAD_MASK
 442          * DDC_CRT2          = RADEON_GPIO_MONID
 443          */
 444         switch (ddc) {
 445         case DDC_NONE_DETECTED:
 446         default:
 447                 ddc_line = 0;
 448                 break;
 449         case DDC_DVI:
 450                 ddc_line = RADEON_GPIO_DVI_DDC;
 451                 break;
 452         case DDC_VGA:
 453                 ddc_line = RADEON_GPIO_VGA_DDC;
 454                 break;
 455         case DDC_LCD:
 456                 ddc_line = RADEON_GPIOPAD_MASK;
 457                 break;
 458         case DDC_GPIO:
 459                 ddc_line = RADEON_MDGPIO_MASK;
 460                 break;
 461         case DDC_MONID:
 462                 if (rdev->family == CHIP_RS300 ||
 463                     rdev->family == CHIP_RS400 ||
 464                     rdev->family == CHIP_RS480)
 465                         ddc_line = RADEON_GPIOPAD_MASK;
 466                 else if (rdev->family == CHIP_R300 ||
 467                          rdev->family == CHIP_R350) {
 468                         ddc_line = RADEON_GPIO_DVI_DDC;
 469                         ddc = DDC_DVI;
 470                 } else
 471                         ddc_line = RADEON_GPIO_MONID;
 472                 break;
 473         case DDC_CRT2:
 474                 if (rdev->family == CHIP_R200 ||
 475                     rdev->family == CHIP_R300 ||
 476                     rdev->family == CHIP_R350) {
 477                         ddc_line = RADEON_GPIO_DVI_DDC;
 478                         ddc = DDC_DVI;
 479                 } else if (rdev->family == CHIP_RS300 ||
 480                            rdev->family == CHIP_RS400 ||
 481                            rdev->family == CHIP_RS480)
 482                         ddc_line = RADEON_GPIO_MONID;
 483                 else if (rdev->family >= CHIP_RV350) {
 484                         ddc_line = RADEON_GPIO_MONID;
 485                         ddc = DDC_MONID;
 486                 } else
 487                         ddc_line = RADEON_GPIO_CRT2_DDC;
 488                 break;
 489         }
 490
 491         if (ddc_line == RADEON_GPIOPAD_MASK) {
 492                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 493                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 494                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 495                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 496                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 497                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 498                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 499                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 500         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 501                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 502                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 503                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 504                 i2c.a_data_reg = RADEON_MDGPIO_A;
 505                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 506                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 507                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 508                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 509         } else {
 510                 i2c.mask_clk_reg = ddc_line;
 511                 i2c.mask_data_reg = ddc_line;
 512                 i2c.a_clk_reg = ddc_line;
 513                 i2c.a_data_reg = ddc_line;
 514                 i2c.en_clk_reg = ddc_line;
 515                 i2c.en_data_reg = ddc_line;
 516                 i2c.y_clk_reg = ddc_line;
 517                 i2c.y_data_reg = ddc_line;
 518         }
 519
 520         if (clk_mask && data_mask) {
 521                 /* system specific masks */
 522                 i2c.mask_clk_mask = clk_mask;
 523                 i2c.mask_data_mask = data_mask;
 524                 i2c.a_clk_mask = clk_mask;
 525                 i2c.a_data_mask = data_mask;
 526                 i2c.en_clk_mask = clk_mask;
 527                 i2c.en_data_mask = data_mask;
 528                 i2c.y_clk_mask = clk_mask;
 529                 i2c.y_data_mask = data_mask;
 530         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 531                    (ddc_line == RADEON_MDGPIO_MASK)) {
 532                 /* default gpiopad masks */
 533                 i2c.mask_clk_mask = (0x20 << 8);
 534                 i2c.mask_data_mask = 0x80;
 535                 i2c.a_clk_mask = (0x20 << 8);
 536                 i2c.a_data_mask = 0x80;
 537                 i2c.en_clk_mask = (0x20 << 8);
 538                 i2c.en_data_mask = 0x80;
 539                 i2c.y_clk_mask = (0x20 << 8);
 540                 i2c.y_data_mask = 0x80;
 541         } else {
 542                 /* default masks for ddc pads */
 543                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 544                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 545                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 546                 i2c.a_data_mask = RADEON_GPIO_A_0;
 547                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 548                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 549                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 550                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 551         }
 552
 553         switch (rdev->family) {
 554         case CHIP_R100:
 555         case CHIP_RV100:
 556         case CHIP_RS100:
 557         case CHIP_RV200:
 558         case CHIP_RS200:
 559         case CHIP_RS300:
 560                 switch (ddc_line) {
 561                 case RADEON_GPIO_DVI_DDC:
 562                         i2c.hw_capable = true;
 563                         break;
 564                 default:
 565                         i2c.hw_capable = false;
 566                         break;
 567                 }
 568                 break;
 569         case CHIP_R200:
 570                 switch (ddc_line) {
 571                 case RADEON_GPIO_DVI_DDC:
 572                 case RADEON_GPIO_MONID:
 573                         i2c.hw_capable = true;
 574                         break;
 575                 default:
 576                         i2c.hw_capable = false;
 577                         break;
 578                 }
 579                 break;
 580         case CHIP_RV250:
 581         case CHIP_RV280:
 582                 switch (ddc_line) {
 583                 case RADEON_GPIO_VGA_DDC:
 584                 case RADEON_GPIO_DVI_DDC:
 585                 case RADEON_GPIO_CRT2_DDC:
 586                         i2c.hw_capable = true;
 587                         break;
 588                 default:
 589                         i2c.hw_capable = false;
 590                         break;
 591                 }
 592                 break;
 593         case CHIP_R300:
 594         case CHIP_R350:
 595                 switch (ddc_line) {
 596                 case RADEON_GPIO_VGA_DDC:
 597                 case RADEON_GPIO_DVI_DDC:
 598                         i2c.hw_capable = true;
 599                         break;
 600                 default:
 601                         i2c.hw_capable = false;
 602                         break;
 603                 }
 604                 break;
 605         case CHIP_RV350:
 606         case CHIP_RV380:
 607         case CHIP_RS400:
 608         case CHIP_RS480:
 609                 switch (ddc_line) {
 610                 case RADEON_GPIO_VGA_DDC:
 611                 case RADEON_GPIO_DVI_DDC:
 612                         i2c.hw_capable = true;
 613                         break;
 614                 case RADEON_GPIO_MONID:
 615                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 616                          * reliably on some pre-r4xx hardware; not sure why.
 617                          */
 618                         i2c.hw_capable = false;
 619                         break;
 620                 default:
 621                         i2c.hw_capable = false;
 622                         break;
 623                 }
 624                 break;
 625         default:
 626                 i2c.hw_capable = false;
 627                 break;
 628         }
 629         i2c.mm_i2c = false;
 630
 631         i2c.i2c_id = ddc;
 632         i2c.hpd = RADEON_HPD_NONE;
 633
 634         if (ddc_line)
 635                 i2c.valid = true;
 636         else
 637                 i2c.valid = false;
 638
 639         return i2c;
 640 }
 641
 642 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 643 {
 644         struct drm_device *dev = rdev->ddev;
 645         struct radeon_i2c_bus_rec i2c;
 646         u16 offset;
 647         u8 id, blocks, clk, data;
 648         int i;
 649
 650         i2c.valid = false;
 651
 652         offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 653         if (offset) {
 654                 blocks = RBIOS8(offset + 2);
 655                 for (i = 0; i < blocks; i++) {
 656                         id = RBIOS8(offset + 3 + (i * 5) + 0);
 657                         if (id == 136) {
 658                                 clk = RBIOS8(offset + 3 + (i * 5) + 3);
 659                                 data = RBIOS8(offset + 3 + (i * 5) + 4);
 660                                 /* gpiopad */
 661                                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 662                                                             (1 << clk), (1 << data));
 663                                 break;
 664                         }
 665                 }
 666         }
 667         return i2c;
 668 }
 669
 670 void radeon_combios_i2c_init(struct radeon_device *rdev)
 671 {
 672         struct drm_device *dev = rdev->ddev;
 673         struct radeon_i2c_bus_rec i2c;
 674
 675         /* actual hw pads
 676          * r1xx/rs2xx/rs3xx
 677          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 678          * r200
 679          * 0x60, 0x64, 0x68, mm
 680          * r300/r350
 681          * 0x60, 0x64, mm
 682          * rv2xx/rv3xx/rs4xx
 683          * 0x60, 0x64, 0x68, gpiopads, mm
 684          */
 685
 686         /* 0x60 */
 687         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 688         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 689         /* 0x64 */
 690         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 691         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 692
 693         /* mm i2c */
 694         i2c.valid = true;
 695         i2c.hw_capable = true;
 696         i2c.mm_i2c = true;
 697         i2c.i2c_id = 0xa0;
 698         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 699
 700         if (rdev->family == CHIP_R300 ||
 701             rdev->family == CHIP_R350) {
 702                 /* only 2 sw i2c pads */
 703         } else if (rdev->family == CHIP_RS300 ||
 704                    rdev->family == CHIP_RS400 ||
 705                    rdev->family == CHIP_RS480) {
 706                 /* 0x68 */
 707                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 708                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 709
 710                 /* gpiopad */
 711                 i2c = radeon_combios_get_i2c_info_from_table(rdev);
 712                 if (i2c.valid)
 713                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 714         } else if ((rdev->family == CHIP_R200) ||
 715                    (rdev->family >= CHIP_R300)) {
 716                 /* 0x68 */
 717                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 718                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 719         } else {
 720                 /* 0x68 */
 721                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 722                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 723                 /* 0x6c */
 724                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 725                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 726         }
 727 }
 728
 729 bool radeon_combios_get_clock_info(struct drm_device *dev)
 730 {
 731         struct radeon_device *rdev = dev->dev_private;
 732         uint16_t pll_info;
 733         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 734         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 735         struct radeon_pll *spll = &rdev->clock.spll;
 736         struct radeon_pll *mpll = &rdev->clock.mpll;
 737         int8_t rev;
 738         uint16_t sclk, mclk;
 739
 740         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 741         if (pll_info) {
 742                 rev = RBIOS8(pll_info);
 743
 744                 /* pixel clocks */
 745                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 746                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 747                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 748                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 749                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 750                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 751
 752                 if (rev > 9) {
 753                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 754                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 755                 } else {
 756                         p1pll->pll_in_min = 40;
 757                         p1pll->pll_in_max = 500;
 758                 }
 759                 *p2pll = *p1pll;
 760
 761                 /* system clock */
 762                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 763                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 764                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 765                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 766
 767                 if (rev > 10) {
 768                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 769                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 770                 } else {
 771                         /* ??? */
 772                         spll->pll_in_min = 40;
 773                         spll->pll_in_max = 500;
 774                 }
 775
 776                 /* memory clock */
 777                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 778                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 779                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 780                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 781
 782                 if (rev > 10) {
 783                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 784                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 785                 } else {
 786                         /* ??? */
 787                         mpll->pll_in_min = 40;
 788                         mpll->pll_in_max = 500;
 789                 }
 790
 791                 /* default sclk/mclk */
 792                 sclk = RBIOS16(pll_info + 0xa);
 793                 mclk = RBIOS16(pll_info + 0x8);
 794                 if (sclk == 0)
 795                         sclk = 200 * 100;
 796                 if (mclk == 0)
 797                         mclk = 200 * 100;
 798
 799                 rdev->clock.default_sclk = sclk;
 800                 rdev->clock.default_mclk = mclk;
 801
 802                 if (RBIOS32(pll_info + 0x16))
 803                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 804                 else
 805                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 806
 807                 return true;
 808         }
 809         return false;
 810 }
 811
 812 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 813 {
 814         struct drm_device *dev = rdev->ddev;
 815         u16 igp_info;
 816
 817         /* sideport is AMD only */
 818         if (rdev->family == CHIP_RS400)
 819                 return false;
 820
 821         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 822
 823         if (igp_info) {
 824                 if (RBIOS16(igp_info + 0x4))
 825                         return true;
 826         }
 827         return false;
 828 }
 829
 830 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 831         0x00000808,             /* r100  */
 832         0x00000808,             /* rv100 */
 833         0x00000808,             /* rs100 */
 834         0x00000808,             /* rv200 */
 835         0x00000808,             /* rs200 */
 836         0x00000808,             /* r200  */
 837         0x00000808,             /* rv250 */
 838         0x00000000,             /* rs300 */
 839         0x00000808,             /* rv280 */
 840         0x00000808,             /* r300  */
 841         0x00000808,             /* r350  */
 842         0x00000808,             /* rv350 */
 843         0x00000808,             /* rv380 */
 844         0x00000808,             /* r420  */
 845         0x00000808,             /* r423  */
 846         0x00000808,             /* rv410 */
 847         0x00000000,             /* rs400 */
 848         0x00000000,             /* rs480 */
 849 };
 850
 851 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 852                                                           struct radeon_encoder_primary_dac *p_dac)
 853 {
 854         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 855         return;
 856 }
 857
 858 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 859                                                                        radeon_encoder
 860                                                                        *encoder)
 861 {
 862         struct drm_device *dev = encoder->base.dev;
 863         struct radeon_device *rdev = dev->dev_private;
 864         uint16_t dac_info;
 865         uint8_t rev, bg, dac;
 866         struct radeon_encoder_primary_dac *p_dac = NULL;
 867         int found = 0;
 868
 869         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 870                         GFP_KERNEL);
 871
 872         if (!p_dac)
 873                 return NULL;
 874
 875         /* check CRT table */
 876         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 877         if (dac_info) {
 878                 rev = RBIOS8(dac_info) & 0x3;
 879                 if (rev < 2) {
 880                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 881                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 882                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 883                 } else {
 884                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 885                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 886                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 887                 }
 888                 /* if the values are zeros, use the table */
 889                 if ((dac == 0) || (bg == 0))
 890                         found = 0;
 891                 else
 892                         found = 1;
 893         }
 894
 895         /* quirks */
 896         /* Radeon 7000 (RV100) */
 897         if (((dev->pdev->device == 0x5159) &&
 898             (dev->pdev->subsystem_vendor == 0x174B) &&
 899             (dev->pdev->subsystem_device == 0x7c28)) ||
 900         /* Radeon 9100 (R200) */
 901            ((dev->pdev->device == 0x514D) &&
 902             (dev->pdev->subsystem_vendor == 0x174B) &&
 903             (dev->pdev->subsystem_device == 0x7149))) {
 904                 /* vbios value is bad, use the default */
 905                 found = 0;
 906         }
 907
 908         if (!found) /* fallback to defaults */
 909                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 910
 911         return p_dac;
 912 }
 913
 914 enum radeon_tv_std
 915 radeon_combios_get_tv_info(struct radeon_device *rdev)
 916 {
 917         struct drm_device *dev = rdev->ddev;
 918         uint16_t tv_info;
 919         enum radeon_tv_std tv_std = TV_STD_NTSC;
 920
 921         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 922         if (tv_info) {
 923                 if (RBIOS8(tv_info + 6) == 'T') {
 924                         switch (RBIOS8(tv_info + 7) & 0xf) {
 925                         case 1:
 926                                 tv_std = TV_STD_NTSC;
 927                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 928                                 break;
 929                         case 2:
 930                                 tv_std = TV_STD_PAL;
 931                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 932                                 break;
 933                         case 3:
 934                                 tv_std = TV_STD_PAL_M;
 935                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 936                                 break;
 937                         case 4:
 938                                 tv_std = TV_STD_PAL_60;
 939                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 940                                 break;
 941                         case 5:
 942                                 tv_std = TV_STD_NTSC_J;
 943                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 944                                 break;
 945                         case 6:
 946                                 tv_std = TV_STD_SCART_PAL;
 947                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 948                                 break;
 949                         default:
 950                                 tv_std = TV_STD_NTSC;
 951                                 DRM_DEBUG_KMS
 952                                     ("Unknown TV standard; defaulting to NTSC\n");
 953                                 break;
 954                         }
 955
 956                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 957                         case 0:
 958                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 959                                 break;
 960                         case 1:
 961                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 962                                 break;
 963                         case 2:
 964                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 965                                 break;
 966                         case 3:
 967                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 968                                 break;
 969                         default:
 970                                 break;
 971                         }
 972                 }
 973         }
 974         return tv_std;
 975 }
 976
 977 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 978         0x00000000,             /* r100  */
 979         0x00280000,             /* rv100 */
 980         0x00000000,             /* rs100 */
 981         0x00880000,             /* rv200 */
 982         0x00000000,             /* rs200 */
 983         0x00000000,             /* r200  */
 984         0x00770000,             /* rv250 */
 985         0x00290000,             /* rs300 */
 986         0x00560000,             /* rv280 */
 987         0x00780000,             /* r300  */
 988         0x00770000,             /* r350  */
 989         0x00780000,             /* rv350 */
 990         0x00780000,             /* rv380 */
 991         0x01080000,             /* r420  */
 992         0x01080000,             /* r423  */
 993         0x01080000,             /* rv410 */
 994         0x00780000,             /* rs400 */
 995         0x00780000,             /* rs480 */
 996 };
 997
 998 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 999                                                      struct radeon_encoder_tv_dac *tv_dac)
1000 {
1001         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1002         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1003                 tv_dac->ps2_tvdac_adj = 0x00880000;
1004         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1005         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006         return;
1007 }
1008
1009 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1010                                                              radeon_encoder
1011                                                              *encoder)
1012 {
1013         struct drm_device *dev = encoder->base.dev;
1014         struct radeon_device *rdev = dev->dev_private;
1015         uint16_t dac_info;
1016         uint8_t rev, bg, dac;
1017         struct radeon_encoder_tv_dac *tv_dac = NULL;
1018         int found = 0;
1019
1020         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1021         if (!tv_dac)
1022                 return NULL;
1023
1024         /* first check TV table */
1025         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1026         if (dac_info) {
1027                 rev = RBIOS8(dac_info + 0x3);
1028                 if (rev > 4) {
1029                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1030                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1031                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1032
1033                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1034                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1035                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1036
1037                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1038                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1039                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1040                         /* if the values are all zeros, use the table */
1041                         if (tv_dac->ps2_tvdac_adj)
1042                                 found = 1;
1043                 } else if (rev > 1) {
1044                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1045                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1046                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1047
1048                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1049                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1050                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1051
1052                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1053                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1054                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1055                         /* if the values are all zeros, use the table */
1056                         if (tv_dac->ps2_tvdac_adj)
1057                                 found = 1;
1058                 }
1059                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1060         }
1061         if (!found) {
1062                 /* then check CRT table */
1063                 dac_info =
1064                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1065                 if (dac_info) {
1066                         rev = RBIOS8(dac_info) & 0x3;
1067                         if (rev < 2) {
1068                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1069                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1070                                 tv_dac->ps2_tvdac_adj =
1071                                     (bg << 16) | (dac << 20);
1072                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1073                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074                                 /* if the values are all zeros, use the table */
1075                                 if (tv_dac->ps2_tvdac_adj)
1076                                         found = 1;
1077                         } else {
1078                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1079                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1080                                 tv_dac->ps2_tvdac_adj =
1081                                     (bg << 16) | (dac << 20);
1082                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1083                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084                                 /* if the values are all zeros, use the table */
1085                                 if (tv_dac->ps2_tvdac_adj)
1086                                         found = 1;
1087                         }
1088                 } else {
1089                         DRM_INFO("No TV DAC info found in BIOS\n");
1090                 }
1091         }
1092
1093         if (!found) /* fallback to defaults */
1094                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1095
1096         return tv_dac;
1097 }
1098
1099 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1100                                                                          radeon_device
1101                                                                          *rdev)
1102 {
1103         struct radeon_encoder_lvds *lvds = NULL;
1104         uint32_t fp_vert_stretch, fp_horz_stretch;
1105         uint32_t ppll_div_sel, ppll_val;
1106         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1107
1108         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1109
1110         if (!lvds)
1111                 return NULL;
1112
1113         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1114         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1115
1116         /* These should be fail-safe defaults, fingers crossed */
1117         lvds->panel_pwr_delay = 200;
1118         lvds->panel_vcc_delay = 2000;
1119
1120         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1121         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1122         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1123
1124         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1125                 lvds->native_mode.vdisplay =
1126                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1127                      RADEON_VERT_PANEL_SHIFT) + 1;
1128         else
1129                 lvds->native_mode.vdisplay =
1130                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1131
1132         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1133                 lvds->native_mode.hdisplay =
1134                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1135                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1136         else
1137                 lvds->native_mode.hdisplay =
1138                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1139
1140         if ((lvds->native_mode.hdisplay < 640) ||
1141             (lvds->native_mode.vdisplay < 480)) {
1142                 lvds->native_mode.hdisplay = 640;
1143                 lvds->native_mode.vdisplay = 480;
1144         }
1145
1146         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1147         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1148         if ((ppll_val & 0x000707ff) == 0x1bb)
1149                 lvds->use_bios_dividers = false;
1150         else {
1151                 lvds->panel_ref_divider =
1152                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1153                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1154                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1155
1156                 if ((lvds->panel_ref_divider != 0) &&
1157                     (lvds->panel_fb_divider > 3))
1158                         lvds->use_bios_dividers = true;
1159         }
1160         lvds->panel_vcc_delay = 200;
1161
1162         DRM_INFO("Panel info derived from registers\n");
1163         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1164                  lvds->native_mode.vdisplay);
1165
1166         return lvds;
1167 }
1168
1169 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1170                                                          *encoder)
1171 {
1172         struct drm_device *dev = encoder->base.dev;
1173         struct radeon_device *rdev = dev->dev_private;
1174         uint16_t lcd_info;
1175         uint32_t panel_setup;
1176         char stmp[30];
1177         int tmp, i;
1178         struct radeon_encoder_lvds *lvds = NULL;
1179
1180         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1181
1182         if (lcd_info) {
1183                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1184
1185                 if (!lvds)
1186                         return NULL;
1187
1188                 for (i = 0; i < 24; i++)
1189                         stmp[i] = RBIOS8(lcd_info + i + 1);
1190                 stmp[24] = 0;
1191
1192                 DRM_INFO("Panel ID String: %s\n", stmp);
1193
1194                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1195                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1196
1197                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1198                          lvds->native_mode.vdisplay);
1199
1200                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1201                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1202
1203                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1204                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1205                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1206
1207                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1208                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1209                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1210                 if ((lvds->panel_ref_divider != 0) &&
1211                     (lvds->panel_fb_divider > 3))
1212                         lvds->use_bios_dividers = true;
1213
1214                 panel_setup = RBIOS32(lcd_info + 0x39);
1215                 lvds->lvds_gen_cntl = 0xff00;
1216                 if (panel_setup & 0x1)
1217                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1218
1219                 if ((panel_setup >> 4) & 0x1)
1220                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1221
1222                 switch ((panel_setup >> 8) & 0x7) {
1223                 case 0:
1224                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1225                         break;
1226                 case 1:
1227                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1228                         break;
1229                 case 2:
1230                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1231                         break;
1232                 default:
1233                         break;
1234                 }
1235
1236                 if ((panel_setup >> 16) & 0x1)
1237                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1238
1239                 if ((panel_setup >> 17) & 0x1)
1240                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1241
1242                 if ((panel_setup >> 18) & 0x1)
1243                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1244
1245                 if ((panel_setup >> 23) & 0x1)
1246                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1247
1248                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1249
1250                 for (i = 0; i < 32; i++) {
1251                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1252                         if (tmp == 0)
1253                                 break;
1254
1255                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1256                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1257                                 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1258
1259                                 if (hss > lvds->native_mode.hdisplay)
1260                                         hss = (10 - 1) * 8;
1261
1262                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1263                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1264                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1265                                         hss;
1266                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1267                                         (RBIOS8(tmp + 23) * 8);
1268
1269                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1270                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1271                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1272                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1273                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1274                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1275
1276                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1277                                 lvds->native_mode.flags = 0;
1278                                 /* set crtc values */
1279                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1280
1281                         }
1282                 }
1283         } else {
1284                 DRM_INFO("No panel info found in BIOS\n");
1285                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1286         }
1287
1288         if (lvds)
1289                 encoder->native_mode = lvds->native_mode;
1290         return lvds;
1291 }
1292
1293 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1294         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1295         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1296         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1297         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1298         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1299         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1300         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1301         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1302         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1303         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1304         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1305         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1306         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1307         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1308         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1309         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1310         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1311         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1312 };
1313
1314 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1315                                             struct radeon_encoder_int_tmds *tmds)
1316 {
1317         struct drm_device *dev = encoder->base.dev;
1318         struct radeon_device *rdev = dev->dev_private;
1319         int i;
1320
1321         for (i = 0; i < 4; i++) {
1322                 tmds->tmds_pll[i].value =
1323                         default_tmds_pll[rdev->family][i].value;
1324                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1325         }
1326
1327         return true;
1328 }
1329
1330 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1331                                               struct radeon_encoder_int_tmds *tmds)
1332 {
1333         struct drm_device *dev = encoder->base.dev;
1334         struct radeon_device *rdev = dev->dev_private;
1335         uint16_t tmds_info;
1336         int i, n;
1337         uint8_t ver;
1338
1339         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1340
1341         if (tmds_info) {
1342                 ver = RBIOS8(tmds_info);
1343                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1344                 if (ver == 3) {
1345                         n = RBIOS8(tmds_info + 5) + 1;
1346                         if (n > 4)
1347                                 n = 4;
1348                         for (i = 0; i < n; i++) {
1349                                 tmds->tmds_pll[i].value =
1350                                     RBIOS32(tmds_info + i * 10 + 0x08);
1351                                 tmds->tmds_pll[i].freq =
1352                                     RBIOS16(tmds_info + i * 10 + 0x10);
1353                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1354                                           tmds->tmds_pll[i].freq,
1355                                           tmds->tmds_pll[i].value);
1356                         }
1357                 } else if (ver == 4) {
1358                         int stride = 0;
1359                         n = RBIOS8(tmds_info + 5) + 1;
1360                         if (n > 4)
1361                                 n = 4;
1362                         for (i = 0; i < n; i++) {
1363                                 tmds->tmds_pll[i].value =
1364                                     RBIOS32(tmds_info + stride + 0x08);
1365                                 tmds->tmds_pll[i].freq =
1366                                     RBIOS16(tmds_info + stride + 0x10);
1367                                 if (i == 0)
1368                                         stride += 10;
1369                                 else
1370                                         stride += 6;
1371                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1372                                           tmds->tmds_pll[i].freq,
1373                                           tmds->tmds_pll[i].value);
1374                         }
1375                 }
1376         } else {
1377                 DRM_INFO("No TMDS info found in BIOS\n");
1378                 return false;
1379         }
1380         return true;
1381 }
1382
1383 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1384                                                 struct radeon_encoder_ext_tmds *tmds)
1385 {
1386         struct drm_device *dev = encoder->base.dev;
1387         struct radeon_device *rdev = dev->dev_private;
1388         struct radeon_i2c_bus_rec i2c_bus;
1389
1390         /* default for macs */
1391         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1392         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1393
1394         /* XXX some macs have duallink chips */
1395         switch (rdev->mode_info.connector_table) {
1396         case CT_POWERBOOK_EXTERNAL:
1397         case CT_MINI_EXTERNAL:
1398         default:
1399                 tmds->dvo_chip = DVO_SIL164;
1400                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1401                 break;
1402         }
1403
1404         return true;
1405 }
1406
1407 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1408                                                   struct radeon_encoder_ext_tmds *tmds)
1409 {
1410         struct drm_device *dev = encoder->base.dev;
1411         struct radeon_device *rdev = dev->dev_private;
1412         uint16_t offset;
1413         uint8_t ver;
1414         enum radeon_combios_ddc gpio;
1415         struct radeon_i2c_bus_rec i2c_bus;
1416
1417         tmds->i2c_bus = NULL;
1418         if (rdev->flags & RADEON_IS_IGP) {
1419                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1420                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1421                 tmds->dvo_chip = DVO_SIL164;
1422                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1423         } else {
1424                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1425                 if (offset) {
1426                         ver = RBIOS8(offset);
1427                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1428                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1429                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1430                         gpio = RBIOS8(offset + 4 + 3);
1431                         if (gpio == DDC_LCD) {
1432                                 /* MM i2c */
1433                                 i2c_bus.valid = true;
1434                                 i2c_bus.hw_capable = true;
1435                                 i2c_bus.mm_i2c = true;
1436                                 i2c_bus.i2c_id = 0xa0;
1437                         } else
1438                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1439                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440                 }
1441         }
1442
1443         if (!tmds->i2c_bus) {
1444                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1445                 return false;
1446         }
1447
1448         return true;
1449 }
1450
1451 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1452 {
1453         struct radeon_device *rdev = dev->dev_private;
1454         struct radeon_i2c_bus_rec ddc_i2c;
1455         struct radeon_hpd hpd;
1456
1457         rdev->mode_info.connector_table = radeon_connector_table;
1458         if (rdev->mode_info.connector_table == CT_NONE) {
1459 #ifdef CONFIG_PPC_PMAC
1460                 if (of_machine_is_compatible("PowerBook3,3")) {
1461                         /* powerbook with VGA */
1462                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1463                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1464                            of_machine_is_compatible("PowerBook3,5")) {
1465                         /* powerbook with internal tmds */
1466                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1467                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1468                            of_machine_is_compatible("PowerBook5,2") ||
1469                            of_machine_is_compatible("PowerBook5,3") ||
1470                            of_machine_is_compatible("PowerBook5,4") ||
1471                            of_machine_is_compatible("PowerBook5,5")) {
1472                         /* powerbook with external single link tmds (sil164) */
1473                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1474                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1475                         /* powerbook with external dual or single link tmds */
1476                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1477                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1478                            of_machine_is_compatible("PowerBook5,8") ||
1479                            of_machine_is_compatible("PowerBook5,9")) {
1480                         /* PowerBook6,2 ? */
1481                         /* powerbook with external dual link tmds (sil1178?) */
1482                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1483                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1484                            of_machine_is_compatible("PowerBook4,2") ||
1485                            of_machine_is_compatible("PowerBook4,3") ||
1486                            of_machine_is_compatible("PowerBook6,3") ||
1487                            of_machine_is_compatible("PowerBook6,5") ||
1488                            of_machine_is_compatible("PowerBook6,7")) {
1489                         /* ibook */
1490                         rdev->mode_info.connector_table = CT_IBOOK;
1491                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1492                         /* PowerMac G4 Silver radeon 7500 */
1493                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1494                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1495                         /* emac */
1496                         rdev->mode_info.connector_table = CT_EMAC;
1497                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1498                         /* mini with internal tmds */
1499                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1500                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1501                         /* mini with external tmds */
1502                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1503                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1504                         /* PowerMac8,1 ? */
1505                         /* imac g5 isight */
1506                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1507                 } else if ((rdev->pdev->device == 0x4a48) &&
1508                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1509                            (rdev->pdev->subsystem_device == 0x4a48)) {
1510                         /* Mac X800 */
1511                         rdev->mode_info.connector_table = CT_MAC_X800;
1512                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1513                             of_machine_is_compatible("PowerMac7,3")) &&
1514                            (rdev->pdev->device == 0x4150) &&
1515                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1516                            (rdev->pdev->subsystem_device == 0x4150)) {
1517                         /* Mac G5 tower 9600 */
1518                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1519                 } else if ((rdev->pdev->device == 0x4c66) &&
1520                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1521                            (rdev->pdev->subsystem_device == 0x4c66)) {
1522                         /* SAM440ep RV250 embedded board */
1523                         rdev->mode_info.connector_table = CT_SAM440EP;
1524                 } else
1525 #endif /* CONFIG_PPC_PMAC */
1526 #ifdef CONFIG_PPC64
1527                 if (ASIC_IS_RN50(rdev))
1528                         rdev->mode_info.connector_table = CT_RN50_POWER;
1529                 else
1530 #endif
1531                         rdev->mode_info.connector_table = CT_GENERIC;
1532         }
1533
1534         switch (rdev->mode_info.connector_table) {
1535         case CT_GENERIC:
1536                 DRM_INFO("Connector Table: %d (generic)\n",
1537                          rdev->mode_info.connector_table);
1538                 /* these are the most common settings */
1539                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1540                         /* VGA - primary dac */
1541                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1542                         hpd.hpd = RADEON_HPD_NONE;
1543                         radeon_add_legacy_encoder(dev,
1544                                                   radeon_get_encoder_enum(dev,
1545                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1546                                                                         1),
1547                                                   ATOM_DEVICE_CRT1_SUPPORT);
1548                         radeon_add_legacy_connector(dev, 0,
1549                                                     ATOM_DEVICE_CRT1_SUPPORT,
1550                                                     DRM_MODE_CONNECTOR_VGA,
1551                                                     &ddc_i2c,
1552                                                     CONNECTOR_OBJECT_ID_VGA,
1553                                                     &hpd);
1554                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1555                         /* LVDS */
1556                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1557                         hpd.hpd = RADEON_HPD_NONE;
1558                         radeon_add_legacy_encoder(dev,
1559                                                   radeon_get_encoder_enum(dev,
1560                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1561                                                                         0),
1562                                                   ATOM_DEVICE_LCD1_SUPPORT);
1563                         radeon_add_legacy_connector(dev, 0,
1564                                                     ATOM_DEVICE_LCD1_SUPPORT,
1565                                                     DRM_MODE_CONNECTOR_LVDS,
1566                                                     &ddc_i2c,
1567                                                     CONNECTOR_OBJECT_ID_LVDS,
1568                                                     &hpd);
1569
1570                         /* VGA - primary dac */
1571                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1572                         hpd.hpd = RADEON_HPD_NONE;
1573                         radeon_add_legacy_encoder(dev,
1574                                                   radeon_get_encoder_enum(dev,
1575                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1576                                                                         1),
1577                                                   ATOM_DEVICE_CRT1_SUPPORT);
1578                         radeon_add_legacy_connector(dev, 1,
1579                                                     ATOM_DEVICE_CRT1_SUPPORT,
1580                                                     DRM_MODE_CONNECTOR_VGA,
1581                                                     &ddc_i2c,
1582                                                     CONNECTOR_OBJECT_ID_VGA,
1583                                                     &hpd);
1584                 } else {
1585                         /* DVI-I - tv dac, int tmds */
1586                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1587                         hpd.hpd = RADEON_HPD_1;
1588                         radeon_add_legacy_encoder(dev,
1589                                                   radeon_get_encoder_enum(dev,
1590                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1591                                                                         0),
1592                                                   ATOM_DEVICE_DFP1_SUPPORT);
1593                         radeon_add_legacy_encoder(dev,
1594                                                   radeon_get_encoder_enum(dev,
1595                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1596                                                                         2),
1597                                                   ATOM_DEVICE_CRT2_SUPPORT);
1598                         radeon_add_legacy_connector(dev, 0,
1599                                                     ATOM_DEVICE_DFP1_SUPPORT |
1600                                                     ATOM_DEVICE_CRT2_SUPPORT,
1601                                                     DRM_MODE_CONNECTOR_DVII,
1602                                                     &ddc_i2c,
1603                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1604                                                     &hpd);
1605
1606                         /* VGA - primary dac */
1607                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1608                         hpd.hpd = RADEON_HPD_NONE;
1609                         radeon_add_legacy_encoder(dev,
1610                                                   radeon_get_encoder_enum(dev,
1611                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1612                                                                         1),
1613                                                   ATOM_DEVICE_CRT1_SUPPORT);
1614                         radeon_add_legacy_connector(dev, 1,
1615                                                     ATOM_DEVICE_CRT1_SUPPORT,
1616                                                     DRM_MODE_CONNECTOR_VGA,
1617                                                     &ddc_i2c,
1618                                                     CONNECTOR_OBJECT_ID_VGA,
1619                                                     &hpd);
1620                 }
1621
1622                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1623                         /* TV - tv dac */
1624                         ddc_i2c.valid = false;
1625                         hpd.hpd = RADEON_HPD_NONE;
1626                         radeon_add_legacy_encoder(dev,
1627                                                   radeon_get_encoder_enum(dev,
1628                                                                         ATOM_DEVICE_TV1_SUPPORT,
1629                                                                         2),
1630                                                   ATOM_DEVICE_TV1_SUPPORT);
1631                         radeon_add_legacy_connector(dev, 2,
1632                                                     ATOM_DEVICE_TV1_SUPPORT,
1633                                                     DRM_MODE_CONNECTOR_SVIDEO,
1634                                                     &ddc_i2c,
1635                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1636                                                     &hpd);
1637                 }
1638                 break;
1639         case CT_IBOOK:
1640                 DRM_INFO("Connector Table: %d (ibook)\n",
1641                          rdev->mode_info.connector_table);
1642                 /* LVDS */
1643                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1644                 hpd.hpd = RADEON_HPD_NONE;
1645                 radeon_add_legacy_encoder(dev,
1646                                           radeon_get_encoder_enum(dev,
1647                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1648                                                                 0),
1649                                           ATOM_DEVICE_LCD1_SUPPORT);
1650                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1651                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1652                                             CONNECTOR_OBJECT_ID_LVDS,
1653                                             &hpd);
1654                 /* VGA - TV DAC */
1655                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1656                 hpd.hpd = RADEON_HPD_NONE;
1657                 radeon_add_legacy_encoder(dev,
1658                                           radeon_get_encoder_enum(dev,
1659                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1660                                                                 2),
1661                                           ATOM_DEVICE_CRT2_SUPPORT);
1662                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1663                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1664                                             CONNECTOR_OBJECT_ID_VGA,
1665                                             &hpd);
1666                 /* TV - TV DAC */
1667                 ddc_i2c.valid = false;
1668                 hpd.hpd = RADEON_HPD_NONE;
1669                 radeon_add_legacy_encoder(dev,
1670                                           radeon_get_encoder_enum(dev,
1671                                                                 ATOM_DEVICE_TV1_SUPPORT,
1672                                                                 2),
1673                                           ATOM_DEVICE_TV1_SUPPORT);
1674                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1675                                             DRM_MODE_CONNECTOR_SVIDEO,
1676                                             &ddc_i2c,
1677                                             CONNECTOR_OBJECT_ID_SVIDEO,
1678                                             &hpd);
1679                 break;
1680         case CT_POWERBOOK_EXTERNAL:
1681                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1682                          rdev->mode_info.connector_table);
1683                 /* LVDS */
1684                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1685                 hpd.hpd = RADEON_HPD_NONE;
1686                 radeon_add_legacy_encoder(dev,
1687                                           radeon_get_encoder_enum(dev,
1688                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1689                                                                 0),
1690                                           ATOM_DEVICE_LCD1_SUPPORT);
1691                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1692                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1693                                             CONNECTOR_OBJECT_ID_LVDS,
1694                                             &hpd);
1695                 /* DVI-I - primary dac, ext tmds */
1696                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1697                 hpd.hpd = RADEON_HPD_2; /* ??? */
1698                 radeon_add_legacy_encoder(dev,
1699                                           radeon_get_encoder_enum(dev,
1700                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1701                                                                 0),
1702                                           ATOM_DEVICE_DFP2_SUPPORT);
1703                 radeon_add_legacy_encoder(dev,
1704                                           radeon_get_encoder_enum(dev,
1705                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1706                                                                 1),
1707                                           ATOM_DEVICE_CRT1_SUPPORT);
1708                 /* XXX some are SL */
1709                 radeon_add_legacy_connector(dev, 1,
1710                                             ATOM_DEVICE_DFP2_SUPPORT |
1711                                             ATOM_DEVICE_CRT1_SUPPORT,
1712                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1713                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1714                                             &hpd);
1715                 /* TV - TV DAC */
1716                 ddc_i2c.valid = false;
1717                 hpd.hpd = RADEON_HPD_NONE;
1718                 radeon_add_legacy_encoder(dev,
1719                                           radeon_get_encoder_enum(dev,
1720                                                                 ATOM_DEVICE_TV1_SUPPORT,
1721                                                                 2),
1722                                           ATOM_DEVICE_TV1_SUPPORT);
1723                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1724                                             DRM_MODE_CONNECTOR_SVIDEO,
1725                                             &ddc_i2c,
1726                                             CONNECTOR_OBJECT_ID_SVIDEO,
1727                                             &hpd);
1728                 break;
1729         case CT_POWERBOOK_INTERNAL:
1730                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1731                          rdev->mode_info.connector_table);
1732                 /* LVDS */
1733                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1734                 hpd.hpd = RADEON_HPD_NONE;
1735                 radeon_add_legacy_encoder(dev,
1736                                           radeon_get_encoder_enum(dev,
1737                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1738                                                                 0),
1739                                           ATOM_DEVICE_LCD1_SUPPORT);
1740                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1741                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1742                                             CONNECTOR_OBJECT_ID_LVDS,
1743                                             &hpd);
1744                 /* DVI-I - primary dac, int tmds */
1745                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1746                 hpd.hpd = RADEON_HPD_1; /* ??? */
1747                 radeon_add_legacy_encoder(dev,
1748                                           radeon_get_encoder_enum(dev,
1749                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1750                                                                 0),
1751                                           ATOM_DEVICE_DFP1_SUPPORT);
1752                 radeon_add_legacy_encoder(dev,
1753                                           radeon_get_encoder_enum(dev,
1754                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1755                                                                 1),
1756                                           ATOM_DEVICE_CRT1_SUPPORT);
1757                 radeon_add_legacy_connector(dev, 1,
1758                                             ATOM_DEVICE_DFP1_SUPPORT |
1759                                             ATOM_DEVICE_CRT1_SUPPORT,
1760                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1761                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1762                                             &hpd);
1763                 /* TV - TV DAC */
1764                 ddc_i2c.valid = false;
1765                 hpd.hpd = RADEON_HPD_NONE;
1766                 radeon_add_legacy_encoder(dev,
1767                                           radeon_get_encoder_enum(dev,
1768                                                                 ATOM_DEVICE_TV1_SUPPORT,
1769                                                                 2),
1770                                           ATOM_DEVICE_TV1_SUPPORT);
1771                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1772                                             DRM_MODE_CONNECTOR_SVIDEO,
1773                                             &ddc_i2c,
1774                                             CONNECTOR_OBJECT_ID_SVIDEO,
1775                                             &hpd);
1776                 break;
1777         case CT_POWERBOOK_VGA:
1778                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1779                          rdev->mode_info.connector_table);
1780                 /* LVDS */
1781                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1782                 hpd.hpd = RADEON_HPD_NONE;
1783                 radeon_add_legacy_encoder(dev,
1784                                           radeon_get_encoder_enum(dev,
1785                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1786                                                                 0),
1787                                           ATOM_DEVICE_LCD1_SUPPORT);
1788                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1789                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1790                                             CONNECTOR_OBJECT_ID_LVDS,
1791                                             &hpd);
1792                 /* VGA - primary dac */
1793                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1794                 hpd.hpd = RADEON_HPD_NONE;
1795                 radeon_add_legacy_encoder(dev,
1796                                           radeon_get_encoder_enum(dev,
1797                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1798                                                                 1),
1799                                           ATOM_DEVICE_CRT1_SUPPORT);
1800                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1801                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1802                                             CONNECTOR_OBJECT_ID_VGA,
1803                                             &hpd);
1804                 /* TV - TV DAC */
1805                 ddc_i2c.valid = false;
1806                 hpd.hpd = RADEON_HPD_NONE;
1807                 radeon_add_legacy_encoder(dev,
1808                                           radeon_get_encoder_enum(dev,
1809                                                                 ATOM_DEVICE_TV1_SUPPORT,
1810                                                                 2),
1811                                           ATOM_DEVICE_TV1_SUPPORT);
1812                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1813                                             DRM_MODE_CONNECTOR_SVIDEO,
1814                                             &ddc_i2c,
1815                                             CONNECTOR_OBJECT_ID_SVIDEO,
1816                                             &hpd);
1817                 break;
1818         case CT_MINI_EXTERNAL:
1819                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1820                          rdev->mode_info.connector_table);
1821                 /* DVI-I - tv dac, ext tmds */
1822                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1823                 hpd.hpd = RADEON_HPD_2; /* ??? */
1824                 radeon_add_legacy_encoder(dev,
1825                                           radeon_get_encoder_enum(dev,
1826                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1827                                                                 0),
1828                                           ATOM_DEVICE_DFP2_SUPPORT);
1829                 radeon_add_legacy_encoder(dev,
1830                                           radeon_get_encoder_enum(dev,
1831                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1832                                                                 2),
1833                                           ATOM_DEVICE_CRT2_SUPPORT);
1834                 /* XXX are any DL? */
1835                 radeon_add_legacy_connector(dev, 0,
1836                                             ATOM_DEVICE_DFP2_SUPPORT |
1837                                             ATOM_DEVICE_CRT2_SUPPORT,
1838                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1839                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1840                                             &hpd);
1841                 /* TV - TV DAC */
1842                 ddc_i2c.valid = false;
1843                 hpd.hpd = RADEON_HPD_NONE;
1844                 radeon_add_legacy_encoder(dev,
1845                                           radeon_get_encoder_enum(dev,
1846                                                                 ATOM_DEVICE_TV1_SUPPORT,
1847                                                                 2),
1848                                           ATOM_DEVICE_TV1_SUPPORT);
1849                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1850                                             DRM_MODE_CONNECTOR_SVIDEO,
1851                                             &ddc_i2c,
1852                                             CONNECTOR_OBJECT_ID_SVIDEO,
1853                                             &hpd);
1854                 break;
1855         case CT_MINI_INTERNAL:
1856                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1857                          rdev->mode_info.connector_table);
1858                 /* DVI-I - tv dac, int tmds */
1859                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1860                 hpd.hpd = RADEON_HPD_1; /* ??? */
1861                 radeon_add_legacy_encoder(dev,
1862                                           radeon_get_encoder_enum(dev,
1863                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1864                                                                 0),
1865                                           ATOM_DEVICE_DFP1_SUPPORT);
1866                 radeon_add_legacy_encoder(dev,
1867                                           radeon_get_encoder_enum(dev,
1868                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1869                                                                 2),
1870                                           ATOM_DEVICE_CRT2_SUPPORT);
1871                 radeon_add_legacy_connector(dev, 0,
1872                                             ATOM_DEVICE_DFP1_SUPPORT |
1873                                             ATOM_DEVICE_CRT2_SUPPORT,
1874                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1875                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1876                                             &hpd);
1877                 /* TV - TV DAC */
1878                 ddc_i2c.valid = false;
1879                 hpd.hpd = RADEON_HPD_NONE;
1880                 radeon_add_legacy_encoder(dev,
1881                                           radeon_get_encoder_enum(dev,
1882                                                                 ATOM_DEVICE_TV1_SUPPORT,
1883                                                                 2),
1884                                           ATOM_DEVICE_TV1_SUPPORT);
1885                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1886                                             DRM_MODE_CONNECTOR_SVIDEO,
1887                                             &ddc_i2c,
1888                                             CONNECTOR_OBJECT_ID_SVIDEO,
1889                                             &hpd);
1890                 break;
1891         case CT_IMAC_G5_ISIGHT:
1892                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1893                          rdev->mode_info.connector_table);
1894                 /* DVI-D - int tmds */
1895                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1896                 hpd.hpd = RADEON_HPD_1; /* ??? */
1897                 radeon_add_legacy_encoder(dev,
1898                                           radeon_get_encoder_enum(dev,
1899                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1900                                                                 0),
1901                                           ATOM_DEVICE_DFP1_SUPPORT);
1902                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1903                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1904                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1905                                             &hpd);
1906                 /* VGA - tv dac */
1907                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1908                 hpd.hpd = RADEON_HPD_NONE;
1909                 radeon_add_legacy_encoder(dev,
1910                                           radeon_get_encoder_enum(dev,
1911                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1912                                                                 2),
1913                                           ATOM_DEVICE_CRT2_SUPPORT);
1914                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1915                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1916                                             CONNECTOR_OBJECT_ID_VGA,
1917                                             &hpd);
1918                 /* TV - TV DAC */
1919                 ddc_i2c.valid = false;
1920                 hpd.hpd = RADEON_HPD_NONE;
1921                 radeon_add_legacy_encoder(dev,
1922                                           radeon_get_encoder_enum(dev,
1923                                                                 ATOM_DEVICE_TV1_SUPPORT,
1924                                                                 2),
1925                                           ATOM_DEVICE_TV1_SUPPORT);
1926                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1927                                             DRM_MODE_CONNECTOR_SVIDEO,
1928                                             &ddc_i2c,
1929                                             CONNECTOR_OBJECT_ID_SVIDEO,
1930                                             &hpd);
1931                 break;
1932         case CT_EMAC:
1933                 DRM_INFO("Connector Table: %d (emac)\n",
1934                          rdev->mode_info.connector_table);
1935                 /* VGA - primary dac */
1936                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1937                 hpd.hpd = RADEON_HPD_NONE;
1938                 radeon_add_legacy_encoder(dev,
1939                                           radeon_get_encoder_enum(dev,
1940                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1941                                                                 1),
1942                                           ATOM_DEVICE_CRT1_SUPPORT);
1943                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1944                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945                                             CONNECTOR_OBJECT_ID_VGA,
1946                                             &hpd);
1947                 /* VGA - tv dac */
1948                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1949                 hpd.hpd = RADEON_HPD_NONE;
1950                 radeon_add_legacy_encoder(dev,
1951                                           radeon_get_encoder_enum(dev,
1952                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1953                                                                 2),
1954                                           ATOM_DEVICE_CRT2_SUPPORT);
1955                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1956                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1957                                             CONNECTOR_OBJECT_ID_VGA,
1958                                             &hpd);
1959                 /* TV - TV DAC */
1960                 ddc_i2c.valid = false;
1961                 hpd.hpd = RADEON_HPD_NONE;
1962                 radeon_add_legacy_encoder(dev,
1963                                           radeon_get_encoder_enum(dev,
1964                                                                 ATOM_DEVICE_TV1_SUPPORT,
1965                                                                 2),
1966                                           ATOM_DEVICE_TV1_SUPPORT);
1967                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1968                                             DRM_MODE_CONNECTOR_SVIDEO,
1969                                             &ddc_i2c,
1970                                             CONNECTOR_OBJECT_ID_SVIDEO,
1971                                             &hpd);
1972                 break;
1973         case CT_RN50_POWER:
1974                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1975                          rdev->mode_info.connector_table);
1976                 /* VGA - primary dac */
1977                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1978                 hpd.hpd = RADEON_HPD_NONE;
1979                 radeon_add_legacy_encoder(dev,
1980                                           radeon_get_encoder_enum(dev,
1981                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1982                                                                 1),
1983                                           ATOM_DEVICE_CRT1_SUPPORT);
1984                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1985                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1986                                             CONNECTOR_OBJECT_ID_VGA,
1987                                             &hpd);
1988                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1989                 hpd.hpd = RADEON_HPD_NONE;
1990                 radeon_add_legacy_encoder(dev,
1991                                           radeon_get_encoder_enum(dev,
1992                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1993                                                                 2),
1994                                           ATOM_DEVICE_CRT2_SUPPORT);
1995                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1996                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1997                                             CONNECTOR_OBJECT_ID_VGA,
1998                                             &hpd);
1999                 break;
2000         case CT_MAC_X800:
2001                 DRM_INFO("Connector Table: %d (mac x800)\n",
2002                          rdev->mode_info.connector_table);
2003                 /* DVI - primary dac, internal tmds */
2004                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2005                 hpd.hpd = RADEON_HPD_1; /* ??? */
2006                 radeon_add_legacy_encoder(dev,
2007                                           radeon_get_encoder_enum(dev,
2008                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2009                                                                   0),
2010                                           ATOM_DEVICE_DFP1_SUPPORT);
2011                 radeon_add_legacy_encoder(dev,
2012                                           radeon_get_encoder_enum(dev,
2013                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2014                                                                   1),
2015                                           ATOM_DEVICE_CRT1_SUPPORT);
2016                 radeon_add_legacy_connector(dev, 0,
2017                                             ATOM_DEVICE_DFP1_SUPPORT |
2018                                             ATOM_DEVICE_CRT1_SUPPORT,
2019                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2020                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2021                                             &hpd);
2022                 /* DVI - tv dac, dvo */
2023                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2024                 hpd.hpd = RADEON_HPD_2; /* ??? */
2025                 radeon_add_legacy_encoder(dev,
2026                                           radeon_get_encoder_enum(dev,
2027                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2028                                                                   0),
2029                                           ATOM_DEVICE_DFP2_SUPPORT);
2030                 radeon_add_legacy_encoder(dev,
2031                                           radeon_get_encoder_enum(dev,
2032                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2033                                                                   2),
2034                                           ATOM_DEVICE_CRT2_SUPPORT);
2035                 radeon_add_legacy_connector(dev, 1,
2036                                             ATOM_DEVICE_DFP2_SUPPORT |
2037                                             ATOM_DEVICE_CRT2_SUPPORT,
2038                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2039                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2040                                             &hpd);
2041                 break;
2042         case CT_MAC_G5_9600:
2043                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2044                          rdev->mode_info.connector_table);
2045                 /* DVI - tv dac, dvo */
2046                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2047                 hpd.hpd = RADEON_HPD_1; /* ??? */
2048                 radeon_add_legacy_encoder(dev,
2049                                           radeon_get_encoder_enum(dev,
2050                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2051                                                                   0),
2052                                           ATOM_DEVICE_DFP2_SUPPORT);
2053                 radeon_add_legacy_encoder(dev,
2054                                           radeon_get_encoder_enum(dev,
2055                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2056                                                                   2),
2057                                           ATOM_DEVICE_CRT2_SUPPORT);
2058                 radeon_add_legacy_connector(dev, 0,
2059                                             ATOM_DEVICE_DFP2_SUPPORT |
2060                                             ATOM_DEVICE_CRT2_SUPPORT,
2061                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2062                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2063                                             &hpd);
2064                 /* ADC - primary dac, internal tmds */
2065                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2066                 hpd.hpd = RADEON_HPD_2; /* ??? */
2067                 radeon_add_legacy_encoder(dev,
2068                                           radeon_get_encoder_enum(dev,
2069                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2070                                                                   0),
2071                                           ATOM_DEVICE_DFP1_SUPPORT);
2072                 radeon_add_legacy_encoder(dev,
2073                                           radeon_get_encoder_enum(dev,
2074                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2075                                                                   1),
2076                                           ATOM_DEVICE_CRT1_SUPPORT);
2077                 radeon_add_legacy_connector(dev, 1,
2078                                             ATOM_DEVICE_DFP1_SUPPORT |
2079                                             ATOM_DEVICE_CRT1_SUPPORT,
2080                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2081                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2082                                             &hpd);
2083                 /* TV - TV DAC */
2084                 ddc_i2c.valid = false;
2085                 hpd.hpd = RADEON_HPD_NONE;
2086                 radeon_add_legacy_encoder(dev,
2087                                           radeon_get_encoder_enum(dev,
2088                                                                 ATOM_DEVICE_TV1_SUPPORT,
2089                                                                 2),
2090                                           ATOM_DEVICE_TV1_SUPPORT);
2091                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2092                                             DRM_MODE_CONNECTOR_SVIDEO,
2093                                             &ddc_i2c,
2094                                             CONNECTOR_OBJECT_ID_SVIDEO,
2095                                             &hpd);
2096                 break;
2097         case CT_SAM440EP:
2098                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2099                          rdev->mode_info.connector_table);
2100                 /* LVDS */
2101                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2102                 hpd.hpd = RADEON_HPD_NONE;
2103                 radeon_add_legacy_encoder(dev,
2104                                           radeon_get_encoder_enum(dev,
2105                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2106                                                                 0),
2107                                           ATOM_DEVICE_LCD1_SUPPORT);
2108                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2109                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2110                                             CONNECTOR_OBJECT_ID_LVDS,
2111                                             &hpd);
2112                 /* DVI-I - secondary dac, int tmds */
2113                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2114                 hpd.hpd = RADEON_HPD_1; /* ??? */
2115                 radeon_add_legacy_encoder(dev,
2116                                           radeon_get_encoder_enum(dev,
2117                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2118                                                                 0),
2119                                           ATOM_DEVICE_DFP1_SUPPORT);
2120                 radeon_add_legacy_encoder(dev,
2121                                           radeon_get_encoder_enum(dev,
2122                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2123                                                                 2),
2124                                           ATOM_DEVICE_CRT2_SUPPORT);
2125                 radeon_add_legacy_connector(dev, 1,
2126                                             ATOM_DEVICE_DFP1_SUPPORT |
2127                                             ATOM_DEVICE_CRT2_SUPPORT,
2128                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2129                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2130                                             &hpd);
2131                 /* VGA - primary dac */
2132                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2133                 hpd.hpd = RADEON_HPD_NONE;
2134                 radeon_add_legacy_encoder(dev,
2135                                           radeon_get_encoder_enum(dev,
2136                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2137                                                                 1),
2138                                           ATOM_DEVICE_CRT1_SUPPORT);
2139                 radeon_add_legacy_connector(dev, 2,
2140                                             ATOM_DEVICE_CRT1_SUPPORT,
2141                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2142                                             CONNECTOR_OBJECT_ID_VGA,
2143                                             &hpd);
2144                 /* TV - TV DAC */
2145                 ddc_i2c.valid = false;
2146                 hpd.hpd = RADEON_HPD_NONE;
2147                 radeon_add_legacy_encoder(dev,
2148                                           radeon_get_encoder_enum(dev,
2149                                                                 ATOM_DEVICE_TV1_SUPPORT,
2150                                                                 2),
2151                                           ATOM_DEVICE_TV1_SUPPORT);
2152                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2153                                             DRM_MODE_CONNECTOR_SVIDEO,
2154                                             &ddc_i2c,
2155                                             CONNECTOR_OBJECT_ID_SVIDEO,
2156                                             &hpd);
2157                 break;
2158         case CT_MAC_G4_SILVER:
2159                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2160                          rdev->mode_info.connector_table);
2161                 /* DVI-I - tv dac, int tmds */
2162                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2163                 hpd.hpd = RADEON_HPD_1; /* ??? */
2164                 radeon_add_legacy_encoder(dev,
2165                                           radeon_get_encoder_enum(dev,
2166                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2167                                                                 0),
2168                                           ATOM_DEVICE_DFP1_SUPPORT);
2169                 radeon_add_legacy_encoder(dev,
2170                                           radeon_get_encoder_enum(dev,
2171                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2172                                                                 2),
2173                                           ATOM_DEVICE_CRT2_SUPPORT);
2174                 radeon_add_legacy_connector(dev, 0,
2175                                             ATOM_DEVICE_DFP1_SUPPORT |
2176                                             ATOM_DEVICE_CRT2_SUPPORT,
2177                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2178                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2179                                             &hpd);
2180                 /* VGA - primary dac */
2181                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2182                 hpd.hpd = RADEON_HPD_NONE;
2183                 radeon_add_legacy_encoder(dev,
2184                                           radeon_get_encoder_enum(dev,
2185                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2186                                                                 1),
2187                                           ATOM_DEVICE_CRT1_SUPPORT);
2188                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2189                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2190                                             CONNECTOR_OBJECT_ID_VGA,
2191                                             &hpd);
2192                 /* TV - TV DAC */
2193                 ddc_i2c.valid = false;
2194                 hpd.hpd = RADEON_HPD_NONE;
2195                 radeon_add_legacy_encoder(dev,
2196                                           radeon_get_encoder_enum(dev,
2197                                                                 ATOM_DEVICE_TV1_SUPPORT,
2198                                                                 2),
2199                                           ATOM_DEVICE_TV1_SUPPORT);
2200                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2201                                             DRM_MODE_CONNECTOR_SVIDEO,
2202                                             &ddc_i2c,
2203                                             CONNECTOR_OBJECT_ID_SVIDEO,
2204                                             &hpd);
2205                 break;
2206         default:
2207                 DRM_INFO("Connector table: %d (invalid)\n",
2208                          rdev->mode_info.connector_table);
2209                 return false;
2210         }
2211
2212         radeon_link_encoder_connector(dev);
2213
2214         return true;
2215 }
2216
2217 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2218                                        int bios_index,
2219                                        enum radeon_combios_connector
2220                                        *legacy_connector,
2221                                        struct radeon_i2c_bus_rec *ddc_i2c,
2222                                        struct radeon_hpd *hpd)
2223 {
2224
2225         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2226            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2227         if (dev->pdev->device == 0x515e &&
2228             dev->pdev->subsystem_vendor == 0x1014) {
2229                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2230                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2231                         return false;
2232         }
2233
2234         /* X300 card with extra non-existent DVI port */
2235         if (dev->pdev->device == 0x5B60 &&
2236             dev->pdev->subsystem_vendor == 0x17af &&
2237             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2238                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2239                         return false;
2240         }
2241
2242         return true;
2243 }
2244
2245 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2246 {
2247         /* Acer 5102 has non-existent TV port */
2248         if (dev->pdev->device == 0x5975 &&
2249             dev->pdev->subsystem_vendor == 0x1025 &&
2250             dev->pdev->subsystem_device == 0x009f)
2251                 return false;
2252
2253         /* HP dc5750 has non-existent TV port */
2254         if (dev->pdev->device == 0x5974 &&
2255             dev->pdev->subsystem_vendor == 0x103c &&
2256             dev->pdev->subsystem_device == 0x280a)
2257                 return false;
2258
2259         /* MSI S270 has non-existent TV port */
2260         if (dev->pdev->device == 0x5955 &&
2261             dev->pdev->subsystem_vendor == 0x1462 &&
2262             dev->pdev->subsystem_device == 0x0131)
2263                 return false;
2264
2265         return true;
2266 }
2267
2268 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2269 {
2270         struct radeon_device *rdev = dev->dev_private;
2271         uint32_t ext_tmds_info;
2272
2273         if (rdev->flags & RADEON_IS_IGP) {
2274                 if (is_dvi_d)
2275                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2276                 else
2277                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2278         }
2279         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2280         if (ext_tmds_info) {
2281                 uint8_t rev = RBIOS8(ext_tmds_info);
2282                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2283                 if (rev >= 3) {
2284                         if (is_dvi_d)
2285                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2286                         else
2287                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2288                 } else {
2289                         if (flags & 1) {
2290                                 if (is_dvi_d)
2291                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2292                                 else
2293                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2294                         }
2295                 }
2296         }
2297         if (is_dvi_d)
2298                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2299         else
2300                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2301 }
2302
2303 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2304 {
2305         struct radeon_device *rdev = dev->dev_private;
2306         uint32_t conn_info, entry, devices;
2307         uint16_t tmp, connector_object_id;
2308         enum radeon_combios_ddc ddc_type;
2309         enum radeon_combios_connector connector;
2310         int i = 0;
2311         struct radeon_i2c_bus_rec ddc_i2c;
2312         struct radeon_hpd hpd;
2313
2314         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2315         if (conn_info) {
2316                 for (i = 0; i < 4; i++) {
2317                         entry = conn_info + 2 + i * 2;
2318
2319                         if (!RBIOS16(entry))
2320                                 break;
2321
2322                         tmp = RBIOS16(entry);
2323
2324                         connector = (tmp >> 12) & 0xf;
2325
2326                         ddc_type = (tmp >> 8) & 0xf;
2327                         if (ddc_type == 5)
2328                                 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2329                         else
2330                                 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2331
2332                         switch (connector) {
2333                         case CONNECTOR_PROPRIETARY_LEGACY:
2334                         case CONNECTOR_DVI_I_LEGACY:
2335                         case CONNECTOR_DVI_D_LEGACY:
2336                                 if ((tmp >> 4) & 0x1)
2337                                         hpd.hpd = RADEON_HPD_2;
2338                                 else
2339                                         hpd.hpd = RADEON_HPD_1;
2340                                 break;
2341                         default:
2342                                 hpd.hpd = RADEON_HPD_NONE;
2343                                 break;
2344                         }
2345
2346                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2347                                                         &ddc_i2c, &hpd))
2348                                 continue;
2349
2350                         switch (connector) {
2351                         case CONNECTOR_PROPRIETARY_LEGACY:
2352                                 if ((tmp >> 4) & 0x1)
2353                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2354                                 else
2355                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2356                                 radeon_add_legacy_encoder(dev,
2357                                                           radeon_get_encoder_enum
2358                                                           (dev, devices, 0),
2359                                                           devices);
2360                                 radeon_add_legacy_connector(dev, i, devices,
2361                                                             legacy_connector_convert
2362                                                             [connector],
2363                                                             &ddc_i2c,
2364                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2365                                                             &hpd);
2366                                 break;
2367                         case CONNECTOR_CRT_LEGACY:
2368                                 if (tmp & 0x1) {
2369                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2370                                         radeon_add_legacy_encoder(dev,
2371                                                                   radeon_get_encoder_enum
2372                                                                   (dev,
2373                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2374                                                                    2),
2375                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2376                                 } else {
2377                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2378                                         radeon_add_legacy_encoder(dev,
2379                                                                   radeon_get_encoder_enum
2380                                                                   (dev,
2381                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2382                                                                    1),
2383                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2384                                 }
2385                                 radeon_add_legacy_connector(dev,
2386                                                             i,
2387                                                             devices,
2388                                                             legacy_connector_convert
2389                                                             [connector],
2390                                                             &ddc_i2c,
2391                                                             CONNECTOR_OBJECT_ID_VGA,
2392                                                             &hpd);
2393                                 break;
2394                         case CONNECTOR_DVI_I_LEGACY:
2395                                 devices = 0;
2396                                 if (tmp & 0x1) {
2397                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2398                                         radeon_add_legacy_encoder(dev,
2399                                                                   radeon_get_encoder_enum
2400                                                                   (dev,
2401                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2402                                                                    2),
2403                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2404                                 } else {
2405                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2406                                         radeon_add_legacy_encoder(dev,
2407                                                                   radeon_get_encoder_enum
2408                                                                   (dev,
2409                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2410                                                                    1),
2411                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2412                                 }
2413                                 /* RV100 board with external TDMS bit mis-set.
2414                                  * Actually uses internal TMDS, clear the bit.
2415                                  */
2416                                 if (dev->pdev->device == 0x5159 &&
2417                                     dev->pdev->subsystem_vendor == 0x1014 &&
2418                                     dev->pdev->subsystem_device == 0x029A) {
2419                                         tmp &= ~(1 << 4);
2420                                 }
2421                                 if ((tmp >> 4) & 0x1) {
2422                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2423                                         radeon_add_legacy_encoder(dev,
2424                                                                   radeon_get_encoder_enum
2425                                                                   (dev,
2426                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2427                                                                    0),
2428                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2429                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2430                                 } else {
2431                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2432                                         radeon_add_legacy_encoder(dev,
2433                                                                   radeon_get_encoder_enum
2434                                                                   (dev,
2435                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2436                                                                    0),
2437                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2438                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2439                                 }
2440                                 radeon_add_legacy_connector(dev,
2441                                                             i,
2442                                                             devices,
2443                                                             legacy_connector_convert
2444                                                             [connector],
2445                                                             &ddc_i2c,
2446                                                             connector_object_id,
2447                                                             &hpd);
2448                                 break;
2449                         case CONNECTOR_DVI_D_LEGACY:
2450                                 if ((tmp >> 4) & 0x1) {
2451                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2452                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2453                                 } else {
2454                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2455                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2456                                 }
2457                                 radeon_add_legacy_encoder(dev,
2458                                                           radeon_get_encoder_enum
2459                                                           (dev, devices, 0),
2460                                                           devices);
2461                                 radeon_add_legacy_connector(dev, i, devices,
2462                                                             legacy_connector_convert
2463                                                             [connector],
2464                                                             &ddc_i2c,
2465                                                             connector_object_id,
2466                                                             &hpd);
2467                                 break;
2468                         case CONNECTOR_CTV_LEGACY:
2469                         case CONNECTOR_STV_LEGACY:
2470                                 radeon_add_legacy_encoder(dev,
2471                                                           radeon_get_encoder_enum
2472                                                           (dev,
2473                                                            ATOM_DEVICE_TV1_SUPPORT,
2474                                                            2),
2475                                                           ATOM_DEVICE_TV1_SUPPORT);
2476                                 radeon_add_legacy_connector(dev, i,
2477                                                             ATOM_DEVICE_TV1_SUPPORT,
2478                                                             legacy_connector_convert
2479                                                             [connector],
2480                                                             &ddc_i2c,
2481                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2482                                                             &hpd);
2483                                 break;
2484                         default:
2485                                 DRM_ERROR("Unknown connector type: %d\n",
2486                                           connector);
2487                                 continue;
2488                         }
2489
2490                 }
2491         } else {
2492                 uint16_t tmds_info =
2493                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2494                 if (tmds_info) {
2495                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2496
2497                         radeon_add_legacy_encoder(dev,
2498                                                   radeon_get_encoder_enum(dev,
2499                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2500                                                                         1),
2501                                                   ATOM_DEVICE_CRT1_SUPPORT);
2502                         radeon_add_legacy_encoder(dev,
2503                                                   radeon_get_encoder_enum(dev,
2504                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2505                                                                         0),
2506                                                   ATOM_DEVICE_DFP1_SUPPORT);
2507
2508                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2509                         hpd.hpd = RADEON_HPD_1;
2510                         radeon_add_legacy_connector(dev,
2511                                                     0,
2512                                                     ATOM_DEVICE_CRT1_SUPPORT |
2513                                                     ATOM_DEVICE_DFP1_SUPPORT,
2514                                                     DRM_MODE_CONNECTOR_DVII,
2515                                                     &ddc_i2c,
2516                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2517                                                     &hpd);
2518                 } else {
2519                         uint16_t crt_info =
2520                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2521                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2522                         if (crt_info) {
2523                                 radeon_add_legacy_encoder(dev,
2524                                                           radeon_get_encoder_enum(dev,
2525                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2526                                                                                 1),
2527                                                           ATOM_DEVICE_CRT1_SUPPORT);
2528                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2529                                 hpd.hpd = RADEON_HPD_NONE;
2530                                 radeon_add_legacy_connector(dev,
2531                                                             0,
2532                                                             ATOM_DEVICE_CRT1_SUPPORT,
2533                                                             DRM_MODE_CONNECTOR_VGA,
2534                                                             &ddc_i2c,
2535                                                             CONNECTOR_OBJECT_ID_VGA,
2536                                                             &hpd);
2537                         } else {
2538                                 DRM_DEBUG_KMS("No connector info found\n");
2539                                 return false;
2540                         }
2541                 }
2542         }
2543
2544         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2545                 uint16_t lcd_info =
2546                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2547                 if (lcd_info) {
2548                         uint16_t lcd_ddc_info =
2549                             combios_get_table_offset(dev,
2550                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2551
2552                         radeon_add_legacy_encoder(dev,
2553                                                   radeon_get_encoder_enum(dev,
2554                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2555                                                                         0),
2556                                                   ATOM_DEVICE_LCD1_SUPPORT);
2557
2558                         if (lcd_ddc_info) {
2559                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2560                                 switch (ddc_type) {
2561                                 case DDC_LCD:
2562                                         ddc_i2c =
2563                                                 combios_setup_i2c_bus(rdev,
2564                                                                       DDC_LCD,
2565                                                                       RBIOS32(lcd_ddc_info + 3),
2566                                                                       RBIOS32(lcd_ddc_info + 7));
2567                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2568                                         break;
2569                                 case DDC_GPIO:
2570                                         ddc_i2c =
2571                                                 combios_setup_i2c_bus(rdev,
2572                                                                       DDC_GPIO,
2573                                                                       RBIOS32(lcd_ddc_info + 3),
2574                                                                       RBIOS32(lcd_ddc_info + 7));
2575                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2576                                         break;
2577                                 default:
2578                                         ddc_i2c =
2579                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2580                                         break;
2581                                 }
2582                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2583                         } else
2584                                 ddc_i2c.valid = false;
2585
2586                         hpd.hpd = RADEON_HPD_NONE;
2587                         radeon_add_legacy_connector(dev,
2588                                                     5,
2589                                                     ATOM_DEVICE_LCD1_SUPPORT,
2590                                                     DRM_MODE_CONNECTOR_LVDS,
2591                                                     &ddc_i2c,
2592                                                     CONNECTOR_OBJECT_ID_LVDS,
2593                                                     &hpd);
2594                 }
2595         }
2596
2597         /* check TV table */
2598         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2599                 uint32_t tv_info =
2600                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2601                 if (tv_info) {
2602                         if (RBIOS8(tv_info + 6) == 'T') {
2603                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2604                                         hpd.hpd = RADEON_HPD_NONE;
2605                                         ddc_i2c.valid = false;
2606                                         radeon_add_legacy_encoder(dev,
2607                                                                   radeon_get_encoder_enum
2608                                                                   (dev,
2609                                                                    ATOM_DEVICE_TV1_SUPPORT,
2610                                                                    2),
2611                                                                   ATOM_DEVICE_TV1_SUPPORT);
2612                                         radeon_add_legacy_connector(dev, 6,
2613                                                                     ATOM_DEVICE_TV1_SUPPORT,
2614                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2615                                                                     &ddc_i2c,
2616                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2617                                                                     &hpd);
2618                                 }
2619                         }
2620                 }
2621         }
2622
2623         radeon_link_encoder_connector(dev);
2624
2625         return true;
2626 }
2627
2628 static const char *thermal_controller_names[] = {
2629         "NONE",
2630         "lm63",
2631         "adm1032",
2632 };
2633
2634 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2635 {
2636         struct drm_device *dev = rdev->ddev;
2637         u16 offset, misc, misc2 = 0;
2638         u8 rev, blocks, tmp;
2639         int state_index = 0;
2640         struct radeon_i2c_bus_rec i2c_bus;
2641
2642         rdev->pm.default_power_state_index = -1;
2643
2644         /* allocate 2 power states */
2645         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2646         if (rdev->pm.power_state) {
2647                 /* allocate 1 clock mode per state */
2648                 rdev->pm.power_state[0].clock_info =
2649                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2650                 rdev->pm.power_state[1].clock_info =
2651                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2652                 if (!rdev->pm.power_state[0].clock_info ||
2653                     !rdev->pm.power_state[1].clock_info)
2654                         goto pm_failed;
2655         } else
2656                 goto pm_failed;
2657
2658         /* check for a thermal chip */
2659         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2660         if (offset) {
2661                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2662
2663                 rev = RBIOS8(offset);
2664
2665                 if (rev == 0) {
2666                         thermal_controller = RBIOS8(offset + 3);
2667                         gpio = RBIOS8(offset + 4) & 0x3f;
2668                         i2c_addr = RBIOS8(offset + 5);
2669                 } else if (rev == 1) {
2670                         thermal_controller = RBIOS8(offset + 4);
2671                         gpio = RBIOS8(offset + 5) & 0x3f;
2672                         i2c_addr = RBIOS8(offset + 6);
2673                 } else if (rev == 2) {
2674                         thermal_controller = RBIOS8(offset + 4);
2675                         gpio = RBIOS8(offset + 5) & 0x3f;
2676                         i2c_addr = RBIOS8(offset + 6);
2677                         clk_bit = RBIOS8(offset + 0xa);
2678                         data_bit = RBIOS8(offset + 0xb);
2679                 }
2680                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2681                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2682                                  thermal_controller_names[thermal_controller],
2683                                  i2c_addr >> 1);
2684                         if (gpio == DDC_LCD) {
2685                                 /* MM i2c */
2686                                 i2c_bus.valid = true;
2687                                 i2c_bus.hw_capable = true;
2688                                 i2c_bus.mm_i2c = true;
2689                                 i2c_bus.i2c_id = 0xa0;
2690                         } else if (gpio == DDC_GPIO)
2691                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2692                         else
2693                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2694                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2695                         if (rdev->pm.i2c_bus) {
2696                                 struct i2c_board_info info = { };
2697                                 const char *name = thermal_controller_names[thermal_controller];
2698                                 info.addr = i2c_addr >> 1;
2699                                 strlcpy(info.type, name, sizeof(info.type));
2700                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2701                         }
2702                 }
2703         } else {
2704                 /* boards with a thermal chip, but no overdrive table */
2705
2706                 /* Asus 9600xt has an f75375 on the monid bus */
2707                 if ((dev->pdev->device == 0x4152) &&
2708                     (dev->pdev->subsystem_vendor == 0x1043) &&
2709                     (dev->pdev->subsystem_device == 0xc002)) {
2710                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2711                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2712                         if (rdev->pm.i2c_bus) {
2713                                 struct i2c_board_info info = { };
2714                                 const char *name = "f75375";
2715                                 info.addr = 0x28;
2716                                 strlcpy(info.type, name, sizeof(info.type));
2717                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2718                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2719                                          name, info.addr);
2720                         }
2721                 }
2722         }
2723
2724         if (rdev->flags & RADEON_IS_MOBILITY) {
2725                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2726                 if (offset) {
2727                         rev = RBIOS8(offset);
2728                         blocks = RBIOS8(offset + 0x2);
2729                         /* power mode 0 tends to be the only valid one */
2730                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2731                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2732                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2733                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2734                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2735                                 goto default_mode;
2736                         rdev->pm.power_state[state_index].type =
2737                                 POWER_STATE_TYPE_BATTERY;
2738                         misc = RBIOS16(offset + 0x5 + 0x0);
2739                         if (rev > 4)
2740                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2741                         rdev->pm.power_state[state_index].misc = misc;
2742                         rdev->pm.power_state[state_index].misc2 = misc2;
2743                         if (misc & 0x4) {
2744                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2745                                 if (misc & 0x8)
2746                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2747                                                 true;
2748                                 else
2749                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2750                                                 false;
2751                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2752                                 if (rev < 6) {
2753                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2754                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2755                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2756                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2757                                 } else {
2758                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2759                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2760                                         if (entries && voltage_table_offset) {
2761                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2762                                                         RBIOS16(voltage_table_offset) * 4;
2763                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2764                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2765                                         } else
2766                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2767                                 }
2768                                 switch ((misc2 & 0x700) >> 8) {
2769                                 case 0:
2770                                 default:
2771                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2772                                         break;
2773                                 case 1:
2774                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2775                                         break;
2776                                 case 2:
2777                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2778                                         break;
2779                                 case 3:
2780                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2781                                         break;
2782                                 case 4:
2783                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2784                                         break;
2785                                 }
2786                         } else
2787                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2788                         if (rev > 6)
2789                                 rdev->pm.power_state[state_index].pcie_lanes =
2790                                         RBIOS8(offset + 0x5 + 0x10);
2791                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2792                         state_index++;
2793                 } else {
2794                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2795                 }
2796         } else {
2797                 /* XXX figure out some good default low power mode for desktop cards */
2798         }
2799
2800 default_mode:
2801         /* add the default mode */
2802         rdev->pm.power_state[state_index].type =
2803                 POWER_STATE_TYPE_DEFAULT;
2804         rdev->pm.power_state[state_index].num_clock_modes = 1;
2805         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2806         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2807         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2808         if ((state_index > 0) &&
2809             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2810                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2811                         rdev->pm.power_state[0].clock_info[0].voltage;
2812         else
2813                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2814         rdev->pm.power_state[state_index].pcie_lanes = 16;
2815         rdev->pm.power_state[state_index].flags = 0;
2816         rdev->pm.default_power_state_index = state_index;
2817         rdev->pm.num_power_states = state_index + 1;
2818
2819         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2820         rdev->pm.current_clock_mode_index = 0;
2821         return;
2822
2823 pm_failed:
2824         rdev->pm.default_power_state_index = state_index;
2825         rdev->pm.num_power_states = 0;
2826
2827         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2828         rdev->pm.current_clock_mode_index = 0;
2829 }
2830
2831 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2832 {
2833         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2834         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2835
2836         if (!tmds)
2837                 return;
2838
2839         switch (tmds->dvo_chip) {
2840         case DVO_SIL164:
2841                 /* sil 164 */
2842                 radeon_i2c_put_byte(tmds->i2c_bus,
2843                                     tmds->slave_addr,
2844                                     0x08, 0x30);
2845                 radeon_i2c_put_byte(tmds->i2c_bus,
2846                                        tmds->slave_addr,
2847                                        0x09, 0x00);
2848                 radeon_i2c_put_byte(tmds->i2c_bus,
2849                                     tmds->slave_addr,
2850                                     0x0a, 0x90);
2851                 radeon_i2c_put_byte(tmds->i2c_bus,
2852                                     tmds->slave_addr,
2853                                     0x0c, 0x89);
2854                 radeon_i2c_put_byte(tmds->i2c_bus,
2855                                        tmds->slave_addr,
2856                                        0x08, 0x3b);
2857                 break;
2858         case DVO_SIL1178:
2859                 /* sil 1178 - untested */
2860                 /*
2861                  * 0x0f, 0x44
2862                  * 0x0f, 0x4c
2863                  * 0x0e, 0x01
2864                  * 0x0a, 0x80
2865                  * 0x09, 0x30
2866                  * 0x0c, 0xc9
2867                  * 0x0d, 0x70
2868                  * 0x08, 0x32
2869                  * 0x08, 0x33
2870                  */
2871                 break;
2872         default:
2873                 break;
2874         }
2875
2876 }
2877
2878 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2879 {
2880         struct drm_device *dev = encoder->dev;
2881         struct radeon_device *rdev = dev->dev_private;
2882         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2883         uint16_t offset;
2884         uint8_t blocks, slave_addr, rev;
2885         uint32_t index, id;
2886         uint32_t reg, val, and_mask, or_mask;
2887         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2888
2889         if (!tmds)
2890                 return false;
2891
2892         if (rdev->flags & RADEON_IS_IGP) {
2893                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2894                 rev = RBIOS8(offset);
2895                 if (offset) {
2896                         rev = RBIOS8(offset);
2897                         if (rev > 1) {
2898                                 blocks = RBIOS8(offset + 3);
2899                                 index = offset + 4;
2900                                 while (blocks > 0) {
2901                                         id = RBIOS16(index);
2902                                         index += 2;
2903                                         switch (id >> 13) {
2904                                         case 0:
2905                                                 reg = (id & 0x1fff) * 4;
2906                                                 val = RBIOS32(index);
2907                                                 index += 4;
2908                                                 WREG32(reg, val);
2909                                                 break;
2910                                         case 2:
2911                                                 reg = (id & 0x1fff) * 4;
2912                                                 and_mask = RBIOS32(index);
2913                                                 index += 4;
2914                                                 or_mask = RBIOS32(index);
2915                                                 index += 4;
2916                                                 val = RREG32(reg);
2917                                                 val = (val & and_mask) | or_mask;
2918                                                 WREG32(reg, val);
2919                                                 break;
2920                                         case 3:
2921                                                 val = RBIOS16(index);
2922                                                 index += 2;
2923                                                 udelay(val);
2924                                                 break;
2925                                         case 4:
2926                                                 val = RBIOS16(index);
2927                                                 index += 2;
2928                                                 mdelay(val);
2929                                                 break;
2930                                         case 6:
2931                                                 slave_addr = id & 0xff;
2932                                                 slave_addr >>= 1; /* 7 bit addressing */
2933                                                 index++;
2934                                                 reg = RBIOS8(index);
2935                                                 index++;
2936                                                 val = RBIOS8(index);
2937                                                 index++;
2938                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2939                                                                     slave_addr,
2940                                                                     reg, val);
2941                                                 break;
2942                                         default:
2943                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2944                                                 break;
2945                                         }
2946                                         blocks--;
2947                                 }
2948                                 return true;
2949                         }
2950                 }
2951         } else {
2952                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2953                 if (offset) {
2954                         index = offset + 10;
2955                         id = RBIOS16(index);
2956                         while (id != 0xffff) {
2957                                 index += 2;
2958                                 switch (id >> 13) {
2959                                 case 0:
2960                                         reg = (id & 0x1fff) * 4;
2961                                         val = RBIOS32(index);
2962                                         WREG32(reg, val);
2963                                         break;
2964                                 case 2:
2965                                         reg = (id & 0x1fff) * 4;
2966                                         and_mask = RBIOS32(index);
2967                                         index += 4;
2968                                         or_mask = RBIOS32(index);
2969                                         index += 4;
2970                                         val = RREG32(reg);
2971                                         val = (val & and_mask) | or_mask;
2972                                         WREG32(reg, val);
2973                                         break;
2974                                 case 4:
2975                                         val = RBIOS16(index);
2976                                         index += 2;
2977                                         udelay(val);
2978                                         break;
2979                                 case 5:
2980                                         reg = id & 0x1fff;
2981                                         and_mask = RBIOS32(index);
2982                                         index += 4;
2983                                         or_mask = RBIOS32(index);
2984                                         index += 4;
2985                                         val = RREG32_PLL(reg);
2986                                         val = (val & and_mask) | or_mask;
2987                                         WREG32_PLL(reg, val);
2988                                         break;
2989                                 case 6:
2990                                         reg = id & 0x1fff;
2991                                         val = RBIOS8(index);
2992                                         index += 1;
2993                                         radeon_i2c_put_byte(tmds->i2c_bus,
2994                                                             tmds->slave_addr,
2995                                                             reg, val);
2996                                         break;
2997                                 default:
2998                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2999                                         break;
3000                                 }
3001                                 id = RBIOS16(index);
3002                         }
3003                         return true;
3004                 }
3005         }
3006         return false;
3007 }
3008
3009 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3010 {
3011         struct radeon_device *rdev = dev->dev_private;
3012
3013         if (offset) {
3014                 while (RBIOS16(offset)) {
3015                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3016                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3017                         uint32_t val, and_mask, or_mask;
3018                         uint32_t tmp;
3019
3020                         offset += 2;
3021                         switch (cmd) {
3022                         case 0:
3023                                 val = RBIOS32(offset);
3024                                 offset += 4;
3025                                 WREG32(addr, val);
3026                                 break;
3027                         case 1:
3028                                 val = RBIOS32(offset);
3029                                 offset += 4;
3030                                 WREG32(addr, val);
3031                                 break;
3032                         case 2:
3033                                 and_mask = RBIOS32(offset);
3034                                 offset += 4;
3035                                 or_mask = RBIOS32(offset);
3036                                 offset += 4;
3037                                 tmp = RREG32(addr);
3038                                 tmp &= and_mask;
3039                                 tmp |= or_mask;
3040                                 WREG32(addr, tmp);
3041                                 break;
3042                         case 3:
3043                                 and_mask = RBIOS32(offset);
3044                                 offset += 4;
3045                                 or_mask = RBIOS32(offset);
3046                                 offset += 4;
3047                                 tmp = RREG32(addr);
3048                                 tmp &= and_mask;
3049                                 tmp |= or_mask;
3050                                 WREG32(addr, tmp);
3051                                 break;
3052                         case 4:
3053                                 val = RBIOS16(offset);
3054                                 offset += 2;
3055                                 udelay(val);
3056                                 break;
3057                         case 5:
3058                                 val = RBIOS16(offset);
3059                                 offset += 2;
3060                                 switch (addr) {
3061                                 case 8:
3062                                         while (val--) {
3063                                                 if (!
3064                                                     (RREG32_PLL
3065                                                      (RADEON_CLK_PWRMGT_CNTL) &
3066                                                      RADEON_MC_BUSY))
3067                                                         break;
3068                                         }
3069                                         break;
3070                                 case 9:
3071                                         while (val--) {
3072                                                 if ((RREG32(RADEON_MC_STATUS) &
3073                                                      RADEON_MC_IDLE))
3074                                                         break;
3075                                         }
3076                                         break;
3077                                 default:
3078                                         break;
3079                                 }
3080                                 break;
3081                         default:
3082                                 break;
3083                         }
3084                 }
3085         }
3086 }
3087
3088 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3089 {
3090         struct radeon_device *rdev = dev->dev_private;
3091
3092         if (offset) {
3093                 while (RBIOS8(offset)) {
3094                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3095                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3096                         uint32_t val, shift, tmp;
3097                         uint32_t and_mask, or_mask;
3098
3099                         offset++;
3100                         switch (cmd) {
3101                         case 0:
3102                                 val = RBIOS32(offset);
3103                                 offset += 4;
3104                                 WREG32_PLL(addr, val);
3105                                 break;
3106                         case 1:
3107                                 shift = RBIOS8(offset) * 8;
3108                                 offset++;
3109                                 and_mask = RBIOS8(offset) << shift;
3110                                 and_mask |= ~(0xff << shift);
3111                                 offset++;
3112                                 or_mask = RBIOS8(offset) << shift;
3113                                 offset++;
3114                                 tmp = RREG32_PLL(addr);
3115                                 tmp &= and_mask;
3116                                 tmp |= or_mask;
3117                                 WREG32_PLL(addr, tmp);
3118                                 break;
3119                         case 2:
3120                         case 3:
3121                                 tmp = 1000;
3122                                 switch (addr) {
3123                                 case 1:
3124                                         udelay(150);
3125                                         break;
3126                                 case 2:
3127                                         mdelay(1);
3128                                         break;
3129                                 case 3:
3130                                         while (tmp--) {
3131                                                 if (!
3132                                                     (RREG32_PLL
3133                                                      (RADEON_CLK_PWRMGT_CNTL) &
3134                                                      RADEON_MC_BUSY))
3135                                                         break;
3136                                         }
3137                                         break;
3138                                 case 4:
3139                                         while (tmp--) {
3140                                                 if (RREG32_PLL
3141                                                     (RADEON_CLK_PWRMGT_CNTL) &
3142                                                     RADEON_DLL_READY)
3143                                                         break;
3144                                         }
3145                                         break;
3146                                 case 5:
3147                                         tmp =
3148                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3149                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3150 #if 0
3151                                                 uint32_t mclk_cntl =
3152                                                     RREG32_PLL
3153                                                     (RADEON_MCLK_CNTL);
3154                                                 mclk_cntl &= 0xffff0000;
3155                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3156                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3157                                                            mclk_cntl);
3158                                                 mdelay(10);
3159 #endif
3160                                                 WREG32_PLL
3161                                                     (RADEON_CLK_PWRMGT_CNTL,
3162                                                      tmp &
3163                                                      ~RADEON_CG_NO1_DEBUG_0);
3164                                                 mdelay(10);
3165                                         }
3166                                         break;
3167                                 default:
3168                                         break;
3169                                 }
3170                                 break;
3171                         default:
3172                                 break;
3173                         }
3174                 }
3175         }
3176 }
3177
3178 static void combios_parse_ram_reset_table(struct drm_device *dev,
3179                                           uint16_t offset)
3180 {
3181         struct radeon_device *rdev = dev->dev_private;
3182         uint32_t tmp;
3183
3184         if (offset) {
3185                 uint8_t val = RBIOS8(offset);
3186                 while (val != 0xff) {
3187                         offset++;
3188
3189                         if (val == 0x0f) {
3190                                 uint32_t channel_complete_mask;
3191
3192                                 if (ASIC_IS_R300(rdev))
3193                                         channel_complete_mask =
3194                                             R300_MEM_PWRUP_COMPLETE;
3195                                 else
3196                                         channel_complete_mask =
3197                                             RADEON_MEM_PWRUP_COMPLETE;
3198                                 tmp = 20000;
3199                                 while (tmp--) {
3200                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3201                                              channel_complete_mask) ==
3202                                             channel_complete_mask)
3203                                                 break;
3204                                 }
3205                         } else {
3206                                 uint32_t or_mask = RBIOS16(offset);
3207                                 offset += 2;
3208
3209                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3210                                 tmp &= RADEON_SDRAM_MODE_MASK;
3211                                 tmp |= or_mask;
3212                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3213
3214                                 or_mask = val << 24;
3215                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3216                                 tmp &= RADEON_B3MEM_RESET_MASK;
3217                                 tmp |= or_mask;
3218                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3219                         }
3220                         val = RBIOS8(offset);
3221                 }
3222         }
3223 }
3224
3225 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3226                                    int mem_addr_mapping)
3227 {
3228         struct radeon_device *rdev = dev->dev_private;
3229         uint32_t mem_cntl;
3230         uint32_t mem_size;
3231         uint32_t addr = 0;
3232
3233         mem_cntl = RREG32(RADEON_MEM_CNTL);
3234         if (mem_cntl & RV100_HALF_MODE)
3235                 ram /= 2;
3236         mem_size = ram;
3237         mem_cntl &= ~(0xff << 8);
3238         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3239         WREG32(RADEON_MEM_CNTL, mem_cntl);
3240         RREG32(RADEON_MEM_CNTL);
3241
3242         /* sdram reset ? */
3243
3244         /* something like this????  */
3245         while (ram--) {
3246                 addr = ram * 1024 * 1024;
3247                 /* write to each page */
3248                 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3249                 /* read back and verify */
3250                 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3251                         return 0;
3252         }
3253
3254         return mem_size;
3255 }
3256
3257 static void combios_write_ram_size(struct drm_device *dev)
3258 {
3259         struct radeon_device *rdev = dev->dev_private;
3260         uint8_t rev;
3261         uint16_t offset;
3262         uint32_t mem_size = 0;
3263         uint32_t mem_cntl = 0;
3264
3265         /* should do something smarter here I guess... */
3266         if (rdev->flags & RADEON_IS_IGP)
3267                 return;
3268
3269         /* first check detected mem table */
3270         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3271         if (offset) {
3272                 rev = RBIOS8(offset);
3273                 if (rev < 3) {
3274                         mem_cntl = RBIOS32(offset + 1);
3275                         mem_size = RBIOS16(offset + 5);
3276                         if ((rdev->family < CHIP_R200) &&
3277                             !ASIC_IS_RN50(rdev))
3278                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3279                 }
3280         }
3281
3282         if (!mem_size) {
3283                 offset =
3284                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3285                 if (offset) {
3286                         rev = RBIOS8(offset - 1);
3287                         if (rev < 1) {
3288                                 if ((rdev->family < CHIP_R200)
3289                                     && !ASIC_IS_RN50(rdev)) {
3290                                         int ram = 0;
3291                                         int mem_addr_mapping = 0;
3292
3293                                         while (RBIOS8(offset)) {
3294                                                 ram = RBIOS8(offset);
3295                                                 mem_addr_mapping =
3296                                                     RBIOS8(offset + 1);
3297                                                 if (mem_addr_mapping != 0x25)
3298                                                         ram *= 2;
3299                                                 mem_size =
3300                                                     combios_detect_ram(dev, ram,
3301                                                                        mem_addr_mapping);
3302                                                 if (mem_size)
3303                                                         break;
3304                                                 offset += 2;
3305                                         }
3306                                 } else
3307                                         mem_size = RBIOS8(offset);
3308                         } else {
3309                                 mem_size = RBIOS8(offset);
3310                                 mem_size *= 2;  /* convert to MB */
3311                         }
3312                 }
3313         }
3314
3315         mem_size *= (1024 * 1024);      /* convert to bytes */
3316         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3317 }
3318
3319 void radeon_combios_asic_init(struct drm_device *dev)
3320 {
3321         struct radeon_device *rdev = dev->dev_private;
3322         uint16_t table;
3323
3324         /* port hardcoded mac stuff from radeonfb */
3325         if (rdev->bios == NULL)
3326                 return;
3327
3328         /* ASIC INIT 1 */
3329         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3330         if (table)
3331                 combios_parse_mmio_table(dev, table);
3332
3333         /* PLL INIT */
3334         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3335         if (table)
3336                 combios_parse_pll_table(dev, table);
3337
3338         /* ASIC INIT 2 */
3339         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3340         if (table)
3341                 combios_parse_mmio_table(dev, table);
3342
3343         if (!(rdev->flags & RADEON_IS_IGP)) {
3344                 /* ASIC INIT 4 */
3345                 table =
3346                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3347                 if (table)
3348                         combios_parse_mmio_table(dev, table);
3349
3350                 /* RAM RESET */
3351                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3352                 if (table)
3353                         combios_parse_ram_reset_table(dev, table);
3354
3355                 /* ASIC INIT 3 */
3356                 table =
3357                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3358                 if (table)
3359                         combios_parse_mmio_table(dev, table);
3360
3361                 /* write CONFIG_MEMSIZE */
3362                 combios_write_ram_size(dev);
3363         }
3364
3365         /* quirk for rs4xx HP nx6125 laptop to make it resume
3366          * - it hangs on resume inside the dynclk 1 table.
3367          */
3368         if (rdev->family == CHIP_RS480 &&
3369             rdev->pdev->subsystem_vendor == 0x103c &&
3370             rdev->pdev->subsystem_device == 0x308b)
3371                 return;
3372
3373         /* quirk for rs4xx HP dv5000 laptop to make it resume
3374          * - it hangs on resume inside the dynclk 1 table.
3375          */
3376         if (rdev->family == CHIP_RS480 &&
3377             rdev->pdev->subsystem_vendor == 0x103c &&
3378             rdev->pdev->subsystem_device == 0x30a4)
3379                 return;
3380
3381         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3382          * - it hangs on resume inside the dynclk 1 table.
3383          */
3384         if (rdev->family == CHIP_RS480 &&
3385             rdev->pdev->subsystem_vendor == 0x103c &&
3386             rdev->pdev->subsystem_device == 0x30ae)
3387                 return;
3388
3389         /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3390          * - it hangs on resume inside the dynclk 1 table.
3391          */
3392         if (rdev->family == CHIP_RS480 &&
3393             rdev->pdev->subsystem_vendor == 0x103c &&
3394             rdev->pdev->subsystem_device == 0x280a)
3395                 return;
3396
3397         /* DYN CLK 1 */
3398         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3399         if (table)
3400                 combios_parse_pll_table(dev, table);
3401
3402 }
3403
3404 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3405 {
3406         struct radeon_device *rdev = dev->dev_private;
3407         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3408
3409         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3410         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3411         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3412
3413         /* let the bios control the backlight */
3414         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3415
3416         /* tell the bios not to handle mode switching */
3417         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3418                            RADEON_ACC_MODE_CHANGE);
3419
3420         /* tell the bios a driver is loaded */
3421         bios_7_scratch |= RADEON_DRV_LOADED;
3422
3423         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3424         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3425         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3426 }
3427
3428 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3429 {
3430         struct drm_device *dev = encoder->dev;
3431         struct radeon_device *rdev = dev->dev_private;
3432         uint32_t bios_6_scratch;
3433
3434         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3435
3436         if (lock)
3437                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3438         else
3439                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3440
3441         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3442 }
3443
3444 void
3445 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3446                                       struct drm_encoder *encoder,
3447                                       bool connected)
3448 {
3449         struct drm_device *dev = connector->dev;
3450         struct radeon_device *rdev = dev->dev_private;
3451         struct radeon_connector *radeon_connector =
3452             to_radeon_connector(connector);
3453         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3454         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3455         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3456
3457         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3458             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3459                 if (connected) {
3460                         DRM_DEBUG_KMS("TV1 connected\n");
3461                         /* fix me */
3462                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3463                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3464                         bios_5_scratch |= RADEON_TV1_ON;
3465                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3466                 } else {
3467                         DRM_DEBUG_KMS("TV1 disconnected\n");
3468                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3469                         bios_5_scratch &= ~RADEON_TV1_ON;
3470                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3471                 }
3472         }
3473         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3474             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3475                 if (connected) {
3476                         DRM_DEBUG_KMS("LCD1 connected\n");
3477                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3478                         bios_5_scratch |= RADEON_LCD1_ON;
3479                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3480                 } else {
3481                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3482                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3483                         bios_5_scratch &= ~RADEON_LCD1_ON;
3484                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3485                 }
3486         }
3487         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3488             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3489                 if (connected) {
3490                         DRM_DEBUG_KMS("CRT1 connected\n");
3491                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3492                         bios_5_scratch |= RADEON_CRT1_ON;
3493                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3494                 } else {
3495                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3496                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3497                         bios_5_scratch &= ~RADEON_CRT1_ON;
3498                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3499                 }
3500         }
3501         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3502             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3503                 if (connected) {
3504                         DRM_DEBUG_KMS("CRT2 connected\n");
3505                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3506                         bios_5_scratch |= RADEON_CRT2_ON;
3507                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3508                 } else {
3509                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3510                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3511                         bios_5_scratch &= ~RADEON_CRT2_ON;
3512                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3513                 }
3514         }
3515         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3516             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3517                 if (connected) {
3518                         DRM_DEBUG_KMS("DFP1 connected\n");
3519                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3520                         bios_5_scratch |= RADEON_DFP1_ON;
3521                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3522                 } else {
3523                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3524                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3525                         bios_5_scratch &= ~RADEON_DFP1_ON;
3526                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3527                 }
3528         }
3529         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3530             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3531                 if (connected) {
3532                         DRM_DEBUG_KMS("DFP2 connected\n");
3533                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3534                         bios_5_scratch |= RADEON_DFP2_ON;
3535                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3536                 } else {
3537                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3538                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3539                         bios_5_scratch &= ~RADEON_DFP2_ON;
3540                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3541                 }
3542         }
3543         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3544         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3545 }
3546
3547 void
3548 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3549 {
3550         struct drm_device *dev = encoder->dev;
3551         struct radeon_device *rdev = dev->dev_private;
3552         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3553         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3554
3555         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3556                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3557                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3558         }
3559         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3560                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3561                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3562         }
3563         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3564                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3565                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3566         }
3567         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3568                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3569                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3570         }
3571         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3572                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3573                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3574         }
3575         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3576                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3577                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3578         }
3579         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3580 }
3581
3582 void
3583 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3584 {
3585         struct drm_device *dev = encoder->dev;
3586         struct radeon_device *rdev = dev->dev_private;
3587         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3588         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3589
3590         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3591                 if (on)
3592                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3593                 else
3594                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3595         }
3596         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3597                 if (on)
3598                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3599                 else
3600                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3601         }
3602         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3603                 if (on)
3604                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3605                 else
3606                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3607         }
3608         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3609                 if (on)
3610                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3611                 else
3612                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3613         }
3614         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3615 }