drivers/gpu/drm/tilcdc/tilcdc_drv.h

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __TILCDC_DRV_H__
  19 #define __TILCDC_DRV_H__
  20
  21 #include <linux/clk.h>
  22 #include <linux/cpufreq.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/slab.h>
  28 #include <linux/of.h>
  29 #include <linux/of_device.h>
  30 #include <linux/list.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_gem_cma_helper.h>
  35 #include <drm/drm_fb_cma_helper.h>
  36 #include <drm/drm_bridge.h>
  37
  38 /* Defaulting to pixel clock defined on AM335x */
  39 #define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
  40 /* Defaulting to max width as defined on AM335x */
  41 #define TILCDC_DEFAULT_MAX_WIDTH  2048
  42 /*
  43  * This may need some tweaking, but want to allow at least 1280x1024@60
  44  * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
  45  * be supportable
  46  */
  47 #define TILCDC_DEFAULT_MAX_BANDWIDTH  (1280*1024*60)
  48
  49
  50 struct tilcdc_drm_private {
  51         void __iomem *mmio;
  52
  53         struct clk *clk;         /* functional clock */
  54         int rev;                 /* IP revision */
  55
  56         /* don't attempt resolutions w/ higher W * H * Hz: */
  57         uint32_t max_bandwidth;
  58         /*
  59          * Pixel Clock will be restricted to some value as
  60          * defined in the device datasheet measured in KHz
  61          */
  62         uint32_t max_pixelclock;
  63         /*
  64          * Max allowable width is limited on a per device basis
  65          * measured in pixels
  66          */
  67         uint32_t max_width;
  68
  69         /* Supported pixel formats */
  70         const uint32_t *pixelformats;
  71         uint32_t num_pixelformats;
  72
  73         /* The context for pm susped/resume cycle is stored here */
  74         struct drm_atomic_state *saved_state;
  75
  76 #ifdef CONFIG_CPU_FREQ
  77         struct notifier_block freq_transition;
  78 #endif
  79
  80         struct workqueue_struct *wq;
  81
  82         struct drm_fbdev_cma *fbdev;
  83
  84         struct drm_crtc *crtc;
  85
  86         unsigned int num_encoders;
  87         struct drm_encoder *encoders[8];
  88
  89         unsigned int num_connectors;
  90         struct drm_connector *connectors[8];
  91
  92         struct drm_encoder *external_encoder;
  93         struct drm_connector *external_connector;
  94         const struct drm_connector_helper_funcs *connector_funcs;
  95
  96         bool is_registered;
  97         bool is_componentized;
  98 };
  99
 100 /* Sub-module for display.  Since we don't know at compile time what panels
 101  * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
 102  * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
 103  * separate drivers.  If they are probed and found to be present, they
 104  * register themselves with tilcdc_register_module().
 105  */
 106 struct tilcdc_module;
 107
 108 struct tilcdc_module_ops {
 109         /* create appropriate encoders/connectors: */
 110         int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
 111 #ifdef CONFIG_DEBUG_FS
 112         /* create debugfs nodes (can be NULL): */
 113         int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
 114         /* cleanup debugfs nodes (can be NULL): */
 115         void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
 116 #endif
 117 };
 118
 119 struct tilcdc_module {
 120         const char *name;
 121         struct list_head list;
 122         const struct tilcdc_module_ops *funcs;
 123 };
 124
 125 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
 126                 const struct tilcdc_module_ops *funcs);
 127 void tilcdc_module_cleanup(struct tilcdc_module *mod);
 128
 129 /* Panel config that needs to be set in the crtc, but is not coming from
 130  * the mode timings.  The display module is expected to call
 131  * tilcdc_crtc_set_panel_info() to set this during modeset.
 132  */
 133 struct tilcdc_panel_info {
 134
 135         /* AC Bias Pin Frequency */
 136         uint32_t ac_bias;
 137
 138         /* AC Bias Pin Transitions per Interrupt */
 139         uint32_t ac_bias_intrpt;
 140
 141         /* DMA burst size */
 142         uint32_t dma_burst_sz;
 143
 144         /* Bits per pixel */
 145         uint32_t bpp;
 146
 147         /* FIFO DMA Request Delay */
 148         uint32_t fdd;
 149
 150         /* TFT Alternative Signal Mapping (Only for active) */
 151         bool tft_alt_mode;
 152
 153         /* Invert pixel clock */
 154         bool invert_pxl_clk;
 155
 156         /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
 157         uint32_t sync_edge;
 158
 159         /* Horizontal and Vertical Sync: Control: 0=ignore */
 160         uint32_t sync_ctrl;
 161
 162         /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
 163         uint32_t raster_order;
 164
 165         /* DMA FIFO threshold */
 166         uint32_t fifo_th;
 167 };
 168
 169 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 170
 171 int tilcdc_crtc_create(struct drm_device *dev);
 172 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
 173 void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
 174 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 175                 const struct tilcdc_panel_info *info);
 176 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 177                                         bool simulate_vesa_sync);
 178 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
 179 int tilcdc_crtc_max_width(struct drm_crtc *crtc);
 180 void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
 181 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 182                 struct drm_framebuffer *fb,
 183                 struct drm_pending_vblank_event *event);
 184
 185 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
 186
 187 #endif /* __TILCDC_DRV_H__ */