5 ForeRunnerHE ATM Adapter driver for ATM on Linux
6 Copyright (C) 1999-2001 Naval Research Laboratory
8 This library is free software; you can redistribute it and/or
9 modify it under the terms of the GNU Lesser General Public
10 License as published by the Free Software Foundation; either
11 version 2.1 of the License, or (at your option) any later version.
13 This library is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 Lesser General Public License for more details.
18 You should have received a copy of the GNU Lesser General Public
19 License along with this library; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 ForeRunnerHE ATM Adapter driver for ATM on Linux
29 Copyright (C) 1999-2001 Naval Research Laboratory
31 Permission to use, copy, modify and distribute this software and its
32 documentation is hereby granted, provided that both the copyright
33 notice and this permission notice appear in all copies of the software,
34 derivative works or modified versions, and any portions thereof, and
35 that both notices appear in supporting documentation.
37 NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
38 DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
39 RESULTING FROM THE USE OF THIS SOFTWARE.
41 This driver was written using the "Programmer's Reference Manual for
42 ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.
45 chas williams <chas@cmf.nrl.navy.mil>
46 eric kinzie <ekinzie@cmf.nrl.navy.mil>
49 4096 supported 'connections'
50 group 0 is used for all traffic
51 interrupt queue 0 is used for all interrupts
52 aal0 support (based on work from ulrich.u.muller@nokia.com)
56 #include <linux/module.h>
57 #include <linux/kernel.h>
58 #include <linux/skbuff.h>
59 #include <linux/pci.h>
60 #include <linux/errno.h>
61 #include <linux/types.h>
62 #include <linux/string.h>
63 #include <linux/delay.h>
64 #include <linux/init.h>
66 #include <linux/sched.h>
67 #include <linux/timer.h>
68 #include <linux/interrupt.h>
69 #include <linux/dma-mapping.h>
70 #include <linux/bitmap.h>
71 #include <linux/slab.h>
73 #include <asm/byteorder.h>
74 #include <asm/uaccess.h>
76 #include <linux/atmdev.h>
77 #include <linux/atm.h>
78 #include <linux/sonet.h>
80 #undef USE_SCATTERGATHER
81 #undef USE_CHECKSUM_HW /* still confused about this */
86 #include <linux/atm_he.h>
88 #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
91 #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
93 #define HPRINTK(fmt,args...) do { } while (0)
98 static int he_open(struct atm_vcc
*vcc
);
99 static void he_close(struct atm_vcc
*vcc
);
100 static int he_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
);
101 static int he_ioctl(struct atm_dev
*dev
, unsigned int cmd
, void __user
*arg
);
102 static irqreturn_t
he_irq_handler(int irq
, void *dev_id
);
103 static void he_tasklet(unsigned long data
);
104 static int he_proc_read(struct atm_dev
*dev
,loff_t
*pos
,char *page
);
105 static int he_start(struct atm_dev
*dev
);
106 static void he_stop(struct he_dev
*dev
);
107 static void he_phy_put(struct atm_dev
*, unsigned char, unsigned long);
108 static unsigned char he_phy_get(struct atm_dev
*, unsigned long);
110 static u8
read_prom_byte(struct he_dev
*he_dev
, int addr
);
114 static struct he_dev
*he_devs
;
115 static bool disable64
;
116 static short nvpibits
= -1;
117 static short nvcibits
= -1;
118 static short rx_skb_reserve
= 16;
119 static bool irq_coalesce
= 1;
122 /* Read from EEPROM = 0000 0011b */
123 static unsigned int readtab
[] = {
138 CLK_HIGH
| SI_HIGH
, /* 1 */
140 CLK_HIGH
| SI_HIGH
/* 1 */
143 /* Clock to read from/write to the EEPROM */
144 static unsigned int clocktab
[] = {
164 static struct atmdev_ops he_ops
=
170 .phy_put
= he_phy_put
,
171 .phy_get
= he_phy_get
,
172 .proc_read
= he_proc_read
,
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
177 #define he_readl(dev, reg) readl((dev)->membase + (reg))
179 /* section 2.12 connection memory access */
181 static __inline__
void
182 he_writel_internal(struct he_dev
*he_dev
, unsigned val
, unsigned addr
,
185 he_writel(he_dev
, val
, CON_DAT
);
186 (void) he_readl(he_dev
, CON_DAT
); /* flush posted writes */
187 he_writel(he_dev
, flags
| CON_CTL_WRITE
| CON_CTL_ADDR(addr
), CON_CTL
);
188 while (he_readl(he_dev
, CON_CTL
) & CON_CTL_BUSY
);
191 #define he_writel_rcm(dev, val, reg) \
192 he_writel_internal(dev, val, reg, CON_CTL_RCM)
194 #define he_writel_tcm(dev, val, reg) \
195 he_writel_internal(dev, val, reg, CON_CTL_TCM)
197 #define he_writel_mbox(dev, val, reg) \
198 he_writel_internal(dev, val, reg, CON_CTL_MBOX)
201 he_readl_internal(struct he_dev
*he_dev
, unsigned addr
, unsigned flags
)
203 he_writel(he_dev
, flags
| CON_CTL_READ
| CON_CTL_ADDR(addr
), CON_CTL
);
204 while (he_readl(he_dev
, CON_CTL
) & CON_CTL_BUSY
);
205 return he_readl(he_dev
, CON_DAT
);
208 #define he_readl_rcm(dev, reg) \
209 he_readl_internal(dev, reg, CON_CTL_RCM)
211 #define he_readl_tcm(dev, reg) \
212 he_readl_internal(dev, reg, CON_CTL_TCM)
214 #define he_readl_mbox(dev, reg) \
215 he_readl_internal(dev, reg, CON_CTL_MBOX)
218 /* figure 2.2 connection id */
220 #define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
222 /* 2.5.1 per connection transmit state registers */
224 #define he_writel_tsr0(dev, val, cid) \
225 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
226 #define he_readl_tsr0(dev, cid) \
227 he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
229 #define he_writel_tsr1(dev, val, cid) \
230 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
232 #define he_writel_tsr2(dev, val, cid) \
233 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
235 #define he_writel_tsr3(dev, val, cid) \
236 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
238 #define he_writel_tsr4(dev, val, cid) \
239 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
243 * NOTE While the transmit connection is active, bits 23 through 0
244 * of this register must not be written by the host. Byte
245 * enables should be used during normal operation when writing
246 * the most significant byte.
249 #define he_writel_tsr4_upper(dev, val, cid) \
250 he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
252 | CON_BYTE_DISABLE_2 \
253 | CON_BYTE_DISABLE_1 \
254 | CON_BYTE_DISABLE_0)
256 #define he_readl_tsr4(dev, cid) \
257 he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
259 #define he_writel_tsr5(dev, val, cid) \
260 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
262 #define he_writel_tsr6(dev, val, cid) \
263 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
265 #define he_writel_tsr7(dev, val, cid) \
266 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
269 #define he_writel_tsr8(dev, val, cid) \
270 he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
272 #define he_writel_tsr9(dev, val, cid) \
273 he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
275 #define he_writel_tsr10(dev, val, cid) \
276 he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
278 #define he_writel_tsr11(dev, val, cid) \
279 he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
282 #define he_writel_tsr12(dev, val, cid) \
283 he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
285 #define he_writel_tsr13(dev, val, cid) \
286 he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
289 #define he_writel_tsr14(dev, val, cid) \
290 he_writel_tcm(dev, val, CONFIG_TSRD | cid)
292 #define he_writel_tsr14_upper(dev, val, cid) \
293 he_writel_internal(dev, val, CONFIG_TSRD | cid, \
295 | CON_BYTE_DISABLE_2 \
296 | CON_BYTE_DISABLE_1 \
297 | CON_BYTE_DISABLE_0)
299 /* 2.7.1 per connection receive state registers */
301 #define he_writel_rsr0(dev, val, cid) \
302 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
303 #define he_readl_rsr0(dev, cid) \
304 he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
306 #define he_writel_rsr1(dev, val, cid) \
307 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
309 #define he_writel_rsr2(dev, val, cid) \
310 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
312 #define he_writel_rsr3(dev, val, cid) \
313 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
315 #define he_writel_rsr4(dev, val, cid) \
316 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
318 #define he_writel_rsr5(dev, val, cid) \
319 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
321 #define he_writel_rsr6(dev, val, cid) \
322 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
324 #define he_writel_rsr7(dev, val, cid) \
325 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
327 static __inline__
struct atm_vcc
*
328 __find_vcc(struct he_dev
*he_dev
, unsigned cid
)
330 struct hlist_head
*head
;
336 vpi
= cid
>> he_dev
->vcibits
;
337 vci
= cid
& ((1 << he_dev
->vcibits
) - 1);
338 head
= &vcc_hash
[vci
& (VCC_HTABLE_SIZE
-1)];
340 sk_for_each(s
, head
) {
342 if (vcc
->dev
== he_dev
->atm_dev
&&
343 vcc
->vci
== vci
&& vcc
->vpi
== vpi
&&
344 vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
351 static int he_init_one(struct pci_dev
*pci_dev
,
352 const struct pci_device_id
*pci_ent
)
354 struct atm_dev
*atm_dev
= NULL
;
355 struct he_dev
*he_dev
= NULL
;
358 printk(KERN_INFO
"ATM he driver\n");
360 if (pci_enable_device(pci_dev
))
362 if (pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(32)) != 0) {
363 printk(KERN_WARNING
"he: no suitable dma available\n");
365 goto init_one_failure
;
368 atm_dev
= atm_dev_register(DEV_LABEL
, &pci_dev
->dev
, &he_ops
, -1, NULL
);
371 goto init_one_failure
;
373 pci_set_drvdata(pci_dev
, atm_dev
);
375 he_dev
= kzalloc(sizeof(struct he_dev
),
379 goto init_one_failure
;
381 he_dev
->pci_dev
= pci_dev
;
382 he_dev
->atm_dev
= atm_dev
;
383 he_dev
->atm_dev
->dev_data
= he_dev
;
384 atm_dev
->dev_data
= he_dev
;
385 he_dev
->number
= atm_dev
->number
;
386 tasklet_init(&he_dev
->tasklet
, he_tasklet
, (unsigned long) he_dev
);
387 spin_lock_init(&he_dev
->global_lock
);
389 if (he_start(atm_dev
)) {
392 goto init_one_failure
;
396 he_dev
->next
= he_devs
;
402 atm_dev_deregister(atm_dev
);
404 pci_disable_device(pci_dev
);
408 static void he_remove_one(struct pci_dev
*pci_dev
)
410 struct atm_dev
*atm_dev
;
411 struct he_dev
*he_dev
;
413 atm_dev
= pci_get_drvdata(pci_dev
);
414 he_dev
= HE_DEV(atm_dev
);
416 /* need to remove from he_devs */
419 atm_dev_deregister(atm_dev
);
422 pci_disable_device(pci_dev
);
427 rate_to_atmf(unsigned rate
) /* cps to atm forum format */
429 #define NONZERO (1 << 14)
437 while (rate
> 0x3ff) {
442 return (NONZERO
| (exp
<< 9) | (rate
& 0x1ff));
445 static void he_init_rx_lbfp0(struct he_dev
*he_dev
)
447 unsigned i
, lbm_offset
, lbufd_index
, lbuf_addr
, lbuf_count
;
448 unsigned lbufs_per_row
= he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
449 unsigned lbuf_bufsize
= he_dev
->cells_per_lbuf
* ATM_CELL_PAYLOAD
;
450 unsigned row_offset
= he_dev
->r0_startrow
* he_dev
->bytes_per_row
;
453 lbm_offset
= he_readl(he_dev
, RCMLBM_BA
);
455 he_writel(he_dev
, lbufd_index
, RLBF0_H
);
457 for (i
= 0, lbuf_count
= 0; i
< he_dev
->r0_numbuffs
; ++i
) {
459 lbuf_addr
= (row_offset
+ (lbuf_count
* lbuf_bufsize
)) / 32;
461 he_writel_rcm(he_dev
, lbuf_addr
, lbm_offset
);
462 he_writel_rcm(he_dev
, lbufd_index
, lbm_offset
+ 1);
464 if (++lbuf_count
== lbufs_per_row
) {
466 row_offset
+= he_dev
->bytes_per_row
;
471 he_writel(he_dev
, lbufd_index
- 2, RLBF0_T
);
472 he_writel(he_dev
, he_dev
->r0_numbuffs
, RLBF0_C
);
475 static void he_init_rx_lbfp1(struct he_dev
*he_dev
)
477 unsigned i
, lbm_offset
, lbufd_index
, lbuf_addr
, lbuf_count
;
478 unsigned lbufs_per_row
= he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
479 unsigned lbuf_bufsize
= he_dev
->cells_per_lbuf
* ATM_CELL_PAYLOAD
;
480 unsigned row_offset
= he_dev
->r1_startrow
* he_dev
->bytes_per_row
;
483 lbm_offset
= he_readl(he_dev
, RCMLBM_BA
) + (2 * lbufd_index
);
485 he_writel(he_dev
, lbufd_index
, RLBF1_H
);
487 for (i
= 0, lbuf_count
= 0; i
< he_dev
->r1_numbuffs
; ++i
) {
489 lbuf_addr
= (row_offset
+ (lbuf_count
* lbuf_bufsize
)) / 32;
491 he_writel_rcm(he_dev
, lbuf_addr
, lbm_offset
);
492 he_writel_rcm(he_dev
, lbufd_index
, lbm_offset
+ 1);
494 if (++lbuf_count
== lbufs_per_row
) {
496 row_offset
+= he_dev
->bytes_per_row
;
501 he_writel(he_dev
, lbufd_index
- 2, RLBF1_T
);
502 he_writel(he_dev
, he_dev
->r1_numbuffs
, RLBF1_C
);
505 static void he_init_tx_lbfp(struct he_dev
*he_dev
)
507 unsigned i
, lbm_offset
, lbufd_index
, lbuf_addr
, lbuf_count
;
508 unsigned lbufs_per_row
= he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
509 unsigned lbuf_bufsize
= he_dev
->cells_per_lbuf
* ATM_CELL_PAYLOAD
;
510 unsigned row_offset
= he_dev
->tx_startrow
* he_dev
->bytes_per_row
;
512 lbufd_index
= he_dev
->r0_numbuffs
+ he_dev
->r1_numbuffs
;
513 lbm_offset
= he_readl(he_dev
, RCMLBM_BA
) + (2 * lbufd_index
);
515 he_writel(he_dev
, lbufd_index
, TLBF_H
);
517 for (i
= 0, lbuf_count
= 0; i
< he_dev
->tx_numbuffs
; ++i
) {
519 lbuf_addr
= (row_offset
+ (lbuf_count
* lbuf_bufsize
)) / 32;
521 he_writel_rcm(he_dev
, lbuf_addr
, lbm_offset
);
522 he_writel_rcm(he_dev
, lbufd_index
, lbm_offset
+ 1);
524 if (++lbuf_count
== lbufs_per_row
) {
526 row_offset
+= he_dev
->bytes_per_row
;
531 he_writel(he_dev
, lbufd_index
- 1, TLBF_T
);
534 static int he_init_tpdrq(struct he_dev
*he_dev
)
536 he_dev
->tpdrq_base
= pci_zalloc_consistent(he_dev
->pci_dev
,
537 CONFIG_TPDRQ_SIZE
* sizeof(struct he_tpdrq
),
538 &he_dev
->tpdrq_phys
);
539 if (he_dev
->tpdrq_base
== NULL
) {
540 hprintk("failed to alloc tpdrq\n");
544 he_dev
->tpdrq_tail
= he_dev
->tpdrq_base
;
545 he_dev
->tpdrq_head
= he_dev
->tpdrq_base
;
547 he_writel(he_dev
, he_dev
->tpdrq_phys
, TPDRQ_B_H
);
548 he_writel(he_dev
, 0, TPDRQ_T
);
549 he_writel(he_dev
, CONFIG_TPDRQ_SIZE
- 1, TPDRQ_S
);
554 static void he_init_cs_block(struct he_dev
*he_dev
)
556 unsigned clock
, rate
, delta
;
559 /* 5.1.7 cs block initialization */
561 for (reg
= 0; reg
< 0x20; ++reg
)
562 he_writel_mbox(he_dev
, 0x0, CS_STTIM0
+ reg
);
564 /* rate grid timer reload values */
566 clock
= he_is622(he_dev
) ? 66667000 : 50000000;
567 rate
= he_dev
->atm_dev
->link_rate
;
568 delta
= rate
/ 16 / 2;
570 for (reg
= 0; reg
< 0x10; ++reg
) {
571 /* 2.4 internal transmit function
573 * we initialize the first row in the rate grid.
574 * values are period (in clock cycles) of timer
576 unsigned period
= clock
/ rate
;
578 he_writel_mbox(he_dev
, period
, CS_TGRLD0
+ reg
);
582 if (he_is622(he_dev
)) {
583 /* table 5.2 (4 cells per lbuf) */
584 he_writel_mbox(he_dev
, 0x000800fa, CS_ERTHR0
);
585 he_writel_mbox(he_dev
, 0x000c33cb, CS_ERTHR1
);
586 he_writel_mbox(he_dev
, 0x0010101b, CS_ERTHR2
);
587 he_writel_mbox(he_dev
, 0x00181dac, CS_ERTHR3
);
588 he_writel_mbox(he_dev
, 0x00280600, CS_ERTHR4
);
590 /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
591 he_writel_mbox(he_dev
, 0x023de8b3, CS_ERCTL0
);
592 he_writel_mbox(he_dev
, 0x1801, CS_ERCTL1
);
593 he_writel_mbox(he_dev
, 0x68b3, CS_ERCTL2
);
594 he_writel_mbox(he_dev
, 0x1280, CS_ERSTAT0
);
595 he_writel_mbox(he_dev
, 0x68b3, CS_ERSTAT1
);
596 he_writel_mbox(he_dev
, 0x14585, CS_RTFWR
);
598 he_writel_mbox(he_dev
, 0x4680, CS_RTATR
);
601 he_writel_mbox(he_dev
, 0x00159ece, CS_TFBSET
);
602 he_writel_mbox(he_dev
, 0x68b3, CS_WCRMAX
);
603 he_writel_mbox(he_dev
, 0x5eb3, CS_WCRMIN
);
604 he_writel_mbox(he_dev
, 0xe8b3, CS_WCRINC
);
605 he_writel_mbox(he_dev
, 0xdeb3, CS_WCRDEC
);
606 he_writel_mbox(he_dev
, 0x68b3, CS_WCRCEIL
);
609 he_writel_mbox(he_dev
, 0x5, CS_OTPPER
);
610 he_writel_mbox(he_dev
, 0x14, CS_OTWPER
);
612 /* table 5.1 (4 cells per lbuf) */
613 he_writel_mbox(he_dev
, 0x000400ea, CS_ERTHR0
);
614 he_writel_mbox(he_dev
, 0x00063388, CS_ERTHR1
);
615 he_writel_mbox(he_dev
, 0x00081018, CS_ERTHR2
);
616 he_writel_mbox(he_dev
, 0x000c1dac, CS_ERTHR3
);
617 he_writel_mbox(he_dev
, 0x0014051a, CS_ERTHR4
);
619 /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
620 he_writel_mbox(he_dev
, 0x0235e4b1, CS_ERCTL0
);
621 he_writel_mbox(he_dev
, 0x4701, CS_ERCTL1
);
622 he_writel_mbox(he_dev
, 0x64b1, CS_ERCTL2
);
623 he_writel_mbox(he_dev
, 0x1280, CS_ERSTAT0
);
624 he_writel_mbox(he_dev
, 0x64b1, CS_ERSTAT1
);
625 he_writel_mbox(he_dev
, 0xf424, CS_RTFWR
);
627 he_writel_mbox(he_dev
, 0x4680, CS_RTATR
);
630 he_writel_mbox(he_dev
, 0x000563b7, CS_TFBSET
);
631 he_writel_mbox(he_dev
, 0x64b1, CS_WCRMAX
);
632 he_writel_mbox(he_dev
, 0x5ab1, CS_WCRMIN
);
633 he_writel_mbox(he_dev
, 0xe4b1, CS_WCRINC
);
634 he_writel_mbox(he_dev
, 0xdab1, CS_WCRDEC
);
635 he_writel_mbox(he_dev
, 0x64b1, CS_WCRCEIL
);
638 he_writel_mbox(he_dev
, 0x6, CS_OTPPER
);
639 he_writel_mbox(he_dev
, 0x1e, CS_OTWPER
);
642 he_writel_mbox(he_dev
, 0x8, CS_OTTLIM
);
644 for (reg
= 0; reg
< 0x8; ++reg
)
645 he_writel_mbox(he_dev
, 0x0, CS_HGRRT0
+ reg
);
649 static int he_init_cs_block_rcm(struct he_dev
*he_dev
)
651 unsigned (*rategrid
)[16][16];
652 unsigned rate
, delta
;
655 unsigned rate_atmf
, exp
, man
;
656 unsigned long long rate_cps
;
657 int mult
, buf
, buf_limit
= 4;
659 rategrid
= kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL
);
663 /* initialize rate grid group table */
665 for (reg
= 0x0; reg
< 0xff; ++reg
)
666 he_writel_rcm(he_dev
, 0x0, CONFIG_RCMABR
+ reg
);
668 /* initialize rate controller groups */
670 for (reg
= 0x100; reg
< 0x1ff; ++reg
)
671 he_writel_rcm(he_dev
, 0x0, CONFIG_RCMABR
+ reg
);
673 /* initialize tNrm lookup table */
675 /* the manual makes reference to a routine in a sample driver
676 for proper configuration; fortunately, we only need this
677 in order to support abr connection */
679 /* initialize rate to group table */
681 rate
= he_dev
->atm_dev
->link_rate
;
685 * 2.4 transmit internal functions
687 * we construct a copy of the rate grid used by the scheduler
688 * in order to construct the rate to group table below
691 for (j
= 0; j
< 16; j
++) {
692 (*rategrid
)[0][j
] = rate
;
696 for (i
= 1; i
< 16; i
++)
697 for (j
= 0; j
< 16; j
++)
699 (*rategrid
)[i
][j
] = (*rategrid
)[i
- 1][j
] / 4;
701 (*rategrid
)[i
][j
] = (*rategrid
)[i
- 1][j
] / 2;
704 * 2.4 transmit internal function
706 * this table maps the upper 5 bits of exponent and mantissa
707 * of the atm forum representation of the rate into an index
712 while (rate_atmf
< 0x400) {
713 man
= (rate_atmf
& 0x1f) << 4;
714 exp
= rate_atmf
>> 5;
717 instead of '/ 512', use '>> 9' to prevent a call
718 to divdu3 on x86 platforms
720 rate_cps
= (unsigned long long) (1 << exp
) * (man
+ 512) >> 9;
723 rate_cps
= 10; /* 2.2.1 minimum payload rate is 10 cps */
725 for (i
= 255; i
> 0; i
--)
726 if ((*rategrid
)[i
/16][i
%16] >= rate_cps
)
727 break; /* pick nearest rate instead? */
730 * each table entry is 16 bits: (rate grid index (8 bits)
731 * and a buffer limit (8 bits)
732 * there are two table entries in each 32-bit register
736 buf
= rate_cps
* he_dev
->tx_numbuffs
/
737 (he_dev
->atm_dev
->link_rate
* 2);
739 /* this is pretty, but avoids _divdu3 and is mostly correct */
740 mult
= he_dev
->atm_dev
->link_rate
/ ATM_OC3_PCR
;
741 if (rate_cps
> (272 * mult
))
743 else if (rate_cps
> (204 * mult
))
745 else if (rate_cps
> (136 * mult
))
747 else if (rate_cps
> (68 * mult
))
754 reg
= (reg
<< 16) | ((i
<< 8) | buf
);
756 #define RTGTBL_OFFSET 0x400
759 he_writel_rcm(he_dev
, reg
,
760 CONFIG_RCMABR
+ RTGTBL_OFFSET
+ (rate_atmf
>> 1));
769 static int he_init_group(struct he_dev
*he_dev
, int group
)
771 struct he_buff
*heb
, *next
;
775 he_writel(he_dev
, 0x0, G0_RBPS_S
+ (group
* 32));
776 he_writel(he_dev
, 0x0, G0_RBPS_T
+ (group
* 32));
777 he_writel(he_dev
, 0x0, G0_RBPS_QI
+ (group
* 32));
778 he_writel(he_dev
, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
779 G0_RBPS_BS
+ (group
* 32));
782 he_dev
->rbpl_table
= kmalloc(BITS_TO_LONGS(RBPL_TABLE_SIZE
)
783 * sizeof(unsigned long), GFP_KERNEL
);
784 if (!he_dev
->rbpl_table
) {
785 hprintk("unable to allocate rbpl bitmap table\n");
788 bitmap_zero(he_dev
->rbpl_table
, RBPL_TABLE_SIZE
);
790 /* rbpl_virt 64-bit pointers */
791 he_dev
->rbpl_virt
= kmalloc(RBPL_TABLE_SIZE
792 * sizeof(struct he_buff
*), GFP_KERNEL
);
793 if (!he_dev
->rbpl_virt
) {
794 hprintk("unable to allocate rbpl virt table\n");
795 goto out_free_rbpl_table
;
798 /* large buffer pool */
799 he_dev
->rbpl_pool
= pci_pool_create("rbpl", he_dev
->pci_dev
,
800 CONFIG_RBPL_BUFSIZE
, 64, 0);
801 if (he_dev
->rbpl_pool
== NULL
) {
802 hprintk("unable to create rbpl pool\n");
803 goto out_free_rbpl_virt
;
806 he_dev
->rbpl_base
= pci_zalloc_consistent(he_dev
->pci_dev
,
807 CONFIG_RBPL_SIZE
* sizeof(struct he_rbp
),
809 if (he_dev
->rbpl_base
== NULL
) {
810 hprintk("failed to alloc rbpl_base\n");
811 goto out_destroy_rbpl_pool
;
814 INIT_LIST_HEAD(&he_dev
->rbpl_outstanding
);
816 for (i
= 0; i
< CONFIG_RBPL_SIZE
; ++i
) {
818 heb
= pci_pool_alloc(he_dev
->rbpl_pool
, GFP_KERNEL
|GFP_DMA
, &mapping
);
821 heb
->mapping
= mapping
;
822 list_add(&heb
->entry
, &he_dev
->rbpl_outstanding
);
824 set_bit(i
, he_dev
->rbpl_table
);
825 he_dev
->rbpl_virt
[i
] = heb
;
826 he_dev
->rbpl_hint
= i
+ 1;
827 he_dev
->rbpl_base
[i
].idx
= i
<< RBP_IDX_OFFSET
;
828 he_dev
->rbpl_base
[i
].phys
= mapping
+ offsetof(struct he_buff
, data
);
830 he_dev
->rbpl_tail
= &he_dev
->rbpl_base
[CONFIG_RBPL_SIZE
- 1];
832 he_writel(he_dev
, he_dev
->rbpl_phys
, G0_RBPL_S
+ (group
* 32));
833 he_writel(he_dev
, RBPL_MASK(he_dev
->rbpl_tail
),
834 G0_RBPL_T
+ (group
* 32));
835 he_writel(he_dev
, (CONFIG_RBPL_BUFSIZE
- sizeof(struct he_buff
))/4,
836 G0_RBPL_BS
+ (group
* 32));
838 RBP_THRESH(CONFIG_RBPL_THRESH
) |
839 RBP_QSIZE(CONFIG_RBPL_SIZE
- 1) |
841 G0_RBPL_QI
+ (group
* 32));
843 /* rx buffer ready queue */
845 he_dev
->rbrq_base
= pci_zalloc_consistent(he_dev
->pci_dev
,
846 CONFIG_RBRQ_SIZE
* sizeof(struct he_rbrq
),
848 if (he_dev
->rbrq_base
== NULL
) {
849 hprintk("failed to allocate rbrq\n");
853 he_dev
->rbrq_head
= he_dev
->rbrq_base
;
854 he_writel(he_dev
, he_dev
->rbrq_phys
, G0_RBRQ_ST
+ (group
* 16));
855 he_writel(he_dev
, 0, G0_RBRQ_H
+ (group
* 16));
857 RBRQ_THRESH(CONFIG_RBRQ_THRESH
) | RBRQ_SIZE(CONFIG_RBRQ_SIZE
- 1),
858 G0_RBRQ_Q
+ (group
* 16));
860 hprintk("coalescing interrupts\n");
861 he_writel(he_dev
, RBRQ_TIME(768) | RBRQ_COUNT(7),
862 G0_RBRQ_I
+ (group
* 16));
864 he_writel(he_dev
, RBRQ_TIME(0) | RBRQ_COUNT(1),
865 G0_RBRQ_I
+ (group
* 16));
867 /* tx buffer ready queue */
869 he_dev
->tbrq_base
= pci_zalloc_consistent(he_dev
->pci_dev
,
870 CONFIG_TBRQ_SIZE
* sizeof(struct he_tbrq
),
872 if (he_dev
->tbrq_base
== NULL
) {
873 hprintk("failed to allocate tbrq\n");
874 goto out_free_rbpq_base
;
877 he_dev
->tbrq_head
= he_dev
->tbrq_base
;
879 he_writel(he_dev
, he_dev
->tbrq_phys
, G0_TBRQ_B_T
+ (group
* 16));
880 he_writel(he_dev
, 0, G0_TBRQ_H
+ (group
* 16));
881 he_writel(he_dev
, CONFIG_TBRQ_SIZE
- 1, G0_TBRQ_S
+ (group
* 16));
882 he_writel(he_dev
, CONFIG_TBRQ_THRESH
, G0_TBRQ_THRESH
+ (group
* 16));
887 pci_free_consistent(he_dev
->pci_dev
, CONFIG_RBRQ_SIZE
*
888 sizeof(struct he_rbrq
), he_dev
->rbrq_base
,
891 list_for_each_entry_safe(heb
, next
, &he_dev
->rbpl_outstanding
, entry
)
892 pci_pool_free(he_dev
->rbpl_pool
, heb
, heb
->mapping
);
894 pci_free_consistent(he_dev
->pci_dev
, CONFIG_RBPL_SIZE
*
895 sizeof(struct he_rbp
), he_dev
->rbpl_base
,
897 out_destroy_rbpl_pool
:
898 pci_pool_destroy(he_dev
->rbpl_pool
);
900 kfree(he_dev
->rbpl_virt
);
902 kfree(he_dev
->rbpl_table
);
907 static int he_init_irq(struct he_dev
*he_dev
)
911 /* 2.9.3.5 tail offset for each interrupt queue is located after the
912 end of the interrupt queue */
914 he_dev
->irq_base
= pci_alloc_consistent(he_dev
->pci_dev
,
915 (CONFIG_IRQ_SIZE
+1) * sizeof(struct he_irq
), &he_dev
->irq_phys
);
916 if (he_dev
->irq_base
== NULL
) {
917 hprintk("failed to allocate irq\n");
920 he_dev
->irq_tailoffset
= (unsigned *)
921 &he_dev
->irq_base
[CONFIG_IRQ_SIZE
];
922 *he_dev
->irq_tailoffset
= 0;
923 he_dev
->irq_head
= he_dev
->irq_base
;
924 he_dev
->irq_tail
= he_dev
->irq_base
;
926 for (i
= 0; i
< CONFIG_IRQ_SIZE
; ++i
)
927 he_dev
->irq_base
[i
].isw
= ITYPE_INVALID
;
929 he_writel(he_dev
, he_dev
->irq_phys
, IRQ0_BASE
);
931 IRQ_SIZE(CONFIG_IRQ_SIZE
) | IRQ_THRESH(CONFIG_IRQ_THRESH
),
933 he_writel(he_dev
, IRQ_INT_A
| IRQ_TYPE_LINE
, IRQ0_CNTL
);
934 he_writel(he_dev
, 0x0, IRQ0_DATA
);
936 he_writel(he_dev
, 0x0, IRQ1_BASE
);
937 he_writel(he_dev
, 0x0, IRQ1_HEAD
);
938 he_writel(he_dev
, 0x0, IRQ1_CNTL
);
939 he_writel(he_dev
, 0x0, IRQ1_DATA
);
941 he_writel(he_dev
, 0x0, IRQ2_BASE
);
942 he_writel(he_dev
, 0x0, IRQ2_HEAD
);
943 he_writel(he_dev
, 0x0, IRQ2_CNTL
);
944 he_writel(he_dev
, 0x0, IRQ2_DATA
);
946 he_writel(he_dev
, 0x0, IRQ3_BASE
);
947 he_writel(he_dev
, 0x0, IRQ3_HEAD
);
948 he_writel(he_dev
, 0x0, IRQ3_CNTL
);
949 he_writel(he_dev
, 0x0, IRQ3_DATA
);
951 /* 2.9.3.2 interrupt queue mapping registers */
953 he_writel(he_dev
, 0x0, GRP_10_MAP
);
954 he_writel(he_dev
, 0x0, GRP_32_MAP
);
955 he_writel(he_dev
, 0x0, GRP_54_MAP
);
956 he_writel(he_dev
, 0x0, GRP_76_MAP
);
958 if (request_irq(he_dev
->pci_dev
->irq
,
959 he_irq_handler
, IRQF_SHARED
, DEV_LABEL
, he_dev
)) {
960 hprintk("irq %d already in use\n", he_dev
->pci_dev
->irq
);
964 he_dev
->irq
= he_dev
->pci_dev
->irq
;
969 static int he_start(struct atm_dev
*dev
)
971 struct he_dev
*he_dev
;
972 struct pci_dev
*pci_dev
;
973 unsigned long membase
;
976 u32 gen_cntl_0
, host_cntl
, lb_swap
;
977 u8 cache_size
, timer
;
980 unsigned int status
, reg
;
983 he_dev
= HE_DEV(dev
);
984 pci_dev
= he_dev
->pci_dev
;
986 membase
= pci_resource_start(pci_dev
, 0);
987 HPRINTK("membase = 0x%lx irq = %d.\n", membase
, pci_dev
->irq
);
990 * pci bus controller initialization
993 /* 4.3 pci bus controller-specific initialization */
994 if (pci_read_config_dword(pci_dev
, GEN_CNTL_0
, &gen_cntl_0
) != 0) {
995 hprintk("can't read GEN_CNTL_0\n");
998 gen_cntl_0
|= (MRL_ENB
| MRM_ENB
| IGNORE_TIMEOUT
);
999 if (pci_write_config_dword(pci_dev
, GEN_CNTL_0
, gen_cntl_0
) != 0) {
1000 hprintk("can't write GEN_CNTL_0.\n");
1004 if (pci_read_config_word(pci_dev
, PCI_COMMAND
, &command
) != 0) {
1005 hprintk("can't read PCI_COMMAND.\n");
1009 command
|= (PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
| PCI_COMMAND_INVALIDATE
);
1010 if (pci_write_config_word(pci_dev
, PCI_COMMAND
, command
) != 0) {
1011 hprintk("can't enable memory.\n");
1015 if (pci_read_config_byte(pci_dev
, PCI_CACHE_LINE_SIZE
, &cache_size
)) {
1016 hprintk("can't read cache line size?\n");
1020 if (cache_size
< 16) {
1022 if (pci_write_config_byte(pci_dev
, PCI_CACHE_LINE_SIZE
, cache_size
))
1023 hprintk("can't set cache line size to %d\n", cache_size
);
1026 if (pci_read_config_byte(pci_dev
, PCI_LATENCY_TIMER
, &timer
)) {
1027 hprintk("can't read latency timer?\n");
1033 * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE
1035 * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]
1036 * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]
1039 #define LAT_TIMER 209
1040 if (timer
< LAT_TIMER
) {
1041 HPRINTK("latency timer was %d, setting to %d\n", timer
, LAT_TIMER
);
1043 if (pci_write_config_byte(pci_dev
, PCI_LATENCY_TIMER
, timer
))
1044 hprintk("can't set latency timer to %d\n", timer
);
1047 if (!(he_dev
->membase
= ioremap(membase
, HE_REGMAP_SIZE
))) {
1048 hprintk("can't set up page mapping\n");
1052 /* 4.4 card reset */
1053 he_writel(he_dev
, 0x0, RESET_CNTL
);
1054 he_writel(he_dev
, 0xff, RESET_CNTL
);
1056 msleep(16); /* 16 ms */
1057 status
= he_readl(he_dev
, RESET_CNTL
);
1058 if ((status
& BOARD_RST_STATUS
) == 0) {
1059 hprintk("reset failed\n");
1063 /* 4.5 set bus width */
1064 host_cntl
= he_readl(he_dev
, HOST_CNTL
);
1065 if (host_cntl
& PCI_BUS_SIZE64
)
1066 gen_cntl_0
|= ENBL_64
;
1068 gen_cntl_0
&= ~ENBL_64
;
1070 if (disable64
== 1) {
1071 hprintk("disabling 64-bit pci bus transfers\n");
1072 gen_cntl_0
&= ~ENBL_64
;
1075 if (gen_cntl_0
& ENBL_64
)
1076 hprintk("64-bit transfers enabled\n");
1078 pci_write_config_dword(pci_dev
, GEN_CNTL_0
, gen_cntl_0
);
1080 /* 4.7 read prom contents */
1081 for (i
= 0; i
< PROD_ID_LEN
; ++i
)
1082 he_dev
->prod_id
[i
] = read_prom_byte(he_dev
, PROD_ID
+ i
);
1084 he_dev
->media
= read_prom_byte(he_dev
, MEDIA
);
1086 for (i
= 0; i
< 6; ++i
)
1087 dev
->esi
[i
] = read_prom_byte(he_dev
, MAC_ADDR
+ i
);
1089 hprintk("%s%s, %pM\n", he_dev
->prod_id
,
1090 he_dev
->media
& 0x40 ? "SM" : "MM", dev
->esi
);
1091 he_dev
->atm_dev
->link_rate
= he_is622(he_dev
) ?
1092 ATM_OC12_PCR
: ATM_OC3_PCR
;
1094 /* 4.6 set host endianess */
1095 lb_swap
= he_readl(he_dev
, LB_SWAP
);
1096 if (he_is622(he_dev
))
1097 lb_swap
&= ~XFER_SIZE
; /* 4 cells */
1099 lb_swap
|= XFER_SIZE
; /* 8 cells */
1101 lb_swap
|= DESC_WR_SWAP
| INTR_SWAP
| BIG_ENDIAN_HOST
;
1103 lb_swap
&= ~(DESC_WR_SWAP
| INTR_SWAP
| BIG_ENDIAN_HOST
|
1104 DATA_WR_SWAP
| DATA_RD_SWAP
| DESC_RD_SWAP
);
1105 #endif /* __BIG_ENDIAN */
1106 he_writel(he_dev
, lb_swap
, LB_SWAP
);
1108 /* 4.8 sdram controller initialization */
1109 he_writel(he_dev
, he_is622(he_dev
) ? LB_64_ENB
: 0x0, SDRAM_CTL
);
1111 /* 4.9 initialize rnum value */
1112 lb_swap
|= SWAP_RNUM_MAX(0xf);
1113 he_writel(he_dev
, lb_swap
, LB_SWAP
);
1115 /* 4.10 initialize the interrupt queues */
1116 if ((err
= he_init_irq(he_dev
)) != 0)
1119 /* 4.11 enable pci bus controller state machines */
1120 host_cntl
|= (OUTFF_ENB
| CMDFF_ENB
|
1121 QUICK_RD_RETRY
| QUICK_WR_RETRY
| PERR_INT_ENB
);
1122 he_writel(he_dev
, host_cntl
, HOST_CNTL
);
1124 gen_cntl_0
|= INT_PROC_ENBL
|INIT_ENB
;
1125 pci_write_config_dword(pci_dev
, GEN_CNTL_0
, gen_cntl_0
);
1128 * atm network controller initialization
1131 /* 5.1.1 generic configuration state */
1134 * local (cell) buffer memory map
1138 * 0 ____________1023 bytes 0 _______________________2047 bytes
1140 * | utility | | rx0 | |
1141 * 5|____________| 255|___________________| u |
1144 * | rx0 | row | tx | l |
1146 * | | 767|___________________| t |
1147 * 517|____________| 768| | y |
1148 * row 518| | | rx1 | |
1149 * | | 1023|___________________|___|
1154 * 1535|____________|
1157 * 2047|____________|
1161 /* total 4096 connections */
1162 he_dev
->vcibits
= CONFIG_DEFAULT_VCIBITS
;
1163 he_dev
->vpibits
= CONFIG_DEFAULT_VPIBITS
;
1165 if (nvpibits
!= -1 && nvcibits
!= -1 && nvpibits
+nvcibits
!= HE_MAXCIDBITS
) {
1166 hprintk("nvpibits + nvcibits != %d\n", HE_MAXCIDBITS
);
1170 if (nvpibits
!= -1) {
1171 he_dev
->vpibits
= nvpibits
;
1172 he_dev
->vcibits
= HE_MAXCIDBITS
- nvpibits
;
1175 if (nvcibits
!= -1) {
1176 he_dev
->vcibits
= nvcibits
;
1177 he_dev
->vpibits
= HE_MAXCIDBITS
- nvcibits
;
1181 if (he_is622(he_dev
)) {
1182 he_dev
->cells_per_row
= 40;
1183 he_dev
->bytes_per_row
= 2048;
1184 he_dev
->r0_numrows
= 256;
1185 he_dev
->tx_numrows
= 512;
1186 he_dev
->r1_numrows
= 256;
1187 he_dev
->r0_startrow
= 0;
1188 he_dev
->tx_startrow
= 256;
1189 he_dev
->r1_startrow
= 768;
1191 he_dev
->cells_per_row
= 20;
1192 he_dev
->bytes_per_row
= 1024;
1193 he_dev
->r0_numrows
= 512;
1194 he_dev
->tx_numrows
= 1018;
1195 he_dev
->r1_numrows
= 512;
1196 he_dev
->r0_startrow
= 6;
1197 he_dev
->tx_startrow
= 518;
1198 he_dev
->r1_startrow
= 1536;
1201 he_dev
->cells_per_lbuf
= 4;
1202 he_dev
->buffer_limit
= 4;
1203 he_dev
->r0_numbuffs
= he_dev
->r0_numrows
*
1204 he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
1205 if (he_dev
->r0_numbuffs
> 2560)
1206 he_dev
->r0_numbuffs
= 2560;
1208 he_dev
->r1_numbuffs
= he_dev
->r1_numrows
*
1209 he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
1210 if (he_dev
->r1_numbuffs
> 2560)
1211 he_dev
->r1_numbuffs
= 2560;
1213 he_dev
->tx_numbuffs
= he_dev
->tx_numrows
*
1214 he_dev
->cells_per_row
/ he_dev
->cells_per_lbuf
;
1215 if (he_dev
->tx_numbuffs
> 5120)
1216 he_dev
->tx_numbuffs
= 5120;
1218 /* 5.1.2 configure hardware dependent registers */
1221 SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |
1222 RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |
1223 (he_is622(he_dev
) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
1224 (he_is622(he_dev
) ? NET_PREF(0x50) : NET_PREF(0x8c)),
1227 he_writel(he_dev
, BANK_ON
|
1228 (he_is622(he_dev
) ? (REF_RATE(0x384) | WIDE_DATA
) : REF_RATE(0x150)),
1232 (he_is622(he_dev
) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
1233 RM_RW_WAIT(1), RCMCONFIG
);
1235 (he_is622(he_dev
) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
1236 TM_RW_WAIT(1), TCMCONFIG
);
1238 he_writel(he_dev
, he_dev
->cells_per_lbuf
* ATM_CELL_PAYLOAD
, LB_CONFIG
);
1241 (he_is622(he_dev
) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
1242 (he_is622(he_dev
) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
1243 RX_VALVP(he_dev
->vpibits
) |
1244 RX_VALVC(he_dev
->vcibits
), RC_CONFIG
);
1246 he_writel(he_dev
, DRF_THRESH(0x20) |
1247 (he_is622(he_dev
) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
1248 TX_VCI_MASK(he_dev
->vcibits
) |
1249 LBFREE_CNT(he_dev
->tx_numbuffs
), TX_CONFIG
);
1251 he_writel(he_dev
, 0x0, TXAAL5_PROTO
);
1253 he_writel(he_dev
, PHY_INT_ENB
|
1254 (he_is622(he_dev
) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
1257 /* 5.1.3 initialize connection memory */
1259 for (i
= 0; i
< TCM_MEM_SIZE
; ++i
)
1260 he_writel_tcm(he_dev
, 0, i
);
1262 for (i
= 0; i
< RCM_MEM_SIZE
; ++i
)
1263 he_writel_rcm(he_dev
, 0, i
);
1266 * transmit connection memory map
1269 * 0x0 ___________________
1275 * 0x8000|___________________|
1278 * 0xc000|___________________|
1281 * 0xe000|___________________|
1283 * 0xf000|___________________|
1285 * 0x10000|___________________|
1288 * |___________________|
1291 * 0x1ffff|___________________|
1296 he_writel(he_dev
, CONFIG_TSRB
, TSRB_BA
);
1297 he_writel(he_dev
, CONFIG_TSRC
, TSRC_BA
);
1298 he_writel(he_dev
, CONFIG_TSRD
, TSRD_BA
);
1299 he_writel(he_dev
, CONFIG_TMABR
, TMABR_BA
);
1300 he_writel(he_dev
, CONFIG_TPDBA
, TPD_BA
);
1304 * receive connection memory map
1306 * 0x0 ___________________
1312 * 0x8000|___________________|
1315 * | LBM | link lists of local
1316 * | tx | buffer memory
1318 * 0xd000|___________________|
1321 * 0xe000|___________________|
1324 * |___________________|
1327 * 0xffff|___________________|
1330 he_writel(he_dev
, 0x08000, RCMLBM_BA
);
1331 he_writel(he_dev
, 0x0e000, RCMRSRB_BA
);
1332 he_writel(he_dev
, 0x0d800, RCMABR_BA
);
1334 /* 5.1.4 initialize local buffer free pools linked lists */
1336 he_init_rx_lbfp0(he_dev
);
1337 he_init_rx_lbfp1(he_dev
);
1339 he_writel(he_dev
, 0x0, RLBC_H
);
1340 he_writel(he_dev
, 0x0, RLBC_T
);
1341 he_writel(he_dev
, 0x0, RLBC_H2
);
1343 he_writel(he_dev
, 512, RXTHRSH
); /* 10% of r0+r1 buffers */
1344 he_writel(he_dev
, 256, LITHRSH
); /* 5% of r0+r1 buffers */
1346 he_init_tx_lbfp(he_dev
);
1348 he_writel(he_dev
, he_is622(he_dev
) ? 0x104780 : 0x800, UBUFF_BA
);
1350 /* 5.1.5 initialize intermediate receive queues */
1352 if (he_is622(he_dev
)) {
1353 he_writel(he_dev
, 0x000f, G0_INMQ_S
);
1354 he_writel(he_dev
, 0x200f, G0_INMQ_L
);
1356 he_writel(he_dev
, 0x001f, G1_INMQ_S
);
1357 he_writel(he_dev
, 0x201f, G1_INMQ_L
);
1359 he_writel(he_dev
, 0x002f, G2_INMQ_S
);
1360 he_writel(he_dev
, 0x202f, G2_INMQ_L
);
1362 he_writel(he_dev
, 0x003f, G3_INMQ_S
);
1363 he_writel(he_dev
, 0x203f, G3_INMQ_L
);
1365 he_writel(he_dev
, 0x004f, G4_INMQ_S
);
1366 he_writel(he_dev
, 0x204f, G4_INMQ_L
);
1368 he_writel(he_dev
, 0x005f, G5_INMQ_S
);
1369 he_writel(he_dev
, 0x205f, G5_INMQ_L
);
1371 he_writel(he_dev
, 0x006f, G6_INMQ_S
);
1372 he_writel(he_dev
, 0x206f, G6_INMQ_L
);
1374 he_writel(he_dev
, 0x007f, G7_INMQ_S
);
1375 he_writel(he_dev
, 0x207f, G7_INMQ_L
);
1377 he_writel(he_dev
, 0x0000, G0_INMQ_S
);
1378 he_writel(he_dev
, 0x0008, G0_INMQ_L
);
1380 he_writel(he_dev
, 0x0001, G1_INMQ_S
);
1381 he_writel(he_dev
, 0x0009, G1_INMQ_L
);
1383 he_writel(he_dev
, 0x0002, G2_INMQ_S
);
1384 he_writel(he_dev
, 0x000a, G2_INMQ_L
);
1386 he_writel(he_dev
, 0x0003, G3_INMQ_S
);
1387 he_writel(he_dev
, 0x000b, G3_INMQ_L
);
1389 he_writel(he_dev
, 0x0004, G4_INMQ_S
);
1390 he_writel(he_dev
, 0x000c, G4_INMQ_L
);
1392 he_writel(he_dev
, 0x0005, G5_INMQ_S
);
1393 he_writel(he_dev
, 0x000d, G5_INMQ_L
);
1395 he_writel(he_dev
, 0x0006, G6_INMQ_S
);
1396 he_writel(he_dev
, 0x000e, G6_INMQ_L
);
1398 he_writel(he_dev
, 0x0007, G7_INMQ_S
);
1399 he_writel(he_dev
, 0x000f, G7_INMQ_L
);
1402 /* 5.1.6 application tunable parameters */
1404 he_writel(he_dev
, 0x0, MCC
);
1405 he_writel(he_dev
, 0x0, OEC
);
1406 he_writel(he_dev
, 0x0, DCC
);
1407 he_writel(he_dev
, 0x0, CEC
);
1409 /* 5.1.7 cs block initialization */
1411 he_init_cs_block(he_dev
);
1413 /* 5.1.8 cs block connection memory initialization */
1415 if (he_init_cs_block_rcm(he_dev
) < 0)
1418 /* 5.1.10 initialize host structures */
1420 he_init_tpdrq(he_dev
);
1422 he_dev
->tpd_pool
= pci_pool_create("tpd", he_dev
->pci_dev
,
1423 sizeof(struct he_tpd
), TPD_ALIGNMENT
, 0);
1424 if (he_dev
->tpd_pool
== NULL
) {
1425 hprintk("unable to create tpd pci_pool\n");
1429 INIT_LIST_HEAD(&he_dev
->outstanding_tpds
);
1431 if (he_init_group(he_dev
, 0) != 0)
1434 for (group
= 1; group
< HE_NUM_GROUPS
; ++group
) {
1435 he_writel(he_dev
, 0x0, G0_RBPS_S
+ (group
* 32));
1436 he_writel(he_dev
, 0x0, G0_RBPS_T
+ (group
* 32));
1437 he_writel(he_dev
, 0x0, G0_RBPS_QI
+ (group
* 32));
1438 he_writel(he_dev
, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1439 G0_RBPS_BS
+ (group
* 32));
1441 he_writel(he_dev
, 0x0, G0_RBPL_S
+ (group
* 32));
1442 he_writel(he_dev
, 0x0, G0_RBPL_T
+ (group
* 32));
1443 he_writel(he_dev
, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1444 G0_RBPL_QI
+ (group
* 32));
1445 he_writel(he_dev
, 0x0, G0_RBPL_BS
+ (group
* 32));
1447 he_writel(he_dev
, 0x0, G0_RBRQ_ST
+ (group
* 16));
1448 he_writel(he_dev
, 0x0, G0_RBRQ_H
+ (group
* 16));
1449 he_writel(he_dev
, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1450 G0_RBRQ_Q
+ (group
* 16));
1451 he_writel(he_dev
, 0x0, G0_RBRQ_I
+ (group
* 16));
1453 he_writel(he_dev
, 0x0, G0_TBRQ_B_T
+ (group
* 16));
1454 he_writel(he_dev
, 0x0, G0_TBRQ_H
+ (group
* 16));
1455 he_writel(he_dev
, TBRQ_THRESH(0x1),
1456 G0_TBRQ_THRESH
+ (group
* 16));
1457 he_writel(he_dev
, 0x0, G0_TBRQ_S
+ (group
* 16));
1460 /* host status page */
1462 he_dev
->hsp
= pci_zalloc_consistent(he_dev
->pci_dev
,
1463 sizeof(struct he_hsp
),
1465 if (he_dev
->hsp
== NULL
) {
1466 hprintk("failed to allocate host status page\n");
1469 he_writel(he_dev
, he_dev
->hsp_phys
, HSP_BA
);
1471 /* initialize framer */
1473 #ifdef CONFIG_ATM_HE_USE_SUNI
1474 if (he_isMM(he_dev
))
1475 suni_init(he_dev
->atm_dev
);
1476 if (he_dev
->atm_dev
->phy
&& he_dev
->atm_dev
->phy
->start
)
1477 he_dev
->atm_dev
->phy
->start(he_dev
->atm_dev
);
1478 #endif /* CONFIG_ATM_HE_USE_SUNI */
1481 /* this really should be in suni.c but for now... */
1484 val
= he_phy_get(he_dev
->atm_dev
, SUNI_TPOP_APM
);
1485 val
= (val
& ~SUNI_TPOP_APM_S
) | (SUNI_TPOP_S_SDH
<< SUNI_TPOP_APM_S_SHIFT
);
1486 he_phy_put(he_dev
->atm_dev
, val
, SUNI_TPOP_APM
);
1487 he_phy_put(he_dev
->atm_dev
, SUNI_TACP_IUCHP_CLP
, SUNI_TACP_IUCHP
);
1490 /* 5.1.12 enable transmit and receive */
1492 reg
= he_readl_mbox(he_dev
, CS_ERCTL0
);
1493 reg
|= TX_ENABLE
|ER_ENABLE
;
1494 he_writel_mbox(he_dev
, reg
, CS_ERCTL0
);
1496 reg
= he_readl(he_dev
, RC_CONFIG
);
1498 he_writel(he_dev
, reg
, RC_CONFIG
);
1500 for (i
= 0; i
< HE_NUM_CS_STPER
; ++i
) {
1501 he_dev
->cs_stper
[i
].inuse
= 0;
1502 he_dev
->cs_stper
[i
].pcr
= -1;
1504 he_dev
->total_bw
= 0;
1507 /* atm linux initialization */
1509 he_dev
->atm_dev
->ci_range
.vpi_bits
= he_dev
->vpibits
;
1510 he_dev
->atm_dev
->ci_range
.vci_bits
= he_dev
->vcibits
;
1512 he_dev
->irq_peak
= 0;
1513 he_dev
->rbrq_peak
= 0;
1514 he_dev
->rbpl_peak
= 0;
1515 he_dev
->tbrq_peak
= 0;
1517 HPRINTK("hell bent for leather!\n");
1523 he_stop(struct he_dev
*he_dev
)
1525 struct he_buff
*heb
, *next
;
1526 struct pci_dev
*pci_dev
;
1527 u32 gen_cntl_0
, reg
;
1530 pci_dev
= he_dev
->pci_dev
;
1532 /* disable interrupts */
1534 if (he_dev
->membase
) {
1535 pci_read_config_dword(pci_dev
, GEN_CNTL_0
, &gen_cntl_0
);
1536 gen_cntl_0
&= ~(INT_PROC_ENBL
| INIT_ENB
);
1537 pci_write_config_dword(pci_dev
, GEN_CNTL_0
, gen_cntl_0
);
1539 tasklet_disable(&he_dev
->tasklet
);
1541 /* disable recv and transmit */
1543 reg
= he_readl_mbox(he_dev
, CS_ERCTL0
);
1544 reg
&= ~(TX_ENABLE
|ER_ENABLE
);
1545 he_writel_mbox(he_dev
, reg
, CS_ERCTL0
);
1547 reg
= he_readl(he_dev
, RC_CONFIG
);
1548 reg
&= ~(RX_ENABLE
);
1549 he_writel(he_dev
, reg
, RC_CONFIG
);
1552 #ifdef CONFIG_ATM_HE_USE_SUNI
1553 if (he_dev
->atm_dev
->phy
&& he_dev
->atm_dev
->phy
->stop
)
1554 he_dev
->atm_dev
->phy
->stop(he_dev
->atm_dev
);
1555 #endif /* CONFIG_ATM_HE_USE_SUNI */
1558 free_irq(he_dev
->irq
, he_dev
);
1560 if (he_dev
->irq_base
)
1561 pci_free_consistent(he_dev
->pci_dev
, (CONFIG_IRQ_SIZE
+1)
1562 * sizeof(struct he_irq
), he_dev
->irq_base
, he_dev
->irq_phys
);
1565 pci_free_consistent(he_dev
->pci_dev
, sizeof(struct he_hsp
),
1566 he_dev
->hsp
, he_dev
->hsp_phys
);
1568 if (he_dev
->rbpl_base
) {
1569 list_for_each_entry_safe(heb
, next
, &he_dev
->rbpl_outstanding
, entry
)
1570 pci_pool_free(he_dev
->rbpl_pool
, heb
, heb
->mapping
);
1572 pci_free_consistent(he_dev
->pci_dev
, CONFIG_RBPL_SIZE
1573 * sizeof(struct he_rbp
), he_dev
->rbpl_base
, he_dev
->rbpl_phys
);
1576 kfree(he_dev
->rbpl_virt
);
1577 kfree(he_dev
->rbpl_table
);
1579 if (he_dev
->rbpl_pool
)
1580 pci_pool_destroy(he_dev
->rbpl_pool
);
1582 if (he_dev
->rbrq_base
)
1583 pci_free_consistent(he_dev
->pci_dev
, CONFIG_RBRQ_SIZE
* sizeof(struct he_rbrq
),
1584 he_dev
->rbrq_base
, he_dev
->rbrq_phys
);
1586 if (he_dev
->tbrq_base
)
1587 pci_free_consistent(he_dev
->pci_dev
, CONFIG_TBRQ_SIZE
* sizeof(struct he_tbrq
),
1588 he_dev
->tbrq_base
, he_dev
->tbrq_phys
);
1590 if (he_dev
->tpdrq_base
)
1591 pci_free_consistent(he_dev
->pci_dev
, CONFIG_TBRQ_SIZE
* sizeof(struct he_tbrq
),
1592 he_dev
->tpdrq_base
, he_dev
->tpdrq_phys
);
1594 if (he_dev
->tpd_pool
)
1595 pci_pool_destroy(he_dev
->tpd_pool
);
1597 if (he_dev
->pci_dev
) {
1598 pci_read_config_word(he_dev
->pci_dev
, PCI_COMMAND
, &command
);
1599 command
&= ~(PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
1600 pci_write_config_word(he_dev
->pci_dev
, PCI_COMMAND
, command
);
1603 if (he_dev
->membase
)
1604 iounmap(he_dev
->membase
);
1607 static struct he_tpd
*
1608 __alloc_tpd(struct he_dev
*he_dev
)
1613 tpd
= pci_pool_alloc(he_dev
->tpd_pool
, GFP_ATOMIC
|GFP_DMA
, &mapping
);
1617 tpd
->status
= TPD_ADDR(mapping
);
1619 tpd
->iovec
[0].addr
= 0; tpd
->iovec
[0].len
= 0;
1620 tpd
->iovec
[1].addr
= 0; tpd
->iovec
[1].len
= 0;
1621 tpd
->iovec
[2].addr
= 0; tpd
->iovec
[2].len
= 0;
1626 #define AAL5_LEN(buf,len) \
1627 ((((unsigned char *)(buf))[(len)-6] << 8) | \
1628 (((unsigned char *)(buf))[(len)-5]))
1632 * aal5 packets can optionally return the tcp checksum in the lower
1633 * 16 bits of the crc (RSR0_TCP_CKSUM)
1636 #define TCP_CKSUM(buf,len) \
1637 ((((unsigned char *)(buf))[(len)-2] << 8) | \
1638 (((unsigned char *)(buf))[(len-1)]))
1641 he_service_rbrq(struct he_dev
*he_dev
, int group
)
1643 struct he_rbrq
*rbrq_tail
= (struct he_rbrq
*)
1644 ((unsigned long)he_dev
->rbrq_base
|
1645 he_dev
->hsp
->group
[group
].rbrq_tail
);
1646 unsigned cid
, lastcid
= -1;
1647 struct sk_buff
*skb
;
1648 struct atm_vcc
*vcc
= NULL
;
1649 struct he_vcc
*he_vcc
;
1650 struct he_buff
*heb
, *next
;
1652 int pdus_assembled
= 0;
1655 read_lock(&vcc_sklist_lock
);
1656 while (he_dev
->rbrq_head
!= rbrq_tail
) {
1659 HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n",
1660 he_dev
->rbrq_head
, group
,
1661 RBRQ_ADDR(he_dev
->rbrq_head
),
1662 RBRQ_BUFLEN(he_dev
->rbrq_head
),
1663 RBRQ_CID(he_dev
->rbrq_head
),
1664 RBRQ_CRC_ERR(he_dev
->rbrq_head
) ? " CRC_ERR" : "",
1665 RBRQ_LEN_ERR(he_dev
->rbrq_head
) ? " LEN_ERR" : "",
1666 RBRQ_END_PDU(he_dev
->rbrq_head
) ? " END_PDU" : "",
1667 RBRQ_AAL5_PROT(he_dev
->rbrq_head
) ? " AAL5_PROT" : "",
1668 RBRQ_CON_CLOSED(he_dev
->rbrq_head
) ? " CON_CLOSED" : "",
1669 RBRQ_HBUF_ERR(he_dev
->rbrq_head
) ? " HBUF_ERR" : "");
1671 i
= RBRQ_ADDR(he_dev
->rbrq_head
) >> RBP_IDX_OFFSET
;
1672 heb
= he_dev
->rbpl_virt
[i
];
1674 cid
= RBRQ_CID(he_dev
->rbrq_head
);
1676 vcc
= __find_vcc(he_dev
, cid
);
1679 if (vcc
== NULL
|| (he_vcc
= HE_VCC(vcc
)) == NULL
) {
1680 hprintk("vcc/he_vcc == NULL (cid 0x%x)\n", cid
);
1681 if (!RBRQ_HBUF_ERR(he_dev
->rbrq_head
)) {
1682 clear_bit(i
, he_dev
->rbpl_table
);
1683 list_del(&heb
->entry
);
1684 pci_pool_free(he_dev
->rbpl_pool
, heb
, heb
->mapping
);
1687 goto next_rbrq_entry
;
1690 if (RBRQ_HBUF_ERR(he_dev
->rbrq_head
)) {
1691 hprintk("HBUF_ERR! (cid 0x%x)\n", cid
);
1692 atomic_inc(&vcc
->stats
->rx_drop
);
1693 goto return_host_buffers
;
1696 heb
->len
= RBRQ_BUFLEN(he_dev
->rbrq_head
) * 4;
1697 clear_bit(i
, he_dev
->rbpl_table
);
1698 list_move_tail(&heb
->entry
, &he_vcc
->buffers
);
1699 he_vcc
->pdu_len
+= heb
->len
;
1701 if (RBRQ_CON_CLOSED(he_dev
->rbrq_head
)) {
1703 HPRINTK("wake_up rx_waitq (cid 0x%x)\n", cid
);
1704 wake_up(&he_vcc
->rx_waitq
);
1705 goto return_host_buffers
;
1708 if (!RBRQ_END_PDU(he_dev
->rbrq_head
))
1709 goto next_rbrq_entry
;
1711 if (RBRQ_LEN_ERR(he_dev
->rbrq_head
)
1712 || RBRQ_CRC_ERR(he_dev
->rbrq_head
)) {
1713 HPRINTK("%s%s (%d.%d)\n",
1714 RBRQ_CRC_ERR(he_dev
->rbrq_head
)
1716 RBRQ_LEN_ERR(he_dev
->rbrq_head
)
1718 vcc
->vpi
, vcc
->vci
);
1719 atomic_inc(&vcc
->stats
->rx_err
);
1720 goto return_host_buffers
;
1723 skb
= atm_alloc_charge(vcc
, he_vcc
->pdu_len
+ rx_skb_reserve
,
1726 HPRINTK("charge failed (%d.%d)\n", vcc
->vpi
, vcc
->vci
);
1727 goto return_host_buffers
;
1730 if (rx_skb_reserve
> 0)
1731 skb_reserve(skb
, rx_skb_reserve
);
1733 __net_timestamp(skb
);
1735 list_for_each_entry(heb
, &he_vcc
->buffers
, entry
)
1736 memcpy(skb_put(skb
, heb
->len
), &heb
->data
, heb
->len
);
1738 switch (vcc
->qos
.aal
) {
1740 /* 2.10.1.5 raw cell receive */
1741 skb
->len
= ATM_AAL0_SDU
;
1742 skb_set_tail_pointer(skb
, skb
->len
);
1745 /* 2.10.1.2 aal5 receive */
1747 skb
->len
= AAL5_LEN(skb
->data
, he_vcc
->pdu_len
);
1748 skb_set_tail_pointer(skb
, skb
->len
);
1749 #ifdef USE_CHECKSUM_HW
1750 if (vcc
->vpi
== 0 && vcc
->vci
>= ATM_NOT_RSV_VCI
) {
1751 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1752 skb
->csum
= TCP_CKSUM(skb
->data
,
1759 #ifdef should_never_happen
1760 if (skb
->len
> vcc
->qos
.rxtp
.max_sdu
)
1761 hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\n", skb
->len
, vcc
->qos
.rxtp
.max_sdu
, cid
);
1765 ATM_SKB(skb
)->vcc
= vcc
;
1767 spin_unlock(&he_dev
->global_lock
);
1768 vcc
->push(vcc
, skb
);
1769 spin_lock(&he_dev
->global_lock
);
1771 atomic_inc(&vcc
->stats
->rx
);
1773 return_host_buffers
:
1776 list_for_each_entry_safe(heb
, next
, &he_vcc
->buffers
, entry
)
1777 pci_pool_free(he_dev
->rbpl_pool
, heb
, heb
->mapping
);
1778 INIT_LIST_HEAD(&he_vcc
->buffers
);
1779 he_vcc
->pdu_len
= 0;
1782 he_dev
->rbrq_head
= (struct he_rbrq
*)
1783 ((unsigned long) he_dev
->rbrq_base
|
1784 RBRQ_MASK(he_dev
->rbrq_head
+ 1));
1787 read_unlock(&vcc_sklist_lock
);
1790 if (updated
> he_dev
->rbrq_peak
)
1791 he_dev
->rbrq_peak
= updated
;
1793 he_writel(he_dev
, RBRQ_MASK(he_dev
->rbrq_head
),
1794 G0_RBRQ_H
+ (group
* 16));
1797 return pdus_assembled
;
1801 he_service_tbrq(struct he_dev
*he_dev
, int group
)
1803 struct he_tbrq
*tbrq_tail
= (struct he_tbrq
*)
1804 ((unsigned long)he_dev
->tbrq_base
|
1805 he_dev
->hsp
->group
[group
].tbrq_tail
);
1807 int slot
, updated
= 0;
1808 struct he_tpd
*__tpd
;
1810 /* 2.1.6 transmit buffer return queue */
1812 while (he_dev
->tbrq_head
!= tbrq_tail
) {
1815 HPRINTK("tbrq%d 0x%x%s%s\n",
1817 TBRQ_TPD(he_dev
->tbrq_head
),
1818 TBRQ_EOS(he_dev
->tbrq_head
) ? " EOS" : "",
1819 TBRQ_MULTIPLE(he_dev
->tbrq_head
) ? " MULTIPLE" : "");
1821 list_for_each_entry(__tpd
, &he_dev
->outstanding_tpds
, entry
) {
1822 if (TPD_ADDR(__tpd
->status
) == TBRQ_TPD(he_dev
->tbrq_head
)) {
1824 list_del(&__tpd
->entry
);
1830 hprintk("unable to locate tpd for dma buffer %x\n",
1831 TBRQ_TPD(he_dev
->tbrq_head
));
1832 goto next_tbrq_entry
;
1835 if (TBRQ_EOS(he_dev
->tbrq_head
)) {
1836 HPRINTK("wake_up(tx_waitq) cid 0x%x\n",
1837 he_mkcid(he_dev
, tpd
->vcc
->vpi
, tpd
->vcc
->vci
));
1839 wake_up(&HE_VCC(tpd
->vcc
)->tx_waitq
);
1841 goto next_tbrq_entry
;
1844 for (slot
= 0; slot
< TPD_MAXIOV
; ++slot
) {
1845 if (tpd
->iovec
[slot
].addr
)
1846 pci_unmap_single(he_dev
->pci_dev
,
1847 tpd
->iovec
[slot
].addr
,
1848 tpd
->iovec
[slot
].len
& TPD_LEN_MASK
,
1850 if (tpd
->iovec
[slot
].len
& TPD_LST
)
1855 if (tpd
->skb
) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
1856 if (tpd
->vcc
&& tpd
->vcc
->pop
)
1857 tpd
->vcc
->pop(tpd
->vcc
, tpd
->skb
);
1859 dev_kfree_skb_any(tpd
->skb
);
1864 pci_pool_free(he_dev
->tpd_pool
, tpd
, TPD_ADDR(tpd
->status
));
1865 he_dev
->tbrq_head
= (struct he_tbrq
*)
1866 ((unsigned long) he_dev
->tbrq_base
|
1867 TBRQ_MASK(he_dev
->tbrq_head
+ 1));
1871 if (updated
> he_dev
->tbrq_peak
)
1872 he_dev
->tbrq_peak
= updated
;
1874 he_writel(he_dev
, TBRQ_MASK(he_dev
->tbrq_head
),
1875 G0_TBRQ_H
+ (group
* 16));
1880 he_service_rbpl(struct he_dev
*he_dev
, int group
)
1882 struct he_rbp
*new_tail
;
1883 struct he_rbp
*rbpl_head
;
1884 struct he_buff
*heb
;
1889 rbpl_head
= (struct he_rbp
*) ((unsigned long)he_dev
->rbpl_base
|
1890 RBPL_MASK(he_readl(he_dev
, G0_RBPL_S
)));
1893 new_tail
= (struct he_rbp
*) ((unsigned long)he_dev
->rbpl_base
|
1894 RBPL_MASK(he_dev
->rbpl_tail
+1));
1896 /* table 3.42 -- rbpl_tail should never be set to rbpl_head */
1897 if (new_tail
== rbpl_head
)
1900 i
= find_next_zero_bit(he_dev
->rbpl_table
, RBPL_TABLE_SIZE
, he_dev
->rbpl_hint
);
1901 if (i
> (RBPL_TABLE_SIZE
- 1)) {
1902 i
= find_first_zero_bit(he_dev
->rbpl_table
, RBPL_TABLE_SIZE
);
1903 if (i
> (RBPL_TABLE_SIZE
- 1))
1906 he_dev
->rbpl_hint
= i
+ 1;
1908 heb
= pci_pool_alloc(he_dev
->rbpl_pool
, GFP_ATOMIC
|GFP_DMA
, &mapping
);
1911 heb
->mapping
= mapping
;
1912 list_add(&heb
->entry
, &he_dev
->rbpl_outstanding
);
1913 he_dev
->rbpl_virt
[i
] = heb
;
1914 set_bit(i
, he_dev
->rbpl_table
);
1915 new_tail
->idx
= i
<< RBP_IDX_OFFSET
;
1916 new_tail
->phys
= mapping
+ offsetof(struct he_buff
, data
);
1918 he_dev
->rbpl_tail
= new_tail
;
1923 he_writel(he_dev
, RBPL_MASK(he_dev
->rbpl_tail
), G0_RBPL_T
);
1927 he_tasklet(unsigned long data
)
1929 unsigned long flags
;
1930 struct he_dev
*he_dev
= (struct he_dev
*) data
;
1934 HPRINTK("tasklet (0x%lx)\n", data
);
1935 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
1937 while (he_dev
->irq_head
!= he_dev
->irq_tail
) {
1940 type
= ITYPE_TYPE(he_dev
->irq_head
->isw
);
1941 group
= ITYPE_GROUP(he_dev
->irq_head
->isw
);
1944 case ITYPE_RBRQ_THRESH
:
1945 HPRINTK("rbrq%d threshold\n", group
);
1947 case ITYPE_RBRQ_TIMER
:
1948 if (he_service_rbrq(he_dev
, group
))
1949 he_service_rbpl(he_dev
, group
);
1951 case ITYPE_TBRQ_THRESH
:
1952 HPRINTK("tbrq%d threshold\n", group
);
1954 case ITYPE_TPD_COMPLETE
:
1955 he_service_tbrq(he_dev
, group
);
1957 case ITYPE_RBPL_THRESH
:
1958 he_service_rbpl(he_dev
, group
);
1960 case ITYPE_RBPS_THRESH
:
1961 /* shouldn't happen unless small buffers enabled */
1964 HPRINTK("phy interrupt\n");
1965 #ifdef CONFIG_ATM_HE_USE_SUNI
1966 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
1967 if (he_dev
->atm_dev
->phy
&& he_dev
->atm_dev
->phy
->interrupt
)
1968 he_dev
->atm_dev
->phy
->interrupt(he_dev
->atm_dev
);
1969 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
1973 switch (type
|group
) {
1975 hprintk("parity error\n");
1978 hprintk("abort 0x%x\n", he_readl(he_dev
, ABORT_ADDR
));
1982 case ITYPE_TYPE(ITYPE_INVALID
):
1983 /* see 8.1.1 -- check all queues */
1985 HPRINTK("isw not updated 0x%x\n", he_dev
->irq_head
->isw
);
1987 he_service_rbrq(he_dev
, 0);
1988 he_service_rbpl(he_dev
, 0);
1989 he_service_tbrq(he_dev
, 0);
1992 hprintk("bad isw 0x%x?\n", he_dev
->irq_head
->isw
);
1995 he_dev
->irq_head
->isw
= ITYPE_INVALID
;
1997 he_dev
->irq_head
= (struct he_irq
*) NEXT_ENTRY(he_dev
->irq_base
, he_dev
->irq_head
, IRQ_MASK
);
2001 if (updated
> he_dev
->irq_peak
)
2002 he_dev
->irq_peak
= updated
;
2005 IRQ_SIZE(CONFIG_IRQ_SIZE
) |
2006 IRQ_THRESH(CONFIG_IRQ_THRESH
) |
2007 IRQ_TAIL(he_dev
->irq_tail
), IRQ0_HEAD
);
2008 (void) he_readl(he_dev
, INT_FIFO
); /* 8.1.2 controller errata; flush posted writes */
2010 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2014 he_irq_handler(int irq
, void *dev_id
)
2016 unsigned long flags
;
2017 struct he_dev
*he_dev
= (struct he_dev
* )dev_id
;
2023 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2025 he_dev
->irq_tail
= (struct he_irq
*) (((unsigned long)he_dev
->irq_base
) |
2026 (*he_dev
->irq_tailoffset
<< 2));
2028 if (he_dev
->irq_tail
== he_dev
->irq_head
) {
2029 HPRINTK("tailoffset not updated?\n");
2030 he_dev
->irq_tail
= (struct he_irq
*) ((unsigned long)he_dev
->irq_base
|
2031 ((he_readl(he_dev
, IRQ0_BASE
) & IRQ_MASK
) << 2));
2032 (void) he_readl(he_dev
, INT_FIFO
); /* 8.1.2 controller errata */
2036 if (he_dev
->irq_head
== he_dev
->irq_tail
/* && !IRQ_PENDING */)
2037 hprintk("spurious (or shared) interrupt?\n");
2040 if (he_dev
->irq_head
!= he_dev
->irq_tail
) {
2042 tasklet_schedule(&he_dev
->tasklet
);
2043 he_writel(he_dev
, INT_CLEAR_A
, INT_FIFO
); /* clear interrupt */
2044 (void) he_readl(he_dev
, INT_FIFO
); /* flush posted writes */
2046 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2047 return IRQ_RETVAL(handled
);
2051 static __inline__
void
2052 __enqueue_tpd(struct he_dev
*he_dev
, struct he_tpd
*tpd
, unsigned cid
)
2054 struct he_tpdrq
*new_tail
;
2056 HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n",
2057 tpd
, cid
, he_dev
->tpdrq_tail
);
2059 /* new_tail = he_dev->tpdrq_tail; */
2060 new_tail
= (struct he_tpdrq
*) ((unsigned long) he_dev
->tpdrq_base
|
2061 TPDRQ_MASK(he_dev
->tpdrq_tail
+1));
2064 * check to see if we are about to set the tail == head
2065 * if true, update the head pointer from the adapter
2066 * to see if this is really the case (reading the queue
2067 * head for every enqueue would be unnecessarily slow)
2070 if (new_tail
== he_dev
->tpdrq_head
) {
2071 he_dev
->tpdrq_head
= (struct he_tpdrq
*)
2072 (((unsigned long)he_dev
->tpdrq_base
) |
2073 TPDRQ_MASK(he_readl(he_dev
, TPDRQ_B_H
)));
2075 if (new_tail
== he_dev
->tpdrq_head
) {
2078 hprintk("tpdrq full (cid 0x%x)\n", cid
);
2081 * push tpd onto a transmit backlog queue
2082 * after service_tbrq, service the backlog
2083 * for now, we just drop the pdu
2085 for (slot
= 0; slot
< TPD_MAXIOV
; ++slot
) {
2086 if (tpd
->iovec
[slot
].addr
)
2087 pci_unmap_single(he_dev
->pci_dev
,
2088 tpd
->iovec
[slot
].addr
,
2089 tpd
->iovec
[slot
].len
& TPD_LEN_MASK
,
2094 tpd
->vcc
->pop(tpd
->vcc
, tpd
->skb
);
2096 dev_kfree_skb_any(tpd
->skb
);
2097 atomic_inc(&tpd
->vcc
->stats
->tx_err
);
2099 pci_pool_free(he_dev
->tpd_pool
, tpd
, TPD_ADDR(tpd
->status
));
2104 /* 2.1.5 transmit packet descriptor ready queue */
2105 list_add_tail(&tpd
->entry
, &he_dev
->outstanding_tpds
);
2106 he_dev
->tpdrq_tail
->tpd
= TPD_ADDR(tpd
->status
);
2107 he_dev
->tpdrq_tail
->cid
= cid
;
2110 he_dev
->tpdrq_tail
= new_tail
;
2112 he_writel(he_dev
, TPDRQ_MASK(he_dev
->tpdrq_tail
), TPDRQ_T
);
2113 (void) he_readl(he_dev
, TPDRQ_T
); /* flush posted writes */
2117 he_open(struct atm_vcc
*vcc
)
2119 unsigned long flags
;
2120 struct he_dev
*he_dev
= HE_DEV(vcc
->dev
);
2121 struct he_vcc
*he_vcc
;
2123 unsigned cid
, rsr0
, rsr1
, rsr4
, tsr0
, tsr0_aal
, tsr4
, period
, reg
, clock
;
2124 short vpi
= vcc
->vpi
;
2127 if (vci
== ATM_VCI_UNSPEC
|| vpi
== ATM_VPI_UNSPEC
)
2130 HPRINTK("open vcc %p %d.%d\n", vcc
, vpi
, vci
);
2132 set_bit(ATM_VF_ADDR
, &vcc
->flags
);
2134 cid
= he_mkcid(he_dev
, vpi
, vci
);
2136 he_vcc
= kmalloc(sizeof(struct he_vcc
), GFP_ATOMIC
);
2137 if (he_vcc
== NULL
) {
2138 hprintk("unable to allocate he_vcc during open\n");
2142 INIT_LIST_HEAD(&he_vcc
->buffers
);
2143 he_vcc
->pdu_len
= 0;
2144 he_vcc
->rc_index
= -1;
2146 init_waitqueue_head(&he_vcc
->rx_waitq
);
2147 init_waitqueue_head(&he_vcc
->tx_waitq
);
2149 vcc
->dev_data
= he_vcc
;
2151 if (vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2154 pcr_goal
= atm_pcr_goal(&vcc
->qos
.txtp
);
2156 pcr_goal
= he_dev
->atm_dev
->link_rate
;
2157 if (pcr_goal
< 0) /* means round down, technically */
2158 pcr_goal
= -pcr_goal
;
2160 HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid
, pcr_goal
);
2162 switch (vcc
->qos
.aal
) {
2164 tsr0_aal
= TSR0_AAL5
;
2168 tsr0_aal
= TSR0_AAL0_SDU
;
2169 tsr4
= TSR4_AAL0_SDU
;
2176 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2177 tsr0
= he_readl_tsr0(he_dev
, cid
);
2178 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2180 if (TSR0_CONN_STATE(tsr0
) != 0) {
2181 hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid
, tsr0
);
2186 switch (vcc
->qos
.txtp
.traffic_class
) {
2188 /* 2.3.3.1 open connection ubr */
2190 tsr0
= TSR0_UBR
| TSR0_GROUP(0) | tsr0_aal
|
2191 TSR0_USE_WMIN
| TSR0_UPDATE_GER
;
2195 /* 2.3.3.2 open connection cbr */
2197 /* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */
2198 if ((he_dev
->total_bw
+ pcr_goal
)
2199 > (he_dev
->atm_dev
->link_rate
* 9 / 10))
2205 spin_lock_irqsave(&he_dev
->global_lock
, flags
); /* also protects he_dev->cs_stper[] */
2207 /* find an unused cs_stper register */
2208 for (reg
= 0; reg
< HE_NUM_CS_STPER
; ++reg
)
2209 if (he_dev
->cs_stper
[reg
].inuse
== 0 ||
2210 he_dev
->cs_stper
[reg
].pcr
== pcr_goal
)
2213 if (reg
== HE_NUM_CS_STPER
) {
2215 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2219 he_dev
->total_bw
+= pcr_goal
;
2221 he_vcc
->rc_index
= reg
;
2222 ++he_dev
->cs_stper
[reg
].inuse
;
2223 he_dev
->cs_stper
[reg
].pcr
= pcr_goal
;
2225 clock
= he_is622(he_dev
) ? 66667000 : 50000000;
2226 period
= clock
/ pcr_goal
;
2228 HPRINTK("rc_index = %d period = %d\n",
2231 he_writel_mbox(he_dev
, rate_to_atmf(period
/2),
2233 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2235 tsr0
= TSR0_CBR
| TSR0_GROUP(0) | tsr0_aal
|
2244 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2246 he_writel_tsr0(he_dev
, tsr0
, cid
);
2247 he_writel_tsr4(he_dev
, tsr4
| 1, cid
);
2248 he_writel_tsr1(he_dev
, TSR1_MCR(rate_to_atmf(0)) |
2249 TSR1_PCR(rate_to_atmf(pcr_goal
)), cid
);
2250 he_writel_tsr2(he_dev
, TSR2_ACR(rate_to_atmf(pcr_goal
)), cid
);
2251 he_writel_tsr9(he_dev
, TSR9_OPEN_CONN
, cid
);
2253 he_writel_tsr3(he_dev
, 0x0, cid
);
2254 he_writel_tsr5(he_dev
, 0x0, cid
);
2255 he_writel_tsr6(he_dev
, 0x0, cid
);
2256 he_writel_tsr7(he_dev
, 0x0, cid
);
2257 he_writel_tsr8(he_dev
, 0x0, cid
);
2258 he_writel_tsr10(he_dev
, 0x0, cid
);
2259 he_writel_tsr11(he_dev
, 0x0, cid
);
2260 he_writel_tsr12(he_dev
, 0x0, cid
);
2261 he_writel_tsr13(he_dev
, 0x0, cid
);
2262 he_writel_tsr14(he_dev
, 0x0, cid
);
2263 (void) he_readl_tsr0(he_dev
, cid
); /* flush posted writes */
2264 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2267 if (vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2270 HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid
,
2271 &HE_VCC(vcc
)->rx_waitq
);
2273 switch (vcc
->qos
.aal
) {
2285 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2287 rsr0
= he_readl_rsr0(he_dev
, cid
);
2288 if (rsr0
& RSR0_OPEN_CONN
) {
2289 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2291 hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid
, rsr0
);
2296 rsr1
= RSR1_GROUP(0) | RSR1_RBPL_ONLY
;
2297 rsr4
= RSR4_GROUP(0) | RSR4_RBPL_ONLY
;
2298 rsr0
= vcc
->qos
.rxtp
.traffic_class
== ATM_UBR
?
2299 (RSR0_EPD_ENABLE
|RSR0_PPD_ENABLE
) : 0;
2301 #ifdef USE_CHECKSUM_HW
2302 if (vpi
== 0 && vci
>= ATM_NOT_RSV_VCI
)
2303 rsr0
|= RSR0_TCP_CKSUM
;
2306 he_writel_rsr4(he_dev
, rsr4
, cid
);
2307 he_writel_rsr1(he_dev
, rsr1
, cid
);
2308 /* 5.1.11 last parameter initialized should be
2309 the open/closed indication in rsr0 */
2310 he_writel_rsr0(he_dev
,
2311 rsr0
| RSR0_START_PDU
| RSR0_OPEN_CONN
| aal
, cid
);
2312 (void) he_readl_rsr0(he_dev
, cid
); /* flush posted writes */
2314 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2321 clear_bit(ATM_VF_ADDR
, &vcc
->flags
);
2324 set_bit(ATM_VF_READY
, &vcc
->flags
);
2330 he_close(struct atm_vcc
*vcc
)
2332 unsigned long flags
;
2333 DECLARE_WAITQUEUE(wait
, current
);
2334 struct he_dev
*he_dev
= HE_DEV(vcc
->dev
);
2337 struct he_vcc
*he_vcc
= HE_VCC(vcc
);
2338 #define MAX_RETRY 30
2339 int retry
= 0, sleep
= 1, tx_inuse
;
2341 HPRINTK("close vcc %p %d.%d\n", vcc
, vcc
->vpi
, vcc
->vci
);
2343 clear_bit(ATM_VF_READY
, &vcc
->flags
);
2344 cid
= he_mkcid(he_dev
, vcc
->vpi
, vcc
->vci
);
2346 if (vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2349 HPRINTK("close rx cid 0x%x\n", cid
);
2351 /* 2.7.2.2 close receive operation */
2353 /* wait for previous close (if any) to finish */
2355 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2356 while (he_readl(he_dev
, RCC_STAT
) & RCC_BUSY
) {
2357 HPRINTK("close cid 0x%x RCC_BUSY\n", cid
);
2361 set_current_state(TASK_UNINTERRUPTIBLE
);
2362 add_wait_queue(&he_vcc
->rx_waitq
, &wait
);
2364 he_writel_rsr0(he_dev
, RSR0_CLOSE_CONN
, cid
);
2365 (void) he_readl_rsr0(he_dev
, cid
); /* flush posted writes */
2366 he_writel_mbox(he_dev
, cid
, RXCON_CLOSE
);
2367 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2369 timeout
= schedule_timeout(30*HZ
);
2371 remove_wait_queue(&he_vcc
->rx_waitq
, &wait
);
2372 set_current_state(TASK_RUNNING
);
2375 hprintk("close rx timeout cid 0x%x\n", cid
);
2377 HPRINTK("close rx cid 0x%x complete\n", cid
);
2381 if (vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2382 volatile unsigned tsr4
, tsr0
;
2385 HPRINTK("close tx cid 0x%x\n", cid
);
2389 * ... the host must first stop queueing packets to the TPDRQ
2390 * on the connection to be closed, then wait for all outstanding
2391 * packets to be transmitted and their buffers returned to the
2392 * TBRQ. When the last packet on the connection arrives in the
2393 * TBRQ, the host issues the close command to the adapter.
2396 while (((tx_inuse
= atomic_read(&sk_atm(vcc
)->sk_wmem_alloc
)) > 1) &&
2397 (retry
< MAX_RETRY
)) {
2406 hprintk("close tx cid 0x%x tx_inuse = %d\n", cid
, tx_inuse
);
2408 /* 2.3.1.1 generic close operations with flush */
2410 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2411 he_writel_tsr4_upper(he_dev
, TSR4_FLUSH_CONN
, cid
);
2412 /* also clears TSR4_SESSION_ENDED */
2414 switch (vcc
->qos
.txtp
.traffic_class
) {
2416 he_writel_tsr1(he_dev
,
2417 TSR1_MCR(rate_to_atmf(200000))
2418 | TSR1_PCR(0), cid
);
2421 he_writel_tsr14_upper(he_dev
, TSR14_DELETE
, cid
);
2424 (void) he_readl_tsr4(he_dev
, cid
); /* flush posted writes */
2426 tpd
= __alloc_tpd(he_dev
);
2428 hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid
);
2429 goto close_tx_incomplete
;
2431 tpd
->status
|= TPD_EOS
| TPD_INT
;
2436 set_current_state(TASK_UNINTERRUPTIBLE
);
2437 add_wait_queue(&he_vcc
->tx_waitq
, &wait
);
2438 __enqueue_tpd(he_dev
, tpd
, cid
);
2439 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2441 timeout
= schedule_timeout(30*HZ
);
2443 remove_wait_queue(&he_vcc
->tx_waitq
, &wait
);
2444 set_current_state(TASK_RUNNING
);
2446 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2449 hprintk("close tx timeout cid 0x%x\n", cid
);
2450 goto close_tx_incomplete
;
2453 while (!((tsr4
= he_readl_tsr4(he_dev
, cid
)) & TSR4_SESSION_ENDED
)) {
2454 HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid
, tsr4
);
2458 while (TSR0_CONN_STATE(tsr0
= he_readl_tsr0(he_dev
, cid
)) != 0) {
2459 HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid
, tsr0
);
2463 close_tx_incomplete
:
2465 if (vcc
->qos
.txtp
.traffic_class
== ATM_CBR
) {
2466 int reg
= he_vcc
->rc_index
;
2468 HPRINTK("cs_stper reg = %d\n", reg
);
2470 if (he_dev
->cs_stper
[reg
].inuse
== 0)
2471 hprintk("cs_stper[%d].inuse = 0!\n", reg
);
2473 --he_dev
->cs_stper
[reg
].inuse
;
2475 he_dev
->total_bw
-= he_dev
->cs_stper
[reg
].pcr
;
2477 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2479 HPRINTK("close tx cid 0x%x complete\n", cid
);
2484 clear_bit(ATM_VF_ADDR
, &vcc
->flags
);
2488 he_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
2490 unsigned long flags
;
2491 struct he_dev
*he_dev
= HE_DEV(vcc
->dev
);
2492 unsigned cid
= he_mkcid(he_dev
, vcc
->vpi
, vcc
->vci
);
2494 #ifdef USE_SCATTERGATHER
2498 #define HE_TPD_BUFSIZE 0xffff
2500 HPRINTK("send %d.%d\n", vcc
->vpi
, vcc
->vci
);
2502 if ((skb
->len
> HE_TPD_BUFSIZE
) ||
2503 ((vcc
->qos
.aal
== ATM_AAL0
) && (skb
->len
!= ATM_AAL0_SDU
))) {
2504 hprintk("buffer too large (or small) -- %d bytes\n", skb
->len
);
2508 dev_kfree_skb_any(skb
);
2509 atomic_inc(&vcc
->stats
->tx_err
);
2513 #ifndef USE_SCATTERGATHER
2514 if (skb_shinfo(skb
)->nr_frags
) {
2515 hprintk("no scatter/gather support\n");
2519 dev_kfree_skb_any(skb
);
2520 atomic_inc(&vcc
->stats
->tx_err
);
2524 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2526 tpd
= __alloc_tpd(he_dev
);
2531 dev_kfree_skb_any(skb
);
2532 atomic_inc(&vcc
->stats
->tx_err
);
2533 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2537 if (vcc
->qos
.aal
== ATM_AAL5
)
2538 tpd
->status
|= TPD_CELLTYPE(TPD_USERCELL
);
2540 char *pti_clp
= (void *) (skb
->data
+ 3);
2543 pti
= (*pti_clp
& ATM_HDR_PTI_MASK
) >> ATM_HDR_PTI_SHIFT
;
2544 clp
= (*pti_clp
& ATM_HDR_CLP
);
2545 tpd
->status
|= TPD_CELLTYPE(pti
);
2547 tpd
->status
|= TPD_CLP
;
2549 skb_pull(skb
, ATM_AAL0_SDU
- ATM_CELL_PAYLOAD
);
2552 #ifdef USE_SCATTERGATHER
2553 tpd
->iovec
[slot
].addr
= pci_map_single(he_dev
->pci_dev
, skb
->data
,
2554 skb_headlen(skb
), PCI_DMA_TODEVICE
);
2555 tpd
->iovec
[slot
].len
= skb_headlen(skb
);
2558 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2559 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2561 if (slot
== TPD_MAXIOV
) { /* queue tpd; start new tpd */
2563 tpd
->skb
= NULL
; /* not the last fragment
2564 so dont ->push() yet */
2567 __enqueue_tpd(he_dev
, tpd
, cid
);
2568 tpd
= __alloc_tpd(he_dev
);
2573 dev_kfree_skb_any(skb
);
2574 atomic_inc(&vcc
->stats
->tx_err
);
2575 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2578 tpd
->status
|= TPD_USERCELL
;
2582 tpd
->iovec
[slot
].addr
= pci_map_single(he_dev
->pci_dev
,
2583 (void *) page_address(frag
->page
) + frag
->page_offset
,
2584 frag
->size
, PCI_DMA_TODEVICE
);
2585 tpd
->iovec
[slot
].len
= frag
->size
;
2590 tpd
->iovec
[slot
- 1].len
|= TPD_LST
;
2592 tpd
->address0
= pci_map_single(he_dev
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2593 tpd
->length0
= skb
->len
| TPD_LST
;
2595 tpd
->status
|= TPD_INT
;
2600 ATM_SKB(skb
)->vcc
= vcc
;
2602 __enqueue_tpd(he_dev
, tpd
, cid
);
2603 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2605 atomic_inc(&vcc
->stats
->tx
);
2611 he_ioctl(struct atm_dev
*atm_dev
, unsigned int cmd
, void __user
*arg
)
2613 unsigned long flags
;
2614 struct he_dev
*he_dev
= HE_DEV(atm_dev
);
2615 struct he_ioctl_reg reg
;
2620 if (!capable(CAP_NET_ADMIN
))
2623 if (copy_from_user(®
, arg
,
2624 sizeof(struct he_ioctl_reg
)))
2627 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2629 case HE_REGTYPE_PCI
:
2630 if (reg
.addr
>= HE_REGMAP_SIZE
) {
2635 reg
.val
= he_readl(he_dev
, reg
.addr
);
2637 case HE_REGTYPE_RCM
:
2639 he_readl_rcm(he_dev
, reg
.addr
);
2641 case HE_REGTYPE_TCM
:
2643 he_readl_tcm(he_dev
, reg
.addr
);
2645 case HE_REGTYPE_MBOX
:
2647 he_readl_mbox(he_dev
, reg
.addr
);
2653 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2655 if (copy_to_user(arg
, ®
,
2656 sizeof(struct he_ioctl_reg
)))
2660 #ifdef CONFIG_ATM_HE_USE_SUNI
2661 if (atm_dev
->phy
&& atm_dev
->phy
->ioctl
)
2662 err
= atm_dev
->phy
->ioctl(atm_dev
, cmd
, arg
);
2663 #else /* CONFIG_ATM_HE_USE_SUNI */
2665 #endif /* CONFIG_ATM_HE_USE_SUNI */
2673 he_phy_put(struct atm_dev
*atm_dev
, unsigned char val
, unsigned long addr
)
2675 unsigned long flags
;
2676 struct he_dev
*he_dev
= HE_DEV(atm_dev
);
2678 HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val
, addr
);
2680 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2681 he_writel(he_dev
, val
, FRAMER
+ (addr
*4));
2682 (void) he_readl(he_dev
, FRAMER
+ (addr
*4)); /* flush posted writes */
2683 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2687 static unsigned char
2688 he_phy_get(struct atm_dev
*atm_dev
, unsigned long addr
)
2690 unsigned long flags
;
2691 struct he_dev
*he_dev
= HE_DEV(atm_dev
);
2694 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2695 reg
= he_readl(he_dev
, FRAMER
+ (addr
*4));
2696 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2698 HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr
, reg
);
2703 he_proc_read(struct atm_dev
*dev
, loff_t
*pos
, char *page
)
2705 unsigned long flags
;
2706 struct he_dev
*he_dev
= HE_DEV(dev
);
2709 struct he_rbrq
*rbrq_tail
;
2710 struct he_tpdrq
*tpdrq_head
;
2711 int rbpl_head
, rbpl_tail
;
2713 static long mcc
= 0, oec
= 0, dcc
= 0, cec
= 0;
2718 return sprintf(page
, "ATM he driver\n");
2721 return sprintf(page
, "%s%s\n\n",
2722 he_dev
->prod_id
, he_dev
->media
& 0x40 ? "SM" : "MM");
2725 return sprintf(page
, "Mismatched Cells VPI/VCI Not Open Dropped Cells RCM Dropped Cells\n");
2727 spin_lock_irqsave(&he_dev
->global_lock
, flags
);
2728 mcc
+= he_readl(he_dev
, MCC
);
2729 oec
+= he_readl(he_dev
, OEC
);
2730 dcc
+= he_readl(he_dev
, DCC
);
2731 cec
+= he_readl(he_dev
, CEC
);
2732 spin_unlock_irqrestore(&he_dev
->global_lock
, flags
);
2735 return sprintf(page
, "%16ld %16ld %13ld %17ld\n\n",
2736 mcc
, oec
, dcc
, cec
);
2739 return sprintf(page
, "irq_size = %d inuse = ? peak = %d\n",
2740 CONFIG_IRQ_SIZE
, he_dev
->irq_peak
);
2743 return sprintf(page
, "tpdrq_size = %d inuse = ?\n",
2747 return sprintf(page
, "rbrq_size = %d inuse = ? peak = %d\n",
2748 CONFIG_RBRQ_SIZE
, he_dev
->rbrq_peak
);
2751 return sprintf(page
, "tbrq_size = %d peak = %d\n",
2752 CONFIG_TBRQ_SIZE
, he_dev
->tbrq_peak
);
2756 rbpl_head
= RBPL_MASK(he_readl(he_dev
, G0_RBPL_S
));
2757 rbpl_tail
= RBPL_MASK(he_readl(he_dev
, G0_RBPL_T
));
2759 inuse
= rbpl_head
- rbpl_tail
;
2761 inuse
+= CONFIG_RBPL_SIZE
* sizeof(struct he_rbp
);
2762 inuse
/= sizeof(struct he_rbp
);
2765 return sprintf(page
, "rbpl_size = %d inuse = %d\n\n",
2766 CONFIG_RBPL_SIZE
, inuse
);
2770 return sprintf(page
, "rate controller periods (cbr)\n pcr #vc\n");
2772 for (i
= 0; i
< HE_NUM_CS_STPER
; ++i
)
2774 return sprintf(page
, "cs_stper%-2d %8ld %3d\n", i
,
2775 he_dev
->cs_stper
[i
].pcr
,
2776 he_dev
->cs_stper
[i
].inuse
);
2779 return sprintf(page
, "total bw (cbr): %d (limit %d)\n",
2780 he_dev
->total_bw
, he_dev
->atm_dev
->link_rate
* 10 / 9);
2785 /* eeprom routines -- see 4.7 */
2787 static u8
read_prom_byte(struct he_dev
*he_dev
, int addr
)
2789 u32 val
= 0, tmp_read
= 0;
2793 val
= readl(he_dev
->membase
+ HOST_CNTL
);
2796 /* Turn on write enable */
2798 he_writel(he_dev
, val
, HOST_CNTL
);
2800 /* Send READ instruction */
2801 for (i
= 0; i
< ARRAY_SIZE(readtab
); i
++) {
2802 he_writel(he_dev
, val
| readtab
[i
], HOST_CNTL
);
2803 udelay(EEPROM_DELAY
);
2806 /* Next, we need to send the byte address to read from */
2807 for (i
= 7; i
>= 0; i
--) {
2808 he_writel(he_dev
, val
| clocktab
[j
++] | (((addr
>> i
) & 1) << 9), HOST_CNTL
);
2809 udelay(EEPROM_DELAY
);
2810 he_writel(he_dev
, val
| clocktab
[j
++] | (((addr
>> i
) & 1) << 9), HOST_CNTL
);
2811 udelay(EEPROM_DELAY
);
2816 val
&= 0xFFFFF7FF; /* Turn off write enable */
2817 he_writel(he_dev
, val
, HOST_CNTL
);
2819 /* Now, we can read data from the EEPROM by clocking it in */
2820 for (i
= 7; i
>= 0; i
--) {
2821 he_writel(he_dev
, val
| clocktab
[j
++], HOST_CNTL
);
2822 udelay(EEPROM_DELAY
);
2823 tmp_read
= he_readl(he_dev
, HOST_CNTL
);
2824 byte_read
|= (unsigned char)
2825 ((tmp_read
& ID_DOUT
) >> ID_DOFFSET
<< i
);
2826 he_writel(he_dev
, val
| clocktab
[j
++], HOST_CNTL
);
2827 udelay(EEPROM_DELAY
);
2830 he_writel(he_dev
, val
| ID_CS
, HOST_CNTL
);
2831 udelay(EEPROM_DELAY
);
2836 MODULE_LICENSE("GPL");
2837 MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
2838 MODULE_DESCRIPTION("ForeRunnerHE ATM Adapter driver");
2839 module_param(disable64
, bool, 0);
2840 MODULE_PARM_DESC(disable64
, "disable 64-bit pci bus transfers");
2841 module_param(nvpibits
, short, 0);
2842 MODULE_PARM_DESC(nvpibits
, "numbers of bits for vpi (default 0)");
2843 module_param(nvcibits
, short, 0);
2844 MODULE_PARM_DESC(nvcibits
, "numbers of bits for vci (default 12)");
2845 module_param(rx_skb_reserve
, short, 0);
2846 MODULE_PARM_DESC(rx_skb_reserve
, "padding for receive skb (default 16)");
2847 module_param(irq_coalesce
, bool, 0);
2848 MODULE_PARM_DESC(irq_coalesce
, "use interrupt coalescing (default 1)");
2849 module_param(sdh
, bool, 0);
2850 MODULE_PARM_DESC(sdh
, "use SDH framing (default 0)");
2852 static struct pci_device_id he_pci_tbl
[] = {
2853 { PCI_VDEVICE(FORE
, PCI_DEVICE_ID_FORE_HE
), 0 },
2857 MODULE_DEVICE_TABLE(pci
, he_pci_tbl
);
2859 static struct pci_driver he_driver
= {
2861 .probe
= he_init_one
,
2862 .remove
= he_remove_one
,
2863 .id_table
= he_pci_tbl
,
2866 module_pci_driver(he_driver
);