drivers/clocksource/time-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370/XP SoC timer handling.
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Timer 0 is used as free-running clocksource, while timer 1 is
  15  * used as clock_event_device.
  16  *
  17  * ---
  18  * Clocksource driver for Armada 370 and Armada XP SoC.
  19  * This driver implements one compatible string for each SoC, given
  20  * each has its own characteristics:
  21  *
  22  *   * Armada 370 has no 25 MHz fixed timer.
  23  *
  24  *   * Armada XP cannot work properly without such 25 MHz fixed timer as
  25  *     doing otherwise leads to using a clocksource whose frequency varies
  26  *     when doing cpufreq frequency changes.
  27  *
  28  * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
  29  */
  30
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/kernel.h>
  34 #include <linux/clk.h>
  35 #include <linux/cpu.h>
  36 #include <linux/timer.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/of.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/of_address.h>
  42 #include <linux/irq.h>
  43 #include <linux/module.h>
  44 #include <linux/sched_clock.h>
  45 #include <linux/percpu.h>
  46 #include <linux/syscore_ops.h>
  47
  48 /*
  49  * Timer block registers.
  50  */
  51 #define TIMER_CTRL_OFF          0x0000
  52 #define  TIMER0_EN               BIT(0)
  53 #define  TIMER0_RELOAD_EN        BIT(1)
  54 #define  TIMER0_25MHZ            BIT(11)
  55 #define  TIMER0_DIV(div)         ((div) << 19)
  56 #define  TIMER1_EN               BIT(2)
  57 #define  TIMER1_RELOAD_EN        BIT(3)
  58 #define  TIMER1_25MHZ            BIT(12)
  59 #define  TIMER1_DIV(div)         ((div) << 22)
  60 #define TIMER_EVENTS_STATUS     0x0004
  61 #define  TIMER0_CLR_MASK         (~0x1)
  62 #define  TIMER1_CLR_MASK         (~0x100)
  63 #define TIMER0_RELOAD_OFF       0x0010
  64 #define TIMER0_VAL_OFF          0x0014
  65 #define TIMER1_RELOAD_OFF       0x0018
  66 #define TIMER1_VAL_OFF          0x001c
  67
  68 #define LCL_TIMER_EVENTS_STATUS 0x0028
  69 /* Global timers are connected to the coherency fabric clock, and the
  70    below divider reduces their incrementing frequency. */
  71 #define TIMER_DIVIDER_SHIFT     5
  72 #define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
  73
  74 /*
  75  * SoC-specific data.
  76  */
  77 static void __iomem *timer_base, *local_base;
  78 static unsigned int timer_clk;
  79 static bool timer25Mhz = true;
  80 static u32 enable_mask;
  81
  82 /*
  83  * Number of timer ticks per jiffy.
  84  */
  85 static u32 ticks_per_jiffy;
  86
  87 static struct clock_event_device __percpu *armada_370_xp_evt;
  88
  89 static void local_timer_ctrl_clrset(u32 clr, u32 set)
  90 {
  91         writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
  92                 local_base + TIMER_CTRL_OFF);
  93 }
  94
  95 static u64 notrace armada_370_xp_read_sched_clock(void)
  96 {
  97         return ~readl(timer_base + TIMER0_VAL_OFF);
  98 }
  99
 100 /*
 101  * Clockevent handling.
 102  */
 103 static int
 104 armada_370_xp_clkevt_next_event(unsigned long delta,
 105                                 struct clock_event_device *dev)
 106 {
 107         /*
 108          * Clear clockevent timer interrupt.
 109          */
 110         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 111
 112         /*
 113          * Setup new clockevent timer value.
 114          */
 115         writel(delta, local_base + TIMER0_VAL_OFF);
 116
 117         /*
 118          * Enable the timer.
 119          */
 120         local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
 121         return 0;
 122 }
 123
 124 static void
 125 armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 126                           struct clock_event_device *dev)
 127 {
 128         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 129
 130                 /*
 131                  * Setup timer to fire at 1/HZ intervals.
 132                  */
 133                 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
 134                 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
 135
 136                 /*
 137                  * Enable timer.
 138                  */
 139                 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 140         } else {
 141                 /*
 142                  * Disable timer.
 143                  */
 144                 local_timer_ctrl_clrset(TIMER0_EN, 0);
 145
 146                 /*
 147                  * ACK pending timer interrupt.
 148                  */
 149                 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 150         }
 151 }
 152
 153 static int armada_370_xp_clkevt_irq;
 154
 155 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
 156 {
 157         /*
 158          * ACK timer interrupt and call event handler.
 159          */
 160         struct clock_event_device *evt = dev_id;
 161
 162         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 163         evt->event_handler(evt);
 164
 165         return IRQ_HANDLED;
 166 }
 167
 168 /*
 169  * Setup the local clock events for a CPU.
 170  */
 171 static int armada_370_xp_timer_setup(struct clock_event_device *evt)
 172 {
 173         u32 clr = 0, set = 0;
 174         int cpu = smp_processor_id();
 175
 176         if (timer25Mhz)
 177                 set = TIMER0_25MHZ;
 178         else
 179                 clr = TIMER0_25MHZ;
 180         local_timer_ctrl_clrset(clr, set);
 181
 182         evt->name               = "armada_370_xp_per_cpu_tick",
 183         evt->features           = CLOCK_EVT_FEAT_ONESHOT |
 184                                   CLOCK_EVT_FEAT_PERIODIC;
 185         evt->shift              = 32,
 186         evt->rating             = 300,
 187         evt->set_next_event     = armada_370_xp_clkevt_next_event,
 188         evt->set_mode           = armada_370_xp_clkevt_mode,
 189         evt->irq                = armada_370_xp_clkevt_irq;
 190         evt->cpumask            = cpumask_of(cpu);
 191
 192         clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
 193         enable_percpu_irq(evt->irq, 0);
 194
 195         return 0;
 196 }
 197
 198 static void armada_370_xp_timer_stop(struct clock_event_device *evt)
 199 {
 200         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 201         disable_percpu_irq(evt->irq);
 202 }
 203
 204 static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
 205                                            unsigned long action, void *hcpu)
 206 {
 207         /*
 208          * Grab cpu pointer in each case to avoid spurious
 209          * preemptible warnings
 210          */
 211         switch (action & ~CPU_TASKS_FROZEN) {
 212         case CPU_STARTING:
 213                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 214                 break;
 215         case CPU_DYING:
 216                 armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
 217                 break;
 218         }
 219
 220         return NOTIFY_OK;
 221 }
 222
 223 static struct notifier_block armada_370_xp_timer_cpu_nb = {
 224         .notifier_call = armada_370_xp_timer_cpu_notify,
 225 };
 226
 227 static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
 228
 229 static int armada_370_xp_timer_suspend(void)
 230 {
 231         timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
 232         timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
 233         return 0;
 234 }
 235
 236 static void armada_370_xp_timer_resume(void)
 237 {
 238         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 239         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 240         writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
 241         writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
 242 }
 243
 244 struct syscore_ops armada_370_xp_timer_syscore_ops = {
 245         .suspend        = armada_370_xp_timer_suspend,
 246         .resume         = armada_370_xp_timer_resume,
 247 };
 248
 249 static void __init armada_370_xp_timer_common_init(struct device_node *np)
 250 {
 251         u32 clr = 0, set = 0;
 252         int res;
 253
 254         timer_base = of_iomap(np, 0);
 255         WARN_ON(!timer_base);
 256         local_base = of_iomap(np, 1);
 257
 258         if (timer25Mhz) {
 259                 set = TIMER0_25MHZ;
 260                 enable_mask = TIMER0_EN;
 261         } else {
 262                 clr = TIMER0_25MHZ;
 263                 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
 264         }
 265         atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
 266         local_timer_ctrl_clrset(clr, set);
 267
 268         /*
 269          * We use timer 0 as clocksource, and private(local) timer 0
 270          * for clockevents
 271          */
 272         armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
 273
 274         ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
 275
 276         /*
 277          * Setup free-running clocksource timer (interrupts
 278          * disabled).
 279          */
 280         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 281         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 282
 283         atomic_io_modify(timer_base + TIMER_CTRL_OFF,
 284                 TIMER0_RELOAD_EN | enable_mask,
 285                 TIMER0_RELOAD_EN | enable_mask);
 286
 287         /*
 288          * Set scale and timer for sched_clock.
 289          */
 290         sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
 291
 292         clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
 293                               "armada_370_xp_clocksource",
 294                               timer_clk, 300, 32, clocksource_mmio_readl_down);
 295
 296         register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
 297
 298         armada_370_xp_evt = alloc_percpu(struct clock_event_device);
 299
 300
 301         /*
 302          * Setup clockevent timer (interrupt-driven).
 303          */
 304         res = request_percpu_irq(armada_370_xp_clkevt_irq,
 305                                 armada_370_xp_timer_interrupt,
 306                                 "armada_370_xp_per_cpu_tick",
 307                                 armada_370_xp_evt);
 308         /* Immediately configure the timer on the boot CPU */
 309         if (!res)
 310                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 311
 312         register_syscore_ops(&armada_370_xp_timer_syscore_ops);
 313 }
 314
 315 static void __init armada_xp_timer_init(struct device_node *np)
 316 {
 317         struct clk *clk = of_clk_get_by_name(np, "fixed");
 318
 319         /* The 25Mhz fixed clock is mandatory, and must always be available */
 320         BUG_ON(IS_ERR(clk));
 321         clk_prepare_enable(clk);
 322         timer_clk = clk_get_rate(clk);
 323
 324         armada_370_xp_timer_common_init(np);
 325 }
 326 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
 327                        armada_xp_timer_init);
 328
 329 static void __init armada_375_timer_init(struct device_node *np)
 330 {
 331         struct clk *clk;
 332
 333         clk = of_clk_get_by_name(np, "fixed");
 334         if (!IS_ERR(clk)) {
 335                 clk_prepare_enable(clk);
 336                 timer_clk = clk_get_rate(clk);
 337         } else {
 338
 339                 /*
 340                  * This fallback is required in order to retain proper
 341                  * devicetree backwards compatibility.
 342                  */
 343                 clk = of_clk_get(np, 0);
 344
 345                 /* Must have at least a clock */
 346                 BUG_ON(IS_ERR(clk));
 347                 clk_prepare_enable(clk);
 348                 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
 349                 timer25Mhz = false;
 350         }
 351
 352         armada_370_xp_timer_common_init(np);
 353 }
 354 CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
 355                        armada_375_timer_init);
 356
 357 static void __init armada_370_timer_init(struct device_node *np)
 358 {
 359         struct clk *clk = of_clk_get(np, 0);
 360
 361         BUG_ON(IS_ERR(clk));
 362         clk_prepare_enable(clk);
 363         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
 364         timer25Mhz = false;
 365
 366         armada_370_xp_timer_common_init(np);
 367 }
 368 CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
 369                        armada_370_timer_init);