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ARM: dts: add 'dr_mode' property to hsotg devices for exynos boards
[linux/fpc-iii.git] / drivers / iommu / amd_iommu_init.c
blobb0522f15730fbbc0b6dda1aa1a100cf9af6b426d
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/iommu.h>
30 #include <asm/pci-direct.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 #include <asm/io_apic.h>
36 #include <asm/irq_remapping.h>
37
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
41
42 /*
43 * definitions for the ACPI scanning code
44 */
45 #define IVRS_HEADER_LENGTH 48
46
47 #define ACPI_IVHD_TYPE 0x10
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
51
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
61
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
64
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
69
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
72
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
81
82 /*
83 * ACPI table definitions
84 *
85 * These data structures are laid over the table to parse the important values
86 * out of it.
87 */
88
89 /*
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
92 */
93 struct ivhd_header {
94 u8 type;
95 u8 flags;
96 u16 length;
97 u16 devid;
98 u16 cap_ptr;
99 u64 mmio_phys;
100 u16 pci_seg;
101 u16 info;
102 u32 efr;
103 } __attribute__((packed));
104
105 /*
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
108 */
109 struct ivhd_entry {
110 u8 type;
111 u16 devid;
112 u8 flags;
113 u32 ext;
114 } __attribute__((packed));
115
116 /*
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
119 */
120 struct ivmd_header {
121 u8 type;
122 u8 flags;
123 u16 length;
124 u16 devid;
125 u16 aux;
126 u64 resv;
127 u64 range_start;
128 u64 range_length;
129 } __attribute__((packed));
130
131 bool amd_iommu_dump;
132 bool amd_iommu_irq_remap __read_mostly;
133
134 static bool amd_iommu_detected;
135 static bool __initdata amd_iommu_disabled;
136
137 u16 amd_iommu_last_bdf; /* largest PCI device id we have
138 to handle */
139 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
140 we find in ACPI */
141 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
142
143 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
144 system */
145
146 /* Array to assign indices to IOMMUs*/
147 struct amd_iommu *amd_iommus[MAX_IOMMUS];
148 int amd_iommus_present;
149
150 /* IOMMUs have a non-present cache? */
151 bool amd_iommu_np_cache __read_mostly;
152 bool amd_iommu_iotlb_sup __read_mostly = true;
153
154 u32 amd_iommu_max_pasid __read_mostly = ~0;
155
156 bool amd_iommu_v2_present __read_mostly;
157 bool amd_iommu_pc_present __read_mostly;
158
159 bool amd_iommu_force_isolation __read_mostly;
160
161 /*
162 * List of protection domains - used during resume
163 */
164 LIST_HEAD(amd_iommu_pd_list);
165 spinlock_t amd_iommu_pd_lock;
166
167 /*
168 * Pointer to the device table which is shared by all AMD IOMMUs
169 * it is indexed by the PCI device id or the HT unit id and contains
170 * information about the domain the device belongs to as well as the
171 * page table root pointer.
172 */
173 struct dev_table_entry *amd_iommu_dev_table;
174
175 /*
176 * The alias table is a driver specific data structure which contains the
177 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * More than one device can share the same requestor id.
179 */
180 u16 *amd_iommu_alias_table;
181
182 /*
183 * The rlookup table is used to find the IOMMU which is responsible
184 * for a specific device. It is also indexed by the PCI device id.
185 */
186 struct amd_iommu **amd_iommu_rlookup_table;
187
188 /*
189 * This table is used to find the irq remapping table for a given device id
190 * quickly.
191 */
192 struct irq_remap_table **irq_lookup_table;
193
194 /*
195 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
196 * to know which ones are already in use.
197 */
198 unsigned long *amd_iommu_pd_alloc_bitmap;
199
200 static u32 dev_table_size; /* size of the device table */
201 static u32 alias_table_size; /* size of the alias table */
202 static u32 rlookup_table_size; /* size if the rlookup table */
203
204 enum iommu_init_state {
205 IOMMU_START_STATE,
206 IOMMU_IVRS_DETECTED,
207 IOMMU_ACPI_FINISHED,
208 IOMMU_ENABLED,
209 IOMMU_PCI_INIT,
210 IOMMU_INTERRUPTS_EN,
211 IOMMU_DMA_OPS,
212 IOMMU_INITIALIZED,
213 IOMMU_NOT_FOUND,
214 IOMMU_INIT_ERROR,
215 };
216
217 /* Early ioapic and hpet maps from kernel command line */
218 #define EARLY_MAP_SIZE 4
219 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
220 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
221 static int __initdata early_ioapic_map_size;
222 static int __initdata early_hpet_map_size;
223 static bool __initdata cmdline_maps;
224
225 static enum iommu_init_state init_state = IOMMU_START_STATE;
226
227 static int amd_iommu_enable_interrupts(void);
228 static int __init iommu_go_to_state(enum iommu_init_state state);
229
230 static inline void update_last_devid(u16 devid)
231 {
232 if (devid > amd_iommu_last_bdf)
233 amd_iommu_last_bdf = devid;
234 }
235
236 static inline unsigned long tbl_size(int entry_size)
237 {
238 unsigned shift = PAGE_SHIFT +
239 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
240
241 return 1UL << shift;
242 }
243
244 /* Access to l1 and l2 indexed register spaces */
245
246 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
247 {
248 u32 val;
249
250 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
251 pci_read_config_dword(iommu->dev, 0xfc, &val);
252 return val;
253 }
254
255 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
256 {
257 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
258 pci_write_config_dword(iommu->dev, 0xfc, val);
259 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
260 }
261
262 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
263 {
264 u32 val;
265
266 pci_write_config_dword(iommu->dev, 0xf0, address);
267 pci_read_config_dword(iommu->dev, 0xf4, &val);
268 return val;
269 }
270
271 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
272 {
273 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
274 pci_write_config_dword(iommu->dev, 0xf4, val);
275 }
276
277 /****************************************************************************
278 *
279 * AMD IOMMU MMIO register space handling functions
280 *
281 * These functions are used to program the IOMMU device registers in
282 * MMIO space required for that driver.
283 *
284 ****************************************************************************/
285
286 /*
287 * This function set the exclusion range in the IOMMU. DMA accesses to the
288 * exclusion range are passed through untranslated
289 */
290 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
291 {
292 u64 start = iommu->exclusion_start & PAGE_MASK;
293 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
294 u64 entry;
295
296 if (!iommu->exclusion_start)
297 return;
298
299 entry = start | MMIO_EXCL_ENABLE_MASK;
300 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
301 &entry, sizeof(entry));
302
303 entry = limit;
304 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
305 &entry, sizeof(entry));
306 }
307
308 /* Programs the physical address of the device table into the IOMMU hardware */
309 static void iommu_set_device_table(struct amd_iommu *iommu)
310 {
311 u64 entry;
312
313 BUG_ON(iommu->mmio_base == NULL);
314
315 entry = virt_to_phys(amd_iommu_dev_table);
316 entry |= (dev_table_size >> 12) - 1;
317 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
318 &entry, sizeof(entry));
319 }
320
321 /* Generic functions to enable/disable certain features of the IOMMU. */
322 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
323 {
324 u32 ctrl;
325
326 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
327 ctrl |= (1 << bit);
328 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
329 }
330
331 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
332 {
333 u32 ctrl;
334
335 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
336 ctrl &= ~(1 << bit);
337 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
338 }
339
340 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
341 {
342 u32 ctrl;
343
344 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
345 ctrl &= ~CTRL_INV_TO_MASK;
346 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
347 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
348 }
349
350 /* Function to enable the hardware */
351 static void iommu_enable(struct amd_iommu *iommu)
352 {
353 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
354 }
355
356 static void iommu_disable(struct amd_iommu *iommu)
357 {
358 /* Disable command buffer */
359 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
360
361 /* Disable event logging and event interrupts */
362 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
363 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
364
365 /* Disable IOMMU hardware itself */
366 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
367 }
368
369 /*
370 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
371 * the system has one.
372 */
373 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
374 {
375 if (!request_mem_region(address, end, "amd_iommu")) {
376 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
377 address, end);
378 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
379 return NULL;
380 }
381
382 return (u8 __iomem *)ioremap_nocache(address, end);
383 }
384
385 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
386 {
387 if (iommu->mmio_base)
388 iounmap(iommu->mmio_base);
389 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
390 }
391
392 /****************************************************************************
393 *
394 * The functions below belong to the first pass of AMD IOMMU ACPI table
395 * parsing. In this pass we try to find out the highest device id this
396 * code has to handle. Upon this information the size of the shared data
397 * structures is determined later.
398 *
399 ****************************************************************************/
400
401 /*
402 * This function calculates the length of a given IVHD entry
403 */
404 static inline int ivhd_entry_length(u8 *ivhd)
405 {
406 return 0x04 << (*ivhd >> 6);
407 }
408
409 /*
410 * This function reads the last device id the IOMMU has to handle from the PCI
411 * capability header for this IOMMU
412 */
413 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
414 {
415 u32 cap;
416
417 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
418 update_last_devid(PCI_DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
419
420 return 0;
421 }
422
423 /*
424 * After reading the highest device id from the IOMMU PCI capability header
425 * this function looks if there is a higher device id defined in the ACPI table
426 */
427 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
428 {
429 u8 *p = (void *)h, *end = (void *)h;
430 struct ivhd_entry *dev;
431
432 p += sizeof(*h);
433 end += h->length;
434
435 find_last_devid_on_pci(PCI_BUS_NUM(h->devid),
436 PCI_SLOT(h->devid),
437 PCI_FUNC(h->devid),
438 h->cap_ptr);
439
440 while (p < end) {
441 dev = (struct ivhd_entry *)p;
442 switch (dev->type) {
443 case IVHD_DEV_SELECT:
444 case IVHD_DEV_RANGE_END:
445 case IVHD_DEV_ALIAS:
446 case IVHD_DEV_EXT_SELECT:
447 /* all the above subfield types refer to device ids */
448 update_last_devid(dev->devid);
449 break;
450 default:
451 break;
452 }
453 p += ivhd_entry_length(p);
454 }
455
456 WARN_ON(p != end);
457
458 return 0;
459 }
460
461 /*
462 * Iterate over all IVHD entries in the ACPI table and find the highest device
463 * id which we need to handle. This is the first of three functions which parse
464 * the ACPI table. So we check the checksum here.
465 */
466 static int __init find_last_devid_acpi(struct acpi_table_header *table)
467 {
468 int i;
469 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
470 struct ivhd_header *h;
471
472 /*
473 * Validate checksum here so we don't need to do it when
474 * we actually parse the table
475 */
476 for (i = 0; i < table->length; ++i)
477 checksum += p[i];
478 if (checksum != 0)
479 /* ACPI table corrupt */
480 return -ENODEV;
481
482 p += IVRS_HEADER_LENGTH;
483
484 end += table->length;
485 while (p < end) {
486 h = (struct ivhd_header *)p;
487 switch (h->type) {
488 case ACPI_IVHD_TYPE:
489 find_last_devid_from_ivhd(h);
490 break;
491 default:
492 break;
493 }
494 p += h->length;
495 }
496 WARN_ON(p != end);
497
498 return 0;
499 }
500
501 /****************************************************************************
502 *
503 * The following functions belong to the code path which parses the ACPI table
504 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
505 * data structures, initialize the device/alias/rlookup table and also
506 * basically initialize the hardware.
507 *
508 ****************************************************************************/
509
510 /*
511 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
512 * write commands to that buffer later and the IOMMU will execute them
513 * asynchronously
514 */
515 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
516 {
517 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
518 get_order(CMD_BUFFER_SIZE));
519
520 if (cmd_buf == NULL)
521 return NULL;
522
523 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
524
525 return cmd_buf;
526 }
527
528 /*
529 * This function resets the command buffer if the IOMMU stopped fetching
530 * commands from it.
531 */
532 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
533 {
534 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
535
536 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
537 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
538
539 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
540 }
541
542 /*
543 * This function writes the command buffer address to the hardware and
544 * enables it.
545 */
546 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
547 {
548 u64 entry;
549
550 BUG_ON(iommu->cmd_buf == NULL);
551
552 entry = (u64)virt_to_phys(iommu->cmd_buf);
553 entry |= MMIO_CMD_SIZE_512;
554
555 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
556 &entry, sizeof(entry));
557
558 amd_iommu_reset_cmd_buffer(iommu);
559 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
560 }
561
562 static void __init free_command_buffer(struct amd_iommu *iommu)
563 {
564 free_pages((unsigned long)iommu->cmd_buf,
565 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
566 }
567
568 /* allocates the memory where the IOMMU will log its events to */
569 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
570 {
571 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
572 get_order(EVT_BUFFER_SIZE));
573
574 if (iommu->evt_buf == NULL)
575 return NULL;
576
577 iommu->evt_buf_size = EVT_BUFFER_SIZE;
578
579 return iommu->evt_buf;
580 }
581
582 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
583 {
584 u64 entry;
585
586 BUG_ON(iommu->evt_buf == NULL);
587
588 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
589
590 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
591 &entry, sizeof(entry));
592
593 /* set head and tail to zero manually */
594 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
595 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
596
597 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
598 }
599
600 static void __init free_event_buffer(struct amd_iommu *iommu)
601 {
602 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
603 }
604
605 /* allocates the memory where the IOMMU will log its events to */
606 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
607 {
608 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
609 get_order(PPR_LOG_SIZE));
610
611 if (iommu->ppr_log == NULL)
612 return NULL;
613
614 return iommu->ppr_log;
615 }
616
617 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
618 {
619 u64 entry;
620
621 if (iommu->ppr_log == NULL)
622 return;
623
624 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
625
626 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
627 &entry, sizeof(entry));
628
629 /* set head and tail to zero manually */
630 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
631 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
632
633 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
634 iommu_feature_enable(iommu, CONTROL_PPR_EN);
635 }
636
637 static void __init free_ppr_log(struct amd_iommu *iommu)
638 {
639 if (iommu->ppr_log == NULL)
640 return;
641
642 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
643 }
644
645 static void iommu_enable_gt(struct amd_iommu *iommu)
646 {
647 if (!iommu_feature(iommu, FEATURE_GT))
648 return;
649
650 iommu_feature_enable(iommu, CONTROL_GT_EN);
651 }
652
653 /* sets a specific bit in the device table entry. */
654 static void set_dev_entry_bit(u16 devid, u8 bit)
655 {
656 int i = (bit >> 6) & 0x03;
657 int _bit = bit & 0x3f;
658
659 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
660 }
661
662 static int get_dev_entry_bit(u16 devid, u8 bit)
663 {
664 int i = (bit >> 6) & 0x03;
665 int _bit = bit & 0x3f;
666
667 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
668 }
669
670
671 void amd_iommu_apply_erratum_63(u16 devid)
672 {
673 int sysmgt;
674
675 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
676 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
677
678 if (sysmgt == 0x01)
679 set_dev_entry_bit(devid, DEV_ENTRY_IW);
680 }
681
682 /* Writes the specific IOMMU for a device into the rlookup table */
683 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
684 {
685 amd_iommu_rlookup_table[devid] = iommu;
686 }
687
688 /*
689 * This function takes the device specific flags read from the ACPI
690 * table and sets up the device table entry with that information
691 */
692 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
693 u16 devid, u32 flags, u32 ext_flags)
694 {
695 if (flags & ACPI_DEVFLAG_INITPASS)
696 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
697 if (flags & ACPI_DEVFLAG_EXTINT)
698 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
699 if (flags & ACPI_DEVFLAG_NMI)
700 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
701 if (flags & ACPI_DEVFLAG_SYSMGT1)
702 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
703 if (flags & ACPI_DEVFLAG_SYSMGT2)
704 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
705 if (flags & ACPI_DEVFLAG_LINT0)
706 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
707 if (flags & ACPI_DEVFLAG_LINT1)
708 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
709
710 amd_iommu_apply_erratum_63(devid);
711
712 set_iommu_for_device(iommu, devid);
713 }
714
715 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
716 {
717 struct devid_map *entry;
718 struct list_head *list;
719
720 if (type == IVHD_SPECIAL_IOAPIC)
721 list = &ioapic_map;
722 else if (type == IVHD_SPECIAL_HPET)
723 list = &hpet_map;
724 else
725 return -EINVAL;
726
727 list_for_each_entry(entry, list, list) {
728 if (!(entry->id == id && entry->cmd_line))
729 continue;
730
731 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
732 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
733
734 *devid = entry->devid;
735
736 return 0;
737 }
738
739 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
740 if (!entry)
741 return -ENOMEM;
742
743 entry->id = id;
744 entry->devid = *devid;
745 entry->cmd_line = cmd_line;
746
747 list_add_tail(&entry->list, list);
748
749 return 0;
750 }
751
752 static int __init add_early_maps(void)
753 {
754 int i, ret;
755
756 for (i = 0; i < early_ioapic_map_size; ++i) {
757 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
758 early_ioapic_map[i].id,
759 &early_ioapic_map[i].devid,
760 early_ioapic_map[i].cmd_line);
761 if (ret)
762 return ret;
763 }
764
765 for (i = 0; i < early_hpet_map_size; ++i) {
766 ret = add_special_device(IVHD_SPECIAL_HPET,
767 early_hpet_map[i].id,
768 &early_hpet_map[i].devid,
769 early_hpet_map[i].cmd_line);
770 if (ret)
771 return ret;
772 }
773
774 return 0;
775 }
776
777 /*
778 * Reads the device exclusion range from ACPI and initializes the IOMMU with
779 * it
780 */
781 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
782 {
783 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
784
785 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
786 return;
787
788 if (iommu) {
789 /*
790 * We only can configure exclusion ranges per IOMMU, not
791 * per device. But we can enable the exclusion range per
792 * device. This is done here
793 */
794 set_dev_entry_bit(devid, DEV_ENTRY_EX);
795 iommu->exclusion_start = m->range_start;
796 iommu->exclusion_length = m->range_length;
797 }
798 }
799
800 /*
801 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
802 * initializes the hardware and our data structures with it.
803 */
804 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
805 struct ivhd_header *h)
806 {
807 u8 *p = (u8 *)h;
808 u8 *end = p, flags = 0;
809 u16 devid = 0, devid_start = 0, devid_to = 0;
810 u32 dev_i, ext_flags = 0;
811 bool alias = false;
812 struct ivhd_entry *e;
813 int ret;
814
815
816 ret = add_early_maps();
817 if (ret)
818 return ret;
819
820 /*
821 * First save the recommended feature enable bits from ACPI
822 */
823 iommu->acpi_flags = h->flags;
824
825 /*
826 * Done. Now parse the device entries
827 */
828 p += sizeof(struct ivhd_header);
829 end += h->length;
830
831
832 while (p < end) {
833 e = (struct ivhd_entry *)p;
834 switch (e->type) {
835 case IVHD_DEV_ALL:
836
837 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
838 " last device %02x:%02x.%x flags: %02x\n",
839 PCI_BUS_NUM(iommu->first_device),
840 PCI_SLOT(iommu->first_device),
841 PCI_FUNC(iommu->first_device),
842 PCI_BUS_NUM(iommu->last_device),
843 PCI_SLOT(iommu->last_device),
844 PCI_FUNC(iommu->last_device),
845 e->flags);
846
847 for (dev_i = iommu->first_device;
848 dev_i <= iommu->last_device; ++dev_i)
849 set_dev_entry_from_acpi(iommu, dev_i,
850 e->flags, 0);
851 break;
852 case IVHD_DEV_SELECT:
853
854 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
855 "flags: %02x\n",
856 PCI_BUS_NUM(e->devid),
857 PCI_SLOT(e->devid),
858 PCI_FUNC(e->devid),
859 e->flags);
860
861 devid = e->devid;
862 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
863 break;
864 case IVHD_DEV_SELECT_RANGE_START:
865
866 DUMP_printk(" DEV_SELECT_RANGE_START\t "
867 "devid: %02x:%02x.%x flags: %02x\n",
868 PCI_BUS_NUM(e->devid),
869 PCI_SLOT(e->devid),
870 PCI_FUNC(e->devid),
871 e->flags);
872
873 devid_start = e->devid;
874 flags = e->flags;
875 ext_flags = 0;
876 alias = false;
877 break;
878 case IVHD_DEV_ALIAS:
879
880 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
881 "flags: %02x devid_to: %02x:%02x.%x\n",
882 PCI_BUS_NUM(e->devid),
883 PCI_SLOT(e->devid),
884 PCI_FUNC(e->devid),
885 e->flags,
886 PCI_BUS_NUM(e->ext >> 8),
887 PCI_SLOT(e->ext >> 8),
888 PCI_FUNC(e->ext >> 8));
889
890 devid = e->devid;
891 devid_to = e->ext >> 8;
892 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
893 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
894 amd_iommu_alias_table[devid] = devid_to;
895 break;
896 case IVHD_DEV_ALIAS_RANGE:
897
898 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
899 "devid: %02x:%02x.%x flags: %02x "
900 "devid_to: %02x:%02x.%x\n",
901 PCI_BUS_NUM(e->devid),
902 PCI_SLOT(e->devid),
903 PCI_FUNC(e->devid),
904 e->flags,
905 PCI_BUS_NUM(e->ext >> 8),
906 PCI_SLOT(e->ext >> 8),
907 PCI_FUNC(e->ext >> 8));
908
909 devid_start = e->devid;
910 flags = e->flags;
911 devid_to = e->ext >> 8;
912 ext_flags = 0;
913 alias = true;
914 break;
915 case IVHD_DEV_EXT_SELECT:
916
917 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
918 "flags: %02x ext: %08x\n",
919 PCI_BUS_NUM(e->devid),
920 PCI_SLOT(e->devid),
921 PCI_FUNC(e->devid),
922 e->flags, e->ext);
923
924 devid = e->devid;
925 set_dev_entry_from_acpi(iommu, devid, e->flags,
926 e->ext);
927 break;
928 case IVHD_DEV_EXT_SELECT_RANGE:
929
930 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
931 "%02x:%02x.%x flags: %02x ext: %08x\n",
932 PCI_BUS_NUM(e->devid),
933 PCI_SLOT(e->devid),
934 PCI_FUNC(e->devid),
935 e->flags, e->ext);
936
937 devid_start = e->devid;
938 flags = e->flags;
939 ext_flags = e->ext;
940 alias = false;
941 break;
942 case IVHD_DEV_RANGE_END:
943
944 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
945 PCI_BUS_NUM(e->devid),
946 PCI_SLOT(e->devid),
947 PCI_FUNC(e->devid));
948
949 devid = e->devid;
950 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
951 if (alias) {
952 amd_iommu_alias_table[dev_i] = devid_to;
953 set_dev_entry_from_acpi(iommu,
954 devid_to, flags, ext_flags);
955 }
956 set_dev_entry_from_acpi(iommu, dev_i,
957 flags, ext_flags);
958 }
959 break;
960 case IVHD_DEV_SPECIAL: {
961 u8 handle, type;
962 const char *var;
963 u16 devid;
964 int ret;
965
966 handle = e->ext & 0xff;
967 devid = (e->ext >> 8) & 0xffff;
968 type = (e->ext >> 24) & 0xff;
969
970 if (type == IVHD_SPECIAL_IOAPIC)
971 var = "IOAPIC";
972 else if (type == IVHD_SPECIAL_HPET)
973 var = "HPET";
974 else
975 var = "UNKNOWN";
976
977 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
978 var, (int)handle,
979 PCI_BUS_NUM(devid),
980 PCI_SLOT(devid),
981 PCI_FUNC(devid));
982
983 ret = add_special_device(type, handle, &devid, false);
984 if (ret)
985 return ret;
986
987 /*
988 * add_special_device might update the devid in case a
989 * command-line override is present. So call
990 * set_dev_entry_from_acpi after add_special_device.
991 */
992 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
993
994 break;
995 }
996 default:
997 break;
998 }
999
1000 p += ivhd_entry_length(p);
1001 }
1002
1003 return 0;
1004 }
1005
1006 /* Initializes the device->iommu mapping for the driver */
1007 static int __init init_iommu_devices(struct amd_iommu *iommu)
1008 {
1009 u32 i;
1010
1011 for (i = iommu->first_device; i <= iommu->last_device; ++i)
1012 set_iommu_for_device(iommu, i);
1013
1014 return 0;
1015 }
1016
1017 static void __init free_iommu_one(struct amd_iommu *iommu)
1018 {
1019 free_command_buffer(iommu);
1020 free_event_buffer(iommu);
1021 free_ppr_log(iommu);
1022 iommu_unmap_mmio_space(iommu);
1023 }
1024
1025 static void __init free_iommu_all(void)
1026 {
1027 struct amd_iommu *iommu, *next;
1028
1029 for_each_iommu_safe(iommu, next) {
1030 list_del(&iommu->list);
1031 free_iommu_one(iommu);
1032 kfree(iommu);
1033 }
1034 }
1035
1036 /*
1037 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1038 * Workaround:
1039 * BIOS should disable L2B micellaneous clock gating by setting
1040 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1041 */
1042 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1043 {
1044 u32 value;
1045
1046 if ((boot_cpu_data.x86 != 0x15) ||
1047 (boot_cpu_data.x86_model < 0x10) ||
1048 (boot_cpu_data.x86_model > 0x1f))
1049 return;
1050
1051 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1052 pci_read_config_dword(iommu->dev, 0xf4, &value);
1053
1054 if (value & BIT(2))
1055 return;
1056
1057 /* Select NB indirect register 0x90 and enable writing */
1058 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1059
1060 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1061 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1062 dev_name(&iommu->dev->dev));
1063
1064 /* Clear the enable writing bit */
1065 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1066 }
1067
1068 /*
1069 * This function clues the initialization function for one IOMMU
1070 * together and also allocates the command buffer and programs the
1071 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1072 */
1073 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1074 {
1075 int ret;
1076
1077 spin_lock_init(&iommu->lock);
1078
1079 /* Add IOMMU to internal data structures */
1080 list_add_tail(&iommu->list, &amd_iommu_list);
1081 iommu->index = amd_iommus_present++;
1082
1083 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1084 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1085 return -ENOSYS;
1086 }
1087
1088 /* Index is fine - add IOMMU to the array */
1089 amd_iommus[iommu->index] = iommu;
1090
1091 /*
1092 * Copy data from ACPI table entry to the iommu struct
1093 */
1094 iommu->devid = h->devid;
1095 iommu->cap_ptr = h->cap_ptr;
1096 iommu->pci_seg = h->pci_seg;
1097 iommu->mmio_phys = h->mmio_phys;
1098
1099 /* Check if IVHD EFR contains proper max banks/counters */
1100 if ((h->efr != 0) &&
1101 ((h->efr & (0xF << 13)) != 0) &&
1102 ((h->efr & (0x3F << 17)) != 0)) {
1103 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1104 } else {
1105 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1106 }
1107
1108 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1109 iommu->mmio_phys_end);
1110 if (!iommu->mmio_base)
1111 return -ENOMEM;
1112
1113 iommu->cmd_buf = alloc_command_buffer(iommu);
1114 if (!iommu->cmd_buf)
1115 return -ENOMEM;
1116
1117 iommu->evt_buf = alloc_event_buffer(iommu);
1118 if (!iommu->evt_buf)
1119 return -ENOMEM;
1120
1121 iommu->int_enabled = false;
1122
1123 ret = init_iommu_from_acpi(iommu, h);
1124 if (ret)
1125 return ret;
1126
1127 /*
1128 * Make sure IOMMU is not considered to translate itself. The IVRS
1129 * table tells us so, but this is a lie!
1130 */
1131 amd_iommu_rlookup_table[iommu->devid] = NULL;
1132
1133 init_iommu_devices(iommu);
1134
1135 return 0;
1136 }
1137
1138 /*
1139 * Iterates over all IOMMU entries in the ACPI table, allocates the
1140 * IOMMU structure and initializes it with init_iommu_one()
1141 */
1142 static int __init init_iommu_all(struct acpi_table_header *table)
1143 {
1144 u8 *p = (u8 *)table, *end = (u8 *)table;
1145 struct ivhd_header *h;
1146 struct amd_iommu *iommu;
1147 int ret;
1148
1149 end += table->length;
1150 p += IVRS_HEADER_LENGTH;
1151
1152 while (p < end) {
1153 h = (struct ivhd_header *)p;
1154 switch (*p) {
1155 case ACPI_IVHD_TYPE:
1156
1157 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1158 "seg: %d flags: %01x info %04x\n",
1159 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1160 PCI_FUNC(h->devid), h->cap_ptr,
1161 h->pci_seg, h->flags, h->info);
1162 DUMP_printk(" mmio-addr: %016llx\n",
1163 h->mmio_phys);
1164
1165 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1166 if (iommu == NULL)
1167 return -ENOMEM;
1168
1169 ret = init_iommu_one(iommu, h);
1170 if (ret)
1171 return ret;
1172 break;
1173 default:
1174 break;
1175 }
1176 p += h->length;
1177
1178 }
1179 WARN_ON(p != end);
1180
1181 return 0;
1182 }
1183
1184
1185 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1186 {
1187 u64 val = 0xabcd, val2 = 0;
1188
1189 if (!iommu_feature(iommu, FEATURE_PC))
1190 return;
1191
1192 amd_iommu_pc_present = true;
1193
1194 /* Check if the performance counters can be written to */
1195 if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
1196 (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
1197 (val != val2)) {
1198 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1199 amd_iommu_pc_present = false;
1200 return;
1201 }
1202
1203 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1204
1205 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1206 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1207 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1208 }
1209
1210 static ssize_t amd_iommu_show_cap(struct device *dev,
1211 struct device_attribute *attr,
1212 char *buf)
1213 {
1214 struct amd_iommu *iommu = dev_get_drvdata(dev);
1215 return sprintf(buf, "%x\n", iommu->cap);
1216 }
1217 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1218
1219 static ssize_t amd_iommu_show_features(struct device *dev,
1220 struct device_attribute *attr,
1221 char *buf)
1222 {
1223 struct amd_iommu *iommu = dev_get_drvdata(dev);
1224 return sprintf(buf, "%llx\n", iommu->features);
1225 }
1226 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1227
1228 static struct attribute *amd_iommu_attrs[] = {
1229 &dev_attr_cap.attr,
1230 &dev_attr_features.attr,
1231 NULL,
1232 };
1233
1234 static struct attribute_group amd_iommu_group = {
1235 .name = "amd-iommu",
1236 .attrs = amd_iommu_attrs,
1237 };
1238
1239 static const struct attribute_group *amd_iommu_groups[] = {
1240 &amd_iommu_group,
1241 NULL,
1242 };
1243
1244 static int iommu_init_pci(struct amd_iommu *iommu)
1245 {
1246 int cap_ptr = iommu->cap_ptr;
1247 u32 range, misc, low, high;
1248
1249 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1250 iommu->devid & 0xff);
1251 if (!iommu->dev)
1252 return -ENODEV;
1253
1254 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1255 &iommu->cap);
1256 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1257 &range);
1258 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1259 &misc);
1260
1261 iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range),
1262 MMIO_GET_FD(range));
1263 iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range),
1264 MMIO_GET_LD(range));
1265
1266 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1267 amd_iommu_iotlb_sup = false;
1268
1269 /* read extended feature bits */
1270 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1271 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1272
1273 iommu->features = ((u64)high << 32) | low;
1274
1275 if (iommu_feature(iommu, FEATURE_GT)) {
1276 int glxval;
1277 u32 max_pasid;
1278 u64 pasmax;
1279
1280 pasmax = iommu->features & FEATURE_PASID_MASK;
1281 pasmax >>= FEATURE_PASID_SHIFT;
1282 max_pasid = (1 << (pasmax + 1)) - 1;
1283
1284 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1285
1286 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1287
1288 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1289 glxval >>= FEATURE_GLXVAL_SHIFT;
1290
1291 if (amd_iommu_max_glx_val == -1)
1292 amd_iommu_max_glx_val = glxval;
1293 else
1294 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1295 }
1296
1297 if (iommu_feature(iommu, FEATURE_GT) &&
1298 iommu_feature(iommu, FEATURE_PPR)) {
1299 iommu->is_iommu_v2 = true;
1300 amd_iommu_v2_present = true;
1301 }
1302
1303 if (iommu_feature(iommu, FEATURE_PPR)) {
1304 iommu->ppr_log = alloc_ppr_log(iommu);
1305 if (!iommu->ppr_log)
1306 return -ENOMEM;
1307 }
1308
1309 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1310 amd_iommu_np_cache = true;
1311
1312 init_iommu_perf_ctr(iommu);
1313
1314 if (is_rd890_iommu(iommu->dev)) {
1315 int i, j;
1316
1317 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1318 PCI_DEVFN(0, 0));
1319
1320 /*
1321 * Some rd890 systems may not be fully reconfigured by the
1322 * BIOS, so it's necessary for us to store this information so
1323 * it can be reprogrammed on resume
1324 */
1325 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1326 &iommu->stored_addr_lo);
1327 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1328 &iommu->stored_addr_hi);
1329
1330 /* Low bit locks writes to configuration space */
1331 iommu->stored_addr_lo &= ~1;
1332
1333 for (i = 0; i < 6; i++)
1334 for (j = 0; j < 0x12; j++)
1335 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1336
1337 for (i = 0; i < 0x83; i++)
1338 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1339 }
1340
1341 amd_iommu_erratum_746_workaround(iommu);
1342
1343 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1344 amd_iommu_groups, "ivhd%d",
1345 iommu->index);
1346
1347 return pci_enable_device(iommu->dev);
1348 }
1349
1350 static void print_iommu_info(void)
1351 {
1352 static const char * const feat_str[] = {
1353 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1354 "IA", "GA", "HE", "PC"
1355 };
1356 struct amd_iommu *iommu;
1357
1358 for_each_iommu(iommu) {
1359 int i;
1360
1361 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1362 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1363
1364 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1365 pr_info("AMD-Vi: Extended features: ");
1366 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1367 if (iommu_feature(iommu, (1ULL << i)))
1368 pr_cont(" %s", feat_str[i]);
1369 }
1370 pr_cont("\n");
1371 }
1372 }
1373 if (irq_remapping_enabled)
1374 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1375 }
1376
1377 static int __init amd_iommu_init_pci(void)
1378 {
1379 struct amd_iommu *iommu;
1380 int ret = 0;
1381
1382 for_each_iommu(iommu) {
1383 ret = iommu_init_pci(iommu);
1384 if (ret)
1385 break;
1386 }
1387
1388 ret = amd_iommu_init_devices();
1389
1390 print_iommu_info();
1391
1392 return ret;
1393 }
1394
1395 /****************************************************************************
1396 *
1397 * The following functions initialize the MSI interrupts for all IOMMUs
1398 * in the system. It's a bit challenging because there could be multiple
1399 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1400 * pci_dev.
1401 *
1402 ****************************************************************************/
1403
1404 static int iommu_setup_msi(struct amd_iommu *iommu)
1405 {
1406 int r;
1407
1408 r = pci_enable_msi(iommu->dev);
1409 if (r)
1410 return r;
1411
1412 r = request_threaded_irq(iommu->dev->irq,
1413 amd_iommu_int_handler,
1414 amd_iommu_int_thread,
1415 0, "AMD-Vi",
1416 iommu);
1417
1418 if (r) {
1419 pci_disable_msi(iommu->dev);
1420 return r;
1421 }
1422
1423 iommu->int_enabled = true;
1424
1425 return 0;
1426 }
1427
1428 static int iommu_init_msi(struct amd_iommu *iommu)
1429 {
1430 int ret;
1431
1432 if (iommu->int_enabled)
1433 goto enable_faults;
1434
1435 if (iommu->dev->msi_cap)
1436 ret = iommu_setup_msi(iommu);
1437 else
1438 ret = -ENODEV;
1439
1440 if (ret)
1441 return ret;
1442
1443 enable_faults:
1444 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1445
1446 if (iommu->ppr_log != NULL)
1447 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1448
1449 return 0;
1450 }
1451
1452 /****************************************************************************
1453 *
1454 * The next functions belong to the third pass of parsing the ACPI
1455 * table. In this last pass the memory mapping requirements are
1456 * gathered (like exclusion and unity mapping ranges).
1457 *
1458 ****************************************************************************/
1459
1460 static void __init free_unity_maps(void)
1461 {
1462 struct unity_map_entry *entry, *next;
1463
1464 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1465 list_del(&entry->list);
1466 kfree(entry);
1467 }
1468 }
1469
1470 /* called when we find an exclusion range definition in ACPI */
1471 static int __init init_exclusion_range(struct ivmd_header *m)
1472 {
1473 int i;
1474
1475 switch (m->type) {
1476 case ACPI_IVMD_TYPE:
1477 set_device_exclusion_range(m->devid, m);
1478 break;
1479 case ACPI_IVMD_TYPE_ALL:
1480 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1481 set_device_exclusion_range(i, m);
1482 break;
1483 case ACPI_IVMD_TYPE_RANGE:
1484 for (i = m->devid; i <= m->aux; ++i)
1485 set_device_exclusion_range(i, m);
1486 break;
1487 default:
1488 break;
1489 }
1490
1491 return 0;
1492 }
1493
1494 /* called for unity map ACPI definition */
1495 static int __init init_unity_map_range(struct ivmd_header *m)
1496 {
1497 struct unity_map_entry *e = NULL;
1498 char *s;
1499
1500 e = kzalloc(sizeof(*e), GFP_KERNEL);
1501 if (e == NULL)
1502 return -ENOMEM;
1503
1504 switch (m->type) {
1505 default:
1506 kfree(e);
1507 return 0;
1508 case ACPI_IVMD_TYPE:
1509 s = "IVMD_TYPEi\t\t\t";
1510 e->devid_start = e->devid_end = m->devid;
1511 break;
1512 case ACPI_IVMD_TYPE_ALL:
1513 s = "IVMD_TYPE_ALL\t\t";
1514 e->devid_start = 0;
1515 e->devid_end = amd_iommu_last_bdf;
1516 break;
1517 case ACPI_IVMD_TYPE_RANGE:
1518 s = "IVMD_TYPE_RANGE\t\t";
1519 e->devid_start = m->devid;
1520 e->devid_end = m->aux;
1521 break;
1522 }
1523 e->address_start = PAGE_ALIGN(m->range_start);
1524 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1525 e->prot = m->flags >> 1;
1526
1527 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1528 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1529 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1530 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1531 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1532 e->address_start, e->address_end, m->flags);
1533
1534 list_add_tail(&e->list, &amd_iommu_unity_map);
1535
1536 return 0;
1537 }
1538
1539 /* iterates over all memory definitions we find in the ACPI table */
1540 static int __init init_memory_definitions(struct acpi_table_header *table)
1541 {
1542 u8 *p = (u8 *)table, *end = (u8 *)table;
1543 struct ivmd_header *m;
1544
1545 end += table->length;
1546 p += IVRS_HEADER_LENGTH;
1547
1548 while (p < end) {
1549 m = (struct ivmd_header *)p;
1550 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1551 init_exclusion_range(m);
1552 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1553 init_unity_map_range(m);
1554
1555 p += m->length;
1556 }
1557
1558 return 0;
1559 }
1560
1561 /*
1562 * Init the device table to not allow DMA access for devices and
1563 * suppress all page faults
1564 */
1565 static void init_device_table_dma(void)
1566 {
1567 u32 devid;
1568
1569 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1570 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1571 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1572 }
1573 }
1574
1575 static void __init uninit_device_table_dma(void)
1576 {
1577 u32 devid;
1578
1579 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1580 amd_iommu_dev_table[devid].data[0] = 0ULL;
1581 amd_iommu_dev_table[devid].data[1] = 0ULL;
1582 }
1583 }
1584
1585 static void init_device_table(void)
1586 {
1587 u32 devid;
1588
1589 if (!amd_iommu_irq_remap)
1590 return;
1591
1592 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1593 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1594 }
1595
1596 static void iommu_init_flags(struct amd_iommu *iommu)
1597 {
1598 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1599 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1600 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1601
1602 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1603 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1604 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1605
1606 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1607 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1608 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1609
1610 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1611 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1612 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1613
1614 /*
1615 * make IOMMU memory accesses cache coherent
1616 */
1617 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1618
1619 /* Set IOTLB invalidation timeout to 1s */
1620 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1621 }
1622
1623 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1624 {
1625 int i, j;
1626 u32 ioc_feature_control;
1627 struct pci_dev *pdev = iommu->root_pdev;
1628
1629 /* RD890 BIOSes may not have completely reconfigured the iommu */
1630 if (!is_rd890_iommu(iommu->dev) || !pdev)
1631 return;
1632
1633 /*
1634 * First, we need to ensure that the iommu is enabled. This is
1635 * controlled by a register in the northbridge
1636 */
1637
1638 /* Select Northbridge indirect register 0x75 and enable writing */
1639 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1640 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1641
1642 /* Enable the iommu */
1643 if (!(ioc_feature_control & 0x1))
1644 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1645
1646 /* Restore the iommu BAR */
1647 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1648 iommu->stored_addr_lo);
1649 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1650 iommu->stored_addr_hi);
1651
1652 /* Restore the l1 indirect regs for each of the 6 l1s */
1653 for (i = 0; i < 6; i++)
1654 for (j = 0; j < 0x12; j++)
1655 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1656
1657 /* Restore the l2 indirect regs */
1658 for (i = 0; i < 0x83; i++)
1659 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1660
1661 /* Lock PCI setup registers */
1662 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1663 iommu->stored_addr_lo | 1);
1664 }
1665
1666 /*
1667 * This function finally enables all IOMMUs found in the system after
1668 * they have been initialized
1669 */
1670 static void early_enable_iommus(void)
1671 {
1672 struct amd_iommu *iommu;
1673
1674 for_each_iommu(iommu) {
1675 iommu_disable(iommu);
1676 iommu_init_flags(iommu);
1677 iommu_set_device_table(iommu);
1678 iommu_enable_command_buffer(iommu);
1679 iommu_enable_event_buffer(iommu);
1680 iommu_set_exclusion_range(iommu);
1681 iommu_enable(iommu);
1682 iommu_flush_all_caches(iommu);
1683 }
1684 }
1685
1686 static void enable_iommus_v2(void)
1687 {
1688 struct amd_iommu *iommu;
1689
1690 for_each_iommu(iommu) {
1691 iommu_enable_ppr_log(iommu);
1692 iommu_enable_gt(iommu);
1693 }
1694 }
1695
1696 static void enable_iommus(void)
1697 {
1698 early_enable_iommus();
1699
1700 enable_iommus_v2();
1701 }
1702
1703 static void disable_iommus(void)
1704 {
1705 struct amd_iommu *iommu;
1706
1707 for_each_iommu(iommu)
1708 iommu_disable(iommu);
1709 }
1710
1711 /*
1712 * Suspend/Resume support
1713 * disable suspend until real resume implemented
1714 */
1715
1716 static void amd_iommu_resume(void)
1717 {
1718 struct amd_iommu *iommu;
1719
1720 for_each_iommu(iommu)
1721 iommu_apply_resume_quirks(iommu);
1722
1723 /* re-load the hardware */
1724 enable_iommus();
1725
1726 amd_iommu_enable_interrupts();
1727 }
1728
1729 static int amd_iommu_suspend(void)
1730 {
1731 /* disable IOMMUs to go out of the way for BIOS */
1732 disable_iommus();
1733
1734 return 0;
1735 }
1736
1737 static struct syscore_ops amd_iommu_syscore_ops = {
1738 .suspend = amd_iommu_suspend,
1739 .resume = amd_iommu_resume,
1740 };
1741
1742 static void __init free_on_init_error(void)
1743 {
1744 free_pages((unsigned long)irq_lookup_table,
1745 get_order(rlookup_table_size));
1746
1747 if (amd_iommu_irq_cache) {
1748 kmem_cache_destroy(amd_iommu_irq_cache);
1749 amd_iommu_irq_cache = NULL;
1750
1751 }
1752
1753 free_pages((unsigned long)amd_iommu_rlookup_table,
1754 get_order(rlookup_table_size));
1755
1756 free_pages((unsigned long)amd_iommu_alias_table,
1757 get_order(alias_table_size));
1758
1759 free_pages((unsigned long)amd_iommu_dev_table,
1760 get_order(dev_table_size));
1761
1762 free_iommu_all();
1763
1764 #ifdef CONFIG_GART_IOMMU
1765 /*
1766 * We failed to initialize the AMD IOMMU - try fallback to GART
1767 * if possible.
1768 */
1769 gart_iommu_init();
1770
1771 #endif
1772 }
1773
1774 /* SB IOAPIC is always on this device in AMD systems */
1775 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1776
1777 static bool __init check_ioapic_information(void)
1778 {
1779 const char *fw_bug = FW_BUG;
1780 bool ret, has_sb_ioapic;
1781 int idx;
1782
1783 has_sb_ioapic = false;
1784 ret = false;
1785
1786 /*
1787 * If we have map overrides on the kernel command line the
1788 * messages in this function might not describe firmware bugs
1789 * anymore - so be careful
1790 */
1791 if (cmdline_maps)
1792 fw_bug = "";
1793
1794 for (idx = 0; idx < nr_ioapics; idx++) {
1795 int devid, id = mpc_ioapic_id(idx);
1796
1797 devid = get_ioapic_devid(id);
1798 if (devid < 0) {
1799 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1800 fw_bug, id);
1801 ret = false;
1802 } else if (devid == IOAPIC_SB_DEVID) {
1803 has_sb_ioapic = true;
1804 ret = true;
1805 }
1806 }
1807
1808 if (!has_sb_ioapic) {
1809 /*
1810 * We expect the SB IOAPIC to be listed in the IVRS
1811 * table. The system timer is connected to the SB IOAPIC
1812 * and if we don't have it in the list the system will
1813 * panic at boot time. This situation usually happens
1814 * when the BIOS is buggy and provides us the wrong
1815 * device id for the IOAPIC in the system.
1816 */
1817 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1818 }
1819
1820 if (!ret)
1821 pr_err("AMD-Vi: Disabling interrupt remapping\n");
1822
1823 return ret;
1824 }
1825
1826 static void __init free_dma_resources(void)
1827 {
1828 amd_iommu_uninit_devices();
1829
1830 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1831 get_order(MAX_DOMAIN_ID/8));
1832
1833 free_unity_maps();
1834 }
1835
1836 /*
1837 * This is the hardware init function for AMD IOMMU in the system.
1838 * This function is called either from amd_iommu_init or from the interrupt
1839 * remapping setup code.
1840 *
1841 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1842 * three times:
1843 *
1844 * 1 pass) Find the highest PCI device id the driver has to handle.
1845 * Upon this information the size of the data structures is
1846 * determined that needs to be allocated.
1847 *
1848 * 2 pass) Initialize the data structures just allocated with the
1849 * information in the ACPI table about available AMD IOMMUs
1850 * in the system. It also maps the PCI devices in the
1851 * system to specific IOMMUs
1852 *
1853 * 3 pass) After the basic data structures are allocated and
1854 * initialized we update them with information about memory
1855 * remapping requirements parsed out of the ACPI table in
1856 * this last pass.
1857 *
1858 * After everything is set up the IOMMUs are enabled and the necessary
1859 * hotplug and suspend notifiers are registered.
1860 */
1861 static int __init early_amd_iommu_init(void)
1862 {
1863 struct acpi_table_header *ivrs_base;
1864 acpi_size ivrs_size;
1865 acpi_status status;
1866 int i, ret = 0;
1867
1868 if (!amd_iommu_detected)
1869 return -ENODEV;
1870
1871 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1872 if (status == AE_NOT_FOUND)
1873 return -ENODEV;
1874 else if (ACPI_FAILURE(status)) {
1875 const char *err = acpi_format_exception(status);
1876 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1877 return -EINVAL;
1878 }
1879
1880 /*
1881 * First parse ACPI tables to find the largest Bus/Dev/Func
1882 * we need to handle. Upon this information the shared data
1883 * structures for the IOMMUs in the system will be allocated
1884 */
1885 ret = find_last_devid_acpi(ivrs_base);
1886 if (ret)
1887 goto out;
1888
1889 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1890 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1891 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1892
1893 /* Device table - directly used by all IOMMUs */
1894 ret = -ENOMEM;
1895 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1896 get_order(dev_table_size));
1897 if (amd_iommu_dev_table == NULL)
1898 goto out;
1899
1900 /*
1901 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1902 * IOMMU see for that device
1903 */
1904 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1905 get_order(alias_table_size));
1906 if (amd_iommu_alias_table == NULL)
1907 goto out;
1908
1909 /* IOMMU rlookup table - find the IOMMU for a specific device */
1910 amd_iommu_rlookup_table = (void *)__get_free_pages(
1911 GFP_KERNEL | __GFP_ZERO,
1912 get_order(rlookup_table_size));
1913 if (amd_iommu_rlookup_table == NULL)
1914 goto out;
1915
1916 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1917 GFP_KERNEL | __GFP_ZERO,
1918 get_order(MAX_DOMAIN_ID/8));
1919 if (amd_iommu_pd_alloc_bitmap == NULL)
1920 goto out;
1921
1922 /*
1923 * let all alias entries point to itself
1924 */
1925 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1926 amd_iommu_alias_table[i] = i;
1927
1928 /*
1929 * never allocate domain 0 because its used as the non-allocated and
1930 * error value placeholder
1931 */
1932 amd_iommu_pd_alloc_bitmap[0] = 1;
1933
1934 spin_lock_init(&amd_iommu_pd_lock);
1935
1936 /*
1937 * now the data structures are allocated and basically initialized
1938 * start the real acpi table scan
1939 */
1940 ret = init_iommu_all(ivrs_base);
1941 if (ret)
1942 goto out;
1943
1944 if (amd_iommu_irq_remap)
1945 amd_iommu_irq_remap = check_ioapic_information();
1946
1947 if (amd_iommu_irq_remap) {
1948 /*
1949 * Interrupt remapping enabled, create kmem_cache for the
1950 * remapping tables.
1951 */
1952 ret = -ENOMEM;
1953 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1954 MAX_IRQS_PER_TABLE * sizeof(u32),
1955 IRQ_TABLE_ALIGNMENT,
1956 0, NULL);
1957 if (!amd_iommu_irq_cache)
1958 goto out;
1959
1960 irq_lookup_table = (void *)__get_free_pages(
1961 GFP_KERNEL | __GFP_ZERO,
1962 get_order(rlookup_table_size));
1963 if (!irq_lookup_table)
1964 goto out;
1965 }
1966
1967 ret = init_memory_definitions(ivrs_base);
1968 if (ret)
1969 goto out;
1970
1971 /* init the device table */
1972 init_device_table();
1973
1974 out:
1975 /* Don't leak any ACPI memory */
1976 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1977 ivrs_base = NULL;
1978
1979 return ret;
1980 }
1981
1982 static int amd_iommu_enable_interrupts(void)
1983 {
1984 struct amd_iommu *iommu;
1985 int ret = 0;
1986
1987 for_each_iommu(iommu) {
1988 ret = iommu_init_msi(iommu);
1989 if (ret)
1990 goto out;
1991 }
1992
1993 out:
1994 return ret;
1995 }
1996
1997 static bool detect_ivrs(void)
1998 {
1999 struct acpi_table_header *ivrs_base;
2000 acpi_size ivrs_size;
2001 acpi_status status;
2002
2003 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2004 if (status == AE_NOT_FOUND)
2005 return false;
2006 else if (ACPI_FAILURE(status)) {
2007 const char *err = acpi_format_exception(status);
2008 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2009 return false;
2010 }
2011
2012 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2013
2014 /* Make sure ACS will be enabled during PCI probe */
2015 pci_request_acs();
2016
2017 if (!disable_irq_remap)
2018 amd_iommu_irq_remap = true;
2019
2020 return true;
2021 }
2022
2023 static int amd_iommu_init_dma(void)
2024 {
2025 struct amd_iommu *iommu;
2026 int ret;
2027
2028 if (iommu_pass_through)
2029 ret = amd_iommu_init_passthrough();
2030 else
2031 ret = amd_iommu_init_dma_ops();
2032
2033 if (ret)
2034 return ret;
2035
2036 init_device_table_dma();
2037
2038 for_each_iommu(iommu)
2039 iommu_flush_all_caches(iommu);
2040
2041 amd_iommu_init_api();
2042
2043 amd_iommu_init_notifier();
2044
2045 return 0;
2046 }
2047
2048 /****************************************************************************
2049 *
2050 * AMD IOMMU Initialization State Machine
2051 *
2052 ****************************************************************************/
2053
2054 static int __init state_next(void)
2055 {
2056 int ret = 0;
2057
2058 switch (init_state) {
2059 case IOMMU_START_STATE:
2060 if (!detect_ivrs()) {
2061 init_state = IOMMU_NOT_FOUND;
2062 ret = -ENODEV;
2063 } else {
2064 init_state = IOMMU_IVRS_DETECTED;
2065 }
2066 break;
2067 case IOMMU_IVRS_DETECTED:
2068 ret = early_amd_iommu_init();
2069 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2070 break;
2071 case IOMMU_ACPI_FINISHED:
2072 early_enable_iommus();
2073 register_syscore_ops(&amd_iommu_syscore_ops);
2074 x86_platform.iommu_shutdown = disable_iommus;
2075 init_state = IOMMU_ENABLED;
2076 break;
2077 case IOMMU_ENABLED:
2078 ret = amd_iommu_init_pci();
2079 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2080 enable_iommus_v2();
2081 break;
2082 case IOMMU_PCI_INIT:
2083 ret = amd_iommu_enable_interrupts();
2084 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2085 break;
2086 case IOMMU_INTERRUPTS_EN:
2087 ret = amd_iommu_init_dma();
2088 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2089 break;
2090 case IOMMU_DMA_OPS:
2091 init_state = IOMMU_INITIALIZED;
2092 break;
2093 case IOMMU_INITIALIZED:
2094 /* Nothing to do */
2095 break;
2096 case IOMMU_NOT_FOUND:
2097 case IOMMU_INIT_ERROR:
2098 /* Error states => do nothing */
2099 ret = -EINVAL;
2100 break;
2101 default:
2102 /* Unknown state */
2103 BUG();
2104 }
2105
2106 return ret;
2107 }
2108
2109 static int __init iommu_go_to_state(enum iommu_init_state state)
2110 {
2111 int ret = 0;
2112
2113 while (init_state != state) {
2114 ret = state_next();
2115 if (init_state == IOMMU_NOT_FOUND ||
2116 init_state == IOMMU_INIT_ERROR)
2117 break;
2118 }
2119
2120 return ret;
2121 }
2122
2123 #ifdef CONFIG_IRQ_REMAP
2124 int __init amd_iommu_prepare(void)
2125 {
2126 return iommu_go_to_state(IOMMU_ACPI_FINISHED);
2127 }
2128
2129 int __init amd_iommu_supported(void)
2130 {
2131 return amd_iommu_irq_remap ? 1 : 0;
2132 }
2133
2134 int __init amd_iommu_enable(void)
2135 {
2136 int ret;
2137
2138 ret = iommu_go_to_state(IOMMU_ENABLED);
2139 if (ret)
2140 return ret;
2141
2142 irq_remapping_enabled = 1;
2143
2144 return 0;
2145 }
2146
2147 void amd_iommu_disable(void)
2148 {
2149 amd_iommu_suspend();
2150 }
2151
2152 int amd_iommu_reenable(int mode)
2153 {
2154 amd_iommu_resume();
2155
2156 return 0;
2157 }
2158
2159 int __init amd_iommu_enable_faulting(void)
2160 {
2161 /* We enable MSI later when PCI is initialized */
2162 return 0;
2163 }
2164 #endif
2165
2166 /*
2167 * This is the core init function for AMD IOMMU hardware in the system.
2168 * This function is called from the generic x86 DMA layer initialization
2169 * code.
2170 */
2171 static int __init amd_iommu_init(void)
2172 {
2173 int ret;
2174
2175 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2176 if (ret) {
2177 free_dma_resources();
2178 if (!irq_remapping_enabled) {
2179 disable_iommus();
2180 free_on_init_error();
2181 } else {
2182 struct amd_iommu *iommu;
2183
2184 uninit_device_table_dma();
2185 for_each_iommu(iommu)
2186 iommu_flush_all_caches(iommu);
2187 }
2188 }
2189
2190 return ret;
2191 }
2192
2193 /****************************************************************************
2194 *
2195 * Early detect code. This code runs at IOMMU detection time in the DMA
2196 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2197 * IOMMUs
2198 *
2199 ****************************************************************************/
2200 int __init amd_iommu_detect(void)
2201 {
2202 int ret;
2203
2204 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2205 return -ENODEV;
2206
2207 if (amd_iommu_disabled)
2208 return -ENODEV;
2209
2210 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2211 if (ret)
2212 return ret;
2213
2214 amd_iommu_detected = true;
2215 iommu_detected = 1;
2216 x86_init.iommu.iommu_init = amd_iommu_init;
2217
2218 return 0;
2219 }
2220
2221 /****************************************************************************
2222 *
2223 * Parsing functions for the AMD IOMMU specific kernel command line
2224 * options.
2225 *
2226 ****************************************************************************/
2227
2228 static int __init parse_amd_iommu_dump(char *str)
2229 {
2230 amd_iommu_dump = true;
2231
2232 return 1;
2233 }
2234
2235 static int __init parse_amd_iommu_options(char *str)
2236 {
2237 for (; *str; ++str) {
2238 if (strncmp(str, "fullflush", 9) == 0)
2239 amd_iommu_unmap_flush = true;
2240 if (strncmp(str, "off", 3) == 0)
2241 amd_iommu_disabled = true;
2242 if (strncmp(str, "force_isolation", 15) == 0)
2243 amd_iommu_force_isolation = true;
2244 }
2245
2246 return 1;
2247 }
2248
2249 static int __init parse_ivrs_ioapic(char *str)
2250 {
2251 unsigned int bus, dev, fn;
2252 int ret, id, i;
2253 u16 devid;
2254
2255 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2256
2257 if (ret != 4) {
2258 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2259 return 1;
2260 }
2261
2262 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2263 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2264 str);
2265 return 1;
2266 }
2267
2268 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2269
2270 cmdline_maps = true;
2271 i = early_ioapic_map_size++;
2272 early_ioapic_map[i].id = id;
2273 early_ioapic_map[i].devid = devid;
2274 early_ioapic_map[i].cmd_line = true;
2275
2276 return 1;
2277 }
2278
2279 static int __init parse_ivrs_hpet(char *str)
2280 {
2281 unsigned int bus, dev, fn;
2282 int ret, id, i;
2283 u16 devid;
2284
2285 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2286
2287 if (ret != 4) {
2288 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2289 return 1;
2290 }
2291
2292 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2293 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2294 str);
2295 return 1;
2296 }
2297
2298 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2299
2300 cmdline_maps = true;
2301 i = early_hpet_map_size++;
2302 early_hpet_map[i].id = id;
2303 early_hpet_map[i].devid = devid;
2304 early_hpet_map[i].cmd_line = true;
2305
2306 return 1;
2307 }
2308
2309 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2310 __setup("amd_iommu=", parse_amd_iommu_options);
2311 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2312 __setup("ivrs_hpet", parse_ivrs_hpet);
2313
2314 IOMMU_INIT_FINISH(amd_iommu_detect,
2315 gart_iommu_hole_init,
2316 NULL,
2317 NULL);
2318
2319 bool amd_iommu_v2_supported(void)
2320 {
2321 return amd_iommu_v2_present;
2322 }
2323 EXPORT_SYMBOL(amd_iommu_v2_supported);
2324
2325 /****************************************************************************
2326 *
2327 * IOMMU EFR Performance Counter support functionality. This code allows
2328 * access to the IOMMU PC functionality.
2329 *
2330 ****************************************************************************/
2331
2332 u8 amd_iommu_pc_get_max_banks(u16 devid)
2333 {
2334 struct amd_iommu *iommu;
2335 u8 ret = 0;
2336
2337 /* locate the iommu governing the devid */
2338 iommu = amd_iommu_rlookup_table[devid];
2339 if (iommu)
2340 ret = iommu->max_banks;
2341
2342 return ret;
2343 }
2344 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2345
2346 bool amd_iommu_pc_supported(void)
2347 {
2348 return amd_iommu_pc_present;
2349 }
2350 EXPORT_SYMBOL(amd_iommu_pc_supported);
2351
2352 u8 amd_iommu_pc_get_max_counters(u16 devid)
2353 {
2354 struct amd_iommu *iommu;
2355 u8 ret = 0;
2356
2357 /* locate the iommu governing the devid */
2358 iommu = amd_iommu_rlookup_table[devid];
2359 if (iommu)
2360 ret = iommu->max_counters;
2361
2362 return ret;
2363 }
2364 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2365
2366 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2367 u64 *value, bool is_write)
2368 {
2369 struct amd_iommu *iommu;
2370 u32 offset;
2371 u32 max_offset_lim;
2372
2373 /* Make sure the IOMMU PC resource is available */
2374 if (!amd_iommu_pc_present)
2375 return -ENODEV;
2376
2377 /* Locate the iommu associated with the device ID */
2378 iommu = amd_iommu_rlookup_table[devid];
2379
2380 /* Check for valid iommu and pc register indexing */
2381 if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
2382 return -ENODEV;
2383
2384 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2385
2386 /* Limit the offset to the hw defined mmio region aperture */
2387 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2388 (iommu->max_counters << 8) | 0x28);
2389 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2390 (offset > max_offset_lim))
2391 return -EINVAL;
2392
2393 if (is_write) {
2394 writel((u32)*value, iommu->mmio_base + offset);
2395 writel((*value >> 32), iommu->mmio_base + offset + 4);
2396 } else {
2397 *value = readl(iommu->mmio_base + offset + 4);
2398 *value <<= 32;
2399 *value = readl(iommu->mmio_base + offset);
2400 }
2401
2402 return 0;
2403 }
2404 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
Linux with added FPC-III support