?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.4.182
[linux/fpc-iii.git] / drivers / ata / libahci.c
blob8116cb2fef2dad7d5a9f51c76666f6720d8e30a0
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "ahci.h"
47 #include "libata.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static void ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
92 #ifdef CONFIG_PM
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
94 #endif
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
99
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
115
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
123
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
132 &dev_attr_em_buffer,
133 &dev_attr_em_message_supported,
134 NULL
135 };
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
137
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
141 NULL
142 };
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
144
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
147
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
152
153 .freeze = ahci_freeze,
154 .thaw = ahci_thaw,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
162
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
167
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
174 #ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177 #endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180 };
181 EXPORT_SYMBOL_GPL(ahci_ops);
182
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186 };
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
189 static bool ahci_em_messages __read_mostly = true;
190 EXPORT_SYMBOL_GPL(ahci_em_messages);
191 module_param(ahci_em_messages, bool, 0444);
192 /* add other LED protocol types when they become supported */
193 MODULE_PARM_DESC(ahci_em_messages,
194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
195
196 /* device sleep idle timeout in ms */
197 static int devslp_idle_timeout __read_mostly = 1000;
198 module_param(devslp_idle_timeout, int, 0644);
199 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
200
201 static void ahci_enable_ahci(void __iomem *mmio)
202 {
203 int i;
204 u32 tmp;
205
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
209 return;
210
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
213 */
214 for (i = 0; i < 5; i++) {
215 tmp |= HOST_AHCI_EN;
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
219 return;
220 msleep(10);
221 }
222
223 WARN_ON(1);
224 }
225
226 static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
228 {
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
232
233 return sprintf(buf, "%x\n", hpriv->cap);
234 }
235
236 static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
238 {
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
242
243 return sprintf(buf, "%x\n", hpriv->cap2);
244 }
245
246 static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
248 {
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
253
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
255 }
256
257 static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
259 {
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
263
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
265 }
266
267 static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
269 {
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
275 u32 em_ctl, msg;
276 unsigned long flags;
277 size_t count;
278 int i;
279
280 spin_lock_irqsave(ap->lock, flags);
281
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
286 return -EINVAL;
287 }
288
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
291 return -EAGAIN;
292 }
293
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
296
297 count = hpriv->em_buf_sz;
298
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
302 ata_port_warn(ap,
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
306 count = PAGE_SIZE;
307 }
308
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
311 buf[i] = msg & 0xff;
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
315 }
316
317 spin_unlock_irqrestore(ap->lock, flags);
318
319 return i;
320 }
321
322 static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
325 {
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
331 const unsigned char *msg_buf = buf;
332 u32 em_ctl, msg;
333 unsigned long flags;
334 int i;
335
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
340 return -EINVAL;
341
342 spin_lock_irqsave(ap->lock, flags);
343
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
347 return -EBUSY;
348 }
349
350 for (i = 0; i < size; i += 4) {
351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
353 writel(msg, em_mmio + i);
354 }
355
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
357
358 spin_unlock_irqrestore(ap->lock, flags);
359
360 return size;
361 }
362
363 static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
365 {
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
370 u32 em_ctl;
371
372 em_ctl = readl(mmio + HOST_EM_CTL);
373
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
379 }
380
381 /**
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
385 *
386 * Some registers containing configuration info might be setup by
387 * BIOS and might be cleared on reset. This function saves the
388 * initial values of those registers into @hpriv such that they
389 * can be restored after controller reset.
390 *
391 * If inconsistent, config values are fixed up by this function.
392 *
393 * If it is not set already this function sets hpriv->start_engine to
394 * ahci_start_engine.
395 *
396 * LOCKING:
397 * None.
398 */
399 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
400 {
401 void __iomem *mmio = hpriv->mmio;
402 u32 cap, cap2, vers, port_map;
403 int i;
404
405 /* make sure AHCI mode is enabled before accessing CAP */
406 ahci_enable_ahci(mmio);
407
408 /* Values prefixed with saved_ are written back to host after
409 * reset. Values without are used for driver operation.
410 */
411 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
412 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
413
414 /* CAP2 register is only defined for AHCI 1.2 and later */
415 vers = readl(mmio + HOST_VERSION);
416 if ((vers >> 16) > 1 ||
417 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
418 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
419 else
420 hpriv->saved_cap2 = cap2 = 0;
421
422 /* some chips have errata preventing 64bit use */
423 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
424 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
425 cap &= ~HOST_CAP_64;
426 }
427
428 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
429 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
430 cap &= ~HOST_CAP_NCQ;
431 }
432
433 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
434 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
435 cap |= HOST_CAP_NCQ;
436 }
437
438 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
439 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
440 cap &= ~HOST_CAP_PMP;
441 }
442
443 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
444 dev_info(dev,
445 "controller can't do SNTF, turning off CAP_SNTF\n");
446 cap &= ~HOST_CAP_SNTF;
447 }
448
449 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
450 dev_info(dev,
451 "controller can't do DEVSLP, turning off\n");
452 cap2 &= ~HOST_CAP2_SDS;
453 cap2 &= ~HOST_CAP2_SADM;
454 }
455
456 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
457 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
458 cap |= HOST_CAP_FBS;
459 }
460
461 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
462 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
463 cap &= ~HOST_CAP_FBS;
464 }
465
466 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
467 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
468 port_map, hpriv->force_port_map);
469 port_map = hpriv->force_port_map;
470 hpriv->saved_port_map = port_map;
471 }
472
473 if (hpriv->mask_port_map) {
474 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
475 port_map,
476 port_map & hpriv->mask_port_map);
477 port_map &= hpriv->mask_port_map;
478 }
479
480 /* cross check port_map and cap.n_ports */
481 if (port_map) {
482 int map_ports = 0;
483
484 for (i = 0; i < AHCI_MAX_PORTS; i++)
485 if (port_map & (1 << i))
486 map_ports++;
487
488 /* If PI has more ports than n_ports, whine, clear
489 * port_map and let it be generated from n_ports.
490 */
491 if (map_ports > ahci_nr_ports(cap)) {
492 dev_warn(dev,
493 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
494 port_map, ahci_nr_ports(cap));
495 port_map = 0;
496 }
497 }
498
499 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
500 if (!port_map && vers < 0x10300) {
501 port_map = (1 << ahci_nr_ports(cap)) - 1;
502 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
503
504 /* write the fixed up value to the PI register */
505 hpriv->saved_port_map = port_map;
506 }
507
508 /* record values to use during operation */
509 hpriv->cap = cap;
510 hpriv->cap2 = cap2;
511 hpriv->port_map = port_map;
512
513 if (!hpriv->start_engine)
514 hpriv->start_engine = ahci_start_engine;
515 }
516 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
517
518 /**
519 * ahci_restore_initial_config - Restore initial config
520 * @host: target ATA host
521 *
522 * Restore initial config stored by ahci_save_initial_config().
523 *
524 * LOCKING:
525 * None.
526 */
527 static void ahci_restore_initial_config(struct ata_host *host)
528 {
529 struct ahci_host_priv *hpriv = host->private_data;
530 void __iomem *mmio = hpriv->mmio;
531
532 writel(hpriv->saved_cap, mmio + HOST_CAP);
533 if (hpriv->saved_cap2)
534 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
535 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
536 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
537 }
538
539 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
540 {
541 static const int offset[] = {
542 [SCR_STATUS] = PORT_SCR_STAT,
543 [SCR_CONTROL] = PORT_SCR_CTL,
544 [SCR_ERROR] = PORT_SCR_ERR,
545 [SCR_ACTIVE] = PORT_SCR_ACT,
546 [SCR_NOTIFICATION] = PORT_SCR_NTF,
547 };
548 struct ahci_host_priv *hpriv = ap->host->private_data;
549
550 if (sc_reg < ARRAY_SIZE(offset) &&
551 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
552 return offset[sc_reg];
553 return 0;
554 }
555
556 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
557 {
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
560
561 if (offset) {
562 *val = readl(port_mmio + offset);
563 return 0;
564 }
565 return -EINVAL;
566 }
567
568 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
569 {
570 void __iomem *port_mmio = ahci_port_base(link->ap);
571 int offset = ahci_scr_offset(link->ap, sc_reg);
572
573 if (offset) {
574 writel(val, port_mmio + offset);
575 return 0;
576 }
577 return -EINVAL;
578 }
579
580 void ahci_start_engine(struct ata_port *ap)
581 {
582 void __iomem *port_mmio = ahci_port_base(ap);
583 u32 tmp;
584
585 /* start DMA */
586 tmp = readl(port_mmio + PORT_CMD);
587 tmp |= PORT_CMD_START;
588 writel(tmp, port_mmio + PORT_CMD);
589 readl(port_mmio + PORT_CMD); /* flush */
590 }
591 EXPORT_SYMBOL_GPL(ahci_start_engine);
592
593 int ahci_stop_engine(struct ata_port *ap)
594 {
595 void __iomem *port_mmio = ahci_port_base(ap);
596 u32 tmp;
597
598 tmp = readl(port_mmio + PORT_CMD);
599
600 /* check if the HBA is idle */
601 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
602 return 0;
603
604 /* setting HBA to idle */
605 tmp &= ~PORT_CMD_START;
606 writel(tmp, port_mmio + PORT_CMD);
607
608 /* wait for engine to stop. This could be as long as 500 msec */
609 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
610 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
611 if (tmp & PORT_CMD_LIST_ON)
612 return -EIO;
613
614 return 0;
615 }
616 EXPORT_SYMBOL_GPL(ahci_stop_engine);
617
618 void ahci_start_fis_rx(struct ata_port *ap)
619 {
620 void __iomem *port_mmio = ahci_port_base(ap);
621 struct ahci_host_priv *hpriv = ap->host->private_data;
622 struct ahci_port_priv *pp = ap->private_data;
623 u32 tmp;
624
625 /* set FIS registers */
626 if (hpriv->cap & HOST_CAP_64)
627 writel((pp->cmd_slot_dma >> 16) >> 16,
628 port_mmio + PORT_LST_ADDR_HI);
629 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
630
631 if (hpriv->cap & HOST_CAP_64)
632 writel((pp->rx_fis_dma >> 16) >> 16,
633 port_mmio + PORT_FIS_ADDR_HI);
634 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
635
636 /* enable FIS reception */
637 tmp = readl(port_mmio + PORT_CMD);
638 tmp |= PORT_CMD_FIS_RX;
639 writel(tmp, port_mmio + PORT_CMD);
640
641 /* flush */
642 readl(port_mmio + PORT_CMD);
643 }
644 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
645
646 static int ahci_stop_fis_rx(struct ata_port *ap)
647 {
648 void __iomem *port_mmio = ahci_port_base(ap);
649 u32 tmp;
650
651 /* disable FIS reception */
652 tmp = readl(port_mmio + PORT_CMD);
653 tmp &= ~PORT_CMD_FIS_RX;
654 writel(tmp, port_mmio + PORT_CMD);
655
656 /* wait for completion, spec says 500ms, give it 1000 */
657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
658 PORT_CMD_FIS_ON, 10, 1000);
659 if (tmp & PORT_CMD_FIS_ON)
660 return -EBUSY;
661
662 return 0;
663 }
664
665 static void ahci_power_up(struct ata_port *ap)
666 {
667 struct ahci_host_priv *hpriv = ap->host->private_data;
668 void __iomem *port_mmio = ahci_port_base(ap);
669 u32 cmd;
670
671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
672
673 /* spin up device */
674 if (hpriv->cap & HOST_CAP_SSS) {
675 cmd |= PORT_CMD_SPIN_UP;
676 writel(cmd, port_mmio + PORT_CMD);
677 }
678
679 /* wake up link */
680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
681 }
682
683 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
684 unsigned int hints)
685 {
686 struct ata_port *ap = link->ap;
687 struct ahci_host_priv *hpriv = ap->host->private_data;
688 struct ahci_port_priv *pp = ap->private_data;
689 void __iomem *port_mmio = ahci_port_base(ap);
690
691 if (policy != ATA_LPM_MAX_POWER) {
692 /*
693 * Disable interrupts on Phy Ready. This keeps us from
694 * getting woken up due to spurious phy ready
695 * interrupts.
696 */
697 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
699
700 sata_link_scr_lpm(link, policy, false);
701 }
702
703 if (hpriv->cap & HOST_CAP_ALPM) {
704 u32 cmd = readl(port_mmio + PORT_CMD);
705
706 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
707 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
708 cmd |= PORT_CMD_ICC_ACTIVE;
709
710 writel(cmd, port_mmio + PORT_CMD);
711 readl(port_mmio + PORT_CMD);
712
713 /* wait 10ms to be sure we've come out of LPM state */
714 ata_msleep(ap, 10);
715 } else {
716 cmd |= PORT_CMD_ALPE;
717 if (policy == ATA_LPM_MIN_POWER)
718 cmd |= PORT_CMD_ASP;
719
720 /* write out new cmd value */
721 writel(cmd, port_mmio + PORT_CMD);
722 }
723 }
724
725 /* set aggressive device sleep */
726 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
727 (hpriv->cap2 & HOST_CAP2_SADM) &&
728 (link->device->flags & ATA_DFLAG_DEVSLP)) {
729 if (policy == ATA_LPM_MIN_POWER)
730 ahci_set_aggressive_devslp(ap, true);
731 else
732 ahci_set_aggressive_devslp(ap, false);
733 }
734
735 if (policy == ATA_LPM_MAX_POWER) {
736 sata_link_scr_lpm(link, policy, false);
737
738 /* turn PHYRDY IRQ back on */
739 pp->intr_mask |= PORT_IRQ_PHYRDY;
740 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
741 }
742
743 return 0;
744 }
745
746 #ifdef CONFIG_PM
747 static void ahci_power_down(struct ata_port *ap)
748 {
749 struct ahci_host_priv *hpriv = ap->host->private_data;
750 void __iomem *port_mmio = ahci_port_base(ap);
751 u32 cmd, scontrol;
752
753 if (!(hpriv->cap & HOST_CAP_SSS))
754 return;
755
756 /* put device into listen mode, first set PxSCTL.DET to 0 */
757 scontrol = readl(port_mmio + PORT_SCR_CTL);
758 scontrol &= ~0xf;
759 writel(scontrol, port_mmio + PORT_SCR_CTL);
760
761 /* then set PxCMD.SUD to 0 */
762 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
763 cmd &= ~PORT_CMD_SPIN_UP;
764 writel(cmd, port_mmio + PORT_CMD);
765 }
766 #endif
767
768 static void ahci_start_port(struct ata_port *ap)
769 {
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 struct ahci_port_priv *pp = ap->private_data;
772 struct ata_link *link;
773 struct ahci_em_priv *emp;
774 ssize_t rc;
775 int i;
776
777 /* enable FIS reception */
778 ahci_start_fis_rx(ap);
779
780 /* enable DMA */
781 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
782 hpriv->start_engine(ap);
783
784 /* turn on LEDs */
785 if (ap->flags & ATA_FLAG_EM) {
786 ata_for_each_link(link, ap, EDGE) {
787 emp = &pp->em_priv[link->pmp];
788
789 /* EM Transmit bit maybe busy during init */
790 for (i = 0; i < EM_MAX_RETRY; i++) {
791 rc = ap->ops->transmit_led_message(ap,
792 emp->led_state,
793 4);
794 /*
795 * If busy, give a breather but do not
796 * release EH ownership by using msleep()
797 * instead of ata_msleep(). EM Transmit
798 * bit is busy for the whole host and
799 * releasing ownership will cause other
800 * ports to fail the same way.
801 */
802 if (rc == -EBUSY)
803 msleep(1);
804 else
805 break;
806 }
807 }
808 }
809
810 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
811 ata_for_each_link(link, ap, EDGE)
812 ahci_init_sw_activity(link);
813
814 }
815
816 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
817 {
818 int rc;
819
820 /* disable DMA */
821 rc = ahci_stop_engine(ap);
822 if (rc) {
823 *emsg = "failed to stop engine";
824 return rc;
825 }
826
827 /* disable FIS reception */
828 rc = ahci_stop_fis_rx(ap);
829 if (rc) {
830 *emsg = "failed stop FIS RX";
831 return rc;
832 }
833
834 return 0;
835 }
836
837 int ahci_reset_controller(struct ata_host *host)
838 {
839 struct ahci_host_priv *hpriv = host->private_data;
840 void __iomem *mmio = hpriv->mmio;
841 u32 tmp;
842
843 /* we must be in AHCI mode, before using anything
844 * AHCI-specific, such as HOST_RESET.
845 */
846 ahci_enable_ahci(mmio);
847
848 /* global controller reset */
849 if (!ahci_skip_host_reset) {
850 tmp = readl(mmio + HOST_CTL);
851 if ((tmp & HOST_RESET) == 0) {
852 writel(tmp | HOST_RESET, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL); /* flush */
854 }
855
856 /*
857 * to perform host reset, OS should set HOST_RESET
858 * and poll until this bit is read to be "0".
859 * reset must complete within 1 second, or
860 * the hardware should be considered fried.
861 */
862 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
863 HOST_RESET, 10, 1000);
864
865 if (tmp & HOST_RESET) {
866 dev_err(host->dev, "controller reset failed (0x%x)\n",
867 tmp);
868 return -EIO;
869 }
870
871 /* turn on AHCI mode */
872 ahci_enable_ahci(mmio);
873
874 /* Some registers might be cleared on reset. Restore
875 * initial values.
876 */
877 ahci_restore_initial_config(host);
878 } else
879 dev_info(host->dev, "skipping global host reset\n");
880
881 return 0;
882 }
883 EXPORT_SYMBOL_GPL(ahci_reset_controller);
884
885 static void ahci_sw_activity(struct ata_link *link)
886 {
887 struct ata_port *ap = link->ap;
888 struct ahci_port_priv *pp = ap->private_data;
889 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
890
891 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
892 return;
893
894 emp->activity++;
895 if (!timer_pending(&emp->timer))
896 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
897 }
898
899 static void ahci_sw_activity_blink(unsigned long arg)
900 {
901 struct ata_link *link = (struct ata_link *)arg;
902 struct ata_port *ap = link->ap;
903 struct ahci_port_priv *pp = ap->private_data;
904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
905 unsigned long led_message = emp->led_state;
906 u32 activity_led_state;
907 unsigned long flags;
908
909 led_message &= EM_MSG_LED_VALUE;
910 led_message |= ap->port_no | (link->pmp << 8);
911
912 /* check to see if we've had activity. If so,
913 * toggle state of LED and reset timer. If not,
914 * turn LED to desired idle state.
915 */
916 spin_lock_irqsave(ap->lock, flags);
917 if (emp->saved_activity != emp->activity) {
918 emp->saved_activity = emp->activity;
919 /* get the current LED state */
920 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
921
922 if (activity_led_state)
923 activity_led_state = 0;
924 else
925 activity_led_state = 1;
926
927 /* clear old state */
928 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
929
930 /* toggle state */
931 led_message |= (activity_led_state << 16);
932 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
933 } else {
934 /* switch to idle */
935 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
936 if (emp->blink_policy == BLINK_OFF)
937 led_message |= (1 << 16);
938 }
939 spin_unlock_irqrestore(ap->lock, flags);
940 ap->ops->transmit_led_message(ap, led_message, 4);
941 }
942
943 static void ahci_init_sw_activity(struct ata_link *link)
944 {
945 struct ata_port *ap = link->ap;
946 struct ahci_port_priv *pp = ap->private_data;
947 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
948
949 /* init activity stats, setup timer */
950 emp->saved_activity = emp->activity = 0;
951 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
952
953 /* check our blink policy and set flag for link if it's enabled */
954 if (emp->blink_policy)
955 link->flags |= ATA_LFLAG_SW_ACTIVITY;
956 }
957
958 int ahci_reset_em(struct ata_host *host)
959 {
960 struct ahci_host_priv *hpriv = host->private_data;
961 void __iomem *mmio = hpriv->mmio;
962 u32 em_ctl;
963
964 em_ctl = readl(mmio + HOST_EM_CTL);
965 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
966 return -EINVAL;
967
968 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
969 return 0;
970 }
971 EXPORT_SYMBOL_GPL(ahci_reset_em);
972
973 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
974 ssize_t size)
975 {
976 struct ahci_host_priv *hpriv = ap->host->private_data;
977 struct ahci_port_priv *pp = ap->private_data;
978 void __iomem *mmio = hpriv->mmio;
979 u32 em_ctl;
980 u32 message[] = {0, 0};
981 unsigned long flags;
982 int pmp;
983 struct ahci_em_priv *emp;
984
985 /* get the slot number from the message */
986 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
987 if (pmp < EM_MAX_SLOTS)
988 emp = &pp->em_priv[pmp];
989 else
990 return -EINVAL;
991
992 spin_lock_irqsave(ap->lock, flags);
993
994 /*
995 * if we are still busy transmitting a previous message,
996 * do not allow
997 */
998 em_ctl = readl(mmio + HOST_EM_CTL);
999 if (em_ctl & EM_CTL_TM) {
1000 spin_unlock_irqrestore(ap->lock, flags);
1001 return -EBUSY;
1002 }
1003
1004 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1005 /*
1006 * create message header - this is all zero except for
1007 * the message size, which is 4 bytes.
1008 */
1009 message[0] |= (4 << 8);
1010
1011 /* ignore 0:4 of byte zero, fill in port info yourself */
1012 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1013
1014 /* write message to EM_LOC */
1015 writel(message[0], mmio + hpriv->em_loc);
1016 writel(message[1], mmio + hpriv->em_loc+4);
1017
1018 /*
1019 * tell hardware to transmit the message
1020 */
1021 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1022 }
1023
1024 /* save off new led state for port/slot */
1025 emp->led_state = state;
1026
1027 spin_unlock_irqrestore(ap->lock, flags);
1028 return size;
1029 }
1030
1031 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1032 {
1033 struct ahci_port_priv *pp = ap->private_data;
1034 struct ata_link *link;
1035 struct ahci_em_priv *emp;
1036 int rc = 0;
1037
1038 ata_for_each_link(link, ap, EDGE) {
1039 emp = &pp->em_priv[link->pmp];
1040 rc += sprintf(buf, "%lx\n", emp->led_state);
1041 }
1042 return rc;
1043 }
1044
1045 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1046 size_t size)
1047 {
1048 unsigned int state;
1049 int pmp;
1050 struct ahci_port_priv *pp = ap->private_data;
1051 struct ahci_em_priv *emp;
1052
1053 if (kstrtouint(buf, 0, &state) < 0)
1054 return -EINVAL;
1055
1056 /* get the slot number from the message */
1057 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1058 if (pmp < EM_MAX_SLOTS)
1059 emp = &pp->em_priv[pmp];
1060 else
1061 return -EINVAL;
1062
1063 /* mask off the activity bits if we are in sw_activity
1064 * mode, user should turn off sw_activity before setting
1065 * activity led through em_message
1066 */
1067 if (emp->blink_policy)
1068 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1069
1070 return ap->ops->transmit_led_message(ap, state, size);
1071 }
1072
1073 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1074 {
1075 struct ata_link *link = dev->link;
1076 struct ata_port *ap = link->ap;
1077 struct ahci_port_priv *pp = ap->private_data;
1078 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1079 u32 port_led_state = emp->led_state;
1080
1081 /* save the desired Activity LED behavior */
1082 if (val == OFF) {
1083 /* clear LFLAG */
1084 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1085
1086 /* set the LED to OFF */
1087 port_led_state &= EM_MSG_LED_VALUE_OFF;
1088 port_led_state |= (ap->port_no | (link->pmp << 8));
1089 ap->ops->transmit_led_message(ap, port_led_state, 4);
1090 } else {
1091 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1092 if (val == BLINK_OFF) {
1093 /* set LED to ON for idle */
1094 port_led_state &= EM_MSG_LED_VALUE_OFF;
1095 port_led_state |= (ap->port_no | (link->pmp << 8));
1096 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1097 ap->ops->transmit_led_message(ap, port_led_state, 4);
1098 }
1099 }
1100 emp->blink_policy = val;
1101 return 0;
1102 }
1103
1104 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1105 {
1106 struct ata_link *link = dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct ahci_port_priv *pp = ap->private_data;
1109 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1110
1111 /* display the saved value of activity behavior for this
1112 * disk.
1113 */
1114 return sprintf(buf, "%d\n", emp->blink_policy);
1115 }
1116
1117 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1118 int port_no, void __iomem *mmio,
1119 void __iomem *port_mmio)
1120 {
1121 struct ahci_host_priv *hpriv = ap->host->private_data;
1122 const char *emsg = NULL;
1123 int rc;
1124 u32 tmp;
1125
1126 /* make sure port is not active */
1127 rc = ahci_deinit_port(ap, &emsg);
1128 if (rc)
1129 dev_warn(dev, "%s (%d)\n", emsg, rc);
1130
1131 /* clear SError */
1132 tmp = readl(port_mmio + PORT_SCR_ERR);
1133 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1134 writel(tmp, port_mmio + PORT_SCR_ERR);
1135
1136 /* clear port IRQ */
1137 tmp = readl(port_mmio + PORT_IRQ_STAT);
1138 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1139 if (tmp)
1140 writel(tmp, port_mmio + PORT_IRQ_STAT);
1141
1142 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1143
1144 /* mark esata ports */
1145 tmp = readl(port_mmio + PORT_CMD);
1146 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1147 ap->pflags |= ATA_PFLAG_EXTERNAL;
1148 }
1149
1150 void ahci_init_controller(struct ata_host *host)
1151 {
1152 struct ahci_host_priv *hpriv = host->private_data;
1153 void __iomem *mmio = hpriv->mmio;
1154 int i;
1155 void __iomem *port_mmio;
1156 u32 tmp;
1157
1158 for (i = 0; i < host->n_ports; i++) {
1159 struct ata_port *ap = host->ports[i];
1160
1161 port_mmio = ahci_port_base(ap);
1162 if (ata_port_is_dummy(ap))
1163 continue;
1164
1165 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1166 }
1167
1168 tmp = readl(mmio + HOST_CTL);
1169 VPRINTK("HOST_CTL 0x%x\n", tmp);
1170 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1171 tmp = readl(mmio + HOST_CTL);
1172 VPRINTK("HOST_CTL 0x%x\n", tmp);
1173 }
1174 EXPORT_SYMBOL_GPL(ahci_init_controller);
1175
1176 static void ahci_dev_config(struct ata_device *dev)
1177 {
1178 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1179
1180 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1181 dev->max_sectors = 255;
1182 ata_dev_info(dev,
1183 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1184 }
1185 }
1186
1187 unsigned int ahci_dev_classify(struct ata_port *ap)
1188 {
1189 void __iomem *port_mmio = ahci_port_base(ap);
1190 struct ata_taskfile tf;
1191 u32 tmp;
1192
1193 tmp = readl(port_mmio + PORT_SIG);
1194 tf.lbah = (tmp >> 24) & 0xff;
1195 tf.lbam = (tmp >> 16) & 0xff;
1196 tf.lbal = (tmp >> 8) & 0xff;
1197 tf.nsect = (tmp) & 0xff;
1198
1199 return ata_dev_classify(&tf);
1200 }
1201 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1202
1203 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1204 u32 opts)
1205 {
1206 dma_addr_t cmd_tbl_dma;
1207
1208 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1209
1210 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1211 pp->cmd_slot[tag].status = 0;
1212 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1213 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1214 }
1215 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1216
1217 int ahci_kick_engine(struct ata_port *ap)
1218 {
1219 void __iomem *port_mmio = ahci_port_base(ap);
1220 struct ahci_host_priv *hpriv = ap->host->private_data;
1221 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1222 u32 tmp;
1223 int busy, rc;
1224
1225 /* stop engine */
1226 rc = ahci_stop_engine(ap);
1227 if (rc)
1228 goto out_restart;
1229
1230 /* need to do CLO?
1231 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1232 */
1233 busy = status & (ATA_BUSY | ATA_DRQ);
1234 if (!busy && !sata_pmp_attached(ap)) {
1235 rc = 0;
1236 goto out_restart;
1237 }
1238
1239 if (!(hpriv->cap & HOST_CAP_CLO)) {
1240 rc = -EOPNOTSUPP;
1241 goto out_restart;
1242 }
1243
1244 /* perform CLO */
1245 tmp = readl(port_mmio + PORT_CMD);
1246 tmp |= PORT_CMD_CLO;
1247 writel(tmp, port_mmio + PORT_CMD);
1248
1249 rc = 0;
1250 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1251 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1252 if (tmp & PORT_CMD_CLO)
1253 rc = -EIO;
1254
1255 /* restart engine */
1256 out_restart:
1257 hpriv->start_engine(ap);
1258 return rc;
1259 }
1260 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1261
1262 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1263 struct ata_taskfile *tf, int is_cmd, u16 flags,
1264 unsigned long timeout_msec)
1265 {
1266 const u32 cmd_fis_len = 5; /* five dwords */
1267 struct ahci_port_priv *pp = ap->private_data;
1268 void __iomem *port_mmio = ahci_port_base(ap);
1269 u8 *fis = pp->cmd_tbl;
1270 u32 tmp;
1271
1272 /* prep the command */
1273 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1274 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1275
1276 /* set port value for softreset of Port Multiplier */
1277 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1278 tmp = readl(port_mmio + PORT_FBS);
1279 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1280 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1281 writel(tmp, port_mmio + PORT_FBS);
1282 pp->fbs_last_dev = pmp;
1283 }
1284
1285 /* issue & wait */
1286 writel(1, port_mmio + PORT_CMD_ISSUE);
1287
1288 if (timeout_msec) {
1289 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1290 0x1, 0x1, 1, timeout_msec);
1291 if (tmp & 0x1) {
1292 ahci_kick_engine(ap);
1293 return -EBUSY;
1294 }
1295 } else
1296 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1297
1298 return 0;
1299 }
1300
1301 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1302 int pmp, unsigned long deadline,
1303 int (*check_ready)(struct ata_link *link))
1304 {
1305 struct ata_port *ap = link->ap;
1306 struct ahci_host_priv *hpriv = ap->host->private_data;
1307 struct ahci_port_priv *pp = ap->private_data;
1308 const char *reason = NULL;
1309 unsigned long now, msecs;
1310 struct ata_taskfile tf;
1311 bool fbs_disabled = false;
1312 int rc;
1313
1314 DPRINTK("ENTER\n");
1315
1316 /* prepare for SRST (AHCI-1.1 10.4.1) */
1317 rc = ahci_kick_engine(ap);
1318 if (rc && rc != -EOPNOTSUPP)
1319 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1320
1321 /*
1322 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1323 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1324 * that is attached to port multiplier.
1325 */
1326 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1327 ahci_disable_fbs(ap);
1328 fbs_disabled = true;
1329 }
1330
1331 ata_tf_init(link->device, &tf);
1332
1333 /* issue the first D2H Register FIS */
1334 msecs = 0;
1335 now = jiffies;
1336 if (time_after(deadline, now))
1337 msecs = jiffies_to_msecs(deadline - now);
1338
1339 tf.ctl |= ATA_SRST;
1340 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1341 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1342 rc = -EIO;
1343 reason = "1st FIS failed";
1344 goto fail;
1345 }
1346
1347 /* spec says at least 5us, but be generous and sleep for 1ms */
1348 ata_msleep(ap, 1);
1349
1350 /* issue the second D2H Register FIS */
1351 tf.ctl &= ~ATA_SRST;
1352 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1353
1354 /* wait for link to become ready */
1355 rc = ata_wait_after_reset(link, deadline, check_ready);
1356 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1357 /*
1358 * Workaround for cases where link online status can't
1359 * be trusted. Treat device readiness timeout as link
1360 * offline.
1361 */
1362 ata_link_info(link, "device not ready, treating as offline\n");
1363 *class = ATA_DEV_NONE;
1364 } else if (rc) {
1365 /* link occupied, -ENODEV too is an error */
1366 reason = "device not ready";
1367 goto fail;
1368 } else
1369 *class = ahci_dev_classify(ap);
1370
1371 /* re-enable FBS if disabled before */
1372 if (fbs_disabled)
1373 ahci_enable_fbs(ap);
1374
1375 DPRINTK("EXIT, class=%u\n", *class);
1376 return 0;
1377
1378 fail:
1379 ata_link_err(link, "softreset failed (%s)\n", reason);
1380 return rc;
1381 }
1382
1383 int ahci_check_ready(struct ata_link *link)
1384 {
1385 void __iomem *port_mmio = ahci_port_base(link->ap);
1386 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1387
1388 return ata_check_ready(status);
1389 }
1390 EXPORT_SYMBOL_GPL(ahci_check_ready);
1391
1392 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1393 unsigned long deadline)
1394 {
1395 int pmp = sata_srst_pmp(link);
1396
1397 DPRINTK("ENTER\n");
1398
1399 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1400 }
1401 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1402
1403 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1404 {
1405 void __iomem *port_mmio = ahci_port_base(link->ap);
1406 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1407 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1408
1409 /*
1410 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1411 * which can save timeout delay.
1412 */
1413 if (irq_status & PORT_IRQ_BAD_PMP)
1414 return -EIO;
1415
1416 return ata_check_ready(status);
1417 }
1418
1419 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1420 unsigned long deadline)
1421 {
1422 struct ata_port *ap = link->ap;
1423 void __iomem *port_mmio = ahci_port_base(ap);
1424 int pmp = sata_srst_pmp(link);
1425 int rc;
1426 u32 irq_sts;
1427
1428 DPRINTK("ENTER\n");
1429
1430 rc = ahci_do_softreset(link, class, pmp, deadline,
1431 ahci_bad_pmp_check_ready);
1432
1433 /*
1434 * Soft reset fails with IPMS set when PMP is enabled but
1435 * SATA HDD/ODD is connected to SATA port, do soft reset
1436 * again to port 0.
1437 */
1438 if (rc == -EIO) {
1439 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1440 if (irq_sts & PORT_IRQ_BAD_PMP) {
1441 ata_link_warn(link,
1442 "applying PMP SRST workaround "
1443 "and retrying\n");
1444 rc = ahci_do_softreset(link, class, 0, deadline,
1445 ahci_check_ready);
1446 }
1447 }
1448
1449 return rc;
1450 }
1451
1452 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1453 unsigned long deadline)
1454 {
1455 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1456 struct ata_port *ap = link->ap;
1457 struct ahci_port_priv *pp = ap->private_data;
1458 struct ahci_host_priv *hpriv = ap->host->private_data;
1459 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1460 struct ata_taskfile tf;
1461 bool online;
1462 int rc;
1463
1464 DPRINTK("ENTER\n");
1465
1466 ahci_stop_engine(ap);
1467
1468 /* clear D2H reception area to properly wait for D2H FIS */
1469 ata_tf_init(link->device, &tf);
1470 tf.command = ATA_BUSY;
1471 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1472
1473 rc = sata_link_hardreset(link, timing, deadline, &online,
1474 ahci_check_ready);
1475
1476 hpriv->start_engine(ap);
1477
1478 if (online)
1479 *class = ahci_dev_classify(ap);
1480
1481 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1482 return rc;
1483 }
1484
1485 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1486 {
1487 struct ata_port *ap = link->ap;
1488 void __iomem *port_mmio = ahci_port_base(ap);
1489 u32 new_tmp, tmp;
1490
1491 ata_std_postreset(link, class);
1492
1493 /* Make sure port's ATAPI bit is set appropriately */
1494 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1495 if (*class == ATA_DEV_ATAPI)
1496 new_tmp |= PORT_CMD_ATAPI;
1497 else
1498 new_tmp &= ~PORT_CMD_ATAPI;
1499 if (new_tmp != tmp) {
1500 writel(new_tmp, port_mmio + PORT_CMD);
1501 readl(port_mmio + PORT_CMD); /* flush */
1502 }
1503 }
1504
1505 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1506 {
1507 struct scatterlist *sg;
1508 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1509 unsigned int si;
1510
1511 VPRINTK("ENTER\n");
1512
1513 /*
1514 * Next, the S/G list.
1515 */
1516 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1517 dma_addr_t addr = sg_dma_address(sg);
1518 u32 sg_len = sg_dma_len(sg);
1519
1520 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1521 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1522 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1523 }
1524
1525 return si;
1526 }
1527
1528 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1529 {
1530 struct ata_port *ap = qc->ap;
1531 struct ahci_port_priv *pp = ap->private_data;
1532
1533 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1534 return ata_std_qc_defer(qc);
1535 else
1536 return sata_pmp_qc_defer_cmd_switch(qc);
1537 }
1538
1539 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1540 {
1541 struct ata_port *ap = qc->ap;
1542 struct ahci_port_priv *pp = ap->private_data;
1543 int is_atapi = ata_is_atapi(qc->tf.protocol);
1544 void *cmd_tbl;
1545 u32 opts;
1546 const u32 cmd_fis_len = 5; /* five dwords */
1547 unsigned int n_elem;
1548
1549 /*
1550 * Fill in command table information. First, the header,
1551 * a SATA Register - Host to Device command FIS.
1552 */
1553 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1554
1555 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1556 if (is_atapi) {
1557 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1558 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1559 }
1560
1561 n_elem = 0;
1562 if (qc->flags & ATA_QCFLAG_DMAMAP)
1563 n_elem = ahci_fill_sg(qc, cmd_tbl);
1564
1565 /*
1566 * Fill in command slot information.
1567 */
1568 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1569 if (qc->tf.flags & ATA_TFLAG_WRITE)
1570 opts |= AHCI_CMD_WRITE;
1571 if (is_atapi)
1572 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1573
1574 ahci_fill_cmd_slot(pp, qc->tag, opts);
1575 }
1576
1577 static void ahci_fbs_dec_intr(struct ata_port *ap)
1578 {
1579 struct ahci_port_priv *pp = ap->private_data;
1580 void __iomem *port_mmio = ahci_port_base(ap);
1581 u32 fbs = readl(port_mmio + PORT_FBS);
1582 int retries = 3;
1583
1584 DPRINTK("ENTER\n");
1585 BUG_ON(!pp->fbs_enabled);
1586
1587 /* time to wait for DEC is not specified by AHCI spec,
1588 * add a retry loop for safety.
1589 */
1590 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1591 fbs = readl(port_mmio + PORT_FBS);
1592 while ((fbs & PORT_FBS_DEC) && retries--) {
1593 udelay(1);
1594 fbs = readl(port_mmio + PORT_FBS);
1595 }
1596
1597 if (fbs & PORT_FBS_DEC)
1598 dev_err(ap->host->dev, "failed to clear device error\n");
1599 }
1600
1601 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1602 {
1603 struct ahci_host_priv *hpriv = ap->host->private_data;
1604 struct ahci_port_priv *pp = ap->private_data;
1605 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1606 struct ata_link *link = NULL;
1607 struct ata_queued_cmd *active_qc;
1608 struct ata_eh_info *active_ehi;
1609 bool fbs_need_dec = false;
1610 u32 serror;
1611
1612 /* determine active link with error */
1613 if (pp->fbs_enabled) {
1614 void __iomem *port_mmio = ahci_port_base(ap);
1615 u32 fbs = readl(port_mmio + PORT_FBS);
1616 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1617
1618 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1619 link = &ap->pmp_link[pmp];
1620 fbs_need_dec = true;
1621 }
1622
1623 } else
1624 ata_for_each_link(link, ap, EDGE)
1625 if (ata_link_active(link))
1626 break;
1627
1628 if (!link)
1629 link = &ap->link;
1630
1631 active_qc = ata_qc_from_tag(ap, link->active_tag);
1632 active_ehi = &link->eh_info;
1633
1634 /* record irq stat */
1635 ata_ehi_clear_desc(host_ehi);
1636 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1637
1638 /* AHCI needs SError cleared; otherwise, it might lock up */
1639 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1640 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1641 host_ehi->serror |= serror;
1642
1643 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1644 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1645 irq_stat &= ~PORT_IRQ_IF_ERR;
1646
1647 if (irq_stat & PORT_IRQ_TF_ERR) {
1648 /* If qc is active, charge it; otherwise, the active
1649 * link. There's no active qc on NCQ errors. It will
1650 * be determined by EH by reading log page 10h.
1651 */
1652 if (active_qc)
1653 active_qc->err_mask |= AC_ERR_DEV;
1654 else
1655 active_ehi->err_mask |= AC_ERR_DEV;
1656
1657 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1658 host_ehi->serror &= ~SERR_INTERNAL;
1659 }
1660
1661 if (irq_stat & PORT_IRQ_UNK_FIS) {
1662 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1663
1664 active_ehi->err_mask |= AC_ERR_HSM;
1665 active_ehi->action |= ATA_EH_RESET;
1666 ata_ehi_push_desc(active_ehi,
1667 "unknown FIS %08x %08x %08x %08x" ,
1668 unk[0], unk[1], unk[2], unk[3]);
1669 }
1670
1671 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1672 active_ehi->err_mask |= AC_ERR_HSM;
1673 active_ehi->action |= ATA_EH_RESET;
1674 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1675 }
1676
1677 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1678 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1679 host_ehi->action |= ATA_EH_RESET;
1680 ata_ehi_push_desc(host_ehi, "host bus error");
1681 }
1682
1683 if (irq_stat & PORT_IRQ_IF_ERR) {
1684 if (fbs_need_dec)
1685 active_ehi->err_mask |= AC_ERR_DEV;
1686 else {
1687 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1688 host_ehi->action |= ATA_EH_RESET;
1689 }
1690
1691 ata_ehi_push_desc(host_ehi, "interface fatal error");
1692 }
1693
1694 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1695 ata_ehi_hotplugged(host_ehi);
1696 ata_ehi_push_desc(host_ehi, "%s",
1697 irq_stat & PORT_IRQ_CONNECT ?
1698 "connection status changed" : "PHY RDY changed");
1699 }
1700
1701 /* okay, let's hand over to EH */
1702
1703 if (irq_stat & PORT_IRQ_FREEZE)
1704 ata_port_freeze(ap);
1705 else if (fbs_need_dec) {
1706 ata_link_abort(link);
1707 ahci_fbs_dec_intr(ap);
1708 } else
1709 ata_port_abort(ap);
1710 }
1711
1712 static void ahci_handle_port_interrupt(struct ata_port *ap,
1713 void __iomem *port_mmio, u32 status)
1714 {
1715 struct ata_eh_info *ehi = &ap->link.eh_info;
1716 struct ahci_port_priv *pp = ap->private_data;
1717 struct ahci_host_priv *hpriv = ap->host->private_data;
1718 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1719 u32 qc_active = 0;
1720 int rc;
1721
1722 /* ignore BAD_PMP while resetting */
1723 if (unlikely(resetting))
1724 status &= ~PORT_IRQ_BAD_PMP;
1725
1726 if (sata_lpm_ignore_phy_events(&ap->link)) {
1727 status &= ~PORT_IRQ_PHYRDY;
1728 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1729 }
1730
1731 if (unlikely(status & PORT_IRQ_ERROR)) {
1732 ahci_error_intr(ap, status);
1733 return;
1734 }
1735
1736 if (status & PORT_IRQ_SDB_FIS) {
1737 /* If SNotification is available, leave notification
1738 * handling to sata_async_notification(). If not,
1739 * emulate it by snooping SDB FIS RX area.
1740 *
1741 * Snooping FIS RX area is probably cheaper than
1742 * poking SNotification but some constrollers which
1743 * implement SNotification, ICH9 for example, don't
1744 * store AN SDB FIS into receive area.
1745 */
1746 if (hpriv->cap & HOST_CAP_SNTF)
1747 sata_async_notification(ap);
1748 else {
1749 /* If the 'N' bit in word 0 of the FIS is set,
1750 * we just received asynchronous notification.
1751 * Tell libata about it.
1752 *
1753 * Lack of SNotification should not appear in
1754 * ahci 1.2, so the workaround is unnecessary
1755 * when FBS is enabled.
1756 */
1757 if (pp->fbs_enabled)
1758 WARN_ON_ONCE(1);
1759 else {
1760 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1761 u32 f0 = le32_to_cpu(f[0]);
1762 if (f0 & (1 << 15))
1763 sata_async_notification(ap);
1764 }
1765 }
1766 }
1767
1768 /* pp->active_link is not reliable once FBS is enabled, both
1769 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1770 * NCQ and non-NCQ commands may be in flight at the same time.
1771 */
1772 if (pp->fbs_enabled) {
1773 if (ap->qc_active) {
1774 qc_active = readl(port_mmio + PORT_SCR_ACT);
1775 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1776 }
1777 } else {
1778 /* pp->active_link is valid iff any command is in flight */
1779 if (ap->qc_active && pp->active_link->sactive)
1780 qc_active = readl(port_mmio + PORT_SCR_ACT);
1781 else
1782 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1783 }
1784
1785
1786 rc = ata_qc_complete_multiple(ap, qc_active);
1787
1788 /* while resetting, invalid completions are expected */
1789 if (unlikely(rc < 0 && !resetting)) {
1790 ehi->err_mask |= AC_ERR_HSM;
1791 ehi->action |= ATA_EH_RESET;
1792 ata_port_freeze(ap);
1793 }
1794 }
1795
1796 static void ahci_port_intr(struct ata_port *ap)
1797 {
1798 void __iomem *port_mmio = ahci_port_base(ap);
1799 u32 status;
1800
1801 status = readl(port_mmio + PORT_IRQ_STAT);
1802 writel(status, port_mmio + PORT_IRQ_STAT);
1803
1804 ahci_handle_port_interrupt(ap, port_mmio, status);
1805 }
1806
1807 static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
1808 {
1809 struct ata_port *ap = dev_instance;
1810 struct ahci_port_priv *pp = ap->private_data;
1811 void __iomem *port_mmio = ahci_port_base(ap);
1812 u32 status;
1813
1814 status = atomic_xchg(&pp->intr_status, 0);
1815 if (!status)
1816 return IRQ_NONE;
1817
1818 spin_lock_bh(ap->lock);
1819 ahci_handle_port_interrupt(ap, port_mmio, status);
1820 spin_unlock_bh(ap->lock);
1821
1822 return IRQ_HANDLED;
1823 }
1824
1825 static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
1826 {
1827 struct ata_port *ap = dev_instance;
1828 void __iomem *port_mmio = ahci_port_base(ap);
1829 struct ahci_port_priv *pp = ap->private_data;
1830 u32 status;
1831
1832 VPRINTK("ENTER\n");
1833
1834 status = readl(port_mmio + PORT_IRQ_STAT);
1835 writel(status, port_mmio + PORT_IRQ_STAT);
1836
1837 atomic_or(status, &pp->intr_status);
1838
1839 VPRINTK("EXIT\n");
1840
1841 return IRQ_WAKE_THREAD;
1842 }
1843
1844 static u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1845 {
1846 unsigned int i, handled = 0;
1847
1848 for (i = 0; i < host->n_ports; i++) {
1849 struct ata_port *ap;
1850
1851 if (!(irq_masked & (1 << i)))
1852 continue;
1853
1854 ap = host->ports[i];
1855 if (ap) {
1856 ahci_port_intr(ap);
1857 VPRINTK("port %u\n", i);
1858 } else {
1859 VPRINTK("port %u (no irq)\n", i);
1860 if (ata_ratelimit())
1861 dev_warn(host->dev,
1862 "interrupt on disabled port %u\n", i);
1863 }
1864
1865 handled = 1;
1866 }
1867
1868 return handled;
1869 }
1870
1871 static irqreturn_t ahci_single_edge_irq_intr(int irq, void *dev_instance)
1872 {
1873 struct ata_host *host = dev_instance;
1874 struct ahci_host_priv *hpriv;
1875 unsigned int rc = 0;
1876 void __iomem *mmio;
1877 u32 irq_stat, irq_masked;
1878
1879 VPRINTK("ENTER\n");
1880
1881 hpriv = host->private_data;
1882 mmio = hpriv->mmio;
1883
1884 /* sigh. 0xffffffff is a valid return from h/w */
1885 irq_stat = readl(mmio + HOST_IRQ_STAT);
1886 if (!irq_stat)
1887 return IRQ_NONE;
1888
1889 irq_masked = irq_stat & hpriv->port_map;
1890
1891 spin_lock(&host->lock);
1892
1893 /*
1894 * HOST_IRQ_STAT behaves as edge triggered latch meaning that
1895 * it should be cleared before all the port events are cleared.
1896 */
1897 writel(irq_stat, mmio + HOST_IRQ_STAT);
1898
1899 rc = ahci_handle_port_intr(host, irq_masked);
1900
1901 spin_unlock(&host->lock);
1902
1903 VPRINTK("EXIT\n");
1904
1905 return IRQ_RETVAL(rc);
1906 }
1907
1908 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1909 {
1910 struct ata_host *host = dev_instance;
1911 struct ahci_host_priv *hpriv;
1912 unsigned int rc = 0;
1913 void __iomem *mmio;
1914 u32 irq_stat, irq_masked;
1915
1916 VPRINTK("ENTER\n");
1917
1918 hpriv = host->private_data;
1919 mmio = hpriv->mmio;
1920
1921 /* sigh. 0xffffffff is a valid return from h/w */
1922 irq_stat = readl(mmio + HOST_IRQ_STAT);
1923 if (!irq_stat)
1924 return IRQ_NONE;
1925
1926 irq_masked = irq_stat & hpriv->port_map;
1927
1928 spin_lock(&host->lock);
1929
1930 rc = ahci_handle_port_intr(host, irq_masked);
1931
1932 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1933 * it should be cleared after all the port events are cleared;
1934 * otherwise, it will raise a spurious interrupt after each
1935 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1936 * information.
1937 *
1938 * Also, use the unmasked value to clear interrupt as spurious
1939 * pending event on a dummy port might cause screaming IRQ.
1940 */
1941 writel(irq_stat, mmio + HOST_IRQ_STAT);
1942
1943 spin_unlock(&host->lock);
1944
1945 VPRINTK("EXIT\n");
1946
1947 return IRQ_RETVAL(rc);
1948 }
1949
1950 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1951 {
1952 struct ata_port *ap = qc->ap;
1953 void __iomem *port_mmio = ahci_port_base(ap);
1954 struct ahci_port_priv *pp = ap->private_data;
1955
1956 /* Keep track of the currently active link. It will be used
1957 * in completion path to determine whether NCQ phase is in
1958 * progress.
1959 */
1960 pp->active_link = qc->dev->link;
1961
1962 if (qc->tf.protocol == ATA_PROT_NCQ)
1963 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1964
1965 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1966 u32 fbs = readl(port_mmio + PORT_FBS);
1967 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1968 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1969 writel(fbs, port_mmio + PORT_FBS);
1970 pp->fbs_last_dev = qc->dev->link->pmp;
1971 }
1972
1973 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1974
1975 ahci_sw_activity(qc->dev->link);
1976
1977 return 0;
1978 }
1979 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1980
1981 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1982 {
1983 struct ahci_port_priv *pp = qc->ap->private_data;
1984 u8 *rx_fis = pp->rx_fis;
1985
1986 if (pp->fbs_enabled)
1987 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1988
1989 /*
1990 * After a successful execution of an ATA PIO data-in command,
1991 * the device doesn't send D2H Reg FIS to update the TF and
1992 * the host should take TF and E_Status from the preceding PIO
1993 * Setup FIS.
1994 */
1995 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1996 !(qc->flags & ATA_QCFLAG_FAILED)) {
1997 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1998 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1999 } else
2000 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2001
2002 return true;
2003 }
2004
2005 static void ahci_freeze(struct ata_port *ap)
2006 {
2007 void __iomem *port_mmio = ahci_port_base(ap);
2008
2009 /* turn IRQ off */
2010 writel(0, port_mmio + PORT_IRQ_MASK);
2011 }
2012
2013 static void ahci_thaw(struct ata_port *ap)
2014 {
2015 struct ahci_host_priv *hpriv = ap->host->private_data;
2016 void __iomem *mmio = hpriv->mmio;
2017 void __iomem *port_mmio = ahci_port_base(ap);
2018 u32 tmp;
2019 struct ahci_port_priv *pp = ap->private_data;
2020
2021 /* clear IRQ */
2022 tmp = readl(port_mmio + PORT_IRQ_STAT);
2023 writel(tmp, port_mmio + PORT_IRQ_STAT);
2024 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2025
2026 /* turn IRQ back on */
2027 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2028 }
2029
2030 void ahci_error_handler(struct ata_port *ap)
2031 {
2032 struct ahci_host_priv *hpriv = ap->host->private_data;
2033
2034 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2035 /* restart engine */
2036 ahci_stop_engine(ap);
2037 hpriv->start_engine(ap);
2038 }
2039
2040 sata_pmp_error_handler(ap);
2041
2042 if (!ata_dev_enabled(ap->link.device))
2043 ahci_stop_engine(ap);
2044 }
2045 EXPORT_SYMBOL_GPL(ahci_error_handler);
2046
2047 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2048 {
2049 struct ata_port *ap = qc->ap;
2050
2051 /* make DMA engine forget about the failed command */
2052 if (qc->flags & ATA_QCFLAG_FAILED)
2053 ahci_kick_engine(ap);
2054 }
2055
2056 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2057 {
2058 struct ahci_host_priv *hpriv = ap->host->private_data;
2059 void __iomem *port_mmio = ahci_port_base(ap);
2060 struct ata_device *dev = ap->link.device;
2061 u32 devslp, dm, dito, mdat, deto;
2062 int rc;
2063 unsigned int err_mask;
2064
2065 devslp = readl(port_mmio + PORT_DEVSLP);
2066 if (!(devslp & PORT_DEVSLP_DSP)) {
2067 dev_info(ap->host->dev, "port does not support device sleep\n");
2068 return;
2069 }
2070
2071 /* disable device sleep */
2072 if (!sleep) {
2073 if (devslp & PORT_DEVSLP_ADSE) {
2074 writel(devslp & ~PORT_DEVSLP_ADSE,
2075 port_mmio + PORT_DEVSLP);
2076 err_mask = ata_dev_set_feature(dev,
2077 SETFEATURES_SATA_DISABLE,
2078 SATA_DEVSLP);
2079 if (err_mask && err_mask != AC_ERR_DEV)
2080 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2081 }
2082 return;
2083 }
2084
2085 /* device sleep was already enabled */
2086 if (devslp & PORT_DEVSLP_ADSE)
2087 return;
2088
2089 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2090 rc = ahci_stop_engine(ap);
2091 if (rc)
2092 return;
2093
2094 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2095 dito = devslp_idle_timeout / (dm + 1);
2096 if (dito > 0x3ff)
2097 dito = 0x3ff;
2098
2099 /* Use the nominal value 10 ms if the read MDAT is zero,
2100 * the nominal value of DETO is 20 ms.
2101 */
2102 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2103 ATA_LOG_DEVSLP_VALID_MASK) {
2104 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2105 ATA_LOG_DEVSLP_MDAT_MASK;
2106 if (!mdat)
2107 mdat = 10;
2108 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2109 if (!deto)
2110 deto = 20;
2111 } else {
2112 mdat = 10;
2113 deto = 20;
2114 }
2115
2116 /* Make dito, mdat, deto bits to 0s */
2117 devslp &= ~GENMASK_ULL(24, 2);
2118 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2119 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2120 (deto << PORT_DEVSLP_DETO_OFFSET) |
2121 PORT_DEVSLP_ADSE);
2122 writel(devslp, port_mmio + PORT_DEVSLP);
2123
2124 hpriv->start_engine(ap);
2125
2126 /* enable device sleep feature for the drive */
2127 err_mask = ata_dev_set_feature(dev,
2128 SETFEATURES_SATA_ENABLE,
2129 SATA_DEVSLP);
2130 if (err_mask && err_mask != AC_ERR_DEV)
2131 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2132 }
2133
2134 static void ahci_enable_fbs(struct ata_port *ap)
2135 {
2136 struct ahci_host_priv *hpriv = ap->host->private_data;
2137 struct ahci_port_priv *pp = ap->private_data;
2138 void __iomem *port_mmio = ahci_port_base(ap);
2139 u32 fbs;
2140 int rc;
2141
2142 if (!pp->fbs_supported)
2143 return;
2144
2145 fbs = readl(port_mmio + PORT_FBS);
2146 if (fbs & PORT_FBS_EN) {
2147 pp->fbs_enabled = true;
2148 pp->fbs_last_dev = -1; /* initialization */
2149 return;
2150 }
2151
2152 rc = ahci_stop_engine(ap);
2153 if (rc)
2154 return;
2155
2156 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2157 fbs = readl(port_mmio + PORT_FBS);
2158 if (fbs & PORT_FBS_EN) {
2159 dev_info(ap->host->dev, "FBS is enabled\n");
2160 pp->fbs_enabled = true;
2161 pp->fbs_last_dev = -1; /* initialization */
2162 } else
2163 dev_err(ap->host->dev, "Failed to enable FBS\n");
2164
2165 hpriv->start_engine(ap);
2166 }
2167
2168 static void ahci_disable_fbs(struct ata_port *ap)
2169 {
2170 struct ahci_host_priv *hpriv = ap->host->private_data;
2171 struct ahci_port_priv *pp = ap->private_data;
2172 void __iomem *port_mmio = ahci_port_base(ap);
2173 u32 fbs;
2174 int rc;
2175
2176 if (!pp->fbs_supported)
2177 return;
2178
2179 fbs = readl(port_mmio + PORT_FBS);
2180 if ((fbs & PORT_FBS_EN) == 0) {
2181 pp->fbs_enabled = false;
2182 return;
2183 }
2184
2185 rc = ahci_stop_engine(ap);
2186 if (rc)
2187 return;
2188
2189 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2190 fbs = readl(port_mmio + PORT_FBS);
2191 if (fbs & PORT_FBS_EN)
2192 dev_err(ap->host->dev, "Failed to disable FBS\n");
2193 else {
2194 dev_info(ap->host->dev, "FBS is disabled\n");
2195 pp->fbs_enabled = false;
2196 }
2197
2198 hpriv->start_engine(ap);
2199 }
2200
2201 static void ahci_pmp_attach(struct ata_port *ap)
2202 {
2203 void __iomem *port_mmio = ahci_port_base(ap);
2204 struct ahci_port_priv *pp = ap->private_data;
2205 u32 cmd;
2206
2207 cmd = readl(port_mmio + PORT_CMD);
2208 cmd |= PORT_CMD_PMP;
2209 writel(cmd, port_mmio + PORT_CMD);
2210
2211 ahci_enable_fbs(ap);
2212
2213 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2214
2215 /*
2216 * We must not change the port interrupt mask register if the
2217 * port is marked frozen, the value in pp->intr_mask will be
2218 * restored later when the port is thawed.
2219 *
2220 * Note that during initialization, the port is marked as
2221 * frozen since the irq handler is not yet registered.
2222 */
2223 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2224 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2225 }
2226
2227 static void ahci_pmp_detach(struct ata_port *ap)
2228 {
2229 void __iomem *port_mmio = ahci_port_base(ap);
2230 struct ahci_port_priv *pp = ap->private_data;
2231 u32 cmd;
2232
2233 ahci_disable_fbs(ap);
2234
2235 cmd = readl(port_mmio + PORT_CMD);
2236 cmd &= ~PORT_CMD_PMP;
2237 writel(cmd, port_mmio + PORT_CMD);
2238
2239 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2240
2241 /* see comment above in ahci_pmp_attach() */
2242 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2243 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2244 }
2245
2246 int ahci_port_resume(struct ata_port *ap)
2247 {
2248 ahci_power_up(ap);
2249 ahci_start_port(ap);
2250
2251 if (sata_pmp_attached(ap))
2252 ahci_pmp_attach(ap);
2253 else
2254 ahci_pmp_detach(ap);
2255
2256 return 0;
2257 }
2258 EXPORT_SYMBOL_GPL(ahci_port_resume);
2259
2260 #ifdef CONFIG_PM
2261 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2262 {
2263 const char *emsg = NULL;
2264 int rc;
2265
2266 rc = ahci_deinit_port(ap, &emsg);
2267 if (rc == 0)
2268 ahci_power_down(ap);
2269 else {
2270 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2271 ata_port_freeze(ap);
2272 }
2273
2274 return rc;
2275 }
2276 #endif
2277
2278 static int ahci_port_start(struct ata_port *ap)
2279 {
2280 struct ahci_host_priv *hpriv = ap->host->private_data;
2281 struct device *dev = ap->host->dev;
2282 struct ahci_port_priv *pp;
2283 void *mem;
2284 dma_addr_t mem_dma;
2285 size_t dma_sz, rx_fis_sz;
2286
2287 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2288 if (!pp)
2289 return -ENOMEM;
2290
2291 if (ap->host->n_ports > 1) {
2292 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2293 if (!pp->irq_desc) {
2294 devm_kfree(dev, pp);
2295 return -ENOMEM;
2296 }
2297 snprintf(pp->irq_desc, 8,
2298 "%s%d", dev_driver_string(dev), ap->port_no);
2299 }
2300
2301 /* check FBS capability */
2302 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2303 void __iomem *port_mmio = ahci_port_base(ap);
2304 u32 cmd = readl(port_mmio + PORT_CMD);
2305 if (cmd & PORT_CMD_FBSCP)
2306 pp->fbs_supported = true;
2307 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2308 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2309 ap->port_no);
2310 pp->fbs_supported = true;
2311 } else
2312 dev_warn(dev, "port %d is not capable of FBS\n",
2313 ap->port_no);
2314 }
2315
2316 if (pp->fbs_supported) {
2317 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2318 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2319 } else {
2320 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2321 rx_fis_sz = AHCI_RX_FIS_SZ;
2322 }
2323
2324 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2325 if (!mem)
2326 return -ENOMEM;
2327 memset(mem, 0, dma_sz);
2328
2329 /*
2330 * First item in chunk of DMA memory: 32-slot command table,
2331 * 32 bytes each in size
2332 */
2333 pp->cmd_slot = mem;
2334 pp->cmd_slot_dma = mem_dma;
2335
2336 mem += AHCI_CMD_SLOT_SZ;
2337 mem_dma += AHCI_CMD_SLOT_SZ;
2338
2339 /*
2340 * Second item: Received-FIS area
2341 */
2342 pp->rx_fis = mem;
2343 pp->rx_fis_dma = mem_dma;
2344
2345 mem += rx_fis_sz;
2346 mem_dma += rx_fis_sz;
2347
2348 /*
2349 * Third item: data area for storing a single command
2350 * and its scatter-gather table
2351 */
2352 pp->cmd_tbl = mem;
2353 pp->cmd_tbl_dma = mem_dma;
2354
2355 /*
2356 * Save off initial list of interrupts to be enabled.
2357 * This could be changed later
2358 */
2359 pp->intr_mask = DEF_PORT_IRQ;
2360
2361 /*
2362 * Switch to per-port locking in case each port has its own MSI vector.
2363 */
2364 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2365 spin_lock_init(&pp->lock);
2366 ap->lock = &pp->lock;
2367 }
2368
2369 ap->private_data = pp;
2370
2371 /* engage engines, captain */
2372 return ahci_port_resume(ap);
2373 }
2374
2375 static void ahci_port_stop(struct ata_port *ap)
2376 {
2377 const char *emsg = NULL;
2378 int rc;
2379
2380 /* de-initialize port */
2381 rc = ahci_deinit_port(ap, &emsg);
2382 if (rc)
2383 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2384 }
2385
2386 void ahci_print_info(struct ata_host *host, const char *scc_s)
2387 {
2388 struct ahci_host_priv *hpriv = host->private_data;
2389 void __iomem *mmio = hpriv->mmio;
2390 u32 vers, cap, cap2, impl, speed;
2391 const char *speed_s;
2392
2393 vers = readl(mmio + HOST_VERSION);
2394 cap = hpriv->cap;
2395 cap2 = hpriv->cap2;
2396 impl = hpriv->port_map;
2397
2398 speed = (cap >> 20) & 0xf;
2399 if (speed == 1)
2400 speed_s = "1.5";
2401 else if (speed == 2)
2402 speed_s = "3";
2403 else if (speed == 3)
2404 speed_s = "6";
2405 else
2406 speed_s = "?";
2407
2408 dev_info(host->dev,
2409 "AHCI %02x%02x.%02x%02x "
2410 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2411 ,
2412
2413 (vers >> 24) & 0xff,
2414 (vers >> 16) & 0xff,
2415 (vers >> 8) & 0xff,
2416 vers & 0xff,
2417
2418 ((cap >> 8) & 0x1f) + 1,
2419 (cap & 0x1f) + 1,
2420 speed_s,
2421 impl,
2422 scc_s);
2423
2424 dev_info(host->dev,
2425 "flags: "
2426 "%s%s%s%s%s%s%s"
2427 "%s%s%s%s%s%s%s"
2428 "%s%s%s%s%s%s%s"
2429 "%s%s\n"
2430 ,
2431
2432 cap & HOST_CAP_64 ? "64bit " : "",
2433 cap & HOST_CAP_NCQ ? "ncq " : "",
2434 cap & HOST_CAP_SNTF ? "sntf " : "",
2435 cap & HOST_CAP_MPS ? "ilck " : "",
2436 cap & HOST_CAP_SSS ? "stag " : "",
2437 cap & HOST_CAP_ALPM ? "pm " : "",
2438 cap & HOST_CAP_LED ? "led " : "",
2439 cap & HOST_CAP_CLO ? "clo " : "",
2440 cap & HOST_CAP_ONLY ? "only " : "",
2441 cap & HOST_CAP_PMP ? "pmp " : "",
2442 cap & HOST_CAP_FBS ? "fbs " : "",
2443 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2444 cap & HOST_CAP_SSC ? "slum " : "",
2445 cap & HOST_CAP_PART ? "part " : "",
2446 cap & HOST_CAP_CCC ? "ccc " : "",
2447 cap & HOST_CAP_EMS ? "ems " : "",
2448 cap & HOST_CAP_SXS ? "sxs " : "",
2449 cap2 & HOST_CAP2_DESO ? "deso " : "",
2450 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2451 cap2 & HOST_CAP2_SDS ? "sds " : "",
2452 cap2 & HOST_CAP2_APST ? "apst " : "",
2453 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2454 cap2 & HOST_CAP2_BOH ? "boh " : ""
2455 );
2456 }
2457 EXPORT_SYMBOL_GPL(ahci_print_info);
2458
2459 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2460 struct ata_port_info *pi)
2461 {
2462 u8 messages;
2463 void __iomem *mmio = hpriv->mmio;
2464 u32 em_loc = readl(mmio + HOST_EM_LOC);
2465 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2466
2467 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2468 return;
2469
2470 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2471
2472 if (messages) {
2473 /* store em_loc */
2474 hpriv->em_loc = ((em_loc >> 16) * 4);
2475 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2476 hpriv->em_msg_type = messages;
2477 pi->flags |= ATA_FLAG_EM;
2478 if (!(em_ctl & EM_CTL_ALHD))
2479 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2480 }
2481 }
2482 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2483
2484 static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2485 struct scsi_host_template *sht)
2486 {
2487 int i, rc;
2488
2489 rc = ata_host_start(host);
2490 if (rc)
2491 return rc;
2492 /*
2493 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2494 * allocated. That is one MSI per port, starting from @irq.
2495 */
2496 for (i = 0; i < host->n_ports; i++) {
2497 struct ahci_port_priv *pp = host->ports[i]->private_data;
2498
2499 /* Do not receive interrupts sent by dummy ports */
2500 if (!pp) {
2501 disable_irq(irq + i);
2502 continue;
2503 }
2504
2505 rc = devm_request_threaded_irq(host->dev, irq + i,
2506 ahci_multi_irqs_intr,
2507 ahci_port_thread_fn, 0,
2508 pp->irq_desc, host->ports[i]);
2509 if (rc)
2510 return rc;
2511 ata_port_desc(host->ports[i], "irq %d", irq + i);
2512 }
2513 return ata_host_register(host, sht);
2514 }
2515
2516 /**
2517 * ahci_host_activate - start AHCI host, request IRQs and register it
2518 * @host: target ATA host
2519 * @sht: scsi_host_template to use when registering the host
2520 *
2521 * LOCKING:
2522 * Inherited from calling layer (may sleep).
2523 *
2524 * RETURNS:
2525 * 0 on success, -errno otherwise.
2526 */
2527 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2528 {
2529 struct ahci_host_priv *hpriv = host->private_data;
2530 int irq = hpriv->irq;
2531 int rc;
2532
2533 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2534 rc = ahci_host_activate_multi_irqs(host, irq, sht);
2535 else if (hpriv->flags & AHCI_HFLAG_EDGE_IRQ)
2536 rc = ata_host_activate(host, irq, ahci_single_edge_irq_intr,
2537 IRQF_SHARED, sht);
2538 else
2539 rc = ata_host_activate(host, irq, ahci_single_level_irq_intr,
2540 IRQF_SHARED, sht);
2541 return rc;
2542 }
2543 EXPORT_SYMBOL_GPL(ahci_host_activate);
2544
2545 MODULE_AUTHOR("Jeff Garzik");
2546 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2547 MODULE_LICENSE("GPL");
Linux with added FPC-III support